1
Precison Edge®
SY10E111A/L
SY100E111A/L
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
DESCRIPTION
FEATURES
Precision Edge®
SY10E111A/L
SY100E111A/L
5V/3.3V 1:9 DIFFERENTIAL
CLOCK DRIVER (w/o ENABLE)
■5V and 3.3V power supply options
■200ps part-to-part skew
■50ps output-to-output skew
■Differential design
■VBB output
■Voltage and temperature compensated outputs
■75KΩ input pulldown resistors
■Fully compatible with Motorola MC100LVE111
■Available in 28-pin PLCC package
The SY10/100E111A/L are low skew 1-to-9 differential
driver designed for clock distribution in mind. The
SY10/100E111A/L's function and performance are similar to
the popular SY10/100E111, with the improvement of lower
jitter and the added feature of low voltage operation. It accepts
one signal input, which can be either differential or single-
ended if the VBB output is used. The signal is fanned out to 9
identical differential outputs.
The E111A/L are specifically designed, modeled and
produced with low skew as the key goal. Optimal design and
layout serve to minimize gate to gate skew within a device, and
empirical modeling is used to determine process control limits
that ensure consistent tpd distributions from lot to lot. The net
result is a dependable, guaranteed low skew device.
To ensure that the tight skew specification is met it is
necessary that both sides of the differential output are
terminated into 50Ω, even if only one side is being used. In
most applications, all nine differential pairs will be used and
therefore terminated. In the case where fewer that nine pairs
are used, it is necessary to terminate at least the output pairs
on the same package side as the pair(s) being used on that
side, in order to maintain minimum skew. Failure to do this will
result in small degradations of propagation delay (on the order
of 10-20ps) of the output(s) being used which, while not being
catastrophic to most designs, will mean a loss of skew margin.
The E111A/L, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This
allows the E111A/L to be used for high performance clock
distribution in +5V/+3.3V systems. Designers can take
advantage of the E111A/L's performance to distribute low
skew clocks across the backplane or the board. In a PECL
environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For
systems incorporating GTL, parallel termination offers the
lowest power by taking advantage of the 1.2V supply as
terminating voltage.
BLOCK DIAGRAM
IN
VBB
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
Q
5
Q
5
Q
6
Q
6
Q
7
Q
7
Q
8
Q
8
IN
Rev.: J Amendment: /0
Rev. Date:
March 2006
Precision Edge is a registered trademark of Micrel, Inc.
Precision Edge®
PIN NAMES
Pin Function
IN, IN Differential Input Pair
Q0, Q0 — Q8, Q8Differential Outputs
VBB VBB Output
VCCO VCC to Output