MC74HC393DTR2 - ON Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 6

 Motorola, Inc. 1995

10/95

 

  

High–Performance Silicon–Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device consists of two independent 4–bit binary ripple counters with

parallel outputs from each counter stage. A ÷ 256 counter can be obtained

by cascading the two binary counters.

Internal flip–flops are triggered by high–to–low transitions of the clock

input. Reset for the counters is asynchronous and active–high. State

changes of the Q outputs do not occur simultaneously because of internal

ripple delays. Therefore, decoded output signals are subject to decoding

spikes and should not be used as clocks or as strobes except when gated

with the Clock of the HC393.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•Chip Complexity: 236 FETs or 59 Equivalent Gates

LOGIC DIAGRAM

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8

PIN 14 = VCC

PIN 7 = GND

BINARY

COUNTER



PIN ASSIGNMENT

FUNCTION TABLE

Inputs

Clock Reset Outputs

X H L

H L No Change

L L No Change

L No Change

L Advance to

Next State

105

Q2b

Q1b

RESET b

CLOCK b

VCC

Q4b

Q3b

Q2a

Q1a

RESET a

CLOCK a

GND

Q3a

Q4a

D SUFFIX

SOIC PACKAGE

CASE 751A–03

N SUFFIX

PLASTIC PACKAGE

CASE 646–06

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

J SUFFIX

CERAMIC PACKAGE

CASE 632–08

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

ÎÎÎÎÎÎ

750

500

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

(Plastic or SOIC DIP)

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎÎ

0.3

0.9

1.2

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

3.98

5.48

ÎÎÎÎ

3.84

5.34

ÎÎÎÎ

3.70

5.20

ÎÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC393

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

5.4

ÎÎÎÎ

4.4

ÎÎÎÎ

3.6

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q1

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

120

ÎÎÎÎ

150

ÎÎÎÎ

180

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q2

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

190

ÎÎÎÎ

240

ÎÎÎÎ

285

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q3

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

240

ÎÎÎÎ

300

ÎÎÎÎ

360

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock to Q4

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

290

ÎÎÎÎ

365

ÎÎÎÎ

435

ÎÎÎ

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

165

ÎÎÎÎ

205

ÎÎÎÎ

250

ÎÎÎ

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Counter)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Counter)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to Clock

(Figure 2)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock

(Figure 1)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

100

ÎÎÎÎ

120

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Reset

(Figure 2)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

125

ÎÎÎÎ

155

ÎÎÎÎ

190

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1000

500

400

ÎÎÎÎ

1000

500

400

ÎÎÎÎ

1000

500

400

ÎÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

PIN DESCRIPTIONS

INPUTS

Clock (Pins 1, 13)

Clock input. The internal flip–flops are toggled and the

counter state advances on high–to–low transitions of the

clock input.

CONTROL INPUTS

Reset (Pins 2, 12)

Active–high, asynchronous reset. A separate reset is pro-

vided for each counter. A high at the Reset input prevents

counting and forces all four outputs low.

OUTPUTS

Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)

Parallel binary outputs Q4 is the most significant bit.

SWITCHING WAVEFORMS

tPHL

VCC

GND

VCC

GND

50%

trec

CLOCK

RESET

Figure 1. Figure 2.

Figure 3. Test Circuit

CLOCK

RESET

1, 13

2, 12

3, 11

4, 10

5, 9

6, 8

EXPANDED LOGIC DIAGRAM

*Includes all probe and jig capacitance

CL*

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

CLOCK

90%90%

50%

10%

tftrVCC

GND

tw1/fmax

tPLH tPHL

90%

50%

10%

tTLH tTHL

D Q

MC54/74HC393

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0

CLOCK

RESET

TIMING DIAGRAM

COUNT SEQUENCE

Count

Outputs

Count

Q4 Q3 Q2 Q1

0 LLLL

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H

MC54/74HC393

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

0.785

0.280

0.200

0.020

0.065

0.015

0.170

0.040

0.750

0.245

0.155

0.015

0.055

0.008

0.125

0.020

19.94

7.11

5.08

0.50

1.65

0.38

4.31

1.01

19.05

6.23

3.94

0.39

1.40

0.21

3.18

0.51

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMESNION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

14 8

1 7

-A-

-B-

-T-

SEATING

PLANE

F G N

0.25 (0.010) T A

MS0.25 (0.010) T B

J 14 PL

D 14 PL

N SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

8.55

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

8.75

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.337

0.150

0.054

0.014

0.016

0.008

0.004

0.228

0.010

0.344

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B– P 7 PL

SEATING

PLANE

D 14 PL MJ

R X 45°

814

0.25 (0.010) T B A

MS S

B0.25 (0.010) M M

MC54/74HC393

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

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MC54/74HC393/D

*MC54/74HC393/D*

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