INTEGRATED CIRCUITS DATA SHEET PCF8566 Universal LCD driver for low multiplex rates Product specification Supersedes data of 1997 Apr 02 File under Integrated Circuits, IC12 1998 May 04 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Oscillator Internal clock External clock Timing Display latch Shift register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 7 I2C-BUS DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Bit transfer Start and stop conditions System configuration Acknowledge PCF8566 I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation 1998 May 04 2 PCF8566 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS 12 APPLICATION INFORMATION 13 CHIP DIMENSIONS AND BONDING PAD LOCATIONS 14 PACKAGE OUTLINES 15 SOLDERING 15.1 15.2 15.2.1 15.2.2 15.3 15.3.1 15.3.2 15.3.3 Introduction DIP Soldering by dipping or by wave Repairing soldered joints SO and VSO Reflow soldering Wave soldering Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS 18 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 1 PCF8566 FEATURES * Single-chip LCD controller/driver * Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing * Selectable display bias configuration: static, 12 or 13 * Internal LCD bias generation with voltage-follower buffers 2 GENERAL DESCRIPTION The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) having low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 24 segments and can easily be cascaded for larger LCD applications. The PCF8566 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). * 24 segment drives: up to twelve 8-segment numeric characters; up to six 15-segment alphanumeric characters; or any graphics of up to 96 elements * 24 x 4-bit RAM for display data storage * Auto-incremented display data loading across device subaddress boundaries * Display memory bank switching in static and duplex drive modes * Versatile blinking modes * LCD and logic supplies may be separated * 2.5 to 6 V power supply range * Low power consumption * Power saving mode for extremely low power consumption in battery-operated and telephone applications * I2C-bus interface * TTL/CMOS compatible * Compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers * May be cascaded for large LCD applications (up to 1536 segments possible) * Cascadable with the 40 segment LCD driver PCF8576C * Optimized pinning for single plane wiring in both single and multiple PCF8566 applications * Space-saving 40 lead plastic very small outline package (VSO40; SOT158-1) * No external components required (even in multiple device applications) * Manufactured in silicon gate CMOS process. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF8566P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 PCF8566T VSO40 plastic very small outline package; 40 leads SOT158-1 1998 May 04 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 15 16 BACKPLANE OUTPUTS 17 to 40 DISPLAY SEGMENT OUTPUTS R LCD VOLTAGE SELECTOR R R VLCD 4 CLK SYNC 12 LCD BIAS GENERATOR SHIFT REGISTER PCF8566 4 3 DISPLAY LATCH TIMING INPUT BANK SELECTOR BLINKER DISPLAY RAM 24 x 4 BITS Universal LCD driver for low multiplex rates VDD 14 BLOCK DIAGRAM 13 5 S0 to S23 Philips Semiconductors 4 andbook, full pagewidth 1998 May 04 BP0 BP2 BP1 BP3 OUTPUT BANK SELECTOR DISPLAY CONTROLLER OSC VSS SCL SDA 6 OSCILLATOR POWERON RESET DATA POINTER COMMAND DECODER 11 2 1 INPUT FILTERS SUBADDRESS COUNTER I2 C-BUS CONTROLLER 10 7 A0 A1 9 A2 MGG383 PCF8566 Fig.1 Block diagram. Product specification SA0 8 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 5 PCF8566 PINNING SYMBOL PIN DESCRIPTION SDA 1 I2C-bus SCL 2 I2C-bus clock input/output SYNC 3 cascade synchronization input/output handbook, halfpage data input/output SDA 1 40 S23 SCL 2 39 S22 SYNC 3 38 S21 CLK 4 external clock input/output CLK 4 37 S20 VDD 5 positive supply voltage VDD 5 36 S19 OSC 6 oscillator input OSC 6 35 S18 A0 7 A0 7 34 S17 A1 8 A1 8 33 S16 A2 9 SA0 10 I2C-bus slave address bit 0 input A2 9 32 S15 VSS 11 logic ground SA0 10 31 S14 VLCD 12 LCD supply voltage VSS 11 BP0 13 BP2 14 BP1 15 BP3 16 I2C-bus subaddress inputs LCD backplane outputs S0 to S23 17 to 40 LCD segment outputs PCF8566 30 S13 VLCD 12 29 S12 BP0 13 28 S11 BP2 14 27 S10 BP1 15 26 S9 BP3 16 25 S8 S0 17 24 S7 S1 18 23 S6 S2 19 22 S5 S3 20 21 S4 MGG382 Fig.2 Pin configuration. 1998 May 04 5 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6 All of the display configurations given in Table 1 can be implemented in the typical system shown in Fig.3. The host microprocessor/microcontroller maintains the two-line I2C-bus communication channel with the PCF8566. The internal oscillator is selected by tying OSC (pin 6) to VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and to the LCD panel chosen for the application. FUNCTIONAL DESCRIPTION The PCF8566 is a versatile peripheral device designed to interface any microprocessor to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 4 backplanes and up to 24 segments. The display configurations possible with the PCF8566 depend on the number of active backplane outputs required; a selection of display configurations is given in Table 1. Table 1 PCF8566 Selection of display configurations ACTIVE BACKPLANE OUTPUTS NUMBER OF SEGMENTS 4 96 12 digits + 12 indicator symbols 6 characters + 12 indicator symbols 96 dots (4 x 24) 3 72 9 digits + 9 indicator symbols 4 characters + 16 indicator symbols 72 dots (3 x 24) 2 48 6 digits + 6 indicator symbols 3 characters + 6 indicator symbols 48 dots (2 x 24) 1 24 3 digits + 3 indicator symbols 1 character + 10 indicator symbols 24 dots 14-SEGMENT ALPHANUMERIC 7-SEGMENT NUMERIC DOT MATRIX handbook, full pagewidth VDD R trise 2 Cbus HOST MICROPROCESSOR/ MICROCONTROLLER VDD SDA SCL OSC VLCD 5 12 1 17 to 40 24 segment drives PCF8566 2 6 13 to 16 7 A0 8 9 A1 A2 10 4 backplanes SA0 VSS Fig.3 Typical system configuration. 6 (up to 96 elements) 11 VSS 1998 May 04 LCD PANEL MGG385 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.1 Power-on reset 6.3 At power-on the PCF8566 resets to a defined starting condition as follows: 2. All segment outputs are set to VDD 3. The drive mode `1 : 4 multiplex with 13bias' is selected 4. Blinking is switched off 5. Input and output bank selectors are reset (as defined in Table 5) 6. The A practical value of Vop is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is Vop 3 Vth. Multiplex drive interface is initialized 7. The data pointer and the subaddress counter are cleared. ratios of 1 : 3 and 1 : 4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD according to the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of Vop = VDD - VLCD and the resulting discrimination ratios (D), are given in Table 2. 1. All backplane outputs are set to VDD I2C-bus PCF8566 ( 3 = 1.732 for 1 : 3 multiplex or 21 3 = 1.528 for 1 : 4 multiplex). The advantage of these modes is a reduction of the LCD full scale voltage Vop as follows: LCD bias generator The full-scale LCD voltage (Vop) is obtained from VDD - VLCD. The LCD voltage may be temperature compensated externally through the VLCD supply to pin 12. Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected between VDD and VLCD. The centre resistor can be switched out of circuit to provide a 12bias voltage level for the 1 : 2 multiplex configuration. 1 : 3 multiplex (12bias): V op = 6V op(mrs) = 2.449V off ( rms ) 1 : 4 multiplex (12bias): V op = 4 3 3 V off ( rms ) = 2.309V off ( rms ) These compare with Vop = 3 Voff(rms) when 13bias is used. Table 2 Preferred LCD drive modes: summary of characteristics LCD DRIVE MODE Static (1 BP) LCD BIAS CONFIGURATION V off ( rms ) ----------------------V op V on ( rms ) ----------------------V op V on ( rms ) D = ---------------------V off ( rms ) static (2 levels) 0 1 2 4 = 0.354 10 4 = 0.791 5 = 2.236 1 : 2 MUX (2 BP) 1 2 (3 levels) 1 : 2 MUX (2 BP) 1 3 (4 levels) 1 3 = 0.333 5 3 = 0.745 5 = 2.236 1 : 3 MUX (3 BP) 1 3 (4 levels) 1 3 = 0.333 33 9 = 0.638 33 3 = 1.915 1 : 4 MUX (4 BP) 1 3 (4 levels) 1 3 = 0.333 3 3 = 0.577 3 = 1.732 1998 May 04 7 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4 PCF8566 LCD drive mode waveforms The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Fig.4. When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566 allows use of 1 or 1 bias in this mode as shown in Figs 5 and 6. 2 3 The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4 multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively. Tframe handbook, full pagewidth LCD segments VDD BP0 VLCD state 1 (on) VDD state 2 (off) Sn VLCD VDD Sn + 1 VLCD (a) waveforms at driver Vop state 1 0 At any instant (t): Vstate 1(t) = VS (t) - VBP0(t) n Von(rms) = Vop -Vop Vop state 2 Vstate 2(t) = VSn + 1(t) - VBP0(t) Voff(rms) = 0 V 0 -Vop (b) resultant waveforms at LCD segment MGG392 Fig.4 Static drive mode waveforms: Vop = VDD - VLCD. 1998 May 04 8 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 Tframe handbook, full pagewidth VDD BP0 LCD segments (VDD + VLCD)/2 VLCD state 1 VDD BP1 state 2 (VDD + VLCD)/2 VLCD VDD Sn VLCD VDD Sn + 1 VLCD (a) waveforms at driver Vop At any instant (t): Vop/2 Vstate 1(t) = VSn(t) - VBP0(t) V Von(rms) = op10 = 0.791Vop 4 0 state 1 -Vop/2 Vstate 2(t) = VS (t) - VBP1(t) n V Voff(rms) = op2 = 0.354Vop 4 -Vop Vop Vop/2 0 state 2 -Vop/2 -Vop (b) resultant waveforms at LCD segment MGG394 Fig.5 Waveforms for 1 : 2 multiplex drive mode with 12 bias: Vop = VDD - VLCD. 1998 May 04 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 Tframe handbook, full pagewidth VDD BP0 LCD segments VDD - Vop/3 VDD - 2Vop/3 VLCD state 1 VDD BP1 Sn Sn + 1 state 2 VDD - Vop/3 VDD - 2Vop/3 VLCD VDD VDD - Vop/3 VDD - 2Vop/3 VLCD VDD VDD - Vop/3 VDD - 2Vop/3 VLCD (a) waveforms at driver state 1 Vop 2Vop/3 Vop/3 0 -Vop/3 At any instant (t): Vstate 1(t) = VSn(t) - VBP0(t) V Von(rms) = op5 = 0.745Vop 3 -2Vop/3 -Vop Vop state 2 2Vop/3 Vop/3 0 -Vop/3 -2Vop/3 -Vop Vstate 2(t) = VS (t) - VBP1(t) n V Voff(rms) = op = 0.333Vop 3 (b) resultant waveforms at LCD segment MGG393 Fig.6 Waveforms for 1 : 2 multiplex drive mode with 13 bias: Vop = VDD - VLCD. 1998 May 04 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 Tframe handbook, full pagewidth BP0 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD BP1 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD BP2 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD Sn VDD VDD - Vop/3 VDD - 2Vop/3 VLCD Sn + 1 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD Sn + 2 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD LCD segments state 1 state 2 (a) waveforms at driver Vop 2Vop/3 Vop/3 state 1 0 -Vop/3 -2Vop/3 -Vop Vop 2Vop/3 Vop/3 state 2 0 -Vop/3 -2Vop/3 -Vop At any instant (t): Vstate 1(t) = VS (t) - VBP0(t) n V Von(rms) = op33 = 0.638Vop 9 Vstate 2(t) = VSn(t) - VBP1(t) V Voff(rms) = op = 0.333Vop 3 (b) resultant waveforms at LCD segment Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop = VDD - VLCD. 1998 May 04 11 MGG395 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Tframe handbook, full pagewidth BP0 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD BP1 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD BP2 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD BP3 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD Sn PCF8566 LCD segments state 1 state 2 VDD VDD - Vop/3 VDD - 2Vop/3 VLCD VDD Sn + 1 VDD - Vop/3 VDD - 2Vop/3 VLCD VDD Sn + 2 Sn + 3 VDD - Vop/3 VDD - 2Vop/3 VLCD VDD VDD - Vop/3 VDD - 2Vop/3 VLCD (a) waveforms at driver state 1 Vop 2Vop/3 Vop/3 0 -Vop/3 At any instant (t): Vstate 1(t) = VSn(t) - VBP0(t) V Von(rms) = op3 = 0.577Vop 3 -2Vop/3 -Vop Vop state 2 2Vop/3 Vop/3 0 -Vop/3 -2Vop/3 -Vop Vstate 2(t) = VS (t) - VBP1(t) n V Voff(rms) = op = 0.333Vop 3 (b) resultant waveforms at LCD segment Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop = VDD - VLCD. 1998 May 04 12 MGG396 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.5 The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. When a device is unable to `digest' a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. Oscillator The internal logic and the LCD drive signals of the PCF8566 or PCF8576 are timed either by the built-in oscillator or from an external clock. The clock frequency (fCLK) determines the LCD frame frequency and the maximum rate for data reception from the I2C-bus. To allow I2C-bus transmissions at their maximum data rate of 100 kHz, fCLK should be chosen to be above 125 kHz. 6.9 Internal clock When the internal oscillator is used, OSC (pin 6) should be tied to VSS. In this case, the output from CLK (pin 4) provides the clock signal for cascaded PCF8566s and PCF8576s in the system. 6.7 6.10 Shift register The shift register serves to transfer display information from the display RAM to the display latch while previous data are displayed. External clock 6.11 The condition for external clock is made by tying OSC (pin 6) to VDD; CLK (pin 4) then becomes the external clock input. 6.8 Display latch The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and one column of the display RAM. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 PCF8566 The LCD drive section includes 24 segment outputs S0 to S23 (pins 17 to 40) which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with the data resident in the display latch. When less than 24 segment outputs are required the unused segment outputs should be left open-circuit. Timing The timing of the PCF8566 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the synchronization signal SYNC maintains the correct timing relationship between the PCF8566s in the system. The timing also generates the LCD frame frequency which it derives as an integer multiple of the clock frequency (Table 3). The frame frequency is set by MODE SET commands when internal clock is used, or by the frequency applied to pin 4 when external clock is used. Table 3 6.12 Normal mode Power saving mode fframe NOMINAL fframe (Hz) fCLK/2880 64 fCLK/480 64 The ratio between the clock frequency and the LCD frame frequency depends on the mode in which the device is operating. In the power saving mode the reduction ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six. The reduced clock frequency results in a significant reduction in power dissipation. 1998 May 04 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required the unused outputs can be left open. In the 1 : 3 multiplex drive mode BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. LCD frame frequencies PCF8566 MODE Segment outputs 6.13 Display RAM The display RAM is a static 24 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the `on' state of the corresponding LCD segment; similarly, a logic 0 indicates the `off' state. 13 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 24 segments operated with respect to backplane BP0 (see Fig.9). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored starting at the display RAM address indicated by the data pointer thereby observing the filling order shown in Fig.10. The data pointer is automatically incremented according to the LCD configuration chosen. That is, after each byte is stored, the contents of the data pointer are incremented by eight (static drive mode), by four (1 : 2 multiplex drive mode), by three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex drive mode). When display data are transmitted to the PCF8566 the display bytes received are stored in the display RAM according to the selected LCD drive mode. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies equally to other LCD types. 6.15 Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should be tied to VSS or VDD. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. With reference to Fig.10, in the static drive mode the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 multiplex drive mode the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 multiplex drive mode these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. In the 1 : 4 multiplex drive mode the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. 6.14 PCF8566 The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are being sent to the display RAM, automatic wrap-over to the next PCF8566 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character. Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. display RAM addresses (rows)/segment outputs (S) handbook, full pagewidth 0 1 2 3 4 19 20 21 22 23 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3 MGG389 Fig.9 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. 1998 May 04 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... static a 2 Sn 3 Sn 4 Sn 5 Sn 6 b f g e 1 15 1:3 Sn 2 Sn 3 Sn 1 Sn 2 Sn 7 DP BP1 e c d DP b f n 4 n 5 n 6 n 7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x n n 1 n 2 n 3 a b x x f g x x e c x x d DP x x n n 1 n 2 b DP c x a d g x f e x x n n 1 a c b DP f e g d LSB c b a f g e d DP BP1 c 0 1 2 3 BP2 DP a b BP0 0 1 2 3 bit/ BP BP1 c d a b f LSB g e c d DP MSB LSB b DP c a d g f e BP2 g e MSB Sn bit/ BP f 1 n 3 BP0 a Sn BP3 MSB a c b DP f LSB e g d DP Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus (X = data bit unchanged). PCF8566 MBE534 Product specification Sn 0 1 2 3 bit/ BP d multiplex n 2 b f e 1:4 n 1 BP0 a g multiplex n MSB 0 1 2 3 bit/ BP g multiplex transmitted display byte 1 Sn c Sn Sn BP0 Sn d 1:2 display RAM filling order handbook, full pagewidth Sn LCD backplanes Philips Semiconductors LCD segments Universal LCD driver for low multiplex rates 1998 May 04 drive mode Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.16 Output bank selector 6.18 This selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to be selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex, bits 0 then 1 are selected and, in the static mode, bit 0 is selected. An additional feature is for an arbitrary selection of LCD segments to be blinked. This applies to the static and 1 : 2 LCD drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the BLINK command. In the 1 : 3 and 1 : 4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display is to be blinked at a frequency other than the nominal blinking frequency, this can be effectively performed by resetting and setting the display enable bit E at the required rate using the MODE SET command. Input bank selector The input bank selector loads display data into the display RAM according to the selected LCD drive configuration. Display data can be loaded in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 drive mode by using the BANK SELECT command. The input bank selector functions independently of the output bank selector. Table 4 Blinker The display blinking capabilities of the PCF8566 are very versatile. The whole display can be blinked at frequencies selected by the BLINK command. The blinking frequencies are integer multiples of the clock frequency; the ratios between the clock and blinking frequencies depend on the mode in which the device is operating, as shown in Table 4. The PCF8566 includes a RAM bank switching feature in the static and 1 : 2 multiplex drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of bit 0 contents. In the 1 : 2 drive mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.17 PCF8566 Blinking frequencies BLINKING MODE NORMAL OPERATING MODE RATIO POWER-SAVING MODE RATIO NOMINAL BLINKING FREQUENCY fblink (Hz) Off - - blinking off 2 Hz fCLK/92160 fCLK/15360 2 1 Hz fCLK/184320 fCLK/30720 1 0.5 Hz fCLK/368640 fCLK/61440 0.5 1998 May 04 16 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7 PCF8566 I2C-BUS DESCRIPTION 7.4 The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 7.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). 7.3 Acknowledge System configuration A device generating a message is a `transmitter', a device receiving a message is a `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves'. SDA SCL data line stable; data valid change of data allowed Fig.11 Bit transfer. 1998 May 04 17 MBA607 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 SDA SDA SCL SCL S P START condition STOP condition MBA608 Fig.12 Definition of START and STOP conditions. SDA SCL MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER / RECEIVER MASTER TRANSMITTER MBA605 Fig.13 System configuration. clock pulse for acknowledgement START condition handbook, full pagewidth SCL FROM MASTER 1 2 8 DATA OUTPUT BY TRANSMITTER S DATA OUTPUT BY RECEIVER MBA606 - 1 Fig.14 Acknowledgement on the I2C-bus. 1998 May 04 18 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7.5 The I2C-bus protocol is shown in Fig.15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8566 slave addresses available. All PCF8566s with the corresponding SA0 level acknowledge in parallel the slave address but all PCF8566s with the alternative SA0 level ignore the whole I2C-bus transfer. After acknowledgement, one or more command bytes (m) follow which define the status of the addressed PCF8566s. The last command byte is tagged with a cleared most-significant bit, the continuation bit C. The command bytes are also acknowledged by all addressed PCF8566s on the bus. PCF8566 I2C-bus controller The PCF8566 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8566 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally left open-circuit or tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are left open-circuit or tied to VSS or VDD according to a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. After the last command byte, a series of display data bytes (n) may follow. These display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data are directed to the intended PCF8566 device. The acknowledgement after each byte is made only by the (A0, A1, A2) addressed PCF8566. After the last display byte, the I2C-bus master issues a STOP condition (P). In the power-saving mode it is possible that the PCF8566 is not able to keep up with the highest transmission rates when large amounts of display data are transmitted. If this situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are completed. This is known as the `clock synchronization feature' of the I2C-bus and serves to slow down fast transmitters. Data loss does not occur. 7.6 7.8 Input filters I2C-bus protocol The five commands available to the PCF8566 are defined in Table 5. Two I2C-bus slave addresses (0111110 and 0111111) are reserved for PCF8566. The least-significant bit of the slave address that a PCF8566 will respond to is defined by the level tied at its input SA0 (pin 10). Therefore, two types of PCF8566 can be distinguished on the same I2C-bus which allows: 1. Up to 16 PCF8566s on the same I2C-bus for very large LCD applications 2. The use of two types of LCD multiplex on the same I2C-bus. 1998 May 04 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most-significant bit position (see Fig.16). When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If the bit is reset, it indicates the last command byte of the transfer. Further bytes will be regarded as display data. To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.7 PCF8566 19 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates handbook, full pagewidth PCF8566 acknowledge by A0, A1 and A2 selected PCF8566 only acknowledge by all addressed PCF8566s R/ W slave address S S 0 1 1 1 1 1 A 0 A C 0 COMMAND A DISPLAY DATA m 1 byte(s) 1 byte Fig.15 I2C-bus protocol. 0 = last command 1 = commands continue C LSB REST OF OPCODE MGG388 Fig.16 General format of command byte. 1998 May 04 20 P n 0 byte(s) MGG390 MSB A update data pointers and if necessary, subaddress counter Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 5 PCF8566 Definition of PCF8566 commands COMMAND/OPCODE OPTIONS DESCRIPTION Mode set C 1 0 LP E B M1 M0 see Table 6 defines LCD drive mode see Table 7 defines LCD bias configuration see Table 8 defines display status; the possibility to disable the display allows implementation of blinking under external control see Table 9 defines power dissipation mode Load data pointer C 0 0 P4 P3 P2 P1 P0 see Table 10 five bits of immediate data, bits P4 to P0, are transferred to the data pointer to define one of twenty-four display RAM addresses 1 0 0 A2 A1 A0 see Table 11 three bits of immediate data, bits A0 to A2, are transferred to the subaddress counter to define one of eight hardware subaddresses 1 1 1 0 I O see Table 12 defines input bank selection (storage of arriving display data) see Table 13 defines output bank selection (retrieval of LCD display data) Device select C 1 Bank select C 1 the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes Blink C Table 6 1 1 1 0 A BF1 BF0 see Table 14 defines the blinking frequency see Table 15 selects the blinking mode; normal operation with frequency set by bits BF1 and BF0, or blinking by alternation of display RAM banks. Alternation blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes LCD drive mode LCD DRIVE MODE BIT M1 BIT M0 Static (1 BP) 0 1 1 : 2 MUX (2 BP) 1 0 1 : 3 MUX (3 BP) 1 1 1 : 4 MUX (4 BP) 0 0 1998 May 04 21 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 7 LCD bias configuration PCF8566 Table 15 Blink mode selection LCD BIAS BLINK MODE BIT B BIT A 1 3bias 0 Normal blinking 0 1 2bias 1 Alternation blinking 1 Table 8 Display status 7.9 DISPLAY STATUS 0 Enabled 1 Table 9 The display controller executes the commands identified by the command decoder. It contains the status registers of the PCF8566 and coordinates their effects. BIT E Disabled (blank) The controller is also responsible for loading display data into the display RAM as required by the filling order. Power dissipation mode MODE BIT LP Normal mode 0 Power-saving mode 1 7.10 P4 P3 P2 P1 P0 5-bit binary value of 0 to 23 Table 11 Device select BITS A0 A1 A2 3-bit binary value of 0 to 7 Table 12 Input bank selection STATIC 1 : 2 MUX BIT 1 RAM bit 0 RAM bits 0, 1 0 RAM bit 2 RAM bits 2, 3 1 The SYNC line is provided to maintain the correct synchronization between all cascaded PCF8566s. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments; or by the definition of a multiplex mode when PCF8566s with differing SA0 levels are cascaded). SYNC is organized as an input/output pin; the output section being realized as an open-drain driver with an internal pull-up resistor. A PCF8566 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. Should synchronization in the cascade be lost, it will be restored by the first PCF8566 to assert SYNC. The timing relationships between the backplane waveforms and the SYNC signal for the various drive modes of the PCF8576 are shown in Fig.18. The waveforms are identical with the parent device PCF8576. Cascade ability between PCF8566s and PCF8576s is possible, giving cost effective LCD applications. Table 13 Output bank selection STATIC 1 : 2 MUX BIT 0 RAM bit 0 RAM bits 0, 1 0 RAM bit 2 RAM bits 2, 3 1 Table 14 Blinking frequency BLINK FREQUENCY BIT BF1 BIT BF0 Off 0 0 2 Hz 0 1 1 Hz 1 0 0.5 Hz 1 1 1998 May 04 Cascaded operation In large display configurations, up to 16 PCF8566s can be distinguished on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). It is also possible to cascade up to 16 PCF8566s. When cascaded, several PCF8566s are synchronized so that they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF8566s of the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (Fig.17). Table 10 Load data pointer BITS Display controller 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 handbook, full pagewidth VDD VLCD 5 12 SDA 1 SCL 2 SYNC 17 to 40 24 segment drives LCD PANEL PCF8566 3 CLK 4 OSC 6 7 8 A0 VLCD VDD R trise 2 Cbus 9 A1 10 A2 VDD SDA SCL SYNC CLK OSC BP0 to BP3 (open-circuit) 11 SA0 VSS VLCD 5 HOST MICROPROCESSOR/ MICROCONTROLLER (up to 1536 elements) 13 to 16 12 1 17 to 40 24 segment drives 2 3 PCF8566 4 13 to 16 4 backplanes 6 BP0 to BP3 7 A0 8 A1 9 A2 10 11 SA0 VSS VSS Fig.17 Cascaded PCF8566 configuration. 1998 May 04 23 MGG384 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 1 Tframe = f frame handbook, full pagewidth BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1 : 2 multiplex drive mode. BP2 SYNC (c) 1 : 3 multiplex drive mode. BP3 SYNC MBE535 (d) 1 : 4 multiplex drive mode. Fig.18 Synchronization of the cascade for the various PCF8566 drive modes. For single plane wiring of PCF8566s, see Chapter "Application information". 1998 May 04 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage -0.5 +7 V VLCD LCD supply voltage VDD - 7 VDD V VI input voltage (SCL, SDA, A0 to A2, OSC, CLK, SYNC and SA0) VSS - 0.5 VDD + 0.5 V VO output voltage (S0 to S23 and BP0 to BP3) VLCD - 0.5 VDD + 0.5 V II DC input current - 20 mA IO DC output current - 25 mA IDD, ISS, ILCD VDD, VSS or VLCD current - 50 mA Ptot power dissipation per package - 400 mW PO power dissipation per output - 100 mW Tstg storage temperature -65 +150 C 9 HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is advised to take handling precautions appropriate to handling MOS devices (see "Handling MOS devices"). 1998 May 04 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 10 DC CHARACTERISTICS VSS = 0 V; VDD = 2.5 to 6 V; VLCD = VDD - 2.5 to VDD - 6 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDD operating supply voltage 2.5 - 6 VLCD LCD supply voltage VDD - 6 - VDD - 2.5 V IDD operating supply current (normal mode) fCLK = 200 kHz; note 1 - 30 90 A ILP power saving mode supply current VDD = 3.5 V; VLCD = 0 V; fCLK = 35 kHz; A0, A1 and A2 tied to VSS; note 1 - 15 40 A V Logic VIL LOW level input voltage VSS - 0.3VDD V VIH HIGH level input voltage 0.7VDD - VDD V VOL LOW level output voltage IO = 0 mA - - 0.05 V VOH HIGH level output voltage IO = 0 mA VDD - 0.05 - - V IOL1 LOW level output current (CLK and SYNC) VOL = 1 V; VDD = 5 V 1 - - mA IOH HIGH level output current (CLK) VOH = 4 V; VDD = 5 V - - -1 mA IOL2 LOW level output current (SDA and SCL) VOL = 0.4 V; VDD = 5 V 3 - - mA ILI leakage current (SA0, CLK, OSC, A0, A1, A2, SCL and SDA) VI = VSS or VDD - - 1 A Ipd pull-down current (A0, A1, A2 and OSC) VI = 1 V; VDD = 5 V 15 50 150 A 15 25 60 k note 2 - 1.3 2 V - - 100 ns note 3 - - 7 pF CBP = 35 nF - 20 - mV - RpuSYNC pull-up resistor (SYNC) Vref power-on reset level tsw tolerable spike width on bus Ci input capacitance LCD outputs VBP DC voltage component (BP0 to BP3) VS DC voltage component (S0 to S23) CS = 5 nF 20 - mV ZBP output impedance (BP0 to BP3) VLCD = VDD - 5 V; note 4 - 1 5 k ZS output impedance (S0 to S23) VLCD = VDD -5 V; note 4 3 7 k - Notes 1. Outputs open; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 2. Resets all logic when VDD < Vref. 3. Periodically sampled, not 100% tested. 4. Outputs measured one at a time. 1998 May 04 26 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 11 AC CHARACTERISTICS VSS = 0 V; VDD = 2.5 to 6 V; VLCD = VDD - 2.5 to VDD - 6 V; Tamb = -40 to +85 C; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fCLK oscillator frequency (normal mode) VDD = 5 V; note 2 125 200 315 kHz fCLKLP oscillator frequency (power saving mode) VDD = 3.5 V 21 31 48 kHz tCLKH CLK HIGH time 1 - - s tCLKL CLK LOW time 1 - - s tPSYNC SYNC propagation delay - - 400 ns tSYNCL SYNC LOW time 1 - - s tPLCD driver delays with test loads - - 30 s VLCD = VDD - 5 V I2C-bus tBUF bus free time 4.7 - - s tHD; STA START condition hold time 4 - - s tLOW SCL LOW time 4.7 - - s tHIGH SCL HIGH time 4 - - s tSU; STA START condition set-up time (repeated start code only) 4.7 - - s tHD; DAT data hold time 0 - - s tSU; DAT data set-up time 250 - - ns tr rise time - - 1 s tf fall time - - 300 ns tSU; STO STOP condition set-up time 4.7 - - s Notes 1. All timing values referred to VIH and VIL levels with an input voltage swing of VSS to VDD. 2. At fCLK < 125 kHz, I2C-bus maximum transmission speed is derated. handbook, full pagewidth CLK (pin 4) 3.3 k (2%) SYNC (pin 3) BP0 to BP3 (pins 13 to 16) SDA, SCL (pins 1, 2) 0.5VDD 1.5 k (2%) VDD 6.8 k VDD (2%) S0 to S23 (pins 17 to 40) Iload 25 A Iload 15 A MGG387 Fig.19 Test loads. 1998 May 04 27 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 1 fCLK handbook, full pagewidth tCLKH tCLKL 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPSYNC tSYNCL 0.5 V BP0 to BP3 S0 to S23 (VDD = 5 V) 0.5 V tPLCD MGG391 Fig.20 Driver timing waveforms. handbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA MGA728 t SU;STA Fig.21 I2C-bus timing waveforms. 1998 May 04 28 t SU;STO Philips Semiconductors Product specification Universal LCD driver for low multiplex rates MGG397 40 PCF8566 MGG398 24 handbook, halfpage handbook, halfpage IDD (A) IDD (A) -40 C 30 -40 C 16 +85 C +85 C 20 8 10 0 0 0 2 4 6 VDD (V) 8 0 a. Normal mode; VLCD = 0 V; external clock = 200 kHz. 2 4 6 VDD (V) 8 b. Low power mode; VLCD = 0 V; external clock = 35 kHz. Fig.22 Typical supply current characteristics. MGG400 MGG399 6 12 handbook, halfpage handbook, halfpage RBP RS (k) (k) 4 8 -40 C 2 4 +25 C +85 C 0 0 0 2 4 6 VDD (V) 8 0 a. Backplane output impedance BP0 to BP3 (RBP); VDD = 5 V; Tamb = -40 to +85 C. 2 6 VDD (V) 8 b. Segment output impedance S0 to S23 (RS); VDD = 5 V. Fig.23 Typical characteristics of LCD outputs. 1998 May 04 4 29 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 40 S23 1 40 S47 SCL 2 39 S22 2 39 S46 SYNC 3 38 S21 3 38 S45 CLK 4 37 S20 4 37 S44 VDD 5 36 S19 5 36 S43 OSC 6 35 S18 6 35 S42 A0 7 34 S17 7 34 S41 A1 8 33 S16 8 33 S40 A2 9 32 S15 9 32 S39 SA0 10 31 S14 10 31 S38 VSS 11 30 S13 11 30 S37 VLCD 12 29 S12 12 29 S36 BP0 13 28 S11 BP0 13 28 S35 BP2 14 27 S10 BP2 14 27 S34 BP1 15 26 S9 BP1 15 26 S33 BP3 16 25 S8 BP3 16 25 S32 S0 17 24 S7 S24 17 24 S31 S1 18 23 S6 S25 18 23 S30 S2 19 22 S5 S26 19 22 S29 S3 20 21 S4 S27 20 21 S28 PCF8566 open-circuit S23 S24 MGG386 PCF8566 Fig.24 Single plane wiring of package PCF8566s. S47 Product specification SEGMENTS PCF8566 Philips Semiconductors SDA Universal LCD driver for low multiplex rates 30 S0 BACKPLANES 12 APPLICATION INFORMATION 1998 May 04 SDA SCL SYNC CLK VDD VSS VLCD handbook, full pagewidth Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 13 CHIP DIMENSIONS AND BONDING PAD LOCATIONS 2.5 mm(1) y S8 S7 S6 S5 S4 S3 S2 S1 S0 BP3 handbook, full pagewidth 25 24 23 22 21 20 19 18 17 16 15 BP1 S9 26 14 BP2 S10 27 13 BP0 S11 28 12 VLCD S12 29 S13 30 S14 31 S15 32 S16 11 0 0 10 SA0 9 A2 33 8 A1 S17 34 7 A0 S18 35 6 OSC 3 (1) Typical value. Pad size: 120 x 120 m Chip area: 7.27 mm. The numbers given in the small squares refer to the pad numbers. Fig.25 Bonding pad locations. 31 4 CLK SDA 2 SYNC 1 SCL 40 S23 39 S22 38 S21 37 x 2.91(1) mm 5 VDD PCF8566 S20 S19 36 1998 May 04 VSS MBH783 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 Table 16 Bonding pad locations (dimensions in mm) All x/y coordinates are referenced to centre of chip, (see Fig.25). PAD NUMBER SYMBOL x y PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SDA SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 200 400 605 856 1062 1080 1080 1080 1080 1080 1080 1080 1080 1080 1080 1074 874 674 474 274 -274 -474 -674 -874 -1074 -1080 -1080 -1080 -1080 -1080 -1080 -1080 -1080 -1080 -1080 -1056 -830 -630 -430 -230 -1235 -1235 -1235 -1235 -1235 -1025 -825 -625 -425 -225 -25 347 547 747 947 1235 1235 1235 1235 1235 1235 1235 1235 1235 1235 765 565 365 165 -35 -235 -435 -635 -835 -1035 -1235 -1235 -1235 -1235 -1235 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1998 May 04 32 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 14 PACKAGE OUTLINES seating plane DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 21 40 pin 1 index E 1 20 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.7 0.51 4.0 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 inches 0.19 0.020 0.16 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 D (1) e e1 L ME MH w Z (1) max. 14.1 13.7 2.54 15.24 3.60 3.05 15.80 15.24 17.42 15.90 0.254 2.25 0.56 0.54 0.10 0.60 0.14 0.12 0.62 0.60 0.69 0.63 0.01 0.089 E (1) Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT129-1 051G08 MO-015AJ 1998 May 04 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-01-14 33 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 VSO40: plastic very small outline package; 40 leads SOT158-1 D E A X c y HE v M A Z 40 21 Q A2 A (A 3) A1 pin 1 index Lp L 1 detail X 20 w M bp e 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 2.70 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 12.3 11.8 2.25 1.7 1.5 1.15 1.05 0.2 0.1 0.1 0.6 0.3 0.012 0.096 0.017 0.0087 0.61 0.010 0.004 0.089 0.012 0.0055 0.60 0.30 0.29 0.03 0.48 0.46 0.067 0.089 0.059 inches 0.11 0.045 0.024 0.008 0.004 0.004 0.041 0.012 7o 0o Notes 1. Plastic or metal protrusions of 0.4 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-01-24 SOT158-1 1998 May 04 EUROPEAN PROJECTION 34 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. 15 SOLDERING 15.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 15.3.2 This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). 15.2 15.2.1 * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. DIP * The longitudinal axis of the package footprint must be parallel to the solder flow. SOLDERING BY DIPPING OR BY WAVE * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. REPAIRING SOLDERED JOINTS A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. 15.3 15.3.1 15.3.3 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. SO and VSO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO and VSO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 May 04 WAVE SOLDERING Wave soldering techniques can be used for all SO and VSO packages if the following conditions are observed: The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. 15.2.2 PCF8566 35 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8566 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 May 04 36 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates NOTES 1998 May 04 37 PCF8566 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates NOTES 1998 May 04 38 PCF8566 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates NOTES 1998 May 04 39 PCF8566 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (c) Philips Electronics N.V. 1998 SCA59 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 415106/1200/06/pp40 Date of release: 1998 May 04 Document order number: 9397 750 03725