DATA SH EET
Product specification
Supersedes data of 1997 Apr 02
File under Integrated Circuits, IC12
1998 May 04
INTEGRATED CIRCUITS
PCF8566
Universal LCD driver for low
multiplex rates
1998 May 04 2
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION
6.1 Power-on reset
6.2 LCD bias generator
6.3 LCD voltage selector
6.4 LCD drive mode waveforms
6.5 Oscillator
6.6 Internal clock
6.7 External clock
6.8 Timing
6.9 Display latch
6.10 Shift register
6.11 Segment outputs
6.12 Backplane outputs
6.13 Display RAM
6.14 Data pointer
6.15 Subaddress counter
6.16 Output bank selector
6.17 Input bank selector
6.18 Blinker
7I
2
C-BUS DESCRIPTION
7.1 Bit transfer
7.2 Start and stop conditions
7.3 System configuration
7.4 Acknowledge
7.5 PCF8566 I2C-bus controller
7.6 Input filters
7.7 I2C-bus protocol
7.8 Command decoder
7.9 Display controller
7.10 Cascaded operation
8 LIMITING VALUES
9 HANDLING
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS
12 APPLICATION INFORMATION
13 CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
14 PACKAGE OUTLINES
15 SOLDERING
15.1 Introduction
15.2 DIP
15.2.1 Soldering by dipping or by wave
15.2.2 Repairing soldered joints
15.3 SO and VSO
15.3.1 Reflow soldering
15.3.2 Wave soldering
15.3.3 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 04 3
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
1 FEATURES
Single-chip LCD controller/driver
Selectable backplane drive configuration: static
or 2, 3 or 4 backplane multiplexing
Selectable display bias configuration: static, 12or 13
Internal LCD bias generation with voltage-follower
buffers
24 segment drives: up to twelve 8-segment numeric
characters; up to six 15-segment alphanumeric
characters; or any graphics of up to 96 elements
24 ×4-bit RAM for display data storage
Auto-incremented display data loading across device
subaddress boundaries
Display memory bank switching in static and duplex
drive modes
Versatile blinking modes
LCD and logic supplies may be separated
2.5 to 6 V power supply range
Low power consumption
Power saving mode for extremely low power
consumption in battery-operated and telephone
applications
I2C-bus interface
TTL/CMOS compatible
Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers
May be cascaded for large LCD applications
(up to 1536 segments possible)
Cascadable with the 40 segment LCD driver PCF8576C
Optimized pinning for single plane wiring in both single
and multiple PCF8566 applications
Space-saving 40 lead plasticvery small outline package
(VSO40; SOT158-1)
No external components required (even in multiple
device applications)
Manufactured in silicon gate CMOS process.
2 GENERAL DESCRIPTION
The PCF8566 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) having low
multiplex rates. It generates the drive signals for any static
or multiplexed LCD containing up to four backplanes and
up to 24 segments and can easily be cascaded for larger
LCD applications. The PCF8566 is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
3 ORDERING INFORMATION
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PCF8566P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
PCF8566T VSO40 plastic very small outline package; 40 leads SOT158-1
1998 May 04 4
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
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4 BLOCK DIAGRAM
a
ndbook, full pagewidth
MGG383
LCD
VOLTAGE
SELECTOR
12
5
TIMING BLINKER
OSCILLATOR
INPUT
FILTERS I C-BUS
CONTROLLER
2
POWER-
ON
RESET
CLK 4
SYNC 3
OSC 6
11
SCL 2
SDA 1
SA0
10
DISPLAY
CONTROLLER
COMMAND
DECODER
BACKPLANE
OUTPUTS
13
BP0
14
BP2
15
BP1
16
BP3
INPUT
BANK
SELECTOR
DISPLAY
RAM
24 × 4 BITS
OUTPUT
BANK
SELECTOR
DATA
POINTER
SUB-
ADDRESS
COUNTER
DISPLAY SEGMENT OUTPUTS
DISPLAY LATCH
SHIFT REGISTER
17 to 40
S0 to S23
A0
7
A1
8
A2
9
PCF8566
LCD BIAS
GENERATOR
VSS
VLCD
VDD
R
R
R
Fig.1 Block diagram.
1998 May 04 5
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
5 PINNING
SYMBOL PIN DESCRIPTION
SDA 1 I2C-bus data input/output
SCL 2 I2C-bus clock input/output
SYNC 3 cascade synchronization
input/output
CLK 4 external clock input/output
VDD 5 positive supply voltage
OSC 6 oscillator input
A0 7 I2C-bus subaddress inputsA1 8
A2 9
SA0 10 I2C-bus slave address bit 0 input
VSS 11 logic ground
VLCD 12 LCD supply voltage
BP0 13
LCD backplane outputs
BP2 14
BP1 15
BP3 16
S0 to S23 17 to 40 LCD segment outputs
Fig.2 Pin configuration.
handbook, halfpage
PCF8566
MGG382
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
SDA
SCL
SYNC
CLK
VDD
OSC
A0
A1
A2
SA0
VSS
VLCD
BP0
BP2
BP1
BP3
S0
S1
S2
S3
1998 May 04 6
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
6 FUNCTIONAL DESCRIPTION
The PCF8566 is a versatile peripheral device designed to
interface any microprocessor to a wide variety of LCDs.
It can directly drive any static or multiplexed LCD
containing up to 4 backplanes and up to 24 segments.
The display configurations possible with the PCF8566
depend on the number of active backplane outputs
required; a selection of display configurations is given in
Table 1.
All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
two-line I2C-bus communication channel with the
PCF8566. The internal oscillator is selected by tying OSC
(pin 6) to VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally.
The only other connections required to complete the
system are to the power supplies (VDD, VSS and VLCD) and
to the LCD panel chosen for the application.
Table 1 Selection of display configurations
ACTIVE
BACKPLANE
OUTPUTS
NUMBER OF
SEGMENTS 7-SEGMENT NUMERIC 14-SEGMENT
ALPHANUMERIC DOT MATRIX
4 96 12 digits + 12 indicator
symbols 6 characters + 12 indicator
symbols 96 dots (4 ×24)
3 72 9 digits + 9 indicator
symbols 4 characters + 16 indicator
symbols 72 dots (3 ×24)
2 48 6 digits + 6 indicator
symbols 3 characters + 6 indicator
symbols 48 dots (2 ×24)
1 24 3 digits + 3 indicator
symbols 1 character + 10 indicator
symbols 24 dots
Fig.3 Typical system configuration.
handbook, full pagewidth
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
OSC
1 17 to 40
13 to 16
2
678
512
91011
24 segment drives
4 backplanes
LCD PANEL
(up to 96
elements)
PCF8566
A0 A1 A2 SA0
VDD
VDD VLCD
VSS
VSS
MGG385
R trise
2 Cbus
1998 May 04 7
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
6.1 Power-on reset
At power-on the PCF8566 resets to a defined starting
condition as follows:
1. All backplane outputs are set to VDD
2. All segment outputs are set to VDD
3. The drive mode ‘1 : 4 multiplex with 13bias’ is selected
4. Blinking is switched off
5. Input and output bank selectors are reset (as defined
in Table 5)
6. The I2C-bus interface is initialized
7. The data pointer and the subaddress counter are
cleared.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
6.2 LCD bias generator
The full-scale LCD voltage (Vop) is obtained from
VDD VLCD. The LCD voltage may be temperature
compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of three series resistors connected
between VDD and VLCD. The centre resistor can be
switched out of circuit to provide a 12bias voltage level for
the 1 : 2 multiplex configuration.
6.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of
the LCD according to the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop =V
DD VLCD and the
resulting discrimination ratios (D), are given in Table 2.
A practical value of Vop is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop 3V
th. Multiplex drive
ratios of 1 : 3 and 1 : 4 with 12bias are possible but the
discrimination and hence the contrast ratios are smaller
( for 1 : 3 multiplex or for
1 : 4 multiplex). The advantage of these modes is a
reduction of the LCD full scale voltage Vop as follows:
1 : 3 multiplex (12bias):
1 : 4 multiplex (12bias):
These compare with Vop =3V
off(rms) when 13bias is used.
3 1.732=21 31.528=
Vop 6Vop(mrs) 2.449Voff rms()
==
V
op 3
43Voff rms() 2.309Voff rms()
==
Table 2 Preferred LCD drive modes: summary of characteristics
LCD DRIVE MODE LCD BIAS
CONFIGURATION
Static (1 BP) static (2 levels) 0 1
1 : 2 MUX (2 BP) 12(3 levels)
1 : 2 MUX (2 BP) 13(4 levels) 13= 0.333
1 : 3 MUX (3 BP) 13(4 levels) 13= 0.333
1 : 4 MUX (4 BP) 13(4 levels) 13= 0.333
Voff rms()
V
op
----------------------- Von rms()
V
op
----------------------- DVon rms()
V
off rms()
-----------------------
=
2 4 0.354=10 40.791=52.236=
530.745=52.236=
33 90.638=33 31.915=
330.577=31.732=
1998 May 04 8
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
6.4 LCD drive mode waveforms
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.4.
When two backplanes are provided in the LCD the 1 : 2 multiplex drive mode applies. The PCF8566 allows use of
12or 13bias in this mode as shown in Figs 5 and 6.
The backplane and segment drive waveforms for the 1 : 3 multiplex drive mode (three LCD backplanes) and for the 1 : 4
multiplex drive mode (four LCD backplanes) are shown in Figs 7 and 8 respectively.
Fig.4 Static drive mode waveforms: Vop =V
DD VLCD.
handbook, full pagewidth
MGG392
state 1 At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop
Vstate 2(t) = VSn + 1(t) VBP0(t)
Voff(rms) = 0 V
0
BP0
state 2 0
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 1
(on) state 2
(off)
VDD
VLCD
VDD
VLCD
VDD
VLCD
Vop
Vop
Vop
Vop
Tframe
Sn
Sn + 1
1998 May 04 9
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.5 Waveforms for 1 : 2 multiplex drive mode with 12bias: Vop =V
DD VLCD.
handbook, full pagewidth
MGG394
state 1
BP0
Sn + 1
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 2
BP1
Sn
state 2
state 1
VDD
(VDD + VLCD)/2
VLCD
VDD
(VDD + VLCD)/2
VLCD
VDD
VLCD
VDD
VLCD
Vop
Vop/2
0
Vop/2
Vop
Vop
Vop/2
0
Vop/2
Vop
Tframe
At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop10 = 0.791Vop
4
Vstate 2(t) = VSn(t) VBP1(t)
Voff(rms) = Vop2 = 0.354Vop
4
1998 May 04 10
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.6 Waveforms for 1 : 2 multiplex drive mode with 13bias: Vop =V
DD VLCD.
h
andbook, full pagewidth
MGG393
state 1 0
BP0
(a) waveforms at driver
(b) resultant waveforms
at LCD segment
LCD segments
state 2
BP1
state 1
state 2 0
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Sn + 1
Sn
Tframe
At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop5 = 0.745Vop
3
Vstate 2(t) = VSn(t) VBP1(t)
Voff(rms) = Vop = 0.333Vop
3
1998 May 04 11
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.7 Waveforms for 1 : 3 multiplex drive mode: Vop =V
DD VLCD.
handbook, full pagewidth
MGG395
state 1 0
BP0
(b) resultant waveforms
at LCD segment
LCD segments
state 2
BP1
state 1
state 2 0
(a) waveforms at driver
BP2
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Sn
Sn + 1
Sn + 2
Tframe
At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop33 = 0.638Vop
9
Vstate 2(t) = VSn(t) VBP1(t)
Voff(rms) = Vop = 0.333Vop
3
1998 May 04 12
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.8 Waveforms for 1 : 4 multiplex drive mode: Vop =V
DD VLCD.
handbook, full pagewidth
MGG396
state 1 0
BP0
(b) resultant waveforms
at LCD segment
LCD segments
state 2
BP1
state 1
state 2 0
BP2
(a) waveforms at driver
BP3
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
VDD
VDD Vop/3
VDD 2Vop/3
VLCD
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Vop
Vop
2Vop/3
2Vop/3
Vop/3
Vop/3
Sn
Sn + 1
Sn + 2
Sn + 3
Tframe
At any instant (t):
Vstate 1(t) = VSn(t) VBP0(t)
Von(rms) = Vop3 = 0.577Vop
3
Vstate 2(t) = VSn(t) VBP1(t)
Voff(rms) = Vop = 0.333Vop
3
1998 May 04 13
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
6.5 Oscillator
The internal logic and the LCD drive signals of the
PCF8566 or PCF8576 are timed either by the built-in
oscillator or from an external clock.
The clock frequency (fCLK) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, fCLK should be chosen to
be above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6 Internal clock
When the internal oscillator is used, OSC (pin 6) should be
tied to VSS. In this case, the output from CLK (pin 4)
provides the clock signal for cascaded PCF8566s and
PCF8576s in the system.
6.7 External clock
The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.
6.8 Timing
The timing of the PCF8566 organizes the internal data flow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs.
In cascaded applications, the synchronization signal
SYNC maintains the correct timing relationship between
the PCF8566s in the system. The timing also generates
the LCD frame frequency which it derives as an integer
multiple of the clock frequency (Table 3). The frame
frequency is set by MODE SET commands when internal
clock is used, or by the frequency applied to pin 4 when
external clock is used.
Table 3 LCD frame frequencies
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
PCF8566 MODE fframe NOMINAL
fframe (Hz)
Normal mode fCLK/2880 64
Power saving mode fCLK/480 64
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus. When a
device is unable to ‘digest’ a display data byte before the
next one arrives, it holds the SCL line LOW until the first
display data byte is stored. This slows down the
transmission rate of the I2C-bus but no data loss occurs.
6.9 Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.10 Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data are displayed.
6.11 Segment outputs
The LCD drive section includes 24 segment outputs
S0 to S23 (pins 17 to 40) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with the data resident in the display latch.
When less than 24 segment outputs are required the
unused segment outputs should be left open-circuit.
6.12 Backplane outputs
The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open. In the 1 : 3 multiplex drive mode BP3
carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode
BP0 and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
6.13 Display RAM
The display RAM is a static 24 ×4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the ‘on’
state of the corresponding LCD segment; similarly, a
logic 0 indicates the ‘off’ state.
1998 May 04 14
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs.
The first RAM column corresponds to the 24 segments
operated with respect to backplane BP0 (see Fig.9).
In multiplexed LCD applications the segment data of the
second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
When display data are transmitted to the PCF8566 the
display bytes received are stored in the display RAM
according to the selected LCD drive mode. To illustrate the
filling order, an example of a 7-segment numeric display
showing all drive modes is given in Fig.10; the RAM filling
organization depicted applies equally to other LCD types.
With reference to Fig.10, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 multiplex drive mode
the eight transmitted data bits are placed in bits 0 and 1 of
four successive display RAM addresses. In the 1 : 3
multiplex drive mode these bits are placed in
bits 0, 1 and 2 of three successive addresses, with bit 2 of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because full bytes are always transmitted.
In the 1 : 4 multiplex drive mode the eight transmitted data
bits are placed in bits 0, 1, 2 and 3 of two successive
display RAM addresses.
6.14 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM.
The sequence commences with the initialization of the
data pointer by the LOAD DATA POINTER command.
Following this, an arriving data byte is stored starting at the
display RAM address indicated by the data pointer thereby
observing the filling order shown in Fig.10. The data
pointer is automatically incremented according to the LCD
configuration chosen. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode), by
three (1 : 3 multiplex drive mode) or by two (1 : 4 multiplex
drive mode).
6.15 Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2 (pins 7, 8, and 9). A0, A1 and A2 should
be tied to VSS or VDD. The subaddress counter value is
defined by the DEVICE SELECT command. If the contents
of the subaddress counter and the hardware subaddress
do not agree then data storage is inhibited but the data
pointer is incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are being sent to the display RAM,
automatic wrap-over to the next PCF8566 occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character.
Fig.9 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs,
and between bits in a RAM word and backplane outputs.
handbook, full pagewidth
0
0
1
2
3
1234 1920212223
display RAM addresses (rows)/segment outputs (S)
display RAM bits
(columns) /
backplane outputs
(BP)
MGG389
1998 May 04 15
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
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handbook, full pagewidth
MBE534
S2
n
S1
n
S7
n
Sn
Sn
S3
n
S5
n
S2
n
S3
n
S1
n
S1
n
S1
n
S2
n
Sn
S6
n
Sn
S4
n
DP
DP
DP
DP
a
fb
g
ec
d
a
fb
g
ec
d
a
fb
g
ec
d
a
fb
g
ec
d
BP0
BP0
BP0
BP1
BP1
BP2
BP1
BP2
BP3
BP0
n
c
x
x
x
0
1
2
3
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n1 n2 n3 n4 n5 n6 n7
bit/
BP
n
a
b
x
x
0
1
2
3
f
g
x
x
e
c
x
x
d
DP
x
x
n1 n2 n3
bit/
BP
n
b
DP
c
x
0
1
2
3
a
d
g
x
f
e
x
x
n1 n2
bit/
BP
n
a
c
b
DP
0
1
2
3
f
e
g
d
n1
bit/
BP
cbaf gedDP
abf gecdDP
bDPcadgf e
acbDPf egd
MSB LSB
MSB LSB
MSB LSB
MSB LSB
drive mode
static
1 : 2
multiplex
1 : 3
multiplex
1 : 4
multiplex
LCD segments LCD backplanes display RAM filling order transmitted display byte
Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus (X = data bit
unchanged).
1998 May 04 16
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
6.16 Output bank selector
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1 : 4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit 1, bit 2
and then bit 3. Similarly in 1 : 3 multiplex, bits 0, 1 and 2
are selected sequentially. In 1 : 2 multiplex, bits 0 then 1
are selected and, in the static mode, bit 0 is selected.
The PCF8566 includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1.
This gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it
is assembled.
6.17 Input bank selector
The input bank selector loads display data into the display
RAM according to the selected LCD drive configuration.
Display data can be loaded in bit 2 in static drive mode or
in bits2and3in1:2 drive mode by using the BANK
SELECT command. The input bank selector functions
independently of the output bank selector.
6.18 Blinker
The display blinking capabilities of the PCF8566 are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and 1 : 2
LCD drive modes and can be implemented without any
communication overheads. By means of the output bank
selector, the displayed RAM banks are exchanged with
alternate RAM banks at the blinking frequency. This mode
can also be specified by the BLINK command.
In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.
Table 4 Blinking frequencies
BLINKING MODE NORMAL OPERATING
MODE RATIO POWER-SAVING
MODE RATIO NOMINAL BLINKING FREQUENCY
fblink (Hz)
Off −− blinking off
2Hz f
CLK/92160 fCLK/15360 2
1Hz f
CLK/184320 fCLK/30720 1
0.5 Hz fCLK/368640 fCLK/61440 0.5
1998 May 04 17
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
7I
2
C-BUS DESCRIPTION
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
7.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is a ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.4 Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the bus by the
transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related
clock pulse, set up and hold times must be taken into
account. A master receiver must signal an end of data to
the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this
event the transmitter must leave the data line HIGH to
enable the master to generate a STOP condition.
Fig.11 Bit transfer.
MBA607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
1998 May 04 18
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.12 Definition of START and STOP conditions.
MBA608
SDA
SCL P
STOP condition
SDA
SCL
S
START condition
Fig.13 System configuration.
MBA605
MASTER
TRANSMITTER /
RECEIVER SLAVE
RECEIVER SLAVE
TRANSMITTER /
RECEIVER MASTER
TRANSMITTER MASTER
TRANSMITTER /
RECEIVER
SDA
SCL
Fig.14 Acknowledgement on the I2C-bus.
handbook, full pagewidth
MBA606 - 1
START
condition
S
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
clock pulse for
acknowledgement
1289
1998 May 04 19
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
7.5 PCF8566 I2C-bus controller
The PCF8566 acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to VSS which defines the hardware subaddress 0.
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to VSS or VDD according to a binary
coding scheme such that no two devices with a common
I2C-bus slave address have the same hardware
subaddress.
In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.6 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7 I2C-bus protocol
Two I2C-bus slave addresses (0111110 and 0111111) are
reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I2C-bus which
allows:
1. Up to 16 PCF8566s on the same I2C-bus for very large
LCD applications
2. The use of two types of LCD multiplex on the same
I2C-bus.
The I2C-bus protocol is shown in Fig.15. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I2C-bus transfer. After acknowledgement, one or more
command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I2C-bus master issues a STOP condition (P).
7.8 Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. All available commands carry a
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined
in Table 5.
1998 May 04 20
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.15 I2C-bus protocol.
handbook, full pagewidth
MGG390
S
A
0
S011111 0AC COMMAND AP
ADISPLAY DATA
slave address /RW
acknowledge by
all addressed
PCF8566s
acknowledge
by A0, A1 and A2
selected
PCF8566 only
m 1 byte(s) n ≥ 0 byte(s)1 byte
update data pointers
and if necessary,
subaddress counter
Fig.16 General format of command byte.
MGG388
REST OF OPCODE
C
MSB LSB
0 = last command
1 = commands continue
1998 May 04 21
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Table 5 Definition of PCF8566 commands
Table 6 LCD drive mode
COMMAND/OPCODE OPTIONS DESCRIPTION
Mode set
C 1 0 LP E B M1 M0 see Table 6 defines LCD drive mode
see Table 7 defines LCD bias configuration
see Table 8 defines display status; the possibility to disable
the display allows implementation of blinking
under external control
see Table 9 defines power dissipation mode
Load data pointer
C 0 0 P4 P3 P2 P1 P0 see Table 10 five bits of immediate data, bits P4 to P0, are
transferred to the data pointer to define one of
twenty-four display RAM addresses
Device select
C1100A2A1A0 see Table 11 three bits of immediate data, bits A0 to A2, are
transferred to the subaddress counter to define
one of eight hardware subaddresses
Bank select
C11110IO see Table 12 defines input bank selection (storage of arriving
display data)
see Table 13 defines output bank selection (retrieval of LCD
display data)
the BANK SELECT command has no effect in
1 : 3 and 1 : 4 multiplex drive modes
Blink
C1110ABF1BF0 see Table 14 defines the blinking frequency
see Table 15 selects the blinking mode; normal operation
with frequency set by bits BF1 and BF0, or
blinking by alternation of display RAM banks.
Alternation blinking does not apply in 1 : 3 and
1 : 4 multiplex drive modes
LCD DRIVE MODE BIT M1 BIT M0
Static (1 BP) 0 1
1 : 2 MUX (2 BP) 1 0
1 : 3 MUX (3 BP) 1 1
1 : 4 MUX (4 BP) 0 0
1998 May 04 22
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Table 7 LCD bias configuration
Table 8 Display status
Table 9 Power dissipation mode
Table 10 Load data pointer
Table 11 Device select
Table 12 Input bank selection
Table 13 Output bank selection
Table 14 Blinking frequency
LCD BIAS BIT B
13bias 0
12bias 1
DISPLAY STATUS BIT E
Disabled (blank) 0
Enabled 1
MODE BIT LP
Normal mode 0
Power-saving mode 1
BITS P4 P3 P2 P1 P0
5-bit binary value of 0 to 23
BITS A0 A1 A2
3-bit binary value of 0 to 7
STATIC 1 : 2 MUX BIT 1
RAM bit 0 RAM bits 0, 1 0
RAM bit 2 RAM bits 2, 3 1
STATIC 1 : 2 MUX BIT 0
RAM bit 0 RAM bits 0, 1 0
RAM bit 2 RAM bits 2, 3 1
BLINK
FREQUENCY BIT BF1 BIT BF0
Off 0 0
2Hz 0 1
1Hz 1 0
0.5 Hz 1 1
Table 15 Blink mode selection
7.9 Display controller
The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8566 and coordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.
7.10 Cascaded operation
In large display configurations, up to 16 PCF8566s can be
distinguished on the same I2C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). It is also
possible to cascade up to 16 PCF8566s. When cascaded,
several PCF8566s are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the outputs of only one device
need to be through-plated to the backplane electrodes of
the display. The other PCF8566s of the cascade
contribute additional segment outputs but their backplane
outputs are left open-circuit (Fig.17).
The SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8566s.
This synchronization is guaranteed after the power-on
reset. The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8566s with differing SA0 levels
are cascaded). SYNC is organized as an input/output pin;
the output section being realized as an open-drain driver
with an internal pull-up resistor. A PCF8566 asserts the
SYNC line at the onset of its last active backplane signal
and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be
restored by the first PCF8566 to assert SYNC. The timing
relationships between the backplane waveforms and the
SYNC signal for the various drive modes of the PCF8576
are shown in Fig.18. The waveforms are identical with the
parent device PCF8576. Cascade ability between
PCF8566s and PCF8576s is possible, giving cost effective
LCD applications.
BLINK MODE BIT A
Normal blinking 0
Alternation blinking 1
1998 May 04 23
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
Fig.17 Cascaded PCF8566 configuration.
handbook, full pagewidth
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
CLK
OSC
SYNC
117 to 40
13 to 16
13 to 16
2
3
4
678
512
91011
7 8 9 10 11
24 segment drives
4 backplanes
24 segment drives LCD PANEL
(up to 1536
elements)
PCF8566
PCF8566
A0 A1 A2 SA0
MGG384
SDA
SCL
SYNC
CLK
OSC
1512
2
3
4
6
17 to 40
BP0 to BP3
(open-circuit)
A0 A1 A2 SA0
BP0 to BP3
VDD VLCD
VSS
VDD VLCD
VSS
VLCD
VDD
VSS
R trise
2 Cbus
1998 May 04 24
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8566
For single plane wiring of PCF8566s, see Chapter “Application information”.
Fig.18 Synchronization of the cascade for the various PCF8566 drive modes.
handbook, full pagewidth
T=
frame fframe
1
BP0
SYNC
BP1
(1/2 bias)
SYNC
BP2
(a) static drive mode.
(b) 1 : 2 multiplex drive mode.
(c) 1 : 3 multiplex drive mode.
(d) 1 : 4 multiplex drive mode.
BP3
SYNC
SYNC
BP1
(1/3 bias)
MBE535