0 Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs R DS078 (v1.5) November 15, 2001 0 5 Advance Product Specification Features * Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices * Simple interface to the Spartan device * * Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages. * Programming support by leading programmer manufacturers. Programmable reset polarity (active High or active Low) * Design support using the Xilinx Alliance and Foundation series software packages. * Low-power CMOS floating gate process * Guaranteed 20 year life data retention * 3.3V PROM Introduction The XC17S00A family of PROMs provide an easy-to-use, cost-effective method for storing Spartan-II/Spartan-IIE device configuration bitstreams. When the Spartan device is in Master Serial mode, it generates a configuration clock that drives the Spartan PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the Spartan device DIN pin. The Spartan device generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When a Spartan device is in Slave Serial mode, the PROM and the Spartan device must both be clocked by an incoming signal. For device programming, either the Xilinx Alliance or the Spartan device design file into a standard HEX format which is then transferred to most commercial PROM programmers. Spartan-II/IIE FPGA Configuration Bits Compatible Spartan-II/IIE PROM XC2S15 197,696 XC17S15A XC2S30 336,768 XC17S30A XC2S50 559,200 XC17S50A XC2S100 781,216 XC17S100A XC2S150 1,040,096 XC17S150A XC2S200 1,335,840 XC17S200A XC2S50E 630,048 XC17S50A XC2S100E 863,840 XC17S100A XC2S150E(1) 1,134,528 XC17S200A XC2S200E 1,442,016 XC17S200A XC2S300E 1,875,648 XC17S300A Notes: 1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA. (c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS078 (v1.5) November 15, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 1 Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) R Pin Description Table 1: XC17S00A PROM Pinouts Pin Name 8-pin PDIP and VOIC 20-pin SOIC 44-pin VQFP DATA 1 1 40 Data output, High-Z state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. CLK 2 3 43 Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE 3 8 13 When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the DATA output is in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can be connected to the FPGAs INIT pin and a pull-up resistor. (OE/RESET) Pin Description The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 programmer software. Third-party programmers have different methods to invert this pin. CE 4 10 15 GND 5 11 18, 41 VCC 7, 8 18, 20 38 When High, this pin resets the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. GND is the ground connection. The VCC pins are to be connected to the positive voltage supply. Notes: 1. Pins not listed are reserved and should not be externally connected. Controlling PROMs FPGA Master Serial Mode Summary Connecting the Spartan device with the PROM: The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the Spartan device mode pins. In Master Serial mode, the Spartan device automatically loads the configuration program from an external memory. The XC17S00A PROM has been designed for compatibility with the Master Serial mode. * The DATA output of the PROM drives the DIN input of the lead Spartan device. * The Master Spartan device CCLK output drives the CLK input of the PROM. * The RESET/OE input of the PROM is connected to the INIT pin of the Spartan device and a pull-up resistor. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. * 2 The CE input of the PROM is connected to the DONE pin of the Spartan device and a pull-up resistor. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Upon power-up or reconfiguration, the Spartan device enters the Master Serial mode when the mode pins are set to Master Serial mode. Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial mode provides a simple configuration interface (Figure 1). Only a serial data line, two control lines, and a clock line are required to configure the Spartan device. Data from the PROM is read sequentially, accessed via the www.xilinx.com 1-800-255-7778 DS078 (v1.5) November 15, 2001 Advance Product Specification R Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the Spartan device is used only for configuration, it must still be held at a defined level during normal operation. The Spartan-II/Spartan-IIE family takes care of this automatically with an on-chip pull-up/down resistor or keeper circuit. Spartan-II/ Spartan-IIE Master Serial 3.3V VCC 3.3V M0 M1 M2 3.3K 3.3K VCC DATA DIN CCLK CLK DONE CE INIT XC17S00A PROM OE/RESET Notes: 1. If the DriveDone configuration option is not active, pull up DONE with a 3.3k resistor. (Low Resets the Address Pointer) CCLK (Output) DIN DOUT (Output) DS078_01_110601 Figure 1: Master Serial Mode The one-time-programmable XC17S00A PROM in Figure 1 supports automatic loading of configuration programs. An DS078 (v1.5) November 15, 2001 Advance Product Specification early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active. www.xilinx.com 1-800-255-7778 3 R Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) Standby Mode The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance state regardless of the state of the OE input. VCC RESET/ OE or OE/ RESET Programming Spartan-II/Spartan-IIE Family PROMs The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. GND CE Address Counter CLK EPROM Cell Matrix TC Output OE DATA DS030_02_011300 Figure 2: Simplified Block Diagram (does not show programming circuit) Important:Always tie the two VCC pins together in your application. Table 2: Truth Table for XC17S00A Control Inputs Control Inputs Outputs RESET(1) CE Internal Address(2) DATA ICC Inactive Low If address < TC: increment If address > TC: don't change Active High-Z Active Reduced Active Low Held reset High-Z Active Inactive High Not changing High-Z Standby Active High Held reset High-Z Standby Notes: 1. The XC17S00A RESET input has programmable polarity 2. TC = Terminal Count = highest address value. TC + 1 = address 0. 4 www.xilinx.com 1-800-255-7778 DS078 (v1.5) November 15, 2001 Advance Product Specification R Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) XC17S15A, XC17S30A, XC17S50A, XC17S100A, XC17S150A, XC17S200A, and XC17S300A Absolute Maximum Ratings(1) Symbol Description Value Units -0.5 to +4.0 V VCC Supply voltage relative to GND VIN Input voltage with respect to GND -0.5 to VCC +0.5 V VTS Voltage applied to High-Z output -0.5 to VCC +0.5 V TSTG Storage temperature (ambient) TSOL Maximum soldering temperature (10s @ 1/16 in.) pC pC -65 to +150 +260 Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. Operating Conditions(1) Symbol Description VCC Commercial Industrial TVCC Min Max Units Supply voltage relative to GND (TA = 0pC to +70pC) 3.0 3.6 V Supply voltage relative to GND (TA = -40pC to +85pC) 3.0 3.6 V VCC rise time from 0V to nominal voltage 1.0 50 ms Notes: 1. During normal read operation, both VCC pins must be connected together. 2. At power-up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If the power supply cannot meet this requirement, then the device may not perform a power-on-reset properly. DC Characteristics Over Operating Condition Symbol Description Min Max Units VIH High-level input voltage 2.0 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = -3 mA) 2.4 - V VOL Low-level output voltage (IOL = +3 mA) - 0.4 V ICCA Supply current, active mode (at maximum frequency) - 15 mA ICCS Supply current, standby mode - 1 m" IL Input or output leakage current -10 10 NA Input Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF Output Capacitance (VIN = GND, f = 1.0 MHz) - 10 pF CIN COUT DS078 (v1.5) November 15, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) AC Characteristics Over Operating Condition(1) CE TSCE TSCE THCE RESET/OE THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS0306_03_011300 Symbol Description Min Max Units TOE RESET/OE to Data Delay - 45 ns TCE CE to Data Delay - 60 ns TCAC CLK to Data Delay - 80 ns TOH Data Hold From CE, RESET/OE, or CLK(2) 0 - ns TDF CE or RESET/OE to Data Float Delay(2,3) - 50 ns TCYC Clock Periods 100 - ns TLC CLK Low Time(2) 50 - ns THC CLK High Time(2) 50 - ns TSCE CE Setup Time to CLK (to guarantee proper counting) 25 - ns THCE CE Hold Time to CLK (to guarantee proper counting) 0 - ns THOE RESET/OE Hold Time (guarantees counters are reset) 25 - ns Notes: 1. AC test load = 50 pF 2. Guaranteed by design, not tested. 3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 6 www.xilinx.com 1-800-255-7778 DS078 (v1.5) November 15, 2001 Advance Product Specification R Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) Ordering Information XC17S15A VO8 C Operating Range/Processing Device Number XC17S15A XC17S30A XC17S50A XC17S100A XC17S150A XC17S200A XC17S300A C = Commercial (TA = 0pC to +70pC) I = Industrial (TA = -40pC to +85pC) Package Type PD8 VO8 SO20 VQ44 = = = = 8-pin Plastic DIP 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package 44-pin Plastic Quad Flat Package Spartan-II 3.3V Valid Ordering Combinations XC17S15APD8C XC17S50APD8C XC17S150APD8C XC17S15AVO8C XC17S50AVO8C XC17S150AVO8C XC17S15ASO20C XC17S50ASO20C XC17S150ASO20C XC17S15APD8I XC17S50APD8I XC17S150APD8I XC17S15AVO8I XC17S50AVO8I XC17S150AVO8I XC17S15ASO20I XC17S50ASO20I XC17S150ASO20I XC17S30APD8C XC17S100APD8C XC17S200APD8C XC17S30AVO8C XC17S100AVO8C XC17S200AVO8C XC17S30ASO20C XC17S100ASO20C XC17S200AVQ44C XC17S30APD8I XC17S100APD8I XC17S200APD8I XC17S30AVO8I XC17S100AVO8I XC17S200AVO8I XC17S30ASO20I XC17S100ASO20I XC17S200AVQ44I XC17S300AVQ44C XC17S300AVQ44I DS078 (v1.5) November 15, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 7 Spartan-II/Spartan-IIE Family of One-Time Programmable Configuration PROMs (XC17S00A) R Marking Information Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. 17S15A V The XC prefix is deleted and the package code is simplified. Device marking is as follows. C Operating Range/Processing Device Marking C = Commercial (TA = 0pC to +70pC) I = Industrial (TA = -40pC to +85pC) 17S15A 17S30A 17S50A 17S100A 17S150A 17S200A 17S300A Package Mark P V S VQ = = = = 8-pin Plastic DIP 8-pin Plastic Small-Outline Thin Package 20-pin Plastic Small-Outline Package 44-pin Plastic Quad Flat Package Revision History The following table shows the revision history for this document. 8 Date Revision Revision 09/14/00 1.0 Initial Xilinx release. 11/13/00 1.1 Updated configuration bits. 04/07/01 1.2 Added to features: "Guaranteed 20 year life data retention", removed "Programming the FPGA with counters" and related text. 06/20/01 1.3 Revised Figure 1 resistor values to match Spartan-II data sheet. 10/09/01 1.4 Added note for unlisted pins, changed ICCA and ICCS, and added power-on supply requirements and note regarding power-on reset. 11/15/01 1.5 Updated for Spartan-IIE FPGA family. www.xilinx.com 1-800-255-7778 DS078 (v1.5) November 15, 2001 Advance Product Specification