AP-252
CMOS EVOLVES
The original CMOS logic families were the 4000-series
and the 74C-series circuits. The 74C-series circuits are
functional equivalents to the corresponding numbered
74-series TTL circuits, but have CMOS logic levels and
retain the other well known characteristics of CMOS
logic.
These characteristics are: low power consumption, high
noise immunity, and slow speed. The low power con-
sumption is inherent to the nature of the CMOS circuit.
The noise immunity is due partly to the CMOS logic
levels, and partly to the slowness of the circuits. The
slow speed is due to the technology used to construct
the transistors in the circuit.
The technology used is called metal-gate CMOS, be-
cause the transistor gates are formed by metal deposi-
tion. More importantly, the gates are formed after the
drain and source regions have been defined, and must
overlap the source and drain somewhat to allow for
alignment tolerances. This overlap plus the relatively
large size of the transistors themselves result in high
electrode capacitance, and that is what limits the speed
of the circuit.
High speed CMOS became feasible with the develop-
ment of the self-aligning silicon gate technology. In this
process polysilicon gates are deposited before the
source and drain regions are defined. Then the source
and drain regions are formed by ion implantation using
the gate itself as a mask for the implantation. This elim-
inates most of the overlap capacitance. In addition, the
process allows smaller transistors. The result is a signif-
icant increase in circuit speed. The 74HC-series of
CMOS logic circuits is based on this technology, and
has speeds comparable to LS TTL, which is to say
about 10 times faster than the 74C-series circuits.
The size reduction that contributes to the higher speed
also demands an accompanying reduction in the maxi-
mum supply voltage. High-speed CMOS is generally
limited to 6V.
WHAT IS CHMOS?
CHMOS is the name given to Intel’s high-speed CMOS
processes. There are two CHMOS processes, one based
on an n-well structure and one based on a p-well struc-
ture. In the n-well structure, n-type wells are diffused
into a p-type substrate. Then the n-channel transistors
(nFETs) are built into the substrate and pFETs are
built into the n-wells. In the p-well structure, p-type
wells are diffused into an n-type substrate. Then the
nFETs are built into the wells and pFETs, into the
substrate. Both processes have their advantages and
disadvantages, which are largely transparent to the
user.
Lower operating voltages are easier to obtain with the
p-well structure than with the n-well structure. But the
p-well structure does not easily adapt to an EPROM
which would be pin-for-pin compatible with HMOS
EPROMs. On the other hand the n-well structure can
be based on the solidly founded HMOS process, in
which nFETs are built into a p-type substrate. This
allows somewhat more than half of the transistors in a
CHMOS chip to be constructed by processes that are
already well characterized.
Currently Intel’s CHMOS microcontrollers and memo-
ry products are n-well devices, whereas CHMOS mi-
croprocessors are p-well devices.
Further discussion of the CHMOS technology is pro-
vided in References 1 and 2 (which are reprinted in the
Microcontroller Handbook).
THE MCSÉ-51 FAMILY IN CHMOS
The 80C51BH is the CHMOS version of Intel’s original
8051. The 80C31BH is the ROMless 80C51BH, equiva-
lent to the 8031. These CHMOS devices are architec-
turally identical with their HMOS counterparts, except
that they have two added features for reduced power.
These are the Idle and Power Down modes of opera-
tion.
In most cases, an 80C51BH can directly replace the
8051 in existing applications. It can execute the same
code at the same speed, accept signals from the same
sources, and drive the same loads. However, the
80C51BH covers a wider range of speeds, will emit
CMOS logic levels to CMOS loads, and will draw about
1/10 the current of an 8051 (and less yet in the reduced
power modes). Interchangeability between the HMOS
and CHMOS devices is discussed in more detail in the
final section of this Application Note.
It should be noted that the 80C51BH CPU is not static.
That means if the clock frequency is too low, the CPU
might forget what it was doing. This is because the
circuitry uses a number of dynamic nodes. A dynamic
node is one that uses the note-to-ground capacitance to
form a temporary storage cell. Dynamic nodes are used
to reduce the transistor count, and hence the chip area,
thus to produce a more economical device.
This is not to say that the on-chip RAM in CHMOS
microcontrollers is dynamic. It’s not. It’s the CPU that
is dynamic, and that is what imposes the minimum
clock frequency specification.
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