BLM18HG102SN1D - MuRata Manufacturing Co., Ltd.

Altera Corporation 1

MAX 7000

Programmable Logic

Device Famil y

March 2001, ver. 6.1 Data Sheet

A-DS-M7000-06.1

Features... ■High-performance, EEPROM-based programmable logic devices

(PLDs) based on second-generation MAX® architecture

■5.0-V in-system programmability (ISP) through the built-in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in

MAX 7000S devices

–ISP circuitry compatible with IEEE Std. 1532

■Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S

devices

■Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S

devices with 128 or more macrocells

■Complete EPLD family with logic densities ranging from 600 to

5,000 usable gates (see Tables 1 and 2)

■5-ns pin-to-pin logic delays with up to 175.4-MHz counter

frequencies (including interconnect)

■PCI-compliant devices available

fFor inf ormation on in-system p ro gramma ble 3.3-V M AX 7000A or 2.5-V

MAX 70 00B devices , see the MAX 7000A Programmable Logic Device Family

Data Sheet or the MAX 7000B Programmable Logic Device Family Data

Sheet.

Table 1. MAX 7000 Device Features

Feature EPM7032 EPM7064 EPM7096 EPM7128E EPM7160E EPM7192E EPM7256E

Usable

gates 600 1,250 1,800 2,500 3,200 3,750 5,000

Macrocells 32 64 96 128 160 192 256

Logic array

blocks 2 4 6 8 10 12 16

Maximum

user I/O pins 36 68 76 100 104 124 164

tPD (ns) 6 6 7.5 7.5 10 12 12

tSU (ns)5566777

tFSU (ns) 2.5 2.5 3 3 3 3 3

tCO1 (ns) 4 4 4.5 4.5 5 6 6

fCNT (MHz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9

2Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

...and More

Features

■Open-drain output option in MAX 7000S devices

■Programmable macrocell flipflops with individual clear, preset,

clock, and clock enab le con tr o ls

■Programmable power-saving mode for a reduction of over 50% in

each macrocell

■Configurable expander product-term distribution, allowing up to

32 prod uc t te r m s per mac r o ce l l

■44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic

pin-grid arr ay (PGA), plastic quad flat pack (PQF P), power quad fla t

pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages

■Programmable security bit for protection of proprietary designs

■3.3-V or 5.0-V operation

–MultiVoltTM I/O interface operation, allowing devices to

interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is

not available in 44-pin packages)

–Pin compatible with low-voltage MAX 7000A and MAX 7000B

devices

■Enhanced features available in MAX 7000E and MAX 7000S devices

–Six pin- or logic-dr iv en outpu t enable signa ls

–Two global clock signals with optional inversion

–Enhanced interconnect resources for improved routability

–Fast input setup times provided by a dedicated path from I/O

pin to macrocell registers

–Programmable output slew-rate control

■Software design support and a utomatic place-and-route provided by

Altera’s development system for Windows-based PCs and Sun

SPARCs tation, and HP 9000 Series 700/800 works tations

Tab le 2. MAX 7000S D evice Features

Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S

Usable gates 600 1,250 2,500 3,200 3,750 5,000

Macrocells 32 64 128 160 192 256

Logic array

blocks 2 4 8 10 12 16

Maximum

user I/O pins 36 68 100 104 124 164

tPD (ns)55667.57.5

tSU (ns) 2.9 2.9 3.4 3.4 4.1 3.9

tFSU (ns) 2.5 2.5 2.5 2.5 3 3

tCO1 (ns) 3.2 3.2 4 3.9 4.7 4.7

fCNT (MHz) 175.4 175.4 147.1 149.3 125.0 128.2

Altera Corporation 3

MAX 7000 Programmable Logic Device Family Data Sheet

■Additional design entry and simulation support provided by

EDIF 2 0 0 and 3 0 0 netlist files, lib ra ry of para meterized

modules (LPM), Verilog HDL, VHDL, and other interfaces to

popular EDA tools from manufacturers such as Cadence,

Exemplar Logic, Mentor Gra phics, OrCA D, Synopsy s, and

VeriBest

■Programming support

–Altera’s Master Programming Unit (MPU) and

programming hardware from third - party manufacturers

program all MAX 7000 devices

–The BitBlasterTM serial download cable, ByteBlasterMVTM

parallel port download cable, and MasterBlasterTM

serial/universal serial bus (USB) download cable program

MAX 70 00 S devi ce s

General

Description

The MAX 7000 family of high-density, high-performance PLDs is

based on Altera’s second-generation MAX architecture. Fabricated

with advanced CMOS technology, the EEPROM-based MAX 7000

family p rovides 600 to 5,000 usable gates, ISP, pin-t o-pin d el ays as

fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S

devices in the -5, -6 , -7, a nd -10 speed gra des as well as MAX 7 000

and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades

comply with the PCI Special Interest Group (PCI SIG) PCI Local Bus

Specification, Revision 2.2. See Table 3 for available speed grades.

Table 3. MAX 7000 Speed Grades

Device Speed Grade

-5 -6 -7 -10P -10 -12P -12 -15 -15T -20

EPM7032 vv v vvv

EPM7032S vvv v

EPM7064 vvvvv

EPM7064S vvv v

EPM7096 vvvv

EPM7128E vvv vv v

EPM7128S vv v v

EPM7160E vv vv v

EPM7160S vv v v

EPM7192E vvv v

EPM7192S vv v

EPM7256E vvv v

EPM7256S vv v

4Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000E devices—including the EPM7128E, EPM7160E,

EPM7192E, and EPM7256E devices—have several enhanced

features: additional global clocking, additional output enable

controls, enhanced int erconnect resou rces, fast input register s, and a

pro gram m a ble slew rate.

In-system programmable MAX 7000 devices—called MAX 7000S

devices—incl ude the EPM7032S , EPM7064S , EPM7128S, EP M7160S,

EPM7 192S, and EPM7256S devices. MAX 7000S devices h ave the

enh anced features o f MAX 7000E devices as well as JTAG BST

circuitry in devices with 128 or more macrocells, ISP, and an open-

drain output option. See Table 4.

Notes:

(1) Available only in EPM7128S, EPM7160S, EPM7192S, and EPM7256S devices

only.

(2) The Mult iVolt I/O interface is not available in 44-pin pac k ag e s.

Table 4. MAX 7000 Device Features

Feature EPM7032

EPM7064

EPM7096

All

MAX 7000E

Devices

All

MAX 7000S

Devices

ISP via JTAG interface v

JTAG BS T circuitry v(1)

Open-drain output option v

Fast input registers vv

Six global output enables vv

Two global clocks vv

Slew-rate control vv

MultiVolt interface (2) vvv

Programmable register vvv

Parallel expanders vvv

Shared expanders vvv

Power-saving mode vvv

Security bit vvv

PCI-compliant devices available vvv

Altera Corporation 5

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000 architecture s u pports 100% TTL emulatio n and

high-density integration of SSI, MSI, and LSI logic functions. The

MAX 7000 architecture easily integrates multiple devices ranging

from PALs, GALs, and 22V10s to MACH and pLSI devices. MAX

7000 devices are available in a wide range of packages, including

PLCC, PGA, PQFP, RQFP, and TQFP packages. See Table 5.

Notes:

(1) When the JTAG interface in MAX 7000S devices is used for either boundary-scan testing or for ISP, four I/O pins

become JTAG pins.

(2) Perform a complete thermal analysis before committing a design to this device package. For more information, see

the Operating Requirements for Altera Devices Data Sheet.

MAX 7000 devices use CMOS EEPROM cells to implement logic

functions. The us er-conf igura ble MAX 7000 architecture

accommodates a variety of independent combinatorial and

sequential logic functions. The devices can be reprogrammed for

quick and effic ient iterations duri ng design developmen t and debug

cycles , and ca n be pro grammed and eras ed up to 1 00 times.

Table 5. MAX 7000 M aximum User I/O Pi ns Note (1)

Device 44-

PLCC

44-

PQFP

44-

TQFP

68-

PLCC

84-

PLCC

100-

PQFP

100-

TQFP

160-

PQFP

160-

PGA

192-

PGA

208-

PQFP

208-

RQFP

EPM7032 36 36 36

EPM7032S 36 36

EPM7064 36 36 52 68 68

EPM7064S 36 36 68 68

EPM7096 52 64 76

EPM7128E 68 84 100

EPM7128S 68 84 84 (2) 100

EPM7160E 64 84 104

EPM7160S 64 84 (2) 104

EPM7192E 124 124

EPM7192S 124

EPM7256E 132 (2) 164 164

EPM7256S 164 (2) 164

6Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

MAX 7000 devices contain from 32 to 256 macrocells that are combined

into groups of 16 macrocells, called logic array blocks (LABs). Each

macrocell has a programmable-AND/fixed-OR array and a configurable

preset func t ions . To bu il d c om plex logic functi ons, ea ch ma croc ell c a n b e

supplemented with both shareable expander product terms and high-

speed parallel expa nder product terms to provide up to 32 product terms

per macrocell.

The MAX 7000 family provides programmable speed/power

optimization. Speed-critical portions of a design can run at high

speed/full power, while the remaining portions run at reduced

speed/low power. This speed/po wer opti mizatio n f eature enables the

designer to configure one or more macrocells to operate at 50% or lower

power while addi ng only a nominal timing dela y. MA X 7000E and

MAX 7000S devices also provide an option that reduces the slew rate of

the output buffers, minimizin g noise transient s when non-s p eed-critica l

signals a re switching. Th e output dri vers of all MAX 7000 de vices (except

44-pin devices) ca n be set f or eith er 3.3-V or 5.0-V opera tion, al lowing

MAX 7000 devices to be used in mixed-voltage systems.

The MAX 700 0 family is supported byAltera development systems, which

are integrated packages that offer schematic, text—inc ludi ng VHDL ,

Verilog HDL, a nd the A ltera Ha rdwar e Desc ript ion Languag e (AHD L)—

and waveform design entry, compilation and logic synthesis, simulation

and timing ana ly sis, and device progra mmin g. The software prov ides

EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for

addition al desi gn entry an d sim ul ation su pport from other ind ustr y-

standard PC- and UNIX-workstation-based EDA tools. The software runs

on Windows-based PCs, as well as Sun SPARCstation, and HP 9000 Series

700/800 workstations.

fFor more information on development tools, see the MAX+PLUS II

Programmable Logic Development System & Software Data Sheet and the

Quartus Programmable Logic Development System & Software Data Sheet.

Functional

Description

The MAX 7000 architecture includes the following elements:

■Logic array blocks

■Macrocells

■Expander product terms (shareable and parallel)

■Programmable interconnect array

■I/O control blocks

Altera Corporation 7

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000 architecture includes four dedicated inputs that can

be used as general-purpose inputs or as high-speed, global control

signals (clock, c le ar, and two o u tput enable si gnals) for each

macrocell and I /O pin. Figure 1 shows the a rchitecture of EPM70 32,

EPM7 064, and EPM7096 devic es.

Figure 1. EPM7032, EPM7064 & EPM7096 D evice B lock Diag ram

I/O

Control

Block

8 to 16

I/O pins

8 to 16

36 I/O

Control

Block

8 to 16 8 to 16

I/O pins

8 to 16

8 to 16 8 to 16

I/O pins

8 to 16

I/O

Control

Block

I/O

Control

Block

8 to 16

I/O pins

8 to 16

LAB A LAB B

LAB C

Macrocells

33 to 48

LAB D

INPUT/GCLRn

INPUT/OE1

INPUT/OE2

Macrocells

17 to 32

Macrocells

49 to 64

PIA

INPUT/GLCK1

Macrocells

1 to 16

8Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 2 shows the architecture of MAX 7000E and MAX 7000S devices.

Figure 2. MAX 7000E & MAX 7000 S Devic e Block Di agram

Logic Array Blocks

The MAX 7000 device architecture is based on the linking of high-

performance, flexible, logic array modules called logic array blocks

(LABs). LA Bs consist of 16-ma crocell arr ays, as sho wn in Figures 1 and 2.

Multiple LABs are linked tog eth er via the progra mma bl e inter co nne ct

array (PI A), a globa l bus that is fed b y all dedi cate d inputs, I /O pins, and

macrocells.

INPUT/GCLRn

6 Output Enables 6 Output Enables

ontro

Bloc

LAB

ontro

Bloc

ontro

Bloc

ontro

Bloc

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

6 to 16 I/O Pins

to1

6 to1

acrocells

7 to

acrocells

Altera Corporation 9

MAX 7000 Programmable Logic Device Family Data Sheet

Each LAB is fed by the following signals:

■36 sign als from the PIA that ar e used for genera l logic inputs

■Global controls that are used for secondary register functions

■Direct input paths from I/O pins to the registers that are used

for fast s etup times for MAX 7000E and MAX 7 000S device s

Macrocells

The MAX 7000 macrocell can be individually configured for either

sequent ia l or combinat ori al logi c opera tio n. The macroc ell co nsis ts

of three functional blocks: the logic array, the product-term select

matrix, and the programmable register. The macrocell of EPM7032,

EPM7 064, and EPM7096 devic es is shown in Figure 3.

Figure 3. EPM7032, EPM7064 & EPM7096 Device Ma crocell

Product

Select

atri

36 Signals

rom PIA 16 Expander

Product

Logic Arra

arallel Lo

Expanders

(

from other

macrocells

)

Shared Lo

Expanders

Clear

Select

Global

Clear Global

Clocks

Clock/

Enable

Select

PRN

CLRN

D/T Q

ENA

Bypass To I/O

Control

Block

to PIA

Programmable

From

I/O pin

Fast Input

Select

VCC

10 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 4 shows a MAX 7000E and MAX 7000S device macrocell.

Figure 4. MAX 7000E & MAX 7000S Device Macrocell

Combinatorial logic is implemented in the logic array, which provides

five product terms per macrocell. The product-ter m select ma trix allocates

these product terms for use as either primary logic inputs (to the OR and

XOR gates) to impl em ent comb ina t oria l func ti ons, or as seconda ry i nputs

to the macrocell ’s register clear, preset, clock, and clock enable control

functions. Two kinds of expander product terms (“expanders”) are

available to supplement macrocell logic resources:

■Shareable expanders, which are inverted product terms that are fed

back into the logic array

■Parallel expanders, w hich are product terms borr owed from adjacent

macrocells

The Altera develo pment syste m automatically optimizes product-ter m

allocation according to the logic requirements of the design.

For registered functions, each macrocell flipflop can be individually

programmed to implement D, T, JK, or S R operation with progra mmable

clock control. The flipflop ca n be by pass ed for combi na torial operation.

During design entry, the designer specifies the desired flipflop type; the

Altera development software then selects the most efficient flipflop

operation for each registered function to optimize resource utilization.

Product-

Term

Select

Matrix

36 Signals

from PIA 16 Expander

Product Terms

Logic Array

Parallel Logic

Expanders

(from other

macrocells)

Shared Logic

Expanders

Clear

Select

Global

Clear Global

Clocks

Clock/

Enable

Select

PRN

CLRN

D/T Q

ENA

Bypass to I/O

Control

Block

to PIA

Programmable

from

I/O pin

Fast Input

Select

VCC

Altera Corporation 11

MAX 7000 Programmable Logic Device Family Data Sheet

Each programmabl e register can be clocked in three differen t modes:

■By a glo bal clock sign al. This mode a chieves the fastest clock -to-

output performance.

■By a glo bal clock signal and enabled by an a c tive-high clock

enable. This mode provides an enable on each flipflop while still

achieving t he fast clock-t o-outpu t perfor mance of the g lobal

clock.

■By an ar ra y cloc k im ple m ent ed wit h a pr od uc t te r m . In th is

mode, the flipflop can be clocked by signals from buried

macrocells or I/O pins.

In EPM7032, EPM7064, and EPM7096 devices, the global clock signal

is avai lable from a dedica ted clock pin, GCLK1, as shown in Figure 1.

In MA X 70 00 E and MA X 7000S dev ic e s, t wo globa l c loc k signal s ar e

available. As shown in Figure 2, these global clock signa ls can be the

true or the complement of either of the global clock pins, GCLK1 or

GCLK2.

Each re gister also supports a synchronous pre set and clear functio ns.

As shown in Figures 3 and 4, the product-term select matrix allocates

product terms to control these operations. Although the

product-term-driven preset and clear of the register are active high,

acti ve-low cont rol can be obtaine d by inver ting the signa l within t he

logic array. In addition, each register cl ear function can be

individually driven by the active-low dedicated global clear pin

(GCLRn). Upon pow er-u p, ea c h reg ister in the device will b e set to a

low state.

All MAX 7000E and MAX 7000S I/O pins have a fast input path to a

macrocell re gist er. This ded icated pat h allows a signal to bypass th e

PIA and combinatorial logic and be driven to an input D flipflop with

an extremely fast (2.5 ns) input setup time.

Expander Product Terms

Althou gh most logic fu nctions can be implemented with th e five

product terms available in each macrocell, the more complex logic

functions require additional product terms. Another macrocell can

be used to supply the required logic resources; however, the

MAX 7000 architec t ure also allo ws bot h sha rea bl e and par alle l

expander product terms (“expanders”) that provide additional

product terms directly to any macrocell in the same LAB. These

expanders help ensure that logic is synthesized with the fewest

possible logic resources to obtain the fastest possible speed.

12 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Shareable Expan ders

Each LAB has 16 shareable expanders that can be viewed as a pool of

uncommitted single product terms (one fro m each macroce ll) with

inverted outputs that feed back into the logic array. Each shareable

expander can be used and shared by any or all macrocells in the LAB to

build complex logic functions. A small delay (tSEXP) is incurred when

shareable expander s are used. Figure 5 shows how shareable expanders

can feed multiple macrocells.

Figur e 5. Shareable Expanders

Shareable exp anders can be sh ared by any or al l macrocel ls in an LAB.

Parallel Expanders

Parallel expanders are unused product terms that can be allocated to a

neighboring macrocell to implement fast, complex logic functions.

Parallel expanders allow up to 20 product terms to directly feed the

macrocell OR logic, with five product terms provided by the macrocell and

15 parallel expanders provided by neighboring macrocells in the LAB.

Macrocell

Product-Term

Logic

Product-Term Select Matrix

Macrocell

Product-Term

Logic

36 Signals

from PIA 16 Shared

Expanders

Altera Corporation 13

MAX 7000 Programmable Logic Device Family Data Sheet

The compile r can allocate up to three set s of up to five parallel expanders

automatically to the macrocells that require additional product terms.

Each set of five parallel expanders incurs a small, incremental timing

delay (tPEXP). For example, if a macrocell requires 14 product terms, the

Compiler uses th e five d edicated pr oduct term s with in th e macro cell and

allocates two sets of parallel expanders; the first set includes five product

terms and the second set includes four product terms, increasing the total

delay by 2 ×tPEXP.

Two groups of 8 macrocells within each LAB (e.g., macrocells

1 through 8 a nd 9 through 16) form two c hains to le nd or borrow paralle l

expanders. A macrocell borrows parallel expanders from lower-

numbered macrocells. For example, macrocell 8 can borrow parallel

expanders from macrocell 7, from macrocells 7 and 6, or from macrocells

7, 6, and 5. Within each group of 8, the lowest-numbered macrocell can

only lend parallel expanders and the highest-numbered macrocell can

only borrow them. Figure 6 shows how parallel expanders can be

borrowed from a neighboring macrocell.

Figure 6. Parallel Expanders

Unused product te rms in a mac rocell can be alloc at ed to a neighb ori n g macrocell.

Preset

Clock

Clear

Product-

Term

Select

Matrix

Preset

Clock

Clear

Product-

Term

Select

Matrix

Macrocell

Product-

Term Logic

From

Macrocell

To Next

Macrocell

Product-

Term Logic

36 Signals

from PIA 16 Shared

Expanders

14 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Programmable Interconnect Array

Logic is routed between LABs via the programmable interconnect array

(PIA). This global bu s is a programmable pat h that co nnects any signal

source to any destination on the device. All MAX 7000 dedicated inputs,

I/O pins, and macrocell outputs feed the PIA, which makes the signals

available t hroug hout t he e nt ire device. On ly the signals r equir ed by ea ch

LAB are actually routed from the PIA into the LAB. Figure 7 shows how

the PIA signals are routed into the LAB. An EEPROM cell controls one

input to a 2-input AND gate, which selects a PIA signal to drive into the

LAB.

Figure 7. PIA Routing

While the routin g delays of chann el-base d routing schem es in masked or

FPGAs are cumulative, variable, and path-depen dent, the MAX 7000 PIA

has a fixed delay. The PIA thus elim in at es skew betw een sign als and

makes timing performance easy to predict.

I/O Contr ol Blocks

The I/O control block allows each I/O pin to be individually configured

for input, output, or bidirectional operation. All I/O pins have a tri-state

buffer that is individually controlled by one of the global output enable

signals or directly connected to ground or VCC. Figure 8 shows the I/O

control block for the MAX 7000 family . The I/O control block of EPM7032,

EPM7064, and EPM7096 devices has two global output enable signals that

are driven by two dedicated active-low output enable pins (OE1 and OE2).

The I/O control block of MAX 7000E and MAX 7000S devices has six

globa l out put en able s ign als th at ar e dr iven b y the t rue or com pleme nt of

two output enable sign als, a subset of the I/O pins, or a subset of the I/O

macrocells.

To LAB

PIA Signals

Altera Corporation 15

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 8. I/O Control Block of MAX 7000 Devices

Note:

(1) The open-drain output option is available only in MAX 700 0S devices.

EPM7032, EPM7064 & EPM 7096 Devic es

MAX 7000E & MAX 7000S Devices

To PIA

GND

VCC

From Macrocell

OE1

OE2

From

Macrocell

Fast Input to

Macrocell

Slew-Rate Control

To PIA

To Other I/O Pins

Six Global Output Enable Signals

PIA

GND

VCC

Open-Drain Output

(1)

16 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

When the tri-state buffer control is connected to ground, the ou tput is

tri-stated (high impedance) and the I/O pin can be used as a dedicated

input. When th e t ri-s tate bu ffer c ont rol is c on nec te d to VCC, the outpu t is

enabled.

The MAX 7000 architecture provides dual I/O feedback, in which

macrocell and pin feedbacks are independent. When an I/O pin is

configured as an input , t he associated macrocell can be used for buried

logic.

In-System

Programma-

bility (ISP)

MAX 7000S devices are in- system programm able via a n

industry-standard 4-pin Joint Test Action Group (JTAG) interface (IEEE

Std. 1149.1-1990). ISP allows quick, efficient iterations during design

development and debugging cycles. The MAX 7000S architecture

internally generates the high programming voltage required to program

EEPROM cell s, allowing in-s ystem progr amming with onl y a single 5.0 V

power supply. During in-system programming, the I/O pins are tri-stated

and pulled-up to eliminate board conflicts. The pull-up value is nominally

50 k¾.

ISP simplifies the manufacturing flow by allowing devices to be mounted

on a printed circuit board with standard in-circuit test equipment before

they are programmed. MAX 7000S devices can be programmed by

downloading the information via in-circuit testers (ICT), embedded

processors, or the Altera MasterBlaster, ByteBlasterMV, ByteBlaster,

BitBlaster download cables. (The ByteBlaster cable is obsolete and is

replaced by the ByteBlasterMV cable, which can program and configure

2.5-V, 3.3-V, and 5.0-V de vices.) Pr ogrammin g the devi ces after the y are

placed on the board elimina tes lead damag e on high-pin -count packages

(e.g., QFP packages) due to device handling and allows devices to be

reprogrammed after a system has already shipped to the field. For

example, product upgrade s can be perfor med in t he fiel d via soft wa re or

modem.

In-system programming ca n be accompl ished with either an adaptive or

constant algorithm. An adaptive algorithm reads information from the

unit and adapts subsequent programming steps to achieve the fastest

possible programming time for that unit. Because some in-circuit testers

cannot support an adaptive algorithm, Altera offers devices tested with a

constant algorithm. Devices tested to the constant algorithm are marked

with an “F” suffix in the ordering code.

The JamTM Standard Test and Programming Language (STAPL) can be

used to program MAX 7000S devices with in-circuit testers, PCs, or

embedded processor.

Altera Corporation 17

MAX 7000 Programmable Logic Device Family Data Sheet

fFor more information on using the Jam language, see Application Note 88

(Using the Jam Language for ISP & ICR via an Embedded Processor).

The ISP cir cuitry in MAX 7000S devices is compa tible with IEE E Std. 1532

specification. The IEEE Std. 1532 is a standard developed to allow

concurrent ISP between multiple PLD vendors.

Programma ble

Speed/Pow er

Control

MAX 7000 devices offer a power-saving mode that supports low-power

operation across user-defined signal paths or the entire device. This

feature allows total power dissipation to be reduced by 50% or more,

because most logic applic ations requir e only a small fraction o f all gates to

operate at maximum frequency.

The designer can program each individual macrocell in a MAX 7000

device for either high-speed (i.e., with the Turbo BitTM option turned on)

or low-power (i.e., with the Turbo Bit option turned off) operation. As a

result, speed-critical paths in the design can run at high speed, while the

remaining paths can operate at reduced power. Macrocells that run at low

power incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC,

tEN, and tSEXP, tACL, and tCPPW paramet e rs.

Output

Configuration

MAX 7000 device outputs can be programmed to meet a variety of

system-level requirements.

MultiVolt I /O Int erface

MAX 7000 devices—except 44-pin devices—support the MultiVolt I/O

interface feature, which allows MAX 7000 devices to interface with

systems that have differing supply voltages. The 5.0-V devices in all

packages can be set for 3.3-V or 5.0-V I/O pin operation. These devices

have one set of VCC pins for internal operation and input buffers

(VCCINT), and another set for I/O output drivers (VCCIO).

The VCCINT pins must always be connected to a 5.0-V power supply.

With a 5.0-V VCCINT level, input voltage thr esholds are at TTL lev els, and

are th er efore comp atible with both 3.3-V and 5.0-V inputs.

The VCCIO pins can be connected to either a 3.3-V or a 5.0-V power

supply, depending on the output requirements. When the VCCIO pi ns a re

connected to a 5.0-V supply, the output levels are compatible with 5.0-V

systems. When VCCIO is connected to a 3.3-V supply, the output high is

3.3 V and is therefore compatible wi th 3.3-V or 5.0-V s ystems. Devices

operating with VCCIO levels lower than 4.75 V incur a nominally greater

timin g delay of tOD2 instead of tOD1.

18 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Open-Drain Output Option (MAX 7000S Devices Only)

MAX 7000S devices provide an optional open-drain (functionally

equivalent to open-collector) output for each I/O pin. This open-drain

output enables the device to provide system-level co nt rol sign als (e.g.,

inte rrupt and write enabl e s ignals) that can be ass erted b y any of several

devices. It can also provide an additional wired-OR plane.

Output pins on 5.0-V MAX 7000S devices with VCCIO = 3.3 V or 5.0 V (with

a pull-up resi stor to the 5.0-V supply) can also drive 5.0-V CMOS input

pins. In this cas e, the pull -up tr ansist or will turn off w hen the pin volta ge

exceeds 3.3 V. Therefore, the pin does not have to be open-drain.

Slew-Rate Control

The output buffer for each MAX 7000E and MAX 7000S I/O pin has an

adju stabl e o utput s lew rate that ca n be configured for low-no ise or high-

speed performan ce. A faster slew rate prov ides high-speed transitions for

high-performance systems. However, these fast transitions may introduce

noise transients into the system. A slow slew rate reduces system noise,

but adds a nominal delay of 4 to 5 ns. In M AX 7000E device s, when the

Turbo Bit is turn ed off, the slew rate is set for low noise perform ance. For

MAX 7000S devices, each I/O pin has an individual EEPROM bit that

controls the slew rate, allowing designers to specify the slew rate on a

pin-by-pin basis.

Programming

with External

Hardware

MAX 7000 devices can be programmed on Windows-based PCs with the

Altera Logic Programmer card, the Master Prog ramming Unit (MPU),

and the appropriate device adapter. The MPU performs a continuity

check to ensure adequate electrical contact between the adapter and the

device.

fFor more information, see the Altera Programming Hardware Data Sheet.

The Altera development system can use text- or waveform-format test

vectors created with the Text Editor or Waveform Editor to test the

programmed device. For added design verification, designers can

perform functional testing to compare the functional behavior of a

MAX 7000 device with the results of simulation . Moreov er, Da ta I/O, BP

Microsystems, and other programming hardware manufacturers also

provide programming support for Altera devices.

fFor more information, see the Programming Hardware Manufacturers.

Altera Corporation 19

MAX 7000 Programmable Logic Device Family Data Sheet

IEEE Std.

1149.1 (JTAG)

Boundary-Scan

Support

MAX 7000 devices support JTAG BST circuitry as specified by IEEE Std.

1149.1-1990. Table 6 describes the JTAG instructions supported by the

MAX 7000 family. The pin-out tables (see the Altera web site

(http://www.altera.com) or the Altera Digital Library for pin-out

information) show the location of the JTAG control pins for each device.

If the JTAG interface is not required, the JTAG pins are available as user

I/O pins.

Table 6. MAX 7000 JT AG Instructions

JTAG Instructio n Devices Description

SAMPLE/PRELOAD EPM7128S

EPM7160S

EPM7192S

EPM7256S

Allows a snapshot of signals at the device pins to be captured and

examined during normal device operation, and permits an initial data

pattern output at the device pins.

EXTEST EPM7128S

EPM7160S

EPM7192S

EPM7256S

Allows the external circuitry and board-level interconnections to be

tested by forcing a test pattern at the output pins and capturing test

results at the input pins.

BYPASS EPM7032S

EPM7064S

EPM7128S

EPM7160S

EPM7192S

EPM7256S

Places the 1-bit bypass register between the TDI and TDO pins, which

allows the BST data to pass synchronously through a selected device

to adjacent devices during normal device operation.

IDCODE EPM7032S

EPM7064S

EPM7128S

EPM7160S

EPM7192S

EPM7256S

Selects the IDCODE register and places it between TDI and TDO,

allowing the IDCODE to be serially shifted out of TDO.

ISP Instructions EPM7032S

EPM7064S

EPM7128S

EPM7160S

EPM7192S

EPM7256S

These instructions are used when programming MAX 7000S devices

via the JTAG ports with the MasterBlaster, ByteBlasterMV, BitBlaster

download cable, or using a Jam File (.jam), Jam Byte-Code file (.jbc),

or Serial Vector Format file (.svf) via an embedded processor or test

equipment.

20 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

The instruction register length of MAX 7000S devices is 10 bits. Tables 7

and 8 show the boundary-scan register length and device IDCODE

information for MA X 7000S de vices.

Note:

(1) This device does not support JTAG boundary-scan testing. Selecting either the

EXTEST or SAMPLE/PRELOAD instruction will select the one-bit bypass register.

Notes:

(1) The most signif ic ant bit (MSB) is on the left.

(2) The least significant bit (LSB) for all JTAG IDCODEs is 1.

Table 7. MAX 7000S Bo undary-Scan R egister Length

Device Boundary-Scan Register Length

EPM7032S 1 (1)

EPM7064S 1 (1)

EPM7128S 288

EPM7160S 312

EPM7192S 360

EPM7256S 480

Table 8. 32-Bit MAX 7000 Device IDCODE Note (1)

Device IDCODE (32 B its)

Version

(4 Bits) Part Nu mb er (16 Bi ts) Manufacturer ’s

Identity (11 Bits) 1 (1 Bit)

(2)

EPM7032S 0000 0111 0000 0011 0010 00001101110 1

EPM7064S 0000 0111 0000 0110 0100 00001101110 1

EPM7128S 0000 0111 0001 0010 1000 00001101110 1

EPM7160S 0000 0111 0001 0110 0000 00001101110 1

EPM7192S 0000 0111 0001 1001 0010 00001101110 1

EPM7256S 0000 0111 0010 0101 0110 00001101110 1

Altera Corporation 21

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 9 shows the timing requirements for the JTAG signals.

Figur e 9. MAX 7000 JTAG Wavefo rms

Table 9 shows the JTAG timing parameters and values for

MAX 7 000S devi ce s.

tJPZX tJPCO

tJPH

tJPXZ

tJCP tJPSU

tJCL

tJCH

TDI

nal

red

nal

ven

tJSZX

tJSSU tJSH

tJSCO tJSXZ

Table 9. JTAG Timing Parameters & Values for MAX 7000S Devices

Symbol Parameter Min Max Unit

tJCP TCK clock period 100 ns

tJCH TCK clock high time 50 ns

tJCL TCK clock low time 50 ns

tJPSU JTAG port setup time 20 ns

tJPH JTAG port hold time 45 ns

tJPCO JTAG port clock to output 25 ns

tJPZX JTAG port high impedance to valid output 25 ns

tJPXZ JTAG port valid output to high impedance 25 ns

tJSSU Capture register setup time 20 ns

tJSH Capture register hold time 45 ns

tJSCO Update register clock to output 25 ns

tJSZX Update register high impedance to valid output 25 ns

tJSXZ Update register valid output to high impedance 25 ns

22 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

fFor more information, see Appl ica tio n Note 39 (IEEE 1149 .1 (JTAG)

Boundary-Scan Testing in Altera Devices).

Design Security All MAX 7000 devices contain a programmable security bit that controls

access to the data progr ammed into the de vice. Whe n this bi t is

programmed, a proprietary design implemented in the device cannot be

copied or retrieved. This feature provides a high level of design security

because pro grammed data wit hin EEPROM cells is invi sible. The security

bit that controls this function, as well as all other programmed data, is

reset only when the device i s reprogrammed.

Generic Testing Each MAX 7000 device is functionally tested. Complete testing of each

programm able EEPROM bit and all inter nal logic elemen ts ensures 100%

programming yield. AC test meas urements are taken unde r conditions

equivalent to those shown in Figure 10. Test patterns can be used and then

erased during early stages of the production flow.

Figur e 10. MAX 7000 AC Test Conditions

QFP Carrier &

Development

Socket

MAX 7000 and MAX 7000E devices in QFP packages with 100 or more

pins are shipped in special plastic carriers to protect the QFP leads. The

carrier is used with a prototype development socket and special

programming hardware available from Altera. This carrier technology

makes it poss ible to progra m, test, era se, and reprogra m a device w ithout

exposing the leads to mechanical stress.

fFor detailed information and carrier dimensions, refer to the QFP Carrier

& Development Socket Data Sheet.

1MAX 70 00S devices are not shipp ed in carrier s.

VCC

To Test

System

C1 (includes JIG

capacitance)

Device input

rise and fall

times < 3 ns

Device

Output

464 Ω

[703 Ω]

250

[8.06 ]

Ω

KΩ

Pow er supp l y transients can affe ct AC

meas ure ments. Sim ul ta neous

transitions of multiple outputs should be

avoided for accurate measurement.

Threshold test s m u s t not be per fo r m ed

under AC conditions. Large-amplitude,

fast ground-current transient s normally

occur as the devic e out puts disc harge

the load capacitances. When these

transients flow through the parasitic

inductance be tween th e de vi ce ground

pin and the test syste m ground,

significant reductions in observable

noise immunity can result. Numbers in

brackets are for 2.5-V devices and

outputs. Number s without brackets are

for 3.3-V devi ces and out puts.

Altera Corporation  23
MAX 7000 Programmable Logic Device Family Data Sheet
Operating 
Conditions
Tables 10 th rou gh 15 provide information about absolute maximum 
ratings, recommended operating conditions, operating conditions, and 
capacitance for 5.0-V MAX 7000 devices.
Table 10. MAX 7000 5.0-V Device Absolute Maximum Ratings Not e (1)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to ground (2) –2.0 7.0 V
VIDC input voltage –2.0 7.0 V
IOUT DC output current, per pin –25 25 mA
TSTG Storage temperature No bias –65 150 ° C
TAMB Ambient temperature Under bias –65 135 ° C
TJJunction temperature Ceramic packages, under bias 150 ° C
PQFP and RQFP packages, under bias 135 ° C
Table 11. MAX 7000 5. 0-V Device R ecommended Oper ating Condit ions
Symbol Parameter Conditions Min Max Unit
VCCINT Supply voltage for internal logic and 
input buffers (3), (4) 4.75 
(4.50) 5.25 
(5.50) V
VCCIO Supply voltage for out put  driv ers,  
5.0-V operation (3), (4) 4.75 
(4.50) 5.25 
(5.50) V
Supply vol ta ge for out put  driv ers,  
3.3-V operation (3), (4), (5) 3.00
(3.00) 3.60
(3.60) V
VCCISP Supply voltage duri ng ISP (6) 4.75 5.25 V
VIInput voltage –0.5 (7) VCCINT + 0.5 V
VOOutput voltage 0V
CCIO V
TAAmbient temperature For commercial use 0 70 ° C
For industri a l use –40 85 ° C
TJJunction temperature For commercial use 0 90 ° C
For industri a l use –40 105 ° C
tRInput rise time 40 ns
tFInput fall time 40 ns

24 Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Table 12. MAX 7000 5.0-V Device DC Operating Conditions Note (8)
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage 2.0 VCCINT + 0.5 V
VIL Low-level input voltage –0.5 (7) 0.8 V
VOH 5.0-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 4.75 V (9) 2.4 V
3.3-V high-level TTL output voltage IOH = –4 mA DC, VCCIO = 3.00 V (9) 2.4 V
3.3-V high-level CMOS output 
voltage IOH = –0.1 mA DC, VCCIO = 3.0 V (9) VCCIO – 0.2 V
VOL 5.0-V low-level TTL output voltage I OL = 12 mA DC, VCCIO = 4.75 V (10) 0.45 V
3.3-V low-level TTL output voltage I OL = 12 mA DC, VCCIO = 3.00 V (10) 0.45 V
3.3-V low-level CMOS output 
voltage IOL = 0.1 mA DC, VCCIO = 3.0 V(10) 0.2 V
IILeakage current of dedicated input 
pins VI = VCC or ground (10) –10 10 µA
IOZ I/O pin tri-state output off-state 
current VO = VCC or ground (10), (11) –40 40 µA
Table 13. MAX 7000 5.0-V Device Capacitance: EPM7032, EPM7064 & EPM7096 Devices Note (12)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 12 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 12 pF
Table 14. MAX 7000 5.0-V Device Capacitance: MAX 7000E Devices Note (12)
Symbol Parameter Conditions Min Max Unit
CIN Input pin capacitance VIN = 0 V, f = 1.0 MHz 15 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 15 pF
Table 15. MAX 7000 5.0-V Device Capacitance: MAX 7000S Devices Note (12)
Symbol Parameter Conditions Min Max Unit
CIN Dedicated input pin capacitance VIN = 0 V, f = 1.0 MHz 10 pF
CI/O I/O pin capacitance VOUT = 0 V, f = 1.0 MHz 10 pF

Altera Corporation 25

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) See the Opera t in g Requirem en t s fo r Alt era Device s Da t a S heet.

(2) Minimu m DC input voltage on I/ O pins is –0.5 V and on 4 dedicated input pins is –0.3 V. During tr ans itions, the

inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than

20 ns.

(3) Number s in paren t hes e s a re for ind us tri a l -t emperature-range de vices.

(4) VCC must rise monotonically.

(5) 3.3-V I/O operation is not available fo r 44-p in pac k ag es.

(6) The VCCISP parameter applies only to MAX 7000S devices.

(7) During in-system programming, the minimum DC input voltage is –0.3 V.

(8) These values are specified under the MAX 7000 recommended operating condition s in Table 11 on page 23.

(9) The parameter is measured with 50% of the outputs each sourcing the specified current. The IOH paramete r refers

to high-level TTL or CMOS output current.

(10) The parameter is measured with 5 0% of the outputs each sinking the specifi ed current. The IOL parameter refers to

low-le vel TTL, PC I, or CMOS output current.

(11) When the JTAG interface is enabled in MAX 7000S de vice s, the i npu t leakage current on the JTAG pins i s t ypically

–60 µA.

(12) Capacitan ce is meas ured at 25° C and is sample - teste d only . The OE1 pin has a maximum capacitance of 20 pF.

Figure 11 shows the typical output drive characteristics of MAX 7000

devices.

Figure 11. Output Drive Characteristics of 5.0-V MAX 700 0 Devices

Timing Model MAX 7000 device timing can be analyzed with the Altera software, with a

variety of popular industry-standard EDA simulators and timing

analy zers, or with the timing model shown in Figure 12. MAX 7000

devices have fixed internal delays that enable the designer to determine

the wor st-case timin g of a ny desi gn. Th e Altera softw are pro vides tim ing

simulation, point-to-point delay prediction, and detailed timing analysis

for a device-wide performance evaluation.

VO Output Voltage (V)

12345

150

120

VCCIO = 3.3 V

IOL

IOH

Room Temperature

3.3

VO Output Voltage (V)

12345

150

120

VCCIO = 5.0 V

IOL

IOH

Room Temperature

Typical

Output

Current (mA)

Typical

Output

Current (mA)

26 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 12. M AX 7000 Timing Model

Notes:

(1) Only availa ble in M A X 7000 E and M AX 7000 S device s .

(2) Not available in 44-pin de vic es.

The timi ng character is t ics of any si gnal path can be d erived from the

timing model and parameters of a particular device. External timing

parameters, which represent pin-to-pin timing delays, can be calculated

as the sum of internal parameters. Figure 13 shows the internal timing

relations hip of internal and external delay para meter s.

fFor more infomration, see Application Note 94 (Understanding MAX 7000

Timing).

Logic Array

Delay

LAD

Output

Delay

OD3

OD2

OD1

ZX2

ZX3

Input

Delay

PRE

CLR

COMB

FSU

PIA

Delay

PIA

Shared

Expander Delay

SEXP

Control Delay

LAC

I/O

Delay

Global Control

Delay

GLOB

Internal Output

Enable Delay

IOE

Parallel

Expander Delay

PEXP

Fast

Input Delay

FIN

(1)

(2)

(1)

(2)

Altera Corporation 27

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 13. Switching Waveforms

Combinatorial Mode

Input Pin

I/O Pin

PIA Delay

Shared Expander

Delay

Logic Array

Input

Parallel Expander

Delay

Logic Array

Output

Output Pin

LAC

, t

LAD

PIA

PEXP

SEXP

COMB

Global Clock Mode

Global

Clock Pin

Global Clock

at Register

Data or Enable

(Logic Array Output)

GLOB

Array Clock Mode

Input or I/O Pin

Clock into PIA

Clock into

Logic Array

Clock at

Data from

Logic Array

to Logic Array

to Pin

ACH

ACL

PIA

CLR

, t

PRE

PIA

tR & tF < 3 ns.

Inputs are driven at 3 V

for a logic hi gh and 0 V

for a logic low. All timing

characteristics are

measured at 1.5 V.

28 Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Tables  thro u gh 23 show the MAX 7000 and MAX 7000E AC operating 
conditions. 
Table 16. MAX 7000 & MAX 7000E External Timing Parameters
Symbol Parameter Conditions -6 Speed Grade -7 Speed Grade Unit
Min Max Min Max
tPD1 Input to non-registere d output C1  = 35 pF 6.0 7.5 ns
tPD2 I/O input to non-registered output C1 = 35 pF 6.0 7.5 ns
tSU Global clock setup time 5.0 6.0 ns
tHGlobal clock hold time 0.0 0.0 ns
tFSU Global clock setup time of fast input (1) 2.5 3.0 ns
tFH Global clock hold time of fast input (1) 0.5 0.5 ns
tCO1 Glob al clock t o  outp ut delay C1 = 35 pF 4.0 4.5 ns
tCH Global clock high time 2.5 3.0 ns
tCL Global clock low time 2.5 3.0 ns
tASU Array clock setup time 2.5 3.0 ns
tAH Array clock hold time 2.0 2.0 ns
tACO1 Array clock to output delay C1 = 35 pF 6.5 7.5 ns
tACH Array clock high time 3.0 3.0 ns
tACL Array clock low time 3.0 3.0 ns
tCPPW Minimum pulse width for clear and 
preset (2) 3.0 3.0 ns
tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 ns
tCNT Minimum global clock period 6.6 8.0 ns
fCNT Maximum internal global clock 
frequency (4) 151.5 125.0 MHz
tACNT Minimum array clock period 6.6 8.0 ns
fACNT Maximum internal array clock 
frequency (4) 151.5 125.0 MHz
fMAX Maximum clock frequency (5) 200 166.7 MHz

Altera Corporation  29
MAX 7000 Programmable Logic Device Family Data Sheet
Table 17. MAX 7000 & MAX 7000 E Intern al Timing Parameters
Symbol Parameter Conditions Speed Grade -6 Speed Grade -7 Unit
Min Max Min Max
tIN Input pad and buffer delay 0.4 0.5 ns
tIO I/O input pad and buffer delay 0.4 0.5 ns
tFIN Fast input delay (1) 0.8 1.0 ns
tSEXP Shared expa nd er delay 3.5 4.0 ns
tPEXP Parallel expander delay 0.8 0.8 ns
tLAD Logic array delay 2.0 3.0 ns
tLAC Logic control array delay 2.0 3.0 ns
tIOE Internal output enable delay (1) 2.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF  2.0 2.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (6) 2.5 2.5 ns
tOD3 Output buffer and pad delay
Sl ow slew rate = on, 
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 7.0 7.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off, VCCIO = 5.0 V C1 = 35 pF  4.0 4.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off, VCCIO = 3.3 V C1 = 35 pF (6) 4.5 4.5 ns
tZX3 Output buffer enable delay
Sl ow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 ns
tSU Register setu p time 3.0 3.0 ns
tHRegister hold time 1.5 2.0 ns
tFSU Register setup time of fast input (1) 2.5 3.0 ns
tFH Register hold time of fast input (1) 0.5 0.5 ns
tRD Register delay 0.8 1.0 ns
tCOMB Combinatorial delay 0.8 1.0 ns
tIC Array clock delay 2.5 3.0 ns
tEN Register ena bl e time 2. 0 3.0 ns
tGLOB Global control delay 0.8 1.0 ns
tPRE Register pre set time 2.0 2.0 ns
tCLR Regist er clear  time 2.0 2.0 ns
tPIA PIA delay 0.8 1.0 ns
tLPA Low- po wer add er (7) 10.0 10.0 ns

30 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Table 18. MAX 7000 & MAX 7000E External Timing Parameters

Symbol Parameter Conditions Speed Grade Unit

MAX 7000E (-10P) MAX 7000 (-10)

MAX 7000E (-10)

Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 10.0 10.0 ns

tPD2 I/O input to non-registered output C1 = 35 pF 10.0 10.0 ns

tSU Global clock setup time 7.0 8.0 ns

tHGlobal clock hold time 0.0 0.0 ns

tFSU Global clock setup time of fast input (1) 3.0 3.0 ns

tFH Global clock hold time of fast input (1) 0.5 0.5 ns

tCO1 Glob al clock to outpu t delay C1 = 35 pF 5.0 5 ns

tCH Global clock high time 4.0 4.0 ns

tCL Global clock low time 4.0 4.0 ns

tASU Array clock setup time 2.0 3.0 ns

tAH Array clock hold time 3.0 3.0 ns

tACO1 Array clock to output delay C1 = 35 pF 10.0 10.0 ns

tACH Array clock high time 4.0 4.0 ns

tACL Array clock low time 4.0 4.0 ns

tCPPW Minimum pulse width for clear and

preset (2) 4.0 4.0 ns

tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 ns

tCNT Minimum global clock period 10.0 10.0 ns

fCNT Maximum internal global clock

frequency (4) 100.0 100.0 MHz

tACNT Minimum array clock period 10.0 10.0 ns

fACNT Maxim um interna l array clock

frequency (4) 100.0 100.0 MHz

fMAX Maxim um clock freque ncy (5) 125.0 125.0 MHz

Altera Corporation  31
MAX 7000 Programmable Logic Device Family Data Sheet
Table 19. MAX 7000 & MAX 7000 E Intern al Timing Parameters
Symbol Parameter Conditions Speed Grade Unit
MAX  7000E ( -10P) MA X 7000  (-10)
MAX 7000E (-10)
Min Max Min Max
tIN Input pad and buffer delay 0.5 1.0 ns
tIO I/O input pad and buffer delay 0.5 1.0 ns
tFIN Fast input de lay (1) 1.0 1.0 ns
tSEXP Shared expander delay 5.0 5.0 ns
tPEXP Parallel expander delay 0.8 0.8 ns
tLAD Logic array delay 5.0 5.0 ns
tLAC Logic control array delay 5.0 5.0 ns
tIOE Internal output enable delay (1) 2.0 2.0 ns
tOD1 Output buffer and  pad delay
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 1.5 2.0 ns
tOD2 Output buffer and  pad delay
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 2.0 2.5 ns
tOD3 Output buffer and  pad delay
Sl ow slew rate = on 
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 5.5 6.0 ns
tZX1 Output buff er ena ble del a y
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 5.0 5.0 ns
tZX2 Output buff er ena ble del a y
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 5.5 5.5 ns
tZX3 Output buff er ena ble del a y
Sl ow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 9.0 9.0 ns
tXZ Output buffer disable delay C1 = 5 pF 5.0 5.0 ns
tSU Register setu p time 2.0 3.0 ns
tHRegister hold time 3. 0 3.0 ns
tFSU Register setup time of fast input (1) 3.0 3.0 ns
tFH Register hold time of fast input (1) 0.5 0.5 ns
tRD Register delay 2.0 1.0 ns
tCOMB Combinatorial delay 2.0 1.0 ns
tIC Array clock delay 5.0 5.0 ns
tEN Register ena bl e time 5.0 5.0 ns
tGLOB Global control delay 1.0 1.0 ns
tPRE Register pre set time 3.0 3.0 ns
tCLR Regist er clear  time 3.0 3.0 ns
tPIA PIA delay 1.0 1.0 ns
tLPA Low- pow er add er (7) 11.0 11.0 ns

32 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Table 20. MAX 7000 & MAX 7000E External Timing Parameters

Symbol Parameter Conditions Speed Grade Unit

MAX 7000E (-12P) MAX 7000 (-12)

MAX 7000E (-12)

Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 12.0 12.0 ns

tPD2 I/O input to non-registered output C1 = 35 pF 12.0 12.0 ns

tSU Global clock setup time 7.0 10.0 ns

tHGlobal clock hold time 0.0 0.0 ns

tFSU Global clock setup time of fast input (1) 3.0 3.0 ns

tFH Global clock hold time of fast input (1) 0.0 0.0 ns

tCO1 Glob al clock to output delay C1 = 35 pF 6.0 6.0 ns

tCH Global clock high time 4.0 4.0 ns

tCL Global clock low time 4.0 4.0 ns

tASU Array clock setup time 3.0 4.0 ns

tAH Array clock hold time 4.0 4.0 ns

tACO1 Array clock to output delay C1 = 35 pF 12.0 12.0 ns

tACH Array clock high time 5.0 5.0 ns

tACL Array clock low time 5.0 5.0 ns

tCPPW Minimum pulse width for clear and

preset (2) 5.0 5.0 ns

tODH Output data hold time after clock C1 = 35 pF (3) 1.0 1.0 ns

tCNT Minimum global clock period 11.0 11.0 ns

fCNT Maximum internal global clock

frequency (4) 90.9 90.9 MHz

tACNT Minimum array clock period 11.0 11.0 ns

fACNT Maxim um interna l array clock

frequency (4) 90.9 90.9 MHz

fMAX Maxim um clock freque ncy (5) 125.0 125.0 MHz

Altera Corporation  33
MAX 7000 Programmable Logic Device Family Data Sheet
Table 21. MAX 7000 & MAX 7000 E Intern al Timing Parameters
Symbol Parameter Conditions Speed Grade Unit
MAX 7000E (-12P) MAX 7000 (-12)
MAX 7000E (-12)
MinMaxMinMax
tIN Input pad and buffer delay 1.0 2.0 ns
tIO I/O input pad and buffer delay 1.0 2.0 ns
tFIN Fast input de lay (1) 1.0 1.0 ns
tSEXP Shared expander delay 7.0 7.0 ns
tPEXP Parallel expander delay 1.0 1.0 ns
tLAD Logic array delay 7.0 5.0 ns
tLAC Logic control array delay 5.0 5.0 ns
tIOE Internal output enable delay (1) 2.0 2.0 ns
tOD1 Output buffer and  pad delay
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 1. 0 3.0 ns
tOD2 Output buffer and  pad delay
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 2.0 4.0 ns
tOD3 Output buffer and  pad delay
Sl ow slew rate = on 
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 5.0 7.0 ns
tZX1 Output buff er ena ble del a y
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 6. 0 6.0 ns
tZX2 Output buff er ena ble del a y
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 7.0 7.0 ns
tZX3 Output buff er ena ble del a y
Sl ow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 10.0 10.0 ns
tXZ Output buffer disable delay C1 = 5 pF 6.0 6.0 ns
tSU Register setu p time 1.0 4.0 ns
tHRegister hol d  time 6.0 4.0 ns
tFSU Register setup time of fast input (1) 4.0 2.0 ns
tFH Register hold time of fast input (1) 0.0 2.0 ns
tRD Register delay 2.0 1.0 ns
tCOMB Combinatorial delay 2.0 1.0 ns
tIC Array clock delay 5.0 5.0 ns
tEN Register ena bl e time 7.0 5.0 ns
tGLOB Global control delay 2.0 0.0 ns
tPRE Register pre set time 4.0 3.0 ns
tCLR Regist er clear  time 4.0 3 .0 ns
tPIA PIA delay 1.0 1.0 ns
tLPA Low- pow er add er (7) 12.0 12.0 ns

34 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Table 22. MAX 7000 & MAX 7000E External Timing Parameters

Symbol Parameter Cond itio n s Speed Gr ad e Unit

-15 -15T -20

Min Max Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 15.0 15.0 20.0 ns

tPD2 I/O input to non-registered

output C1 = 35 pF 15.0 15.0 20.0 ns

tSU Global clock setup time 11.0 11.0 12.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input (1) 3.0 –5.0 ns

tFH Global clock hold time of fast

input (1) 0.0 –0.0 ns

tCO1 Global clock to outpu t delay C1 = 35 pF 8.0 8.0 12.0 ns

tCH Global clock high time 5.0 6.0 6.0 ns

tCL Global clock lo w time 5.0 6.0 6.0 ns

tASU Array clock setup time 4.0 4.0 5.0 ns

tAH Array clock hold time 4.0 4.0 5.0 ns

tACO1 Array clock to output delay C1 = 35 pF 15.0 15.0 20.0 ns

tACH Array clock high time 6.0 6.5 8.0 ns

tACL Array clock low time 6.0 6.5 8.0 ns

tCPPW Minimum pulse width for clear

and pres et (2) 6.0 6.5 8.0 ns

tODH Output data hold time after

clock C1 = 35 pF (3) 1.0 1.0 1.0 ns

tCNT Minimum global clock period 13.0 13.0 16.0 ns

fCNT Maximum internal global clock

frequency (4) 76.9 76.9 62.5 MHz

tACNT Minimum array clo ck period 13.0 13.0 16.0 ns

fACNT Maximum internal array clock

frequency (4) 76.9 76.9 62.5 MHz

fMAX Maximum clock frequency (5) 100 83.3 83.3 MHz

Altera Corporation  35
MAX 7000 Programmable Logic Device Family Data Sheet
Table 23. MAX 7000 & MAX 7000 E Intern al Timing Parameters
Symb ol Para me te r Conditions Speed Grade Unit
-15-15T-20
MinMaxMinMaxMinMax
tIN Input pad and buffer delay 2.0 2.0 3.0 ns
tIO I/O input pad and buffer delay 2.0 2.0 3.0 ns
tFIN Fast input delay (1) 2.0 –4.0 ns
tSEXP Shared expander delay 8.0 10.0 9.0 ns
tPEXP Parall e l expand er del a y 1.0 1.0 2.0 n s
tLAD Logic array delay 6.0 6.0 8.0 ns
tLAC Logi c  contro l array del a y 6.0 6.0 8.0 n s
tIOE Internal output enable delay (1) 3.0 –4.0 ns
tOD1 Output buffer and pad delay
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 4.0 4.0 5.0 ns
tOD2 Output buffer and pad delay
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 5.0 –6.0 ns
tOD3 Output buffer and pad delay
Slow slew rate = on 
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 8.0 –9.0 ns
tZX1 Output buffer enable delay
Slow slew rate = off 
VCCIO = 5.0 V
C1 = 35 pF 6.0 6.0 10.0 ns
tZX2 Output buffer enable delay
Slow slew rate = off 
VCCIO = 3.3 V
C1 = 35 pF (6) 7.0 –11.0 ns
tZX3 Output buffer enable delay
Slow slew rate = on
VCCIO = 5.0 V or 3.3 V
C1 = 35 pF (1) 10.0 –14.0 ns
tXZ Output buffer disable del ay C1 = 5 pF 6.0 6.0 10.0 ns
tSU Register setup time 4.0 4.0 4.0 ns
tHRegister hold  time 4.0 4.0 5.0 ns
tFSU Register setup time of fast input (1) 2.0 –4.0 ns
tFH Registe r hold time  of fast inpu t (1) 2.0 –3.0 ns
tRD Register dela y 1.0 1.0 1.0 ns
tCOMB Combinatorial delay 1.0 1.0 1.0 ns
tIC Array clock delay 6.0 6.0 8.0 ns
tEN Register enable time 6.0 6.0 8.0 ns
tGLOB Global control delay 1.0 1.0 3.0 ns
tPRE Register preset time 4.0 4.0 4.0 ns
tCLR Register clear time 4.0 4.0 4.0 ns
tPIA PIA delay 2.0 2.0 3.0 ns
tLPA Low-power adder (7) 13.0 15.0 15.0 ns

36 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This parameter applies to MAX 7000E devic e s only.

(2) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(3) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(4) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(5) The fMAX values represent the highest frequency for pipelined data.

(6) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and indust ri al us e.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

Tables 24 and 25 sho w the EPM7032S AC operat ing conditions.

Table 24. EPM7032S External Timing Parameters (Part 1 of 2)

Symb ol Pa r am e ter Conditions Speed Grad e Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns

tPD2 I/O input to non-regist ered

output C1 = 35 pF 5.0 6.0 7.5 10.0 ns

tSU Global clock setup time 2.9 4.0 5.0 7.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input 2.5 2.5 2.5 3.0 ns

tFH Global clock hold time of fast

input 0.0 0.0 0.0 0.5 ns

tCO1 Global clock to output delay C1 = 35 pF 3.2 3.5 4.3 5.0 ns

tCH Global clock high time 2.0 2.5 3.0 4.0 ns

tCL Global clock low time 2.0 2.5 3.0 4.0 ns

tASU Array clock setu p time 0.7 0.9 1.1 2.0 ns

tAH Array clock hold time 1.8 2.1 2.7 3.0 ns

tACO1 Array clock to output delay C1 = 35 pF 5.4 6.6 8.2 10.0 ns

tACH Ar ray clock high time 2.5 2.5 3.0 4.0 ns

tACL Ar ray clock low time 2.5 2.5 3.0 4.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 2.5 2.5 3.0 4.0 ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.0 1.0 1.0 1.0 ns

tCNT Minimum global clock period 5.7 7.0 8.6 10.0 ns

fCNT Maximum internal global clock

frequency (3) 175.4 142.9 116.3 100.0 MHz

tACNT Minimum array cl ock period 5.7 7.0 8.6 10.0 ns

Altera Corporation 37

MAX 7000 Programmable Logic Device Family Data Sheet

fACNT Maximum internal array clock

frequency (3) 175.4 142.9 116.3 100.0 MHz

fMAX Maximum clock frequency (4) 250.0 200.0 166.7 125.0 MHz

Table 25. EPM7032S Internal Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

tIN Input pad and buffer delay 0.2 0.2 0.3 0.5 ns

tIO I/O input pad and buffer delay 0.2 0.2 0.3 0.5 ns

tFIN Fast input delay 2.2 2.1 2.5 1.0 ns

tSEXP Shar ed expa nd er delay 3.1 3 .8 4.6 5.0 n s

tPEXP Paral lel expander delay 0.9 1.1 1.4 0.8 ns

tLAD Logic array delay 2.6 3.3 4.0 5.0 ns

tLAC Logic control array delay 2.5 3.3 4.0 5.0 ns

tIOE Internal output enable delay 0.7 0.8 1.0 2.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 0.4 1.5 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 0.7 0.8 0.9 2.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 5.4 5.5 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 4.5 4.5 5.5 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns

tSU Register setu p time 0.8 1. 0 1.3 2.0 ns

tHRegister hold tim e 1.7 2. 0 2.5 3.0 ns

tFSU Register setup time of fast

input 1.9 1.8 1.7 3.0 ns

tFH Register hold time of fast

input 0.6 0.7 0.8 0.5 ns

tRD Register dela y 1.2 1 .6 1.9 2.0 ns

tCOMB Combinatorial delay 0.9 1.1 1.4 2.0 ns

tIC Array clock delay 2.7 3.4 4.2 5.0 ns

tEN Register ena bl e time 2.6 3.3 4.0 5.0 n s

tGLOB Global control delay 1.6 1.4 1.7 1.0 ns

tPRE Regist er pre set time 2.0 2 .4 3.0 3.0 ns

Table 24. EPM7032S Exter nal Timing Para meters (P art 2 of 2)

Symbol Parameter Condit ions Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

38 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(2) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(3) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and indust ri al us e.

(6) For EPM7064S -5, EPM7064S-6, EPM7128S - 6, EPM7160S-6, EPM7160 S-7, EPM 7192S - 7, and EP M 7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing val ue.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

Tables 26 and 27 sho w the EPM7064S AC operat ing conditions.

tCLR Regis ter clear tim e 2.0 2.4 3.0 3.0 ns

tPIA PIA d elay (6) 1.1 1.1 1.4 1.0 ns

tLPA Low- po wer add er (7) 12.0 10.0 10.0 11.0 ns

Table 25. EPM7032S Inter nal Timing Parameters (Part 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

Table 26. EPM7064S External Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 5.0 6.0 7.5 10.0 ns

tPD2 I/O input to non-regist ered

output C1 = 35 pF 5.0 6.0 7.5 10.0 ns

tSU Global clock setup time 2.9 3.6 6.0 7.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input 2.5 2.5 3.0 3.0 ns

tFH Global clock hold time of fast

input 0.0 0.0 0.5 0.5 ns

tCO1 Global clock to output delay C1 = 35 pF 3.2 4.0 4.5 5.0 ns

tCH Global clock high time 2.0 2.5 3.0 4.0 ns

tCL Global clock low time 2.0 2.5 3.0 4.0 ns

tASU Array clock setu p time 0.7 0.9 3.0 2.0 ns

tAH Array clock hold time 1.8 2.1 2 .0 3.0 ns

Altera Corporation 39

MAX 7000 Programmable Logic Device Family Data Sheet

tACO1 Array clock to output delay C1 = 35 pF 5.4 6.7 7.5 10.0 ns

tACH Array clock high time 2.5 2.5 3.0 4.0 ns

tACL Array clock low time 2.5 2.5 3.0 4.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 2.52.53.04.0ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.01.01.01.0ns

tCNT Minimum global clock period 5.7 7.1 8.0 10.0 ns

fCNT Maximum internal global clock

frequency (3) 175.4 140.8 125.0 100.0 MHz

tACNT Minimum array clock period 5.7 7.1 8.0 10.0 ns

fACNT Maximum internal array clock

frequency (3) 175.4 140.8 125.0 100.0 MHz

fMAX Maximum clock frequency (4) 250.0 200.0 166.7 125.0 MHz

Table 27. EPM7064S Internal Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

tIN Input pad and buffer delay 0.2 0.2 0.5 0.5 ns

tIO I/O input pad and buffer delay 0.2 0.2 0.5 0.5 ns

tFIN Fast input delay 2.2 2.6 1.0 1.0 ns

tSEXP Shar ed expa nd er delay 3.1 3.8 4.0 5.0 ns

tPEXP Paral lel expander delay 0.9 1.1 0.8 0.8 ns

tLAD Logic array delay 2.6 3.2 3.0 5.0 ns

tLAC Logic control array delay 2.5 3.2 3.0 5.0 ns

tIOE Internal output enable delay 0.7 0.8 2.0 2.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.2 0.3 2.0 1.5 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 0.7 0.8 2.5 2.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.2 5.3 7.0 5.5 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 4.0 5.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 4.5 4.5 5.5 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 9.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 4.0 5.0 ns

tSU Register setu p time 0. 8 1 .0 3.0 2 .0 ns

tHRegister hold tim e 1.7 2.0 2.0 3 .0 ns

Table 26. EPM7064S Exter nal Timing Para meters (P art 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

MinMaxMinMaxMinMaxMinMax

40 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(2) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(3) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and indust ri al us e.

(6) For EPM7064S -5, EPM7064S-6, EPM7128S - 6, EPM7160S-6, EPM7160 S-7, EPM 7192S - 7, and EP M 7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing val ue.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

tFSU Regis ter setu p time of fast

input 1.9 1.8 3.0 3.0 ns

tFH Register hold time of fast

input 0.6 0.7 0.5 0.5 ns

tRD Register del a y 1.2 1.6 1.0 2.0 ns

tCOMB Combinatorial delay 0.9 1.0 1.0 2.0 ns

tIC Array clock delay 2.7 3.3 3.0 5.0 ns

tEN Register enable time 2.6 3.2 3.0 5.0 ns

tGLOB Global control delay 1.6 1.9 1.0 1.0 ns

tPRE Register pre set time 2.0 2.4 2.0 3.0 ns

tCLR Regis ter clear tim e 2.0 2.4 2.0 3.0 ns

tPIA PIA d elay (6) 1.1 1.3 1.0 1.0 ns

tLPA Low- po wer add er (7) 12.0 11.0 10.0 11.0 ns

Table 27. EPM7064S Inter nal Timing Parameters (Part 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-5 -6 -7 -10

Min Max Min Max Min Max Min Max

Altera Corporation 41

MAX 7000 Programmable Logic Device Family Data Sheet

Tables 28 and 29 show the EPM7128S AC operating conditions.

Table 28. EPM7128S External Timing Par ameters

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

MinMaxMinMaxMinMaxMinMax

tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns

tPD2 I/O input to non-registered

output C1 = 35 pF 6.0 7.5 10.0 15.0 ns

tSU Global clock setup time 3.4 6.0 7.0 11.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 0.0 n s

tFSU Global clock setup time of fast

input 2.53.03.03.0ns

tFH Global clock hold time of fast

input 0.00.50.50.0ns

tCO1 Global clock to output delay C1 = 35 pF 4.0 4.5 5.0 8.0 ns

tCH Global clock high time 3.0 3.0 4.0 5.0 ns

tCL Global clock low time 3.0 3.0 4.0 5.0 ns

tASU Array clock setup time 0.9 3.0 2.0 4.0 ns

tAH Array clock hold time 1.8 2.0 5.0 4.0 ns

tACO1 Array clock to output delay C1 = 35 pF 6.5 7.5 10.0 15.0 ns

tACH Array clock high time 3.0 3.0 4.0 6.0 ns

tACL Array clock low time 3.0 3.0 4.0 6.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 3.03.04.06.0ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.01.01.01.0ns

tCNT Minimum global clock period 6.8 8.0 10.0 13.0 ns

fCNT Maximum internal global clock

frequency (3) 147.1 125.0 100.0 76.9 MHz

tACNT Minimum array clock period 6.8 8.0 10.0 13.0 ns

fACNT Maximum internal array clock

frequency (3) 147.1 125.0 100.0 76.9 MHz

fMAX Maximum clock frequency (4) 166.7 166.7 125.0 100.0 MHz

42 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Table 29. EPM7128S Internal Timing Parameters

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

tIN Input pad and buffer delay 0.2 0.5 0.5 2.0 ns

tIO I/O input pad and buffer delay 0.2 0.5 0.5 2.0 ns

tFIN Fast input delay 2.6 1.0 1.0 2.0 ns

tSEXP Shar ed expa nd er delay 3.7 4.0 5.0 8.0 ns

tPEXP Paral lel expander delay 1.1 0.8 0.8 1.0 ns

tLAD Logic array delay 3.0 3.0 5.0 6.0 ns

tLAC Logic control array delay 3.0 3.0 5.0 6.0 ns

tIOE Internal output enable delay 0.7 2.0 2.0 3.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.4 2.0 1.5 4.0 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 0.9 2.5 2.0 5.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.4 7.0 5.5 8.0 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 4.5 5.5 7.0 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns

tSU Register setu p time 1 .0 3.0 2.0 4.0 ns

tHRegister hold tim e 1.7 2 .0 5.0 4 .0 ns

tFSU Register setup time of fast

input 1.9 3.0 3.0 2.0 ns

tFH Register hold time of fast

input 0.6 0.5 0.5 1.0 ns

tRD Register dela y 1.4 1.0 2.0 1 .0 ns

tCOMB Combinatorial delay 1.0 1.0 2.0 1.0 ns

tIC Array clock delay 3.1 3.0 5.0 6.0 ns

tEN Register ena bl e time 3.0 3.0 5.0 6.0 ns

tGLOB Global control delay 2.0 1.0 1.0 1.0 ns

tPRE Regist er pre set time 2.4 2.0 3.0 4.0 ns

tCLR Register clear time 2.4 2.0 3.0 4.0 ns

tPIA PIA de l a y (6) 1.4 1.0 1.0 2.0 ns

tLPA Low-po wer add er (7) 11.0 10.0 11.0 13.0 ns

Altera Corporation 43

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(2) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(3) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and indust ri al us e.

(6) For EPM7064S -5, EPM7064S-6, EPM7128S - 6, EPM7160S-6, EPM7160 S-7, EPM 7192S - 7, and EP M 7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing val ue.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

Tables 30 and 31 show the EPM7160S AC operating conditions.

Table 30. EPM7160S External Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 6.0 7.5 10.0 15.0 ns

tPD2 I/O input to non-regist ered

output C1 = 35 pF 6.0 7.5 10.0 15.0 ns

tSU Global clock setup time 3.4 4.2 7.0 11.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input 2.5 3.0 3.0 3.0 ns

tFH Global clock hold time of fast

input 0.0 0.0 0.5 0.0 ns

tCO1 Global clock to output delay C1 = 35 pF 3.9 4.8 5 8 ns

tCH Global clock high time 3.0 3.0 4.0 5.0 ns

tCL Global clock low time 3.0 3.0 4.0 5.0 ns

tASU Array clock setu p time 0.9 1.1 2.0 4.0 ns

tAH Array clock hold time 1.7 2.1 3 .0 4.0 ns

tACO1 Array clock to output delay C1 = 35 pF 6.4 7.9 10.0 15.0 ns

tACH Ar ray clock high time 3.0 3.0 4 .0 6.0 ns

tACL Ar ray clock low time 3.0 3.0 4.0 6.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 2.5 3.0 4.0 6.0 ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.0 1.0 1.0 1.0 ns

tCNT Minimum global clock period 6.7 8.2 10.0 13.0 ns

fCNT Maximum internal global clock

frequency (3) 149.3 122.0 100.0 76.9 MHz

tACNT Minimum array cl ock perio d 6.7 8.2 10.0 13.0 ns

44 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

fACNT Maximum internal array clock

frequency (3) 149.3 122.0 100.0 76.9 MHz

fMAX Maximum clock frequency (4) 166.7 166.7 125.0 100.0 MHz

Table 31. EPM7160S Internal Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

tIN Input pad and buffer delay 0.2 0.3 0.5 2.0 ns

tIO I/O input pad and buffer delay 0.2 0.3 0.5 2.0 ns

tFIN Fast input delay 2.6 3.2 1.0 2.0 ns

tSEXP Shar ed expa nd er delay 3.6 4.3 5.0 8.0 ns

tPEXP Paral lel expander delay 1.0 1.3 0.8 1.0 ns

tLAD Logic array delay 2.8 3.4 5.0 6.0 ns

tLAC Logic control array delay 2.8 3.4 5.0 6.0 ns

tIOE Internal output enable delay 0.7 0.9 2.0 3.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.4 0.5 1.5 4.0 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 0.9 1.0 2.0 5.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.4 5.5 5.5 8.0 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 4.0 5.0 6.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 4.5 5.5 7.0 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 9.0 10.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 4.0 5.0 6.0 ns

tSU Register setu p time 1 .0 1.2 2.0 4.0 ns

tHRegister hold tim e 1.6 2 .0 3.0 4 .0 ns

tFSU Register setup time of fast

input 1.9 2.2 3.0 2.0 ns

tFH Register hold time of fast

input 0.6 0.8 0.5 1.0 ns

tRD Register dela y 1.3 1.6 2.0 1 .0 ns

tCOMB Combinatorial delay 1.0 1.3 2.0 1.0 ns

tIC Array clock delay 2.9 3.5 5.0 6.0 ns

tEN Register ena bl e time 2.8 3.4 5.0 6.0 ns

tGLOB Global control delay 2.0 2.4 1.0 1.0 ns

tPRE Regist er pre set time 2.4 3.0 3.0 4.0 ns

Table 30. EPM7160S Exter nal Timing Para meters (P art 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

MinMaxMinMaxMinMaxMinMax

Altera Corporation 45

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(2) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(3) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.

(6) For EPM7064S -5, EPM7064S-6, EPM7128S - 6, EPM7160S-6, EPM7160 S-7, EPM 7192S - 7, and EP M 7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing val ue.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

Tables 32 and 33 sho w the EPM7192S AC operat ing conditions.

tCLR Regis ter clear tim e 2.4 3.0 3.0 4.0 ns

tPIA PIA d elay (6) 1.6 2.0 1.0 2.0 ns

tLPA Low- po wer add er (7) 11.0 10.0 11.0 13.0 ns

Table 31. EPM7160S Inter nal Timing Parameters (Part 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-6 -7 -10 -15

Min Max Min Max Min Max Min Max

Table 32. EPM7192S External Timing Parameters (Part 1 of 2)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns

tPD2 I/O input to non-regist ered

output C1 = 35 pF 7.5 10.0 15.0 ns

tSU Global clock setup time 4.1 7.0 11.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input 3.0 3.0 3.0 ns

tFH Global clock hold time of fast

input 0.0 0.5 0.0 ns

tCO1 Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns

tCH Global clock high time 3.0 4.0 5.0 ns

tCL Global clock low time 3.0 4.0 5.0 ns

tASU Array clock setu p time 1.0 2.0 4.0 ns

tAH Array clock hold time 1.8 3.0 4.0 ns

46 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

tACO1 Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns

tACH Array clock high time 3.0 4.0 6.0 ns

tACL Array clock low time 3.0 4.0 6.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 3.0 4.0 6.0 ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.0 1.0 1.0 ns

tCNT Minimum global clock period 8.0 10.0 13.0 ns

fCNT Maximum internal global clock

frequency (3) 125.0 100.0 76.9 MHz

tACNT Minimum array clock period 8.0 10.0 13.0 ns

fACNT Maximum internal array clock

frequency (3) 125.0 100.0 76.9 MHz

fMAX Maximum clock frequency (4) 166.7 125.0 100.0 MHz

Table 33. EPM7192S Internal Timing Parameters (Part 1 of 2)

Symb ol Parame ter Co nd itio n s Speed Grade U n it

-7 -10 -15

Min Max Min Max Min Max

tIN Input pad and buffer delay 0.3 0.5 2.0 ns

tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns

tFIN Fast input delay 3.2 1.0 2.0 ns

tSEXP Shar ed expa nd er delay 4.2 5.0 8.0 ns

tPEXP Parallel expander delay 1.2 0.8 1.0 ns

tLAD Logic array delay 3.1 5.0 6.0 ns

tLAC Logic control array delay 3.1 5.0 6.0 ns

tIOE Internal output enable delay 0.9 2.0 3.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 1.0 2.0 5.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 7.0 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 5.5 7.0 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns

tSU Register setu p time 1.1 2.0 4.0 ns

tHRegister hold tim e 1.7 3.0 4.0 ns

Table 32. EPM7192S Exter nal Timing Para meters (P art 2 of 2)

Symbol Parameter Cond itio n s Speed Gr ad e Unit

-7 -10 -15

Min Max Min Max Min Max

Altera Corporation 47

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA parameter

mus t be ad d e d to this mini mum width if the cl e a r or reset sig n al inc orporat e s the tLAD parameter into the signal

path.

(2) This par amete r is a gu ideline that is sample -te st ed o nly and is b ase d on e xtensive device c har ac ter ization. This

parameter applies for both global and array clocking.

(3) These parameter s are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Operating conditions: VCCIO = 3.3 V ± 10% for commercial and indust ri al us e.

(6) For EPM7064S -5, EPM7064S-6, EPM7128S - 6, EPM7160S-6, EPM7160 S-7, EPM 7192S - 7, and EP M 7256S-7 devices,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing val ue.

(7) The tLPA paramete r must be add e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW parame te rs fo r m a crocells

runni ng in the low- pow er m ode .

tFSU Regis ter setu p time of fast

input 2.3 3.0 2.0 ns

tFH Register hold time of fast

input 0.7 0.5 1.0 ns

tRD Register del a y 1.4 2.0 1.0 ns

tCOMB Combinatorial delay 1.2 2.0 1.0 ns

tIC Array clock delay 3.2 5.0 6.0 ns

tEN Register enable time 3.1 5.0 6.0 ns

tGLOB Global control delay 2.5 1.0 1.0 ns

tPRE Register pre set time 2.7 3.0 4.0 ns

tCLR Regis ter clear time 2.7 3.0 4.0 ns

tPIA PIA d elay (6) 2.4 1.0 2.0 ns

tLPA Low- po wer add er (7) 10.0 11.0 13.0 ns

Table 33. EPM7192S Inter nal Timing Parameters (Part 2 of 2)

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

48 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Tables 34 and 35 show the EPM7256S AC operat ing conditions.

Table 34. EPM7256S External Timing Par ameters

Symbol Parameter Cond itio n s Speed Gr ad e Unit

-7 -10 -15

Min Max Min Max Min Max

tPD1 Input to non-registered output C1 = 35 pF 7.5 10.0 15.0 ns

tPD2 I/O input to non-registered

output C1 = 35 pF 7.5 10.0 15.0 ns

tSU Global clock setup time 3.9 7.0 11.0 ns

tHGlobal clock hold time 0.0 0.0 0.0 ns

tFSU Global clock setup time of fast

input 3.0 3.0 3.0 ns

tFH Global clock hold time of fast

input 0.0 0.5 0.0 ns

tCO1 Global clock to output delay C1 = 35 pF 4.7 5.0 8.0 ns

tCH Global clock high time 3.0 4.0 5.0 ns

tCL Global clock lo w time 3.0 4.0 5.0 ns

tASU Array clock setup time 0.8 2.0 4.0 ns

tAH Array clock hold time 1.9 3.0 4.0 ns

tACO1 Array clock to output delay C1 = 35 pF 7.8 10.0 15.0 ns

tACH Array clock high time 3.0 4.0 6.0 ns

tACL Array clock low time 3.0 4.0 6.0 ns

tCPPW Minimum pulse width for clear

and pres et (1) 3.0 4.0 6.0 ns

tODH Output data hold time after

clock C1 = 35 pF (2) 1.0 1.0 1.0 ns

tCNT Minimum global clock period 7.8 10.0 13.0 ns

fCNT Maximum internal global clock

frequency (3) 128.2 100.0 76.9 MHz

tACNT Minimum array clock period 7.8 10.0 13.0 ns

fACNT Maximum internal array clock

frequency (3) 128.2 100.0 76.9 MHz

fMAX Maximum clock frequency (4) 166.7 125.0 100.0 MHz

Altera Corporation 49

MAX 7000 Programmable Logic Device Family Data Sheet

Table 35. EPM7256S Inter nal Timing Parameters

Symbol Parameter Conditions Speed Grade Unit

-7 -10 -15

Min Max Min Max Min Max

tIN Input pad and buffer delay 0.3 0.5 2.0 ns

tIO I/O input pad and buffer delay 0.3 0.5 2.0 ns

tFIN Fast input delay 3.4 1.0 2.0 ns

tSEXP Shared exp and er dela y 3.9 5.0 8.0 ns

tPEXP Parallel expander delay 1.1 0.8 1.0 ns

tLAD Logic array delay 2.6 5.0 6.0 ns

tLAC Logic control array delay 2.6 5.0 6.0 ns

tIOE Internal output enable delay 0.8 2.0 3.0 ns

tOD1 Output buffer and pad delay C1 = 35 pF 0.5 1.5 4.0 ns

tOD2 Output buffer and pad delay C1 = 35 pF (5) 1.0 2.0 5.0 ns

tOD3 Output buffer and pad delay C1 = 35 pF 5.5 5.5 8.0 ns

tZX1 Output buffer enable delay C1 = 35 pF 4.0 5.0 6.0 ns

tZX2 Output buffer enable delay C1 = 35 pF (5) 4.5 5.5 7.0 ns

tZX3 Output buffer enable delay C1 = 35 pF 9.0 9.0 10.0 ns

tXZ Output buffer disable delay C1 = 5 pF 4.0 5.0 6.0 ns

tSU Register setu p tim e 1.1 2.0 4. 0 ns

tHRegister hol d time 1.6 3.0 4. 0 ns

tFSU Regis ter setu p time of fast

input 2.4 3.0 2.0 ns

tFH Register hold time of fast

input 0.6 0.5 1.0 ns

tRD Register del a y 1.1 2.0 1.0 ns

tCOMB Combinatorial delay 1.1 2.0 1.0 ns

tIC Array clock delay 2.9 5.0 6.0 ns

tEN Register enable time 2.6 5.0 6.0 ns

tGLOB Global control delay 2.8 1.0 1.0 ns

tPRE Register pre set time 2.7 3.0 4.0 ns

tCLR Regis ter clear time 2.7 3.0 4.0 ns

tPIA PIA d elay (6) 3.0 1.0 2.0 ns

tLPA Low- po wer add er (7) 10.0 11.0 13.0 ns

50 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Notes to tables:

(1) This minimum pulse width for preset and clear applies for both global clear and array controls. The tLPA paramete r

must be adde d to th is minimum width if the cl ea r or reset signal incorporates the tLAD param e te r in to the sign al

path.

(2) This par ame ter is a guide line that is sample- test e d only and is based on exten sive devic e ch ar ac te r ization. This

parameter applies for both global and array clocking.

(3) These para meters are measured with a 16-bit loadable, enab led, up/down counter programmed into eac h LA B.

(4) The fMAX values represent the highest frequency for pipelined data.

(5) Oper ating conditions: VCCIO = 3.3 V ± 10% for commercial and industrial use.

(6) For EPM7064S - 5, EPM7064S-6, EPM712 8S -6 , EPM7160S-6, EPM7160 S-7, EPM7 192S - 7, and EPM 7256S - 7 device s,

these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these

devices, add an additional 0.1 ns to the PIA timing value.

(7) The tLPA parame te r must be ad d e d to the tLAD, tLAC, tIC, tEN, tSEXP, tACL, and tCPPW param e ters for mac rocells

runni ng in the low- pow er m ode .

Power

Consumption

Supply power (P) versus frequency (fMAX in MHz) for MAX 7000 dev ices

is calculated with the following equation:

P = PINT + PIO = ICCINT × VCC + PIO

The PIO value, which depends on the device output load characteristics

and switching frequency, can be calculated using the guidelines given in

Appli ca t io n No te 74 (E va lu at i ng Po w e r fo r A lt er a De v ice s ).

The ICCINT value, which depends on the switching frequency and the

application logic, is calculated with the following equation:

ICCINT =

A × MCTON + B × (MCDEV – MCTON) + C × MCUSED × fMAX × togLC

The parameters in this equation are shown below:

MCTON = Number of macro cells with the Turbo Bit option t urned on,

as reported in the MAX+PLUS II Report File (.rpt)

MCDEV = Number of macrocells in the device

MCUSED = Total number of macrocells in the design, as reported

in the MAX+PLUS II Report File (.rpt)

fMAX = Highest clock frequency to the device

togLC = Average ratio of logic cells toggling at each clock

(typically 0.1 2 5)

A, B, C = Constants, shown in Table 36

Altera Corporation 51

MAX 7000 Programmable Logic Device Family Data Sheet

This calculation provides an ICC estimate based on typical conditions

using a pattern of a 16-bit, loadable, enabled, up/down counter in each

LAB with no outpu t load . Actu a l ICC values should be verified during

operation because this measurement is sensitive to the actual pattern in

the device and the environmental operating conditions.

Tab le 36. MAX 7000 ICC Equation Constants

Device A B C

EPM7032 1.87 0.52 0.144

EPM7064 1.63 0.74 0.144

EPM7096 1.63 0.74 0.144

EPM7128E 1.17 0.54 0.096

EPM7160E 1.17 0.54 0.096

EPM7192E 1.17 0.54 0.096

EPM7256E 1.17 0.54 0.096

EPM7032S 0.93 0.40 0.040

EPM7064S 0.93 0.40 0.040

EPM7128S 0.93 0.40 0.040

EPM7160S 0.93 0.40 0.040

EPM7192S 0.93 0.40 0.040

EPM7256S 0.93 0.40 0.040

52 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 14 shows typical supply current versus frequency for MAX 7000

devices.

Figure 14. ICC vs. Frequency for MAX 7000 Devices (Part 1 of 2)

Frequency (MHz)

EPM7064

EPM7032

050

Frequency (MHz)

200100 150

High Speed

151.5 MHz

180

100

140

VCC = 5.0 V

Room Temperature

050 200100 150

Low Power

60.2 MHz

151.5 MHz

200

300

100

VCC = 5.0 V

Room Temperature

EPM7096

050

Frequency (MHz)

250

100

150

350

450

150

High Speed

VCC = 5.0 V

Room Temperature

Low Power

Typical I

Active (mA)

CC Typical I

Active (mA)

Typical I

Active (mA)

60.2 MHz

125 MHz

55.5 MHz

High Speed

Low Power

Altera Corporation 53

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 14. ICC vs . Frequency for MAX 70 00 Devi ces (Part 2 of 2)

VCC = 5.0 V

Room Temperature

Frequency (MHz)

500

300

400

200

100

25 50 100 125

90.9 MHz

43.5 MHz

EPM7192E

VCC = 5.0 V

Room Temperature

Frequency (MHz)

750

450

600

300

150

25 50 100

90.9 MHz

43.4 MHz

EPM7256E

VCC = 5.0 V

Room Temperature

Frequency (MHz)

500

300

400

Low Power

200

100

50 100

100 MHz

47.6 MHz

EPM7160E

150 200

VCC = 5.0 V

Room Temperature

Frequency (MHz)

500

300

400

High Speed

200

100

50 100

125 MHz

55.5 MHz

EPM7128E

150 200

High Speed

Low Power

Typical I

Active (mA)

Typical I

Active (mA)

Typical I

Active (mA)

Typical I

Active (mA)

125

54 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 15 shows typical supply current versus frequency for MAX 7000S

devices.

Figure 15. ICC vs. Frequency for MAX 7000S Devices (Part 1 of 2)

VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

50 100 150 200

142.9 MHz

58.8 MHz

EPM7032S

60 VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

50 100 150200

175.4 MHz

56.5 MHz

EPM7064S

100

120

VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

50 100 150 200

147.1 MHz

56.2 MHz

EPM7128S

120

200

280

160

240

VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

50 100 150200

149.3 MHz

56.5 MHz

EPM7160S

120

180

240

300

Typical I

Active (mA)

Typical I

Active (mA)

Typical I

Active (mA)

Typical I

Active (mA)

Altera Corporation 55

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 15. ICC vs. Frequency for MAX 70 00S Devices (Par t 2 of 2)

Device

Pin-Outs

See the Alter a web s ite (http://www.altera.com) or the Altera Digital

Library for pin-out information.

EPM7192S

VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

25 100 125

125.0 MHz

55.6 MHz

120

180

240

300

50 75

EPM7256S

VCC = 5.0 V

Room Temperature

Frequency (MHz)

High Speed

Low Power

25 100 125

128.2 MHz

56.2 MHz

100

200

300

400

50 75

Typical I

Active (mA)

CC Typical I

Active (mA)

56 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figures 16 through 22 show the packa ge pin -out dia gra ms for MA X 7000

devices.

Figure 16. 44-Pin Package Pi n-Out D iagram

Package outlines not drawn to scale .

Notes:

(1) The pin fu nctions shown in pare nthesis are only av ailab le in M AX 7000E and MAX 7000S devic es.

(2) JTAG por ts are available in MAX 7000S devices only .

44-Pin PLCC

I/O

VCC

INPUT/OE2/(GCLK2)

(1)

INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

I/O/(TDO)

(2)

I/O

VCC

I/O

I/O/(TCK)

(2)

I/O

GND

I/O

GND

VCC

I/O

6 5 4 3 2 1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

EPM7032

EPM7032S

EPM7064

EPM7064S

(2)

I/O/(TDI)

I/O

GND

I/O

(2)

I/O/(TMS)

I/O

VCC

I/O

44-Pin PQFP

Pin 12 Pin 23

Pin 34

Pin 1

I/O

VCC

INPUT/OE2/(GCLK2)

(1)

INPUT/GCLRn

INPUT/OE1

INPUT//GCLK1

GND

I/O

I/O/(TDO)

(2)

I/O

VCC

I/O

I/O/(TCK)

(2)

I/O

GND

I/O

GND

VCC

I/O

GND

I/O

(2)

I/O/(TMS)

I/O

VCC

I/O

EPM7032

44-Pin TQFP

Pin 12 Pin 23

Pin 34

Pin 1

I/O

VCC

INPUT/OE2/(GCLK2)

(1)

INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

I/O/(TDO)

(2)

I/O

VCC

I/O

I/O/(TCK)

(2)

I/O

GND

I/O

GND

VCC

I/O

(2)

I/O/(TDI)

I/O

GND

I/O

(2)

I/O/(TMS)

I/O

VCC

I/O

EPM7032

EPM7032S

EPM7064

EPM7064S

(2)

I/O/(TDI)

Altera Corporation 57

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 17. 68-Pin Package Pin -Out Diagram

Package outlines not drawn to scale.

Notes:

(1) The pin functions shown in parenthesis are only available in MAX 7000E and MAX

7000S devices.

(2) JTAG ports are ava ilab le in MAX 7000S devic e s only .

68-Pin PLCC

EPM7064

EPM7096

I/O

GND

I/O/(TDO)

(2)

I/O

VCCIO

I/O

I/O/(TCK)

(2)

I/O

GND

I/O

VCCIO

(2)

I/O/(TDI)

I/O

GND

I/O

(2)

I/O/(TMS)

I/O

VCCIO

I/O

GND

I/O

GND

I/O

VCCINT

INPUT/OE2/(GCLK2)

(1)

INPUT/GCLRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

VCCIO

I/O

VCCIO

I/O

GND

VCCINT

I/O

GND

I/O

VCCIO

58 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 18. 84-Pin Package Pi n-Out D iagram

Package outline not drawn to scale.

Notes:

(1) Pins 6, 39, 46, and 79 are no-con nec t (N.C. ) pins on EPM7096, EPM7160E, and EP M7160S devices.

(2) The pin fu nctions shown in pare nthesis are only av ailab le in M AX 7000E and MAX 7000S devic es.

(3) JTAG por ts are available in M A X 700 0S devices only .

I/O

VCCIO

I/O/(TDI)

(3)

I/O

GND

I/O

I/O/(TMS)

(3)

I/O

VCCIO

I/O

GND

I/O

GND

I/O

(1)

I/O

VCCINT

INPUT/OE2/(GCLK2)

(2)

INPUT/GLCRn

INPUT/OE1

INPUT/GCLK1

GND

I/O

(1)

VCCIO

I/O

GND

I/O/(TDO)

(3)

I/O

VCCIO

I/O

I/O/(TCK)

(3)

I/O

GND

I/O

VCCIO

I/O

(1)

I/O

GND

VCCINT

I/O

(1)

GND

I/O

VCCIO

EPM7064

EPM7064S

EPM7096

EPM7128E

EPM7128S

EPM7160E

EPM7160S

84-Pin PLCC

Altera Corporation 59

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 19. 100-Pin Package Pin-Out Diagram

Package outline not drawn to scale.

Figure 20. 160-Pin Package Pin-Out Diagram

Package outline not drawn to scale.

100-Pin PQFP

Pin 31

EPM7064

EPM7096

EPM7128E

EPM7128S

EPM7160E

Pin 81

Pin 1

Pin 51

100-Pin TQFP

Pin 1

Pin 26

Pin 76

Pin 51

EPM7064S

EPM7128S

EPM7160S

Pin 1

EPM7128E

EPM7128S

EPM7160E

EPM7160S

EPM7192E

EPM7192S

EPM7256E

Pin 121

Pin 81

Pin 41

160-Pin PGA 160-Pin PQFP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

EPM7192E

Bottom

View

60 Altera Corporation

MAX 7000 Programmable Logic Device Family Data Sheet

Figure 21 . 192-Pin Package Pi n-Ou t Diagram

Package outline not drawn to scale.

Figure 22 . 208-Pin Package Pi n-Ou t Diagram

Package outline not drawn to scale.

192-Pin PGA

EPM7256E

Bottom

View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

208-Pin PQFP/RQFP

Pin 1 Pin 157

Pin 105Pin 53

EPM7256E

EPM7256S

Altera Corporation 61

MAX 7000 Programmable Logic Device Family Data Sheet

Altera, Bit Blaste r, ByteB las ter, JAM, Ma sterBl aster , MA X, M AX+PL US II, Multi Vol t, Qu art us, Turbo Bit, and

specific device designations are trademarks and/or service marks of Altera Corporation in the United States

or other countries. Altera acknowledges the trademarks of other organizations for their respective products or

services mentioned in this document, specifically: Verilog is a registered trademark of Cadence Design

Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending

applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to

current specificatio ns in acco rdance with Alte ra’s standard warranty, but reserves the right to make changes

to any produ cts and service s at any time wi thout notice. A ltera assume s no responsibil ity or liabi lity arisin g

out of the application or use of any information, product, or service described herein except as expressly agreed

to in writing by Altera Corporation. Altera customers are advised to obtain the latest version

of device specifications before relying on any published information and before placing

orders fo r prod ucts or services.

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San Jose, CA 95134

(408) 544-7000

http://www.altera.com

Applications Hotline:

(800) 800-EPLD

Customer Ma rk eting:

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MAX 7000 Programmable Logic Device Family Data Sheet

62 Altera Corporation

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