1
MAX24288
IEEE 1588 Packet Timestamper and Clock
and 1Gbps Parallel-to-Serial MII Converter
General D es cripti on
The MAX24288 is a flexible, low-cost IEEE 1588
clock and tim es tamper with an SGMII or 1000BASE-X
serial interface and a parallel MII interface that can
be configured for GMII, RGMII, or 10/100 MII. The
device provides all required hardware support for
high-accuracy time and frequency synchronization
using the IEEE1588 Precis ion Tim e Protocol. In both
the transmit and receive directions 1588 packets are
identified and timestamped with high precision.
System software makes use of these timestamps to
determ ine the tim e offs et between the s ystem and its
timing master. Software can then correct any time
error by steering the device’s 1588 clock subsystem
appropriat ely. The dev ice provides th e necessar y I/O
to time-s ynchronize with a 1588 m aster elsewhere in
the same system or to be the master to which slave
components can synchronize.
In addition, the MAX24288 is a full-featured, gigabit
parallel-to-serial MII converter. It provides full SGMII
revision 1.8 compliance and also interfaces directly to
1Gbps 1000BASE-X SFP o ptic a l modules .
Applications
1588-Enabled Equipment with 1G Ethernet Ports
Wireless Ba se Stat ions and Controllers
Switches, Routers, DSLAMs, PON Equipment
Pseudowire Circuit Emulation Equipment
Test and Measurement Systems
Industrial and Factory Automation Equipment
Medical Equipment
Order ing Informat ion
PART TEMP RANGE PIN-PACKAGE
MAX24288ETK+ -40°C to +85°C 68 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
SPI is a trademark of Motorola, Inc.
Highlighted Feat ures
♦ Complete H ardware Support for IEEE 1588
♦ Ordinary, Boundary, and Transparent Clocks
♦ Flexible Block for Any 1588 Architectur e
♦ 1588 Clock Hardware
♦ Steerable by Software with 2-8ns Time
Resolution and 2-32ns Period Resolution
♦ 1ns Input Timestamp Accuracy and Output
Edge Placement Accuracy
♦ Three Time/Frequency Controls: Direct Time
Write, Time Adjustment, and High-Resolution
Frequency Adjustment
♦ Programmable Clock and Time-Alignment I/O
♦ Input Event Timestamper Detects Incoming
Time Alignment (e.g., 1 PPS) or Clock Edges
♦ Output Event Generator Provides Output Clock
Signal or Time Alignment Signal
♦ Built-In Support for Telecom Equipment Timing
Architecture with Dual Redundant Timing Cards
♦ 1588 Timestamping Hardware
♦ 1588 v1 and v2 Packets, Transmit and Receive
♦ Packet Classifier Supports 1588 Over Ethernet,
IPv4/UDP, IPv6/UDP, or MPLS and Is
Programmable for More Complex Stacks
♦ Supports 802.1Q VLAN Tags and MAC-in-MAC
♦ One-Step Operation: On-the-Fly Timestamp
Insertion or Transparent Clock Corrections; No
Need for Follow-Up Packets
♦ Can Insert All Timestamps, Receive and
Transmit, Into Packets for Easy Software Access
♦ Optional Two-Step Operation
♦ Parallel-to-Serial MII Conversion
♦ Bidirectional Wire-Speed Interface Conversion
♦ Serial: 1000BASE-X or SGMII v1.8 (4, 6, or 8 Pin)
♦ Parallel: GMII, RGMII, or 10/100 MII
♦ Translates Link Speed and Duplex Mode
Negotiation Between MDIO and SGMII PCS
♦ Full Support for 1588 + Sy nchronous Ethernet
♦ MDIO and SPI™ Interfaces
♦ 1.2V Operation with 3.3V I/O
Short Form Data Sheet
April 2012
MAX24288
2
Short Form Data Sheet
Applicat ion Examples
Example 1: S ingl e-Port 15 88 Slave Node
SFP Module
Ethernet
over fiber
1.25G
Serial
MAX24288
Local
OSC
GMII
Processor
MAC
MDIO
1588 recovered clock, e.g. 25MHz
1588 recovered time, e.g. 1 PPS
1588
Software
to frequency-syntonized
or time-synchronized
system components
Ethernet
over copper SGMII
1000BASE-T
PHY
-OR- -OR-
Example 2: Multiport Sys tem with Switch-Con nected 1588 Slave Node
Processor
1588
Software
SFP Modules
or
1000BASE-T
PHYs
Ethernet
over fiber
1.25G
Serial
GbE Switch
IC
SGMII
to other PHYs
MAX24288
Local
OSC
GMII
MAC
MDIO
1588 recovered clock, e.g. 25MHz
1588 recovered time, e.g. 1 PPS
to frequency-syntonized
or time-synchronized
system components
Example 3: Multiport Sys tem, B oundar y or T r anspare nt Cloc k, Po r t Card Logi c
Processor
SFP Module
Ethernet
over fiber
1.25G
Serial
MAX24288
GMII
MAC
MDIO
system clock, e.g. 25MHz
system time, e.g. 1 PPS from central
timing function
Ethernet
over copper SGMII
1000BASE-T
PHY
-OR- -OR-
packet data to/from central switch function
line clock, e.g. 25MHz
line clocks from other ports to central timing function
for SyncE or
1588 + SyncE operation
1588
Software
Example 4: Multiport Sys tem, B oundar y or T r anspare nt Cloc k, Central T iming Function
Processor
1588
Software
system time, e.g. 1 PPS
to all port cards
packet data to/from central switch function
line clocks, e.g. 25MHz
from port cards,
for SyncE or
1588+SyncE operation
MAC
MAX24288
1588 Clock
GMII
MDIO
1.25G
Serial
Local OSC
Stratum 3+
DS31400
Clock Sync IC
clk
system clock, e.g. 25MHz
other clocks,
various frequencies
MAX24288
3
Short Form Data Sheet
Block Diagr am
Receive
GMII
RGMII
MII
RXD[7:0]
RXCLK
RX_DV
RX_ER
COL
CRS
1588
Packet
Classifier
and
Modifier
D
C
D
C
PCS
Decoder
(10b/8b)
RD[9:0]
125MHz
Receive
CDR
RDP
RDN
Transmit
GMII
RGMII
MII
TXD[7:0]
TXCLK
GTXCLK
TX_EN
TX_ER
D
C
D
C
PCS
Encoder
(8b/10b)
TD[9:0]
125MHz
De-
Serializer
RD
1.25GHz
Serializer
Transmit
Driver
TD
625MHz
TDP
TDN
TCLKP
TCLKN
Tx SOP
Detect
1588
Time
Engine
TS3
Time
Stamper
time
PEG1
Prog. Event
Generator
Control
and
Status
JTAG GPIO Control
TX PLL
REFCLK
125MHz
125MHz, 62.5MHz, 25MHz, 2.5MHz
625MHz
JTCLK
JTMS
JTDI
JTDO
MDIO
MDC
RST_N
GPIO1
GPIO2
GPIO3
GPO1
GPO2
SCLK
SDI
SDO
CS_N
MAX24288
Auto-
Negotiate
PEG2
Prog. Event
Generator
GPIO4
GPIO5
GPIO6
GPIO7
Output
Clock
Generator
125MHz, 8 phases
TLB Loopback
DLB Loopback
Rate
Adaption
Buffer
Rate
Adaption
Buffer
TS2
Time
Stamper
TS1
Time
Stamper
D
C
D
C
1588
Packet
Classifier
and
Modifier
ALOS
Rx SOP
Detect
Rx SOP
Tx SOP
Tx SOP Rx SOP
RCLK
RCLK
RLB Loopback
JTRST_N
Detail ed Features
General Feat ures
• Control and status through MDIO interface or SPI interface
• High-sp eed MDIO interf ac e (12.5 MH z slave only) with optiona l preamble suppr es sion
• Optional SPI 4-wire serial microprocessor interface (25MHz, slave only)
• Operates from a 10, 12.8, 25, or 125MHz reference clock
• Optional 125MHz output clock for MAC to use as GTXCLK
Parallel-Ser ial MII Conversion Features
• Bidire c ti on a l wir e -speed interface conversion
• Serial Interface: 1000BASE-X or SGMII revision 1.8 (4, 6, or 8 Pins)
• Parallel Interface: GMII, RGMII (10, 100, and 1000Mbps) or 10/100 MII (DTE or DCE)
• 8-pin source-clocked SGMII mode
• 4-pin 1000BA SE-X SerDes mode to interface with optical modules
• Connects processors with parallel MII interfaces to 1000BASE-X SFP optical modules
• Connects processors with parallel MII interfaces to PHY or switch ICs with SGMII interfaces
• Interface conversion is transparent to MAC layer and higher layers
• Translates link speed and duplex mode between GMII/MII MDIO and SGMII PCS
MAX24288
4
Short Form Data Sheet
1588 Clock Feat ur es
• Steerable by software with 2-8ns time resolution and 2-32ns period resolution
• 1ns input timestamp accuracy and output edge placement accuracy
• Initialized and steered by software on an external processor to follow an external 1588 master
• Three time/frequency controls: direct time write, time adjustment, and high-resolution frequency adjustment
• Programmable clock and time-alignment I/O to synchronize all boards in large systems
o Can frequency-lock to an input clock signal from elsewhere in the system
o Can timestamp an input time alignment signal to time-lock to a master elsewhere in the system (e.g., 1 PPS)
o Can provide an output clock signal to slave components elsewhere in the system (125MHz/ N , 1 ≤ N ≤ 255)
o Can provide an output time alignment signal to slave components elsewhere in the system (e.g., 1 PPS)
• Input signal timestamper can stamp rising edges, falling edges or both
• Flexible programmable event generator (PEG) can output 1 PPS, one pulse per period, and a wide variety of
clock signals
• Full support for dual redundant timing cards to match architecture used in SONET/SDH
• Full support for switches and routers as transparent clocks or boundary clocks
• Compatible with a wide variety of 1588 system architectures
1588 Timestamper Features
• Identifies and timestamps 1588 v1 and v2 packets in both transmit and receive directions
• Programmable packet classifier can identify packets transported by a variety of protocol stacks
o 1588 over Ethernet
o 1588 over IPv4/UDP
o 1588 over IPv6/UDP
o 1588 over MPLS
o Configurable for more complex stacks as well
o Recognizes 802.1Q VLAN tags and 802.1ah MAC-in-MAC
o Can be configured to identify CESoP or SAToP for timing over adaptive-mode circuit emulation
• Transmit and receive timestamping with 1ns resolution
• One-step operation minimizes network bandwidth consumption
o On-the-fly timestamp insertion
o On-the-fly corrections in transparent clocks
o No need for follow-up packets
• Can insert ALL timestamps (receive and transmit) into packets for easy software access
o Three insert methods: direct overwrite, read-add-write, and read-subtract-write
o Eliminates reads from timestamp FIFOs
o Minimizes processor bus traffic
• Optional two-step operation
• Optional 8-entry timestamp FIFOs
Synchronous Ethernet Features
• Full support for 1588 over Synchronous Ethernet
• Receive path bit clock can be output on a GPIO pin to line-time the system from the Ethernet port
• Transmit path can be frequency-locked to a system clock signal connected to the REFCLK pin
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One Enterprise, Aliso Viejo
CA 92656 USA
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-6100
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