MCM44100B•MCM4L4100B
1
MOTOROLA DRAM
4M x 1 CMOS Dynamic RAM
Fast Page Mode
The MCM44100B is a 0.8µ CMOS high–speed dynamic random access memory.
It is organized as 4,194,304 one–bit words and fabricated with CMOS silicon–gate
process technology. Advanced circuit design and fine line processing provide high
performance, improved reliability, and low cost.
The MCM44100B requires only 11 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 300 mil J–lead small outline
package.
•Three–State Data Output
•Fast Page Mode
•Test Mode
•TTL–Compatible Inputs and Outputs
•RAS–Only Refresh
•CAS Before RAS Refresh
•Hidden Refresh
•1024 Cycle Refresh:
MCM44100B = 16 ms
MCM4L4100B = 128 ms
•Fast Access Time (tRAC):
MCM44100B–60 and MCM4L4100B–60 = 60 ns (Max)
MCM44100B–70 and MCM4L4100B–70 = 70 ns (Max)
MCM44100B–80 and MCM4L4100B–80 = 80 ns (Max)
•Low Active Power Dissipation:
MCM44100B–60 and MCM4L4100B–60 = 605 mW (Max)
MCM44100B–70 and MCM4L4100B–70 = 550 mW (Max)
MCM44100B–80 and MCM4L4100B–80 = 495 mW (Max)
•Low Standby Power Dissipation:
MCM44100B and MCM4L4100B = 11 mW (Max, TTL Levels)
MCM44100B = 5.5 mW (Max, CMOS Levels)
MCM4L4100B = 1.1 mW (Max, CMOS Levels)
Order this document
by MCM44100B/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
MCM44100B
MCM4L4100B
PIN NAMES
A0 – A10 Address Inputs. . . . . . . . . . . . .
D Data Input. . . . . . . . . . . . . . . . . . . . . . . .
Q Data Output. . . . . . . . . . . . . . . . . . . . .
WRead/Write Input. . . . . . . . . . . . . . . . .
RAS Row Address Strobe. . . . . . . . . . . .
CAS Column Address Strobe. . . . . . . . .
VCC Power Supply (+ 5 V). . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . .
N PACKAGE
300 MIL SOJ
CASE 822B-01
300 MIL SOJ
PIN ASSIGNMENT
5
4
3
2
1
14
15
16
17
18
13
12
11
10
9
22
23
24
25
26
A10
NC
RAS
W
D
VCC
A3
A2
A1
A0
A9
NC
CAS
Q
VSS
A4
A5
A6
A7
A8
REV 1
10/95
Motorola, Inc. 1995
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
MCM44100B•MCM4L4100B
2MOTOROLA DRAM
BLOCK DIAGRAM
RAS
CAS
W
VSS
VCC
1024
4096
Q
D
A9
A10
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW
ADDRESS
BUFFERS (11)
DATA OUT
BUFFER
COLUMN
DECODER
SENS AMP
I/O GATING
MEMORY
ARRAY
SUBSTRATE BIAS
GENERATOR
#2 CLOCK
GENERATOR
#1 CLOCK
GENERATOR
DATA IN
BUFFER
COLUMN
ADDRESS
BUFFERS (11)
ROW
DECODER
REFRESH
CONTROLLER
REFRESH
COUNTER (10)
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage VCC – 1 to + 7 V
Voltage Relative to VSS for Any Pin
Except VCC Vin, Vout – 1 to + 7 V
Data Out Current Iout 50 mA
Power Dissipation PD1 W
Operating Temperature Range TA0 to + 70 °C
Storage Temperature Range Tstg – 55 to + 125 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MCM44100B•MCM4L4100B
3
MOTOROLA DRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (All voltages referenced to VSS)
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V
VSS 0 0 0
Logic High Voltage, All Inputs VIH 2.4 — 6.5 V
Logic Low Voltage, All Inputs VIL – 1.0 — 0.8 V
DC CHARACTERISTICS AND SUPPLY CURRENTS
Characteristic Symbol Min Max Unit Notes
VCC Power Supply Current MCM44100B–60 and MCM4L4100B–60, tRC = 110 ns
MCM44100B–70 and MCM4L4100B–70, tRC = 130 ns
MCM44100B–80 and MCM4L4100B–80, tRC = 150 ns
ICC1 —
—
—
110
100
90
mA 1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 — 2.0 mA
VCC Power Supply Current During RAS–Only Refresh Cycles (CAS = VIH)
MCM44100B–60 and MCM4L4100B–60, tRC = 110 ns
MCM44100B–70 and MCM4L4100B–70, tRC = 130 ns
MCM44100B–80 and MCM4L4100B–80, tRC = 150 ns
ICC3 —
—
—
110
100
90
mA 1, 2
VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL)
MCM44100B–60 and MCM4L4100B–60, tPC = 45 ns
MCM44100B–70 and MCM4L4100B–70, tPC = 45 ns
MCM44100B–80 and MCM4L4100B–80, tPC = 50 ns
ICC4 —
—
—
110
100
90
mA 1, 3
VCC Power Supply Current (Standby) (RAS = CAS = VCC – 0.2 V) MCM44100B
MCM4L4100B
ICC5 —
—1.0
200 mA
µA
VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM44100B–60 and MCM4L4100B–60, tRC = 110 ns
MCM44100B–70 and MCM4L4100B–70, tRC = 130 ns
MCM44100B–80 and MCM4L4100B–80, tRC = 150 ns
ICC6 —
—
—
110
100
90
mA 1
VCC Power Supply Current, Battery Backup Mode — MCM4L4100B Only
(tRC = 125 µs; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC – 0.2 V;
Din = VCC – 0.2 V or 0.2 V or OPEN; A0 – A10 = VCC – 0.2 V or 0.2 V)
tRAS = 300 ns to 1 µs
tRAS = Min to 300 ns
ICC7
—
—400
300
µA 1, 4
Standby Current RAS = VIH
CAS = VIL
Q = Enable
ICC8 — 5 mA 1
Input Leakage Current (0 V ≤ Vin ≤ 6.5 V) Ilkg(I) – 10 10 µA
Output Leakage Current (CAS = VIH, 0 V ≤ Vout ≤ 5.5 V) Ilkg(O) – 10 10 µA
Output High Voltage (IOH = – 5 mA) VOH 2.4 VCC V
Output Low Voltage (IOL = 4.2 mA) VOL 0 0.4 V
NOTES:
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Column address can be changed once or less while RAS = VIL.
3. Column address can be changed once or less while CAS = VIH.
4. tRAS (max) = 1 µs is only applied to refresh of battery–back up. tRAS (max) = 10 µs is applied to functional operating.
CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic Symbol Max Unit
Input Capacitance A0 – A10, D Cin 5 pF
RAS, CAS, W 7
I/O Capacitance (CAS = VIH to Disable Output) Q Cout 7 pF
NOTE:Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
MCM44100B•MCM4L4100B
4MOTOROLA DRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol MCM44100B–60
MCM4L4100B–60 MCM44100B–70
MCM4L4100B–70 MCM44100B–80
MCM4L4100B–80
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Random Read or Write Cycle Time tRELREL tRC 110 — 130 — 150 — ns 5
Read–Write Cycle Time tRELREL tRWC 130 — 155 — 175 — ns 5
Fast Page Mode Cycle Time tCELCEL tPC 40 — 45 — 50 — ns
Fast Page Mode Read–Write Cycle
Time tCELCEL tPRWC 60 — 70 — 75 — ns
Access Time from RAS tRELQV tRAC — 60 — 70 — 80 ns 6,7,8
Access Time from CAS tCELQV tCAC — 15 — 20 — 20 ns 6,8,9,10
Access Time from Column Address tAVQV tAA — 30 — 35 — 40 ns 6,8,10,11
Access Time from Precharge CAS tCEHQV tCPA — 35 — 40 — 45 ns 6,8,10
Output Buffer and Turn–Off Delay tCEHQZ tOFF 0 15 0 20 0 20 ns 12
Transition Time (Rise and Fall) tTtT3 50 3 50 3 50 ns 1
RAS Precharge Time tREHREL tRP 45 — 50 — 60 — ns
RAS Pulse Width tRELREH tRAS 60 10 k 70 10 k 80 10 k ns
RAS Pulse Width (Fast Page
Mode) tRELREH tRASP — 100 k — 100 k — 100 k ns
RAS Hold Time tCELREH tRSH 15 — 20 — 20 — ns
CAS Hold Time tRELCEH tCSH 60 — 70 — 80 — ns
CAS Precharge to RAS Hold Time tCEHREH tRHCP 35 — 40 — 45 — ns
CAS Pulse Width tCELCEH tCAS 15 10 k 20 10 k 20 10 k ns
RAS to CAS Delay Time tRELCEL tRCD 20 45 20 50 20 60 ns 13
RAS to Column Address Delay
Time tRELAV tRAD 15 30 15 35 15 40 ns 14
CAS to RAS Precharge Time tCEHREL tCRP 10 — 10 — 10 — ns
CAS Precharge Time tCEHCEL tCP 10 — 10 — 10 — ns
Row Address Setup Time tAVREL tASR 0 — 0 — 0 — ns
Row Address Hold Time tRELAX tRAH 10 — 10 — 10 — ns
NOTES: (continued)
11. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. T ransition times are measured between VIH and VIL.
12.An initial pause of 100 µs is required after power–up followed by 8 initialization cycles (RAS only refresh cycle or CAS before RAS refresh
cycle) before proper device operation is guaranteed.
13.The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
14.AC measurements assume tT = 5.0 ns.
15.The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range is ensured.
16.Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
17.Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown
in this table, tRAC exceeds the value shown.
18.In a test mode read cycle, the value of tRAC, tAA, tCAC, and tCPA is delayed for 2 ns to 5 ns for the specified value. These parameters should
be in the test mode cycles by adding the above value to the specified value in the data sheet.
9.Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
10.Access time is determined by the longer of tAA or tCAC or tCPA.
11. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
12.tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
13.Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD
is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
14.Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD
is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.
MCM44100B•MCM4L4100B
5
MOTOROLA DRAM
READ, WRITE, AND READ–WRITE CYCLES (Continued)
Symbol MCM44100B–60
MCM4L4100B–60 MCM44100B–70
MCM4L4100B–70 MCM44100B–80
MCM4L4100B–80
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Column Address Setup Time tAVCEL tASC 0 — 0 — 0 — ns
Column Address Hold Time tCELAX tCAH 15 — 15 — 15 — ns
Column Address to RAS Lead Time tAVREH tRAL 30 — 35 — 40 — ns
Read Command Setup Time tWHCEL tRCS 0 — 0 — 0 — ns
Read Command Hold Time
Referenced to CAS tCEHWX tRCH 0 — 0 — 0 — ns 15
Read Command Hold Time
Referenced to RAS tREHWX tRRH 0 — 0 — 0 — ns 15
Write Command Hold Time
Referenced to CAS tCELWH tWCH 15 — 10 — 10 — ns
Write Command Pulse Width tWLWH tWP 10 — 15 — 15 — ns
Write Command to RAS Lead Time tWLREH tRWL 15 — 20 — 20 — ns
Write Command to CAS Lead Time tWLCEH tCWL 15 — 20 — 20 — ns
Data in Setup Time tDVCEL tDS 0 — 0 — 0 — ns 16
Data in Hold Time tCELDX tDH 15 — 15 — 15 — ns 16
Refresh Period MCM44100B
MCM4L4100B tRVRV tRFSH —
—16
128 —
—16
128 —
—16
128 ms
Write Command Setup Time tWLCEL tWCS 0 — 0 — 0 — ns 17
CAS to Write Delay tCELWL tCWD 15 — 20 — 20 — ns 17
RAS to Write Delay tRELWL tRWD 60 — 70 — 80 — ns 17
Column Address to Write Delay
Time tAVWL tAWD 30 — 35 — 40 — ns 17
CAS Precharge to Write Delay
Time (Page Mode) tCEHWL tCPWD 35 — 40 — 45 — ns 17
CAS Setup Time for CAS Before
RAS Refresh tRELCEL tCSR 10 — 5 — 5 — ns
CAS Hold Time for CAS Before
RAS Refresh tRELCEH tCHR 10 — 10 — 10 — ns
RAS Precharge to CAS Active Time tREHCEL tRPC 10 — 10 — 10 — ns
CAS Precharge Time for CAS
Before RAS Counter Time tCEHCEL tCPT 40 — 40 — 40 — ns
Write Command Setup Time
(Test Mode) tWLREL tWTS 0 — 0 — 0 — ns
Write Command Hold Time
(Test Mode) tRELWH tWTH 10 — 10 — 10 — ns
Write to RAS Precharge Time
(CAS Before RAS Refresh) tWHREL tWRP 0 — 0 — 0 — ns
Write to RAS Hold Time
(CAS Before RAS Refresh) tRELWL tWRH 10 — 10 — 10 — ns
NOTES:
15.Either tRRH or tRCH must be satisfied for a read cycle.
16.These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in read–write cycles.
17.tWCS, tRWD, tCWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance)
throughout the entire cycle; if tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min), and tCPWD ≥ tCPWD (min) (page mode),
the cycle is a read–write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
MCM44100B•MCM4L4100B
6MOTOROLA DRAM
READ CYCLE
HIGH–Z
tCSH
VALID DATA
D (DATA OUT) OL
VOH
V
RCS
tRCH
t
RRH
t
OFF
t
CAC
t
AA
t
RAC
t
tCAS
W
CAS
RAS
ADDRESSES
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
RAH
t
CAH
t
ASR
tRAD
t
ASC
t
CRP
t
CP
t
CRP
tRCD
tRSH
t
RP
t
RAS
tRC
t
ROW
ADDRESS COLUMN
ADDRESS
EARLY WRITE CYCLE
WCS
tWCH
t
CWL
t
RWL
t
DH
t
tCAS
W
CAS
RAS
OL
VOH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
DS
t
WP
t
RAH
t
CAH
t
ASR
tRAD
t
ASC
t
CSH
tCRP
t
CP
t
CRP
tRCD
tRSH
t
RP
t
RAS
tRC
t
HIGH–Z
VALID DATA
D (DATA OUT)
D (DATA IN)
ADDRESSES COLUMN
ADDRESS
ROW
ADDRESS
MCM44100B•MCM4L4100B
7
MOTOROLA DRAM
READ–WRITE CYCLE
W
CAS
RAS
HIGH–Z
VALID DATA
VALID DATA
D (DATA OUT)
D (DATA IN)
ADDRESSES
OL
VOH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
RAC
tOFF
t
AA
tCAC
t
DH
t
DS
t
RCS
t
WP
t
CWD
t
RWD
tAWD
t
RAH
t
CAH
t
ASR
tASC
t
RAD
tCWL
t
CSH
t
CRP
t
CP
t
RWL
t
CAS
t
CRP
tRCD
tRSH
t
RP
t
RAS
tRWC
t
ROW
ADDRESS COLUMN
ADDRESS
FAST PAGE MODE READ CYCLE
CPA
tCPA
t
W
CAS
RAS
D (DATA OUT)
ADDRESSES
CP
t
CAH
tCAH
t
RCH
t
RCH
tRRH
t
OFF
tOFF
t
CAC
tCAC
t
AA
tAA
t
RCS
t
RCS
t
ASC
t
ASC
t
CP
t
CAS
t
CAS
t
OL
VOH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
RAC
t
OFF
t
AA
t
CAC
t
PC
t
RCS
t
CRP
t
RAH
tRCH
t
CAH
t
ASR
tASC
t
RAD
t
CSH
t
CP
tCAS
tRSH
t
RCD
t
RASP
tRP
t
RHCP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
VALID
DATA VALID
DATA VALID
DATA
MCM44100B•MCM4L4100B
8MOTOROLA DRAM
FAST PAGE MODE EARLY WRITE CYCLE
IL
VIH
V
D (DATA IN)
D (DATA OUT) OL
VOH
VHIGH–Z
VALID DATA
VALID DATA
VALID DATA
CAH
t
WCS
t
WCS
tWCS
t
WCH
tWCH
t
WCH
t
WP
t
WP
t
WP
t
DS
tt
DS
tt DH
t
DH
t
DS
tt DH
t
RAH
t
W
CAS
RAS
ADDRESSES
CP
t
CAH
t
ASC
t
CP
t
CAS
t
CAS
t
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
PC
t
CRP
t
CAH
t
ASR
t
ASC
t
RAD
t
CP
t
CAS
tRSH
t
RCD
t
RASP
tRP
t
RHCP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
ASC
t
FAST PAGE MODE READ–WRITE CYCLE
CWD
t
CP
tCP
t
CP
tPRWC
t
CSH
t
CWL
t
CWL
tRWL
t
CWD
t
CPWD
t
AWD
tAWD
t
DH
tDH
t
DS
tDS
t
WP
tWP
t
CPA
t
AA
tAA
t
CAC
tCAC
t
OFF
t
OFF
tOFF
t
CPA
t
RAC
tAA
t
CAC
t
CPWD
t
WP
t
DH
t
DS
t
RWD
t
CWL
t
CWD
t
AWD
t
RCS
t
ASC
t
CAH
t
CAH
tASC
t
CAS
t
CAS
t
IL
VIH
V
D (DATA IN)
D (DATA OUT) OL
VOH
V
RAH
t
W
CAS
RAS
ADDRESSES
IL
VIH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
RAL
t
CRP
t
CAH
t
ASR
tASC
t
RAD
t
CAS
t
RSH
t
RCD
t
RASP
tRP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
VALID
DATA VALID
DATA VALID
DATA
VALID
DATA VALID
DATA VALID
DATA
MCM44100B•MCM4L4100B
9
MOTOROLA DRAM
RAS–ONLY REFRESH CYCLE
(W and A10 are Don’t Care)
A0 – A9
RPC
t
RAH
t
ASR
t
CRP
t
RP
t
RAS
t
RC
t
HIGH–Z
IL
VIH
V
IL
VIH
V
D (DATA OUT) OL
VOH
V
IL
VIH
VROW
ADDRESS
RAS
CAS
CAS BEFORE RAS REFRESH CYCLE
(A0 – A10 are Don’t Care)
HIGH–Z
WIL
VIH
VWRH
t
OFF
t
CHR
t
WRP
t
CP
t
CSR
t
RPC
t
RP
t
RAS
t
RC
t
CAS IL
VIH
V
RAS IL
VIH
V
D (DATA OUT) OL
VOH
V
MCM44100B•MCM4L4100B
10 MOTOROLA DRAM
HIDDEN REFRESH CYCLE
tRAH
tASR tASC
tRSH
tRAL
tRAD
tRCD
tT
tRAS
(REFRESH)
tRAS
(REFRESH)
WE
CAS
RAS
ADDRESS
Dout VALID OUTPUT
tRC tRC tRC
tRAS
(READ) tRP
tRP tRP
tCRP
tCHR
tCAH
tRCS tRCH
tRRH
tCAC
tAA
tRAC tOFF
ROW COLUMN
tCAS
IL
VIH
V
OL
VOH
V
IL
VIH
V
IL
VIH
V
IL
VIH
V
HIDDEN REFRESH CYCLE (EARLY WRITE)
HIGH–Z
IL
VIH
V
D (DATA OUT) OL
VOH
V
DH
t
DS
tWP
t
WRP
tWRH
t
WCS
tWCH
t
RWL
t
VALID DATA
COLUMN
ADDRESS
RAL
t
CAH
t
RAD
t
ASC
t
RAH
t
ASR
t
CHR
t
RAS
t
D (DATA IN) IL
VIH
V
WIL
VIH
V
CAS
RAS
ADDRESSES IL
VIH
V
IL
VIH
VCP
t
CRP
tRCD
tRSH
t
RP
tRAS
t
RC
t
ROW
ADDRESS
MCM44100B•MCM4L4100B
11
MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
WCH
t
CSR
t
Q (DATA OUT) OL
VOH
V
WIL
VIH
V
D (DATA IN)
WRP
tWRH
tCWL
t
RWL
t
AWD
t
DH
t
DS
t
WP
t
CAC
t
OFF
t
AA
t
CWL
t
CWD
t
RCS
t
WRP
tWRH
t
DH
t
DS
t
WP
t
WCS
t
RWL
t
D (DATA IN)
Q (DATA OUT) OL
VOH
V
WIL
VIH
V
Q (DATA OUT) OL
VOH
V
WIL
VIH
VRCH
t
RCS
t
CPT
t
CAH
t
ASC
t
RAL
t
RRH
t
CAS
t
RSH
t
WRP
tWRH
t
CHR
t
RAS
t
OFF
t
CAC
t
AA
t
CAS IL
VIH
V
RAS
ADDRESSES IL
VIH
V
RP
t
HIGH–Z
HIGH–Z
COLUMN ADDRESS
VALID DATA
VALID DATA
VALID DATA
VALID DATA
READ–WRITE CYCLE
EARLY WRITE CYCLE
READ CYCLE
IL
VIH
V
IL
VIH
V
IL
VIH
V
HIGH–Z
MCM44100B•MCM4L4100B
12 MOTOROLA DRAM
DEVICE INITIALIZATION
On power–up, an initial pause of 100 microseconds is
required for the internal substrate generator to establish the
correct bias voltage. This must be followed by a minimum of
eight active cycles of the row address strobe (clock) to
initialize all dynamic nodes within the RAM. During an
extended inactive state (greater than 16 milliseconds or 128
milliseconds in case of low power device, with the device
powered up), a wakeup sequence of eight active cycles is
necessary to ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multi-
plexed at the beginning of a memory cycle by two clocks,
row address strobe (RAS) and column address strobe
(CAS), into two separate 11–bit address fields. A total of
twenty–two address bits, eleven rows and eleven columns,
will decode one of the 4,194,304 bit locations in the device.
RAS active transition is followed by CAS active transition
(active = VIL, tRCD minimum) for all read or write cycles. The
delay between RAS and CAS active transitions, referred to
as the multiplex window, gives a system designer flexibility
in setting up the external addresses into the RAM.
The external CAS signal is ignored until an internal RAS
signal is available. This “gate” feature on the external CAS
clock enables the internal CAS line as soon as the row
address hold time (tRAH) specification is met (and defines
tRCD minimum). The multiplex window can be used to
absorb skew delays in switching the address bus from row
to column addresses and in generating the CAS clock.
There are three other variations in addressing the 4M
RAM: RAS–only refresh cycle, CAS before RAS refresh
cycle, and page mode.
READ CYCLE
The DRAM may be read with four different cycles: “nor-
mal” random read cycle, page mode read cycle, read–write
cycle, and page mode read–write cycle. The normal read
cycle is outlined here, while the other cycles are discussed
in separate sections.
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latch-
ing the desired bit location. The write (W) input level must be
high (VIH), tRCS (minimum) before the CAS active transition,
to enable read mode.
Both the RAS and CAS clocks trigger a sequence of
events that are controlled by several delayed internal clocks.
The internal clocks are linked in such a manner that the read
access time of the device is independent of the address mul-
tiplex window; however, CAS must be active before or at
tRCD maximum to guarantee valid data out (Q) at tRAC
(access time from RAS active transition). If the tRCD maxi-
mum is exceeded, read access time is determined by the
CAS clock active transition (tCAC).
The RAS and CAS clocks must remain active for mini-
mum times of tRAS and tCAS, respectively, to complete the
read cycle. W must remain high throughout the cycle, and
for time tRRH or tRCH after RAS or CAS inactive transition,
respectively, to maintain the data at that bit location. Once
RAS transitions to inactive, it must remain inactive for a
minimum time of tRP to precharge the internal device cir-
cuitry for the next active cycle. Q is valid, but not latched, as
long as the CAS clock is active. When the CAS clock transi-
tions to inactive, the output will switch to High–Z (three–
state).
WRITE CYCLE
The user can write to the DRAM with any of four cycles:
early write, late write, page mode early write, and page
mode read–write. Early and late write modes are discussed
here, while page mode write operations are covered
elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIL). Early and late write modes are distinguished by the
active transition of W, with respect to CAS. Minimum active
time tRAS and tCAS, and precharge time tRP apply to write
mode, as in the read mode.
An early write cycle is characterized by W active transition
at minimum time tWCS before CAS active transition. Data
in (D) is referenced to CAS in an early write cycle. RAS
and CAS clocks must stay active for tRWL and tCWL,
respectively, after the start of the early write operation to
complete the cycle.
Q remains in three–state condition throughout an early
write cycle because W active transition precedes or coin-
cides with CAS active transition, keeping data–out buffers
disabled. This feature can be utilized on systems with a
common I/O bus, provided all writes are performed with
early write cycles, to prevent bus contention.
A late write cycle occurs when W active transition is made
after CAS active transition. W active transition could be
delayed for almost 10 microseconds after CAS active tran-
sition, (tRCD + tCWD + tRWL + 2tT) ≤ tRAS, if other timing
minimums (tRCD, tRWL, and tT) are maintained. D is refer-
enced to W active transition in a late write cycle. Output
buffers are enabled by CAS active transition but Q may be
indeterminate (see note 17 of the AC Operating Conditions
table). RAS and CAS must remain active for tRWL and tCWL,
respectively, after W active transition to complete the write
cycle.
READ–WRITE CYCLE
A read–write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussed in the WRITE CYCLE sec-
tion, except W must remain high for tCWD minimum after
the CAS active transition, to guarantee valid Q before writing
the bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 4M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC. Page mode opera-
tion consists of keeping RAS active while toggling CAS be-
tween VIH and VIL. The row is latched by RAS active
transition, while each CAS active transition allows selection
of a new column location on the row.
A page mode cycle is initiated by a normal read, write, or
read–write cycle, as described in prior sections. Once the
timing requirements for the first cycle are met, CAS transi-
tions to inactive for minimum of tCP, while RAS remains low
(VIL). The second CAS active transition while RAS is low
initiates the first page mode cycle (tPC or tPRWC). Either a
MCM44100B•MCM4L4100B
13
MOTOROLA DRAM
read, write, or read–write operation can be performed in a
page mode cycle, subject to the same conditions as in nor-
mal operation (previously described). These operations can
be intermixed in consecutive page mode cycles and per-
formed in any order. The maximum number of consecutive
page mode cycles is limited by tRASP. Page mode operation
is ended when RAS transitions to inactive, coincident with or
following CAS inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Each bit must be peri-
odically refreshed (recharged) to maintain the correct bit
state. Bits in the MCM44100B require refresh every 16 milli-
seconds, while refresh time for the MCM4L4100B is 128 mil-
liseconds.
This is accomplished by cycling through the 1024 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row
is addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM44100B, and 124.8 micro-
seconds for the MCM4L4100B. Burst refresh, a refresh of all
1024 rows consecutively, must be performed every 16 milli-
seconds on the MCM44100B and 128 milliseconds on the
MCM4L4100B.
A normal read, write, or read–write operation to the RAM
will refresh all the bits (4096) associated with the particular
row decoded. Three other methods of refresh, RAS–only
refresh, CAS before RAS refresh, and hidden refresh are
available on this device for greater system flexibility.
RAS–Only Refresh
RAS–only refresh consists of RAS transition to active,
latching the row address to be refreshed, while CAS remains
high (VIH) throughout the cycle. An external counter is
employed to ensure all rows are refreshed within the speci-
fied limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS
active before RAS. This clock order activates an internal
refresh counter that generates the row address to be
refreshed. External address lines are ignored during the
automatic refresh cycle. The output buffer remains at the
same state it was in during the previous cycle (hidden
refresh). W must be inactive for time tWRP before and time
tWRH after RAS active transition to prevent switching the de-
vice into test mode.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while main-
taining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for
tRP and back to active, starts the hidden refresh. This is
essentially the execution of a CAS before RAS refresh from
a cycle in progress (see Figure 1). W is subject to the same
conditions with respect to RAS active transition (to prevent
test mode entry) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested
with a CAS before RAS refresh counter test. This test is
performed with a read–write operation. During the test, the
internal refresh counter generates the row address, while
the external address supplies the column address. The en-
tire array is refreshed after 1024 cycles, as indicated by the
check data written in each row. See CAS before RAS
refresh counter test cycle timing diagram.
The test can be performed after a minimum of 8 CAS
before RAS initialization cycles. Test procedure:
1. Write 0s into all memory cells with normal write mode.
2. Select a column address, read 0 out and write 1 into the
cell by performing the CAS before RAS refresh count-
er test, read–write cycle. Repeat this operation 1024
times.
3. Read the 1s which were written in step two in normal
read mode.
4. Using the same starting column address as in step two,
read 1 out and write 0 into the cell by performing the CAS
before RAS refresh counter test, read–write cycle.
Repeat this operation 1024 times.
5. Read 0s which were written in step four in normal read
mode.
6. Repeat steps one through five using complement data.
HIGH–Z
Q
CAS
RAS
VALID DATA OUT
MEMORY CYCLE CAS BEFORE RAS
REFRESH CYCLE CAS BEFORE RAS
REFRESH CYCLE
Figure 1. Hidden Refresh Cycle
MCM44100B•MCM4L4100B
14 MOTOROLA DRAM
TEST MODE
The internal organization of this device (512K x 8) allows
it to be tested as if it were a 512K x 1 DRAM. Nineteen of
the twenty two addresses are used when operating the de-
vice in test mode. Row address A0, and column addresses
A0 and A10 are ignored by the device in test mode. A test
mode cycle reads and/or writes data to a bit in each of eight
512K blocks (B0 – B7) in parallel. External data out is deter-
mined by the internal test mode logic of the device. See the
following truth table and test mode block diagram.
W, CAS before RAS timing puts the device in Test Mode
as shown in the test mode timing diagram. A CAS before
RAS or a RAS–only refresh cycle puts the device back into
normal mode. Refresh is performed in test mode by using a
W, CAS before RAS refresh cycle which uses internal
refresh address counter.
TEST MODE TRUTH TABLE
D B0 B1 B2 B3 B4 B5 B6 B7 Q
0 0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 1 1
— Any Other 0
W, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(D and A0 – A10 are Don’t Care)
IL
VIH
V
W
CAS
RAS
Q (DATA OUT)
IL
VIH
V
IL
VIH
V
OL
VOH
V
tRC
tRAS tRP
tRPC tCHR
tCSR
tCP
tWTH
tWTS
tOFF
HIGH–Z
TEST MODE – READ CYCLE
IL
VIH
V
IL
VIH
V
IL
VIH
V
HIGH–Z
OL
V
OH
V
Q (DATA OUT)
W
CAS
RAS
tRP
tRAS
tRC
tRAC VALID DATA
tCAC
tAA
tRCS
tOFF
tRCH
tRRH
ROW
ADDRESS COLUMN ADDRESS
tASR tRAH
ADDRESSES
IL
VIH
VtRCD tCSH tRSH
tCAS
tCRP
tRAD
tCRP
tASC
tRAL
tCAH
MCM44100B•MCM4L4100B
15
MOTOROLA DRAM
TEST MODE – EARLY WRITE CYCLE
IL
VIH
V
RAS
tRP
tRAS
tRC
CAS IL
VIH
V
tRCD tRSH
tCAS
tCRP tCSH
IL
V
IH
VROW
ADDRESS COLUMN ADDRESS
ADDRESSES
tCAH
tRAD tRAL
tRAH tASC
tASR
tCWL
tWP
tWCH
VALID DATA
tRWL
tDS tDH
Q (DATA OUT) HIGH–Z
OH
V
OL
V
IL
VIH
V
IL
VIH
V
W
D (DATA IN)
tWCS
CRP
t
TEST MODE – FAST PAGE MODE READ CYCLE
tCAC
tCAC
tOFF tOFF
tOFF
tRAC
tCAC
tRRH
tAA tAA
tAA
tRCH
tRCS tRCS
tRCH
tRCS
tCAH
tRAL
tASC
tCAH
tASC
tRAH
tASR tASC tCAH
tCAS
tRSH
tCAS
tCAS
tRCD
tCRP tRHCP
tRP
tRASP
IL
VIH
V
IL
VIH
V
IL
V
IH
V
IL
VIH
V
Q (DATA OUT)
W
ADDRESSES
CAS
RAS
ROW
ADD COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA OUT VALID
DATA OUT VALID
DATA OUT
tCP
OL
V
OH
V
tRCH
tCPA
tPC
tCP
tCSH
tRAD
tCPA
MCM44100B•MCM4L4100B
16 MOTOROLA DRAM
TEST MODE – FAST PAGE MODE EARLY WRITE CYCLE
IL
VIH
V
tDH
tDS
tDH
tDS
tDH
tDS
tWCH
tWP
tWP
tWP
tRAD
tCAH
tRAL
tASC
tCAH
tASC
tRAH
tASR
tASC
tCAH
tCAS
tRSH
tCAS
tCAS
tRCD
tCRP
tRHCP
tRP
tRASP
IL
V
IH
V
IL
V
IH
V
IL
VIH
V
W
Q (DATA IN)
ADDRESSES
CAS
RAS
VALID
DATA IN VALID
DATA IN VALID
DATA IN
ROW
ADD COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
IL
V
IH
V
tCP
tWCS
tWCS tWCS
tPC
tWCH
tWCH
tCP
Q (DATA OUT) HIGH–Z
OH
V
OL
V
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
MCM 44100B or 4L4100B X XX XX
Package (N = 300 mil SOJ)
Shipping Method (R2 = Tape and Reel, Blank = Rails)
Speed (60 = ns, 70 = 70 ns, 80 = 80 ns)
Full Part Numbers — MCM44100BN60 MCM44100BN60R2
MCM44100BN70 MCM44100BN70R2
MCM44100BN80 MCM44100BN80R2
MCM4L4100BN60 MCM4L4100BN60R2
MCM4L4100BN70 MCM4L4100BN70R2
MCM4L4100BN80 MCM4L4100BN80R2
MCM44100B•MCM4L4100B
17
MOTOROLA DRAM
N PACKAGE
300 MIL SOJ
CASE 822B–01
PACKAGE DIMENSIONS
0.004 (0.10)
DIM
AMIN MAX MIN MAX
MILLIMETERS
0.661 0.680 16.79 17.27
INCHES
B0.295 0.305 7.50 7.74
C0.128 0.148 3.25 3.76
D0.015 0.021 0.38 0.53
E0.085 0.103 2.16 2.61
F0.026 0.032 0.66 0.81
G0.050 BSC 1.27 BSC
H––– 0.020 ––– 0.50
K0.025 0.045 0.63 1.14
L0.100 BSC 2.54 BSC
M0 20 0 20
N0.035 0.059 0.89 1.50
P0.330 0.340 8.39 8.63
R0.260 0.275 6.60 6.98
S0.027 0.040 0.69 1.02
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.006 (0.15) PER SIDE.
4. DIMENSION R TO BE DETERMINED AT DATUM
-T-.
5. FOR LEAD IDENTIFICATION PURPOSES PIN
POSITIONS 6, 7, 8, 19, 20 AND 21 ARE NOT USED.
-T-
_ _ _ _
15
26 14
9
18
13
22
MG
F
H
K
L
20X
RADIUS
BRK
E
R
C
D
DETAIL Z
N
0.007 (0.18) MT A S
-A-
SEATING
PLANE
DETAIL Z
0.010 (0.25) MT B S
0.007 (0.18) MT B S
P
S
-B-
M
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
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MCM44100B•MCM4L4100B
18 MOTOROLA DRAM
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MCM44100B/D
*MCM44100B/D*
◊
