MOTOROLA Order this document by MCM44100B/D SEMICONDUCTOR TECHNICAL DATA 4M x 1 CMOS Dynamic RAM MCM44100B MCM4L4100B Fast Page Mode The MCM44100B is a 0.8 CMOS high-speed dynamic random access memory. It is organized as 4,194,304 one-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The MCM44100B requires only 11 address lines; row and column address inputs are multiplexed. The device is packaged in a standard 300 mil J-lead small outline package. * * * * * * * * Three-State Data Output Fast Page Mode Test Mode TTL-Compatible Inputs and Outputs RAS-Only Refresh CAS Before RAS Refresh Hidden Refresh 1024 Cycle Refresh: MCM44100B = 16 ms MCM4L4100B = 128 ms * Fast Access Time (tRAC): MCM44100B-60 and MCM4L4100B-60 = 60 ns (Max) MCM44100B-70 and MCM4L4100B-70 = 70 ns (Max) MCM44100B-80 and MCM4L4100B-80 = 80 ns (Max) * Low Active Power Dissipation: MCM44100B-60 and MCM4L4100B-60 = 605 mW (Max) MCM44100B-70 and MCM4L4100B-70 = 550 mW (Max) MCM44100B-80 and MCM4L4100B-80 = 495 mW (Max) * Low Standby Power Dissipation: MCM44100B and MCM4L4100B = 11 mW (Max, TTL Levels) MCM44100B = 5.5 mW (Max, CMOS Levels) MCM4L4100B = 1.1 mW (Max, CMOS Levels) N PACKAGE 300 MIL SOJ CASE 822B-01 PIN NAMES A0 - A10 . . . . . . . . . . . . . Address Inputs D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output W . . . . . . . . . . . . . . . . . Read/Write Input RAS . . . . . . . . . . . . Row Address Strobe CAS . . . . . . . . . Column Address Strobe VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . No Connection PIN ASSIGNMENT 300 MIL SOJ D 1 26 VSS W 2 25 Q RAS 3 24 CAS NC 4 23 NC A10 5 22 A9 A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 REV 1 10/95 Motorola, Inc. 1995 MOTOROLA DRAM MCM44100B*MCM4L4100B 1 BLOCK DIAGRAM W CAS #2 CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RAS COLUMN ADDRESS BUFFERS (11) DATA IN BUFFER D DATA OUT BUFFER Q COLUMN DECODER REFRESH CONTROLLER SENS AMP I/O GATING REFRESH COUNTER (10) 4096 ROW ADDRESS BUFFERS (11) ROW DECODER 1024 #1 CLOCK GENERATOR MEMORY ARRAY SUBSTRATE BIAS GENERATOR VCC VSS ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VCC - 1 to + 7 V Vin, Vout - 1 to + 7 V Data Out Current Iout 50 mA Power Dissipation PD 1 W Operating Temperature Range TA 0 to + 70 C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. Storage Temperature Range Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM44100B*MCM4L4100B 2 MOTOROLA DRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (All voltages referenced to VSS) Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 Logic High Voltage, All Inputs VIH 2.4 -- 6.5 V Logic Low Voltage, All Inputs VIL - 1.0 -- 0.8 V Parameter Supply Voltage (Operating Voltage Range) DC CHARACTERISTICS AND SUPPLY CURRENTS Characteristic Symbol Min Max Unit Notes ICC1 -- -- -- 110 100 90 mA 1, 2 VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 -- 2.0 mA VCC Power Supply Current During RAS-Only Refresh Cycles (CAS = VIH) MCM44100B-60 and MCM4L4100B-60, tRC = 110 ns MCM44100B-70 and MCM4L4100B-70, tRC = 130 ns MCM44100B-80 and MCM4L4100B-80, tRC = 150 ns ICC3 -- -- -- 110 100 90 VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL) MCM44100B-60 and MCM4L4100B-60, tPC = 45 ns MCM44100B-70 and MCM4L4100B-70, tPC = 45 ns MCM44100B-80 and MCM4L4100B-80, tPC = 50 ns ICC4 -- -- -- 110 100 90 VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) ICC5 -- -- 1.0 200 -- -- -- 110 100 90 VCC Power Supply Current MCM44100B-60 and MCM4L4100B-60, tRC = 110 ns MCM44100B-70 and MCM4L4100B-70, tRC = 130 ns MCM44100B-80 and MCM4L4100B-80, tRC = 150 ns MCM44100B MCM4L4100B VCC Power Supply Current During CAS Before RAS Refresh Cycle MCM44100B-60 and MCM4L4100B-60, tRC = 110 ns MCM44100B-70 and MCM4L4100B-70, tRC = 130 ns MCM44100B-80 and MCM4L4100B-80, tRC = 150 ns ICC6 VCC Power Supply Current, Battery Backup Mode -- MCM4L4100B Only (tRC = 125 s; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC - 0.2 V; Din = VCC - 0.2 V or 0.2 V or OPEN; A0 - A10 = VCC - 0.2 V or 0.2 V) tRAS = 300 ns to 1 s tRAS = Min to 300 ns ICC7 Standby Current mA 1, 2 mA 1, 3 mA A mA 1 A 1, 4 1 -- -- 400 300 ICC8 -- 5 mA Input Leakage Current (0 V Vin 6.5 V) Ilkg(I) - 10 10 A Output Leakage Current (CAS = VIH, 0 V Vout 5.5 V) Ilkg(O) - 10 10 A VOH 2.4 VCC V RAS = VIH CAS = VIL Q = Enable Output High Voltage (IOH = - 5 mA) Output Low Voltage (IOL = 4.2 mA) VOL 0 0.4 V NOTES: 1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open. 2. Column address can be changed once or less while RAS = VIL. 3. Column address can be changed once or less while CAS = VIH. 4. tRAS (max) = 1 s is only applied to refresh of battery-back up. tRAS (max) = 10 s is applied to functional operating. CAPACITANCE (f = 1.0 MHz, TA = 25C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested) Characteristic Input Capacitance A0 - A10, D Symbol Max Unit Cin 5 pF RAS, CAS, W 7 I/O Capacitance (CAS = VIH to Disable Output) Q Cout NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I t/V. MOTOROLA DRAM 7 pF MCM44100B*MCM4L4100B 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4) MCM44100B-60 MCM44100B-70 MCM4L4100B-60 MCM4L4100B-70 Symbol MCM44100B-80 MCM4L4100B-80 Parameter Std Alt Min Max Min Max Min Max Unit Notes Random Read or Write Cycle Time tRELREL tRC 110 -- 130 -- 150 -- ns 5 Read-Write Cycle Time tRELREL tRWC 130 -- 155 -- 175 -- ns 5 Fast Page Mode Cycle Time tCELCEL tPC 40 -- 45 -- 50 -- ns Fast Page Mode Read-Write Cycle Time tCELCEL tPRWC 60 -- 70 -- 75 -- ns Access Time from RAS tRELQV tRAC -- 60 -- 70 -- 80 ns Access Time from CAS 6,7,8 tCELQV tCAC -- 15 -- 20 -- 20 ns 6,8,9,10 Access Time from Column Address tAVQV tAA -- 30 -- 35 -- 40 ns 6,8,10,11 Access Time from Precharge CAS tCEHQV tCPA -- 35 -- 40 -- 45 ns 6,8,10 Output Buffer and Turn-Off Delay tCEHQZ tOFF 0 15 0 20 0 20 ns 12 1 Transition Time (Rise and Fall) tT tT 3 50 3 50 3 50 ns RAS Precharge Time tREHREL tRP 45 -- 50 -- 60 -- ns RAS Pulse Width tRELREH tRAS 60 10 k 70 10 k 80 10 k ns RAS Pulse Width (Fast Page Mode) tRELREH tRASP -- 100 k -- 100 k -- 100 k ns RAS Hold Time tCELREH tRSH 15 -- 20 -- 20 -- ns CAS Hold Time tRELCEH tCSH 60 -- 70 -- 80 -- ns CAS Precharge to RAS Hold Time tCEHREH tRHCP 35 -- 40 -- 45 -- ns CAS Pulse Width tCELCEH tCAS 15 10 k 20 10 k 20 10 k ns RAS to CAS Delay Time tRELCEL tRCD 20 45 20 50 20 60 ns 13 tRELAV tRAD 15 30 15 35 15 40 ns 14 CAS to RAS Precharge Time tCEHREL tCRP 10 -- 10 -- 10 -- ns CAS Precharge Time tCEHCEL tCP 10 -- 10 -- 10 -- ns RAS to Column Address Delay Time Row Address Setup Time tAVREL tASR 0 -- 0 -- 0 -- ns Row Address Hold Time tRELAX tRAH 10 -- 10 -- 10 -- ns NOTES: (continued) 11. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 12. An initial pause of 100 s is required after power-up followed by 8 initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle) before proper device operation is guaranteed. 13. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 14. AC measurements assume tT = 5.0 ns. 15. The specifications for t RC (min) and t RWC (min) are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 16. Measured with a current load equivalent to 2 TTL (- 200 A, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and VOL = 0.8 V. 17. Assumes that tRCD t RCD (max) and tRAD t RAD (max). If t RCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 18. In a test mode read cycle, the value of tRAC, tAA, tCAC, and tCPA is delayed for 2 ns to 5 ns for the specified value. These parameters should be in the test mode cycles by adding the above value to the specified value in the data sheet. 9. Assumes that tRCD tRCD (max) and tRAD tRAD (max). 10. Access time is determined by the longer of tAA or tCAC or tCPA. 11. Assumes that tRCD tRCD (max) and tRAD tRAD (max). 12. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 13. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 14. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. MCM44100B*MCM4L4100B 4 MOTOROLA DRAM READ, WRITE, AND READ-WRITE CYCLES (Continued) MCM44100B-60 MCM4L4100B-60 Symbol Parameter MCM44100B-70 MCM4L4100B-70 MCM44100B-80 MCM4L4100B-80 Std Alt Min Max Min Max Min Max Unit Column Address Setup Time tAVCEL tASC 0 -- 0 -- 0 -- ns Column Address Hold Time tCELAX tCAH 15 -- 15 -- 15 -- ns Column Address to RAS Lead Time tAVREH tRAL 30 -- 35 -- 40 -- ns Read Command Setup Time tWHCEL tRCS 0 -- 0 -- 0 -- ns Read Command Hold Time Referenced to CAS tCEHWX tRCH 0 -- 0 -- 0 -- ns 15 Read Command Hold Time Referenced to RAS tREHWX tRRH 0 -- 0 -- 0 -- ns 15 Write Command Hold Time Referenced to CAS tCELWH tWCH 15 -- 10 -- 10 -- ns Write Command Pulse Width tWLWH tWP 10 -- 15 -- 15 -- ns Write Command to RAS Lead Time tWLREH tRWL 15 -- 20 -- 20 -- ns Write Command to CAS Lead Time tWLCEH tCWL 15 -- 20 -- 20 -- ns Data in Setup Time tDVCEL tDS 0 -- 0 -- 0 -- ns 16 tCELDX tDH 15 -- 15 -- 15 -- ns 16 tRVRV tRFSH -- -- 16 128 -- -- 16 128 -- -- 16 128 ms Write Command Setup Time tWLCEL tWCS 0 -- 0 -- 0 -- ns 17 CAS to Write Delay tCELWL tCWD 15 -- 20 -- 20 -- ns 17 RAS to Write Delay Data in Hold Time Refresh Period MCM44100B MCM4L4100B Notes tRELWL tRWD 60 -- 70 -- 80 -- ns 17 Column Address to Write Delay Time tAVWL tAWD 30 -- 35 -- 40 -- ns 17 CAS Precharge to Write Delay Time (Page Mode) tCEHWL tCPWD 35 -- 40 -- 45 -- ns 17 CAS Setup Time for CAS Before RAS Refresh tRELCEL tCSR 10 -- 5 -- 5 -- ns CAS Hold Time for CAS Before RAS Refresh tRELCEH tCHR 10 -- 10 -- 10 -- ns RAS Precharge to CAS Active Time tREHCEL tRPC 10 -- 10 -- 10 -- ns CAS Precharge Time for CAS Before RAS Counter Time tCEHCEL tCPT 40 -- 40 -- 40 -- ns Write Command Setup Time (Test Mode) tWLREL tWTS 0 -- 0 -- 0 -- ns Write Command Hold Time (Test Mode) tRELWH tWTH 10 -- 10 -- 10 -- ns Write to RAS Precharge Time (CAS Before RAS Refresh) tWHREL tWRP 0 -- 0 -- 0 -- ns Write to RAS Hold Time (CAS Before RAS Refresh) tRELWL tWRH 10 -- 10 -- 10 -- ns NOTES: 15. Either tRRH or tRCH must be satisfied for a read cycle. 16. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in read-write cycles. 17. tWCS, tRWD, tCWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD tCWD (min), tRWD tRWD (min), tAWD tAWD (min), and tCPWD tCPWD (min) (page mode), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. MOTOROLA DRAM MCM44100B*MCM4L4100B 5 READ CYCLE t RC t RAS t RP V IH RAS V IL t CSH t CRP t CRP t RCD t RSH t CAS V IH CAS t CP V IL t RAL t CAH t RAD t ASR V IH ADDRESSES t ASC ROW ADDRESS V IL COLUMN ADDRESS t RAH t RCH t RCS W D (DATA OUT) t RRH V IH V IL t CAC t AA t OFF t RAC VOH HIGH-Z V OL VALID DATA EARLY WRITE CYCLE t RC t RAS RAS V IH V IL t RCD t CRP CAS t RSH t CSH t CP V IL t RAL t CAH t RAD V IH V IL t ASC ROW ADDRESS COLUMN ADDRESS t RAH t CWL t WCS W t CRP t CAS V IH t ASR ADDRESSES t RP t WCH t WP V IH V IL t RWL t DH t DS D (DATA IN) D (DATA OUT) V IH V IL VOH V OL MCM44100B*MCM4L4100B 6 VALID DATA HIGH-Z MOTOROLA DRAM READ-WRITE CYCLE t RWC t RAS RAS V IL t RSH t RCD t CAS t CRP CAS t RWL V IL t RAD t ASR V IH ROW ADDRESS V IL t CWL t RAL t CAH t ASC COLUMN ADDRESS t RAH t AWD t RWD W t CWD t WP V IH V IL t DH t RCS D (DATA IN) t CRP t CP V IH t CSH ADDRESSES t RP V IH t DS V IH VALID DATA V IL t CAC t AA t OFF t RAC D (DATA OUT) VOH HIGH-Z V OL VALID DATA FAST PAGE MODE READ CYCLE t RASP RAS V IH V IL t CSH t RCD t CRP CAS t RSH t PC t CAS t CAS t CAS t CP t CP V IL t ASC V IH V IL t CAH ROW ADDRESS t ASC COLUMN ADDRESS t CAH t CAH t ASC t RAL COLUMN ADDRESS COLUMN ADDRESS t RAH t RCS t RCS t RCS t RCH V IH V IL t CAC t AA t AA t AA t CPA t CPA VOH VALID DATA V OL t OFF MOTOROLA DRAM t CAC t CAC t RAC D (DATA OUT) t RRH t RCH t RCH t RAD W t CP V IH t ASR ADDRESSES t RP t RHCP VALID DATA t OFF VALID DATA t OFF MCM44100B*MCM4L4100B 7 FAST PAGE MODE EARLY WRITE CYCLE RAS t RASP V IH t RP t RHCP V IL t RCD t PC t CRP CAS V IH t CP t CP V IL t ASC t RAH t ASR V IH ROW ADDRESS V IL COLUMN ADDRESS t CAH COLUMN ADDRESS COLUMN ADDRESS t WCS t WCH t WCS t WCH t WCH t WP t WP V IH t RAL t ASC t CAH t CAH t RAD t WCS W t CAS t CP t ASC ADDRESSES t RSH t CAS t CAS t WP V IL t DS D (DATA IN) V IH D (DATA OUT) VOH t DS t DS t DH t DH VALID DATA V IL t DH VALID DATA VALID DATA HIGH-Z V OL FAST PAGE MODE READ-WRITE CYCLE RAS t RP t RASP V IH V IL t CSH t PRWC t CP t CRP CAS t CAS t RCD t RSH t CP t CP t CAS t CAS V IH V IL t RAL t ASC t ASR ADDRESSES V IH V IL ROW ADDRESS t ASC t CAH t CAH t RAH COLUMN ADDRESS t RAD t RCS t ASC t CAH COLUMN ADDRESS tCWD tCWD t CWL V IL V IH VALID DATA V IL t CAC t WP tCPWD tDH VALID DATA t RAC t CPA VALID DATA V OL t OFF t WP tDH VALID DATA t CAC t AA t CPA t AA VOH MCM44100B*MCM4L4100B 8 tDS tDS t WP tCPWD tDH tRWD D (DATA OUT) t CWL t AWD t AWD V IH tDS D (DATA IN) t RWL tCWD t CWL t AWD W COLUMN ADDRESS t CAC t AA VALID DATA t OFF VALID DATA t OFF MOTOROLA DRAM RAS-ONLY REFRESH CYCLE (W and A10 are Don't Care) t RC RAS t RP t RAS V IH V IL t CRP t RPC V IH CAS V IL t RAH t ASR V IH A0 - A9 D (DATA OUT) ROW ADDRESS V IL VOH HIGH-Z V OL CAS BEFORE RAS REFRESH CYCLE (A0 - A10 are Don't Care) t RC RAS t RAS V IH V IL t CP CAS tCSR t RPC t CHR V IH V IL t WRP W t RP t WRH V IH V IL t OFF D (DATA OUT) VOH V OL MOTOROLA DRAM HIGH-Z MCM44100B*MCM4L4100B 9 HIDDEN REFRESH CYCLE tRC tRC tRAS (READ) RAS tRAS (REFRESH) tRP tRP V IL tCHR tRSH tRCD tCRP tCAS V IH V IL tASR tASC tRAL tRAD tRAH ADDRESS tRAS (REFRESH) tRP V IH tT CAS tRC V IH V IL tCAH ROW COLUMN tRCH tRRH tRCS WE V IH tCAC V IL tAA tRAC Dout tOFF VOH VALID OUTPUT V OL HIDDEN REFRESH CYCLE (EARLY WRITE) t RC V IH RAS t RP V IL t CRP t RCD t CHR t RSH t CP V IH CAS V IL t RAD t ASR t RAH ADDRESSES V IH V IL t RAL t ASC t CAH COLUMN ADDRESS ROW ADDRESS t RWL t WCH W t RAS t RAS t WRP t WRH t WCS V IH V IL t WP t DS D (DATA IN) D (DATA OUT) VIH V IL VOH V OL MCM44100B*MCM4L4100B 10 t DH VALID DATA HIGH-Z MOTOROLA DRAM CAS BEFORE RAS REFRESH COUNTER TEST CYCLE t RAS RAS V IH V IL t CSR CAS t CPT t CHR t CAS V IH V IL t ASC ADDRESSES t RP t RSH V IH t CAH COLUMN ADDRESS V IL t CAC t RAL t AA READ CYCLE Q (DATA OUT) VOH t OFF VALID DATA HIGH-Z V OL t RRH t WRP W t WRH t RCH t RCS V IH V IL EARLY WRITE CYCLE VOH Q (DATA OUT) V OL HIGH-Z t WRP W t WRH t WCS V IH t RWL t CWL t WCH t WP V IL t DS D (DATA IN) V IH t DH VALID DATA V IL t CAC t OFF READ-WRITE CYCLE Q (DATA OUT) VOH VALID DATA HIGH-Z V OL t WRP W D (DATA IN) t CWL t AA t WRH t RWL t AWD V IH V IL t RCS tCWD V IH VALID DATA V IL tDS MOTOROLA DRAM t WP tDH MCM44100B*MCM4L4100B 11 DEVICE INITIALIZATION On power-up, an initial pause of 100 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight active cycles of the row address strobe (clock) to initialize all dynamic nodes within the RAM. During an extended inactive state (greater than 16 milliseconds or 128 milliseconds in case of low power device, with the device powered up), a wakeup sequence of eight active cycles is necessary to ensure proper operation. ADDRESSING THE RAM The eleven address pins on the device are time multiplexed at the beginning of a memory cycle by two clocks, row address strobe (RAS) and column address strobe (CAS), into two separate 11-bit address fields. A total of twenty-two address bits, eleven rows and eleven columns, will decode one of the 4,194,304 bit locations in the device. RAS active transition is followed by CAS active transition (active = VIL, tRCD minimum) for all read or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the RAM. The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock enables the internal CAS line as soon as the row address hold time (tRAH) specification is met (and defines t RCD minimum). The multiplex window can be used to absorb skew delays in switching the address bus from row to column addresses and in generating the CAS clock. There are three other variations in addressing the 4M RAM: RAS-only refresh cycle, CAS before RAS refresh cycle, and page mode. READ CYCLE The DRAM may be read with four different cycles: "normal" random read cycle, page mode read cycle, read-write cycle, and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate sections. The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching the desired bit location. The write (W) input level must be high (VIH), tRCS (minimum) before the CAS active transition, to enable read mode. Both the RAS and CAS clocks trigger a sequence of events that are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window; however, CAS must be active before or at tRCD maximum to guarantee valid data out (Q) at tRAC (access time from RAS active transition). If the tRCD maximum is exceeded, read access time is determined by the CAS clock active transition (tCAC). The RAS and CAS clocks must remain active for minimum times of tRAS and t CAS, respectively, to complete the read cycle. W must remain high throughout the cycle, and for time t RRH or t RCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of tRP to precharge the internal device circuitry for the next active cycle. Q is valid, but not latched, as MCM44100B*MCM4L4100B 12 long as the CAS clock is active. When the CAS clock transitions to inactive, the output will switch to High-Z (three- state). WRITE CYCLE The user can write to the DRAM with any of four cycles: early write, late write, page mode early write, and page mode read-write. Early and late write modes are discussed here, while page mode write operations are covered elsewhere. A write cycle begins as described in ADDRESSING THE RAM. Write mode is enabled by the transition of W to active (VIL). Early and late write modes are distinguished by the active transition of W, with respect to CAS. Minimum active time tRAS and t CAS, and precharge time tRP apply to write mode, as in the read mode. An early write cycle is characterized by W active transition at minimum time tWCS before CAS active transition. Data in (D) is referenced to CAS in an early write cycle. RAS and CAS clocks must stay active for t RWL and t CWL , respectively, after the start of the early write operation to complete the cycle. Q remains in three-state condition throughout an early write cycle because W active transition precedes or coincides with CAS active transition, keeping data-out buffers disabled. This feature can be utilized on systems with a common I/O bus, provided all writes are performed with early write cycles, to prevent bus contention. A late write cycle occurs when W active transition is made after CAS active transition. W active transition could be delayed for almost 10 microseconds after CAS active transition, (t RCD + tCWD + tRWL + 2tT) t RAS, if other timing minimums (t RCD, t RWL, and tT) are maintained. D is referenced to W active transition in a late write cycle. Output buffers are enabled by CAS active transition but Q may be indeterminate (see note 17 of the AC Operating Conditions table). RAS and CAS must remain active for tRWL and tCWL, respectively, after W active transition to complete the write cycle. READ-WRITE CYCLE A read-write cycle performs a read and then a write at the same address, during the same cycle. This cycle is basically a late write cycle, as discussed in the WRITE CYCLE section, except W must remain high for tCWD minimum after the CAS active transition, to guarantee valid Q before writing the bit. PAGE MODE CYCLES Page mode allows fast successive data operations at all 2048 column locations on a selected row of the 4M dynamic RAM. Read access time in page mode (tCAC) is typically half the regular RAS clock access time, tRAC. Page mode operation consists of keeping RAS active while toggling CAS between V IH and V IL . The row is latched by RAS active transition, while each CAS active transition allows selection of a new column location on the row. A page mode cycle is initiated by a normal read, write, or read-write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for minimum of tCP, while RAS remains low (VIL). The second CAS active transition while RAS is low initiates the first page mode cycle (tPC or tPRWC). Either a MOTOROLA DRAM read, write, or read-write operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by tRASP. Page mode operation is ended when RAS transitions to inactive, coincident with or following CAS inactive transition. refreshed. External address lines are ignored during the automatic refresh cycle. The output buffer remains at the same state it was in during the previous cycle (hidden refresh). W must be inactive for time tWRP before and time tWRH after RAS active transition to prevent switching the device into test mode. REFRESH CYCLES Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the end of a read or write cycle, while RAS cycles inactive for tRP and back to active, starts the hidden refresh. This is essentially the execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). W is subject to the same conditions with respect to RAS active transition (to prevent test mode entry) as in CAS before RAS refresh. The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the MCM44100B require refresh every 16 milliseconds, while refresh time for the MCM4L4100B is 128 milliseconds. This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6 microseconds for the MCM44100B, and 124.8 microseconds for the MCM4L4100B. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM44100B and 128 milliseconds on the MCM4L4100B. A normal read, write, or read-write operation to the RAM will refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are available on this device for greater system flexibility. RAS-Only Refresh RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high (V IH ) throughout the cycle. An external counter is employed to ensure all rows are refreshed within the specified limit. CAS Before RAS Refresh CAS before RAS refresh is enabled by bringing CAS active before RAS. This clock order activates an internal refresh counter that generates the row address to be MEMORY CYCLE Hidden Refresh CAS BEFORE RAS REFRESH COUNTER TEST The internal refresh counter of this device can be tested with a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal refresh counter generates the row address, while the external address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram. The test can be performed after a minimum of 8 CAS before RAS initialization cycles. Test procedure: 1. Write 0s into all memory cells with normal write mode. 2. Select a column address, read 0 out and write 1 into the cell by performing the CAS before RAS refresh counter test, read-write cycle. Repeat this operation 1024 times. 3. Read the 1s which were written in step two in normal read mode. 4. Using the same starting column address as in step two, read 1 out and write 0 into the cell by performing the CAS before RAS refresh counter test, read-write cycle. Repeat this operation 1024 times. 5. Read 0s which were written in step four in normal read mode. 6. Repeat steps one through five using complement data. CAS BEFORE RAS REFRESH CYCLE CAS BEFORE RAS REFRESH CYCLE RAS CAS Q HIGH-Z VALID DATA OUT Figure 1. Hidden Refresh Cycle MOTOROLA DRAM MCM44100B*MCM4L4100B 13 TEST MODE The internal organization of this device (512K x 8) allows it to be tested as if it were a 512K x 1 DRAM. Nineteen of the twenty two addresses are used when operating the device in test mode. Row address A0, and column addresses A0 and A10 are ignored by the device in test mode. A test mode cycle reads and/or writes data to a bit in each of eight 512K blocks (B0 - B7) in parallel. External data out is deter- mined by the internal test mode logic of the device. See the following truth table and test mode block diagram. W, CAS before RAS timing puts the device in Test Mode as shown in the test mode timing diagram. A CAS before RAS or a RAS-only refresh cycle puts the device back into normal mode. Refresh is performed in test mode by using a W, CAS before RAS refresh cycle which uses internal refresh address counter. TEST MODE TRUTH TABLE D B0 B1 B2 B3 B4 B5 B6 B7 Q 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 -- Any Other 0 W, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY) (D and A0 - A10 are Don't Care) tRC tRAS tRP RAS V IH V IL tCHR tRPC tCP tCSR CAS V IH V IL tWTH tWTS V IH W V IL tOFF Q (DATA OUT) V OH HIGH-Z V OL TEST MODE - READ CYCLE t RC RAS t RP t RAS V IH V IL t CSH CAS ADDRESSES V IH V IL t RCD t CRP t ASR V IH V IL t RAD tRAH t RAL t CAH tASC ROW ADDRESS COLUMN ADDRESS tRCS W t CRP t RSH t CAS tRRH t RCH V IH t CAC V IL tAA Q (DATA OUT) t VOL VOH MCM44100B*MCM4L4100B 14 HIGH-Z t OFF RAC VALID DATA MOTOROLA DRAM TEST MODE - EARLY WRITE CYCLE t RC RAS t RP t RAS V IH V IL t RCD t RSH tCSH t CRP t RAD t ASR ADDRESSES tRAH V IH t RAL t CAH tASC ROW ADDRESS V IL W t CRP t CAS V IH CAS V IL COLUMN ADDRESS t CWL t WCS V IH t WCH t WP V IL t RWL D (DATA IN) V IH VALID DATA V IL t DS t DH VOH Q (DATA OUT) HIGH-Z VOL TEST MODE - FAST PAGE MODE READ CYCLE RAS t PC V IL t t RCD t CAS V IH t CAH t ASC ROW ADD t CAH t ASC COLUMN ADDRESS t RHCP t CAS t t t CAH COLUMN ADDRESS t RCS RCS t RCH RCH RAL t ASC COLUMN ADDRESS RCS t RAD t RRH t RCH V IH V IL t AA t t Q (DATA OUT) t CAS t RSH t t RAH V IL W t t CP V IL t ASR ADDRESSES t CP CSH t CRP V IH CAS t RP t RASP V IH V OH V OL t AA CAC t RAC VALID DATA OUT t OFF MOTOROLA DRAM t AA t t CAC t CPA CAC CPA VALID DATA OUT t OFF VALID DATA OUT t OFF MCM44100B*MCM4L4100B 15 TEST MODE - FAST PAGE MODE EARLY WRITE CYCLE RAS t RP t RASP V IH t V IL t CRP RCD t CAS t CAS t t CAH t ASC V IH ROW ADD V IL t CAH t ASC COLUMN ADDRESS t CAH t WCH tWCS t WP t WP RAL COLUMN ADDRESS t WCH t WCH tWCS tWCS V IH t ASC COLUMN ADDRESS t RAD W t CAS t ASR t RAH ADDRESSES tCP tCP V IH V IL t RSH t PC t CAS RHCP t WP V IL t DS Q (DATA IN) V IH t DH t t DH DS VALID DATA IN V IL VALID DATA IN VOH Q (DATA OUT) VOL t t DH DS VALID DATA IN HIGH-Z ORDERING INFORMATION (Order by Full Part Number) MCM 44100B or 4L4100B X XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (60 = ns, 70 = 70 ns, 80 = 80 ns) Package (N = 300 mil SOJ) Full Part Numbers -- MCM44100BN60 MCM44100BN70 MCM44100BN80 MCM4L4100BN60 MCM4L4100BN70 MCM4L4100BN80 MCM44100B*MCM4L4100B 16 MCM44100BN60R2 MCM44100BN70R2 MCM44100BN80R2 MCM4L4100BN60R2 MCM4L4100BN70R2 MCM4L4100BN80R2 MOTOROLA DRAM PACKAGE DIMENSIONS N PACKAGE 300 MIL SOJ CASE 822B-01 H BRK 26 1 22 18 14 5 9 13 F N 20X D 0.007 (0.18) M T A S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.006 (0.15) PER SIDE. 4. DIMENSION R TO BE DETERMINED AT DATUM -T-. 5. FOR LEAD IDENTIFICATION PURPOSES PIN POSITIONS 6, 7, 8, 19, 20 AND 21 ARE NOT USED. DETAIL Z P 0.007 (0.18) M T B S -A-B- L M G M K E C 0.004 (0.10) -TDETAIL Z SEATING PLANE S RADIUS R 0.010 (0.25) M T B S DIM A B C D E F G H K L M N P R S INCHES MIN MAX 0.661 0.680 0.295 0.305 0.128 0.148 0.015 0.021 0.085 0.103 0.026 0.032 0.050 BSC --- 0.020 0.025 0.045 0.100 BSC 0_ 20 _ 0.035 0.059 0.330 0.340 0.260 0.275 0.027 0.040 MILLIMETERS MIN MAX 16.79 17.27 7.50 7.74 3.25 3.76 0.38 0.53 2.16 2.61 0.66 0.81 1.27 BSC --- 0.50 0.63 1.14 2.54 BSC 0_ 20 _ 0.89 1.50 8.39 8.63 6.60 6.98 0.69 1.02 Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MCM44100B*MCM4L4100B 18 *MCM44100B/D* MCM44100B/D MOTOROLA DRAM