Serial Input, 14-Bit/16-Bit DAC AD7849 FEATURES FUNCTIONAL BLOCK DIAGRAM VDD R ROFS R R APPLICATIONS Industrial process controls PC analog I/O boards Instrumentation VCC VREF+ 16-SEGMENT SWITCH MATRIX 14-bit/16-bit multiplying DAC Guaranteed monotonicity Output control on power-up and power-down internal or external control Versatile serial interface DAC clears to 0 V in both unipolar and bipolar output ranges RST IN G1 10-BIT/ 12-BIT DAC 10/ 12 A2 R VREF- R A1 VOUT A3 LOGIC CIRCUITRY G2 DAC LATCH 4 10/ 12 AD7849 INPUT LATCH VOLTAGE MONITOR AGND RST OUT DGND SDIN SCLK SYNC CLR BIN/ DCEN SDOUT LDAC VSS COMP 01008-001 INPUT SHIFT REGISTER/ CONTROL LOGIC Figure 1. GENERAL DESCRIPTION The AD7849 is a 14-bit/16-bit serial input multiplying digitalto-analog converter (DAC). The DAC architecture ensures excellent differential linearity performance, and monotonicity is guaranteed to 14 bits for the A grade and to 16 bits for all other grades over the specified temperature ranges. During power-up and power-down sequences (when the supply voltages are changing), the VOUT pin is clamped to 0 V via a low impedance path. To prevent the output of A3 from being shorted to 0 V during this time, Transmission Gate G1 is also opened. These conditions are maintained until the power supplies stabilize, and a valid word is written to the DAC register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the reset in (RSTIN) control input. For instance, if the RSTIN input is driven from a battery supervisor chip, then at power-off or during a brown out, the RSTIN input is driven low to open G1 and close G2. The DAC must be reloaded, with RSTIN high, to reenable the output. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. The AD7849 has a versatile serial interface structure and can be controlled over three lines to facilitate opto-isolator applications. SDOUT is the output of the on-chip shift register and can be used in a daisy-chain fashion to program devices in the multichannel system. The daisy-chain enable (DCEN) input controls this function. The BIN/COMP pin sets the DAC coding; with BIN/COMP set to 0, the coding is straight binary; and with BIN/COMP set to 1, the coding is twos complement. This allows the user to reset the DAC to 0 V in both the unipolar and bipolar output ranges. The part is available in a 20-lead PDIP package and a 20-lead SOIC package. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1995-2011 Analog Devices, Inc. All rights reserved. AD7849 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................8 Applications....................................................................................... 1 Terminology .................................................................................... 10 Functional Block Diagram .............................................................. 1 Circuit Description......................................................................... 11 General Description ......................................................................... 1 Digital-to-Analog Conversion.................................................. 11 Revision History ............................................................................... 2 Digital Interface.......................................................................... 12 Specifications..................................................................................... 3 Applying the AD7849 ................................................................ 13 Reset Specifications ...................................................................... 4 Microprocessor Interfacing....................................................... 15 AC Performance Characteristics ................................................ 5 Applications Information .............................................................. 17 Timing Characteristics ................................................................ 5 Opto-Isolated Interface ............................................................. 17 Absolute Maximum Ratings............................................................ 6 Outline Dimensions ....................................................................... 18 ESD Caution.................................................................................. 6 Ordering Guide .......................................................................... 19 Pin Configuration and Function Descriptions............................. 7 REVISION HISTORY 3/11--Rev. B to Rev. C Deleted 20-Lead CERDIP (Q-20) Package and T Version .............................................................................Universal Updated Format..................................................................Universal Deleted AD7849-to-ADSP-2101/ADSP-2102 Interface Section and Figure 20; Renumbered Sequentially.................................... 12 Rev. C | Page 2 of 20 AD7849 SPECIFICATIONS VDD = 14.25 V to 15.75 V; VSS = -14.25 V to -15.75 V; VCC = 4.75 V to 5.25 V; VOUT loaded with 2 k, 200 pF to 0 V; VREF+ = 5 V; ROFS connected to 0 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for A, B, C versions is -40C to +85C. Table 1. Parameter RESOLUTION A Version 14 B Version 16 C Version 16 Unit Bits UNIPOLAR OUTPUT Relative Accuracy at 25C TMIN to TMAX Differential Nonlinearity 4 5 0.25 6 16 0.9 4 8 0.5 LSB typ LSB max LSB max Gain Error at 25C TMIN to TMAX Offset Error at 25C TMIN to TMAX Gain Temperature Coefficient 1 1 4 1 6 2 4 16 4 24 2 4 16 4 16 2 Offset Temperature Coefficient1 2 2 2 LSB typ LSB max LSB typ LSB max ppm FSR/ C typ ppm FSR/ C typ 2 3 0.25 3 8 0.9 2 4 0.5 LSB typ LSB max LSB max Gain Error at 25C TMIN to TMAX Offset Error at 25C TMIN to TMAX Bipolar Zero Error at 25C TMIN to TMAX Gain Temperature Coefficient1 1 4 0.5 3 0.5 4 2 4 16 2 12 2 12 2 4 16 2 8 2 8 2 Offset Temperature Coefficient1 2 2 2 2 2 2 LSB typ LSB max LSB typ LSB max LSB typ LSB max ppm FSR/ C typ ppm FSR/ C typ ppm FSR/ C typ 25 43 VSS + 6 to VDD - 6 VSS + 6 to VDD - 6 25 43 VSS + 6 to VDD - 6 VSS + 6 to VDD - 6 25 43 VSS + 6 to VDD - 6 VSS + 6 to VDD - 6 k min k max V VSS + 4 to VDD - 4 2 200 0.3 25 VSS + 4 to VDD - 4 2 200 0.3 25 VSS + 4 to VDD - 4 2 200 0.3 25 V max BIPOLAR OUTPUT Relative Accuracy at 25C TMIN to TMAX Differential Nonlinearity Bipolar Zero Temperature Coefficient1 REFERENCE INPUT Input Resistance VREF+ Range VREF- Range OUTPUT CHARACTERISTICS Output Voltage Swing Resistive Load Capacitive Load Output Resistance Short-Circuit Current Test Conditions/Comments A version: 1 LSB = 2 (VREF+ - VREF-)/214; B, C versions: 1 LSB = 2 (VREF+ - VREF-)/216 VREF- = 0 V, VOUT = 0 V to 10 V All grades guaranteed monotonic over temperature VOUT load = 10 M VREF- = 5 V, VOUT = -10 V to +10 V Rev. C | Page 3 of 20 All grades guaranteed monotonic over temperature VOUT load = 10 M Resistance from VREF+ to VREF- Typically 34 k V k min pF max typ mA typ To 0 V To 0 V Voltage range: -10 V to +10 V AD7849 Parameter DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH Input Capacitance, CIN DIGITAL OUTPUTS Output Low Voltage, VOL Output High Voltage, VOH Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS 2 VDD VSS VCC IDD A Version B Version C Version Unit 2.4 0.8 10 10 2.4 0.8 10 10 2.4 0.8 10 10 V min V max A max pF max 0.4 4.0 10 10 0.4 4.0 10 10 0.4 4.0 10 10 V max V min A max pF max 14.25/15.75 -14.25/-15.75 4.75/5.25 5 14.25/15.75 -14.25/-15.75 4.75/5.25 5 14.25/15.75 -14.25/-15.75 4.75/5.25 5 V min/V max V min/V max V min/V max mA max ISS 5 5 5 mA max ICC Power Supply Sensitivity 3 Power Dissipation 2.5 0.4 100 2.5 1.5 100 2.5 1.5 100 mA max LSB/V max mW typ Test Conditions/Comments ISINK = 1.6 mA ISOURCE = 400 A VOUT unloaded, VINH = VDD - 0.1 V, VINL = 0.1 V VOUT unloaded, VINH = VDD - 0.1 V, VINL = 0.1 V VINH = VDD - 0.1 V, VINL = 0.1 V VOUT unloaded 1 Guaranteed by design and characterization, not production tested. The AD7849 is functional with power supplies of 12 V. See the Typical Performance Characteristics section. 3 Sensitivity of gain error, offset error, and bipolar zero error to VDD, VSS variations. 2 RESET SPECIFICATIONS These specifications apply when the device goes into reset mode during power-up or power-down sequence. VOUT unloaded. Table 2. Parameter VA, 1 Low Threshold Voltage for VDD, VSS VB, High Threshold Voltage for VDD, VSS VC, Low Threshold Voltage for VCC VD, High Threshold Voltage for VCC G2 RON 1 All Versions 1.2 0 9.5 6.4 1 0 4 2.5 1 Unit V max V typ V max V min V max V typ V max V min k typ Test Conditions/Comments This is the lower VDD/VSS threshold voltage for the reset function. Above this, the reset is activated. This is the higher VDD/VSS threshold voltage for the reset function. Below this, the reset is activated. Typically, 8 V. This is the lower VCC threshold voltage for the reset function. Above this, the reset is activated. This is the higher VCC threshold voltage for the reset function. Below this, the reset is activated. Typically, 3 V. On resistance of G2; VDD = 2 V; VSS = -2 V; IG2 = 1 mA. A pull-down resistor (65 k) on VOUT maintains 0 V output when VDD/VSS is below VA. Rev. C | Page 4 of 20 AD7849 AC PERFORMANCE CHARACTERISTICS These characteristics are included for design guidance and are no subject to test. VREF+ = 5 V; VDD = 14.25 V to 15.75 V; VSS = -14.25 V to -15.75 V; VCC = 4.75 V to 5.25 V; ROFS connected to 0 V. Table 3. Parameter DYNAMIC PERFORMANCE Output Settling Time 1 1 A, B, C Versions Unit Test Conditions/Comments s typ s typ V/s typ nV-sec typ To 0.006% FSR. VOUT loaded. VREF- = 0 V. To 0.003% FSR. VOUT loaded. VREF- = -5 V. Slew Rate Digital-to-Analog Glitch Impulse 7 10 4 250 AC Feedthrough 150 1 nV-sec typ mV p-p typ Digital Feedthrough 5 nV-sec typ Output Noise Voltage Density, 1 kHz to 100 kHz 80 nV/Hz typ DAC alternatively loaded with 00 ... 00 and 111 ... 11. VOUT loaded. LDAC permanently low. BIN/COMP set to 1. VREF- = -5 V. LDAC frequency = 100 kHz. VREF- = 0 V, VREF+ = 1 V rms, 10 kHz sine wave. DAC loaded with all 0s. BIN/COMP set to 0. DAC alternatively loaded with all 1s and 0s. SYNC high. Measured at VOUT. VREF+ = VREF- = 0 V. BIN/COMP set to 0. LDAC = 0. Settling time does not include deglitching time of 5 s (typical). TIMING CHARACTERISTICS VDD = 14.25 V to 15.75 V; VSS = -14.25 V to -15.75 V; VCC = 4.75 V to 5.25 V; RL = 2 k, CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted. Guaranteed by characterization. All input signals are specified tr = tf = 5 ns (10% to 90% of 5 V and timed from a voltage level of 1.6 V. Table 4. Parameter t1 1 t2 t3 t4 t5 t6 2 t7 tr tf 1 2 Limit at 25C (All Versions) 200 50 70 10 40 80 80 30 30 Limit at TMIN, TMAX (All Versions) 200 50 70 10 40 80 80 30 30 SCLK mark/space ratio range is 40/60 to 60/40. SDO load capacitance is 50 pF. Rev. C | Page 5 of 20 Unit ns min ns min ns min ns min ns min ns max ns min s max s max Test Conditions/Comments SCLK cycle time SYNC-to-SCLK setup time SYNC-to-SCLK hold time Data setup time Data hold time SCLK falling edge to SDO valid LDAC, CLR pulse width Digital input rise time Digital input fall time AD7849 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 5. Parameter VDD to DGND VCC to DGND 1 VSS to DGND VREF+ to DGND VREF- to DGND VOUT to DGND 2 ROFS to DGND Digital Input Voltage to DGND Input Current to any Pin Except Supplies3 Operating Temperature Range Storage Temperature Range Junction Temperature 20-Lead PDIP Power Dissipation JA Thermal Impedance Lead Temperature (Soldering, 10 sec) 20-Lead SOIC Power Dissipation JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) ESD CAUTION 875 mW 102C/W 260C 875 mW 74C/W 215C 220C VCC must not exceed VDD by more than 0.4 V. If it is possible for this to happen during power-up or power-down (for example, if VCC is greater than 0.4 V while VDD is still 0 V), the following diode protection scheme ensures protection. VDD 1N4148 VCC SD103C 1N5711 1N5712 VDD VCC AD7849 01008-002 1 Rating -0.4 V to +17 V -0.4 V, VDD + 0.4 V or +7 V (whichever is lower) -0.4 V to -17 V VDD + 0.4 V, VSS - 0.4 V VDD + 0.4 V, VSS - 0.4 V VDD + 0.4 V, VSS - 0.4 V or 10 V (whichever is lower) VDD + 0.4 V, VSS - 0.4 V -0.4 V to VCC + 0.4 V 10 mA -40C to +85C -65C to +150C 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 VOUT can be shorted to DGND, + 10 V, - 10 V, provided that the power dissipation of the package is not exceeded. 3 Transient currents of up to 100 mA do not cause SCR latch-up. Rev. C | Page 6 of 20 AD7849 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREF+ 1 20 ROFS VREF- 2 19 VOUT VSS 3 18 NC SYNC 4 17 VDD 16 AGND SCLK 5 AD7849 TOP VIEW (Not to Scale) 15 RSTOUT 14 RSTIN SDOUT 7 6 DCEN 8 13 CLR BIN/COMP 9 12 SDIN DGND 10 11 LDAC NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 01008-003 VCC Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic VREF+ VREF- VSS SYNC SCLK VCC SDOUT 8 DCEN 9 BIN/COMP 10 11 DGND LDAC 12 13 SDIN CLR 14 RSTIN 15 RSTOUT 16 17 18 19 20 AGND VDD NC VOUT ROFS Description VREF+ Input. The DAC is specified for VREF+ of 5 V. The DAC is fully multiplying so that the VREF+ range is +5 V to -5 V. VREF- Input. The DAC is specified for VREF- of -5 V. The DAC is fully multiplying so that the VREF- range is -5 V to +5 V. Negative supply for the analog circuitry. This is nominally -15 V. Data Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data-word. Serial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge. Positive supply for the digital circuitry. This is nominally 5 V. Serial Data Output. With DCEN at Logic 1, this output is enabled, and the serial data in the input shift register is clocked out on each rising edge of SCLK. Daisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used; otherwise, this pin must be connected low. Logic Input. This input selects the data format to be either binary or twos complement. In the unipolar output range, natural binary format is selected by connecting the input to Logic 0. In the bipolar output range, offset binary is selected by connecting this input to Logic 0, and twos complement is selected by connecting it to a Logic 1. Digital Ground. Ground reference point for the on-chip digital circuitry. Load DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this signal, or alternatively, if this input is permanently low, an automatic update mode is selected where the DAC is updated on the 16th falling SCLK edge. Serial Data Input. The 16-bit serial data-word is applied to this input. Clear Logic Input. Taking this input low sets VOUT to 0 V in both the unipolar output range and the bipolar twos complement output range. It sets VOUT to VREF- in the offset binary bipolar output range. Reset Logic Input. This input allows external access to the internal reset logic. Applying Logic 0 to this input, resets the DAC output to 0 V. In normal operation, it should be tied to Logic 1. Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It can be used to control other system components, if desired. This is the analog ground for the device. It is the point to which the output gets shorted in reset mode. Positive Supply for the Analog Circuitry. This is 15 V nominal. No Connect. Leave unconnected. DAC Output Voltage Pin. Input to Summing Resistor of DAC Output Amplifier. This is used to select the output voltage ranges. Also, see Figure 20 to Figure 23 in the Applying the AD7849 section. Rev. C | Page 7 of 20 AD7849 TYPICAL PERFORMANCE CHARACTERISTICS 7 VDD = +15V VSS = -15V 6 VREF+ = 1V rms VREF- = 0V C1 FREQ 9.9942kHz VREF+ 1 5 VOUT (mV p-p) C1 RMS 728mV C4 RMS 556V VOUT 4 4 3 2 M 20.0s CH1 1.00V 1.00mV -300mV 0 100 1k Figure 3. AC Feedthrough 10k FREQUENCY (Hz) 1M 100k 01008-007 CH1 CH4 01008-004 1 Figure 6. AC Feedthrough vs. Frequency LDAC SYNC 1 1 SDIN 2 SDIN 2 C4 AREA 247.964n VS VOUT 4 5.00V CH2 5.00V CH4 200mV M 1.00s CH1 3.7V CH1 Figure 4. Digital-to-Analog Glitch Impulse Without Internal Deglitcher 5.00V CH2 5.00V CH4 50.0mV M 5.00s CH1 -2.3V 01008-008 CH1 01008-005 VOUT 4 Figure 7. Digital-to-Analog Glitch Impulse With Internal Deglitcher 22 20 C1 p-p 10.4V 18 VREF+ 1 14 C2 p-p 20.8V 12 10 8 VOUT C2 RISE 2.79230s 2 C2 FALL 3.20385s 100k 1M CH1 10.0V CH2 20.0V M 2.5s CH1 -400mV Figure 8. Pulse Response (Large Signal) Figure 5. Large Signal Frequency Response Rev. C | Page 8 of 20 01008-009 VDD = +15V 6 V = -15V SS VREF+ = 5 SINE WAVE 4 V REF- = 0V GAIN = 2 2 100 1k 10k FREQUENCY (Hz) 01008-006 VOUT (V p-p) 16 AD7849 VDD C1 RISE 3.808ms C1 p-p 104mV VREF+ 1 1 C2 RISE 8s VOUT 2 C2 p-p 216mV C2 RISE 458ns CH1 100mV CH2 200mV M 2.00s CH1 -10mV LDAC 3 01008-010 C2 FALL 452.4ns CH1 CH3 10.0V 5.0V M 10.0ms CH1 7.8mV Figure 12. Turn-On Characteristics Figure 9. Pulse Response (Small Signal) 2.0 CH2 10.0V 01008-013 VOUT 2 TA = 25C VREF+ = 5V VREF- = 0V GAIN = 1 7.8V VDD 1.5 C1 FALL 4.7621ms INL (LSB) 1 1.0 VOUT 0.5 12.25 13.50 VDD/VSS (V) 14.75 16.00 CH1 TA = 25C VREF+ = 5V VREF- = 0V GAIN = 1 0.250 0.125 12 13 14 VDD/VSS (V) 15 16 01008-012 DNL (LSB) 0.375 0 11 CH2 10.0V M 1.00ms CH1 Figure 13. Turn-Off Characteristics Figure 10. Typical Integral Nonlinearity vs. Supplies 0.500 10.0V Figure 11. Typical Differential Nonlinearity vs. Supplies Rev. C | Page 9 of 20 7.8mV 01008-014 0 11.00 01008-011 2 AD7849 TERMINOLOGY Least Significant Bit This is the analog weighting of 1 bit of the digital word in a DAC. For the B version and the C versions, 1 LSB = (VREF+ - VREF-)/216. For the A version, 1 LSB = (VREF+ - VREF-)/214. Offset Error This is the error present at the device output with all 0s loaded in the DAC. It is due to the op amp input offset voltage and bias current and the DAC leakage current. Relative Accuracy Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for both endpoints (that is, offset and gain errors are adjusted out) and is normally expressed in least significant bits or as a percentage of full-scale range. Bipolar Zero Error When the AD7849 is connected for bipolar output and (100 ... 000) is loaded to the DAC, the deviation of the analog output from the ideal midscale of 0 V is called the bipolar zero error. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal change between any two adjacent codes. A specified differential nonlinearity of less than 1 LSB over the operating temperature range ensures monotonicity. Gain Error Gain error is a measure of the output error between an ideal DAC and the actual device output with all 1s loaded after offset error has been adjusted out. Gain error is adjustable to zero with an external potentiometer. Digital-to-Analog Glitch Impulse This is the amount of charge injected from the digital inputs to the analog output when the inputs change state. Normally, this is specified as the area of the glitch in nV-secs. Multiplying Feedthrough Error This is an ac error due to capacitive feedthrough from either of the VREF terminals to VOUT when the DAC is loaded with all 0s. Digital Feedthrough When the DAC is not selected (SYNC is held high), high frequency logic activity on the digital inputs is capacitively coupled through the device to show up as noise on the VOUT pin. This noise is digital feedthrough. Rev. C | Page 10 of 20 AD7849 CIRCUIT DESCRIPTION ROFS DIGITAL-TO-ANALOG CONVERSION R 10k Figure 15 shows the digital-to-analog section of the AD7849. There are three on-chip DACs, each of which has its own buffer amplifier. DAC1 and DAC2 are 4-bit DACs. They share a 16-resistor string, but they have their own analog multiplexers. The voltage reference is applied to the resistor string. DAC3 is a 12-bit voltage mode DAC with its own output stage. R 10k C1 G3 G1 VOUT DAC 3 ONE-SHOT LOGIC CIRCUITRY LDAC VOLTAGE MONITOR G2 AGND RSTOUT Figure 14. Output Stage When the supply voltages are changing, the VOUT pin is clamped to 0 V via a low impedance path. To prevent the output of A3 from being shorted to 0 V during this time, Transmission Gate G1 is opened. These conditions are maintained until the power supplies stabilize, and a valid word is written to the DAC register. At this time, G2 opens and G1 closes. Both transmission gates are also externally controllable via the reset in (RSTIN) control input. For instance, if the RSTIN input is driven from a battery supervisor chip, then at power-off or during a brownout, the RSTIN input will be driven low to open G1 and closeG2. The DAC has to be reloaded, with RSTIN high, to reenable the output. Conversely, the on-chip voltage detector output (RSTOUT) is also available to the user to control other parts of the system. To prevent nonmonotonicity in the DAC due to amplifier offset voltages, DAC1 and DAC2 leap-frog along the resistor string. For example, when switching from Segment 1 to Segment 2, DAC1 switches from the bottom of Segment 1 to the top of Segment 2 while DAC 2 remains connected to the top of Segment 1. The code driving DAC3 is automatically complemented to compensate for the inversion of its inputs. This means that any linearity effects due to amplifier offset voltages remain unchanged when switching from one segment to the next, and 16-bit monotonicity is ensured if DAC3 is monotonic. Therefore, 12-bit resistor matching in DAC3 guarantees overall 16-bit monotonicity. This is much more achievable than the 16-bit matching that a conventional R-2R structure would need. The AD7849 output buffer is configured as a track-and-hold amplifier. Although normally tracking its input, this amplifier isplaced in hold mode for approximately 5 s after the leading edge of LDAC. This short state keeps the DAC output at its previous voltage while the AD7849 is internally changing to its new value. therefore, any glitches that occur in the transition are not seen at the output. In systems where LDAC is permanently low, deglitching is not in operation. Output Stage The output stage of the AD7849 is shown in Figure 14. It is capable of driving a 2 k load in parallel with 200 pF. The feedback and offset resistors allow the output stage to be configured for gains of 1 or 2. Additionally, the offset resistor can be used to shift the output range. The AD7849 has a special feature to ensure output stability during power-up and power-down sequences. This feature is available for control applications where actuators must not be allowed to move in an uncontrolled fashion. R DAC 1 R S3 R DAC 3 S4 A1 S15 S17 DAC 2 S2 S1 S14 R S16 10-BIT/12-BIT DAC OUTPUT STAGE 10/12 R R DB15 TO DB12 VREF- A2 Figure 15. Digital-to-Analog Conversion Rev. C | Page 11 of 20 01008-016 DB15 TO DB12 01008-015 The four MSBs of the 16-bit digital input code drive DAC1 and DAC2, while the 12 LSBs control DAC3. Using DAC1 and DAC2, the MSBs select a pair of adjacent nodes on the resistor string and present that voltage to the positive and negative inputs of DAC3. This DAC interpolates between these two voltages to produce the analog output voltage. VREF+ RSTIN AD7849 t1 SCLK t3 t2 SYNC BIN/COMP t4 SDIN (AD7849B/C) DB0 DB15 t4 SDIN (AD7849A) t5 t5 DB13 DB0 t7 01008-017 LDAC, CLR NOTES 1. DCEN IS TIED PERMANENTLY LOW. Figure 16. Timing Diagram (Standalone Mode) The AD7849 contains an input serial-to-parallel shift register and a DAC latch. A simplified diagram of the input loading circuitry is shown in Figure 16. Serial data on the SDIN input is loaded to the input register under control of DCEN, SYNC and SCLK. When a complete word is held in the shift register, it can then be loaded into the DAC latch under control of LDAC. Only the data in the DAC latch determines the analog output on the AD7849. The daisy-chain enable (DCEN) input is used to select either the standalone mode or the daisy-chain mode. The loading format is slightly different depending on which mode is selected. Serial Data Loading Format (Standalone Mode) When DCEN is at Logic 0, standalone mode is selected. In this mode, a low SYNC input provides the frame synchronization signal that tells the AD7849 that valid serial data on the SDIN input is available for the next 16 falling edges of SCLK. An internal counter/decoder circuit provides a low gating signal so that only 16 data bits are clocked into the input shift register. After 16 SCLK pulses, the internal gating signal goes inactive (high), thus locking out any further clock pulses. Therefore, either a continuous clock or a burst clock source can be used to clock in data. The SYNC input is taken high after the complete 16-bit word is loaded in. The B version and C version are 16-bit resolution DACs and have a straight 16-bit load format, with the MSB (DB15) being loaded first. The A version is a 14-bit DAC; however, the loading structure is still 16 bit. The MSB (DB13) is loaded first, and the final two bits of the 16-bit stream must be 0s. The DAC latch, and hence the analog output, can be updated in two ways. The status of the LDAC input is examined after SYNC is taken low. Depending on its status, one of two update modes is selected. If LDAC = 0, then automatic update mode is selected. In this mode, the DAC latch and analog output are updated automatically when the last bit in the serial data stream is clocked in. The update thus takes place on the 16th falling SCLK edge. If LDAC = 1, then automatic update mode is disabled. The DAC latch update and output update are now separate. The DAC latch is updated on the falling edge of LDAC. However, the output update is delayed for a further 5 s by means of an internal track-and-hold amplifier in the output stage. This function results in a lower digital-to-analog glitch impulse at the DAC output. Note that the LDAC input must be taken back high again before the next data transfer is initiated. DCEN SYNC RESET EN SCLK /16 GATED SIGNAL COUNTER/ DECODER GATED SCLK INPUT SHIFT REGISTER (16 BITS) SDOUT SDIN AUTO-UPDATE CIRCUITRY LDAC CLR Rev. C | Page 12 of 20 DAC LATCH (14/16 BITS) Figure 17. Simplified Loading Structure 01008-018 DIGITAL INTERFACE AD7849 t1 SCLK t3 t2 SYNC BIN/COMP t4 t5 SDIN (AD7849B/C) DB15 (N) DB0 (N) DB15 (N + 1) DB0 (N + 1) DB15 (N) DB0 (N) t6 SDOUT (AD7849B/C) t4 t5 SDIN (AD7849A) DB13 (N) DB13 (N + 1) DB0 (N) DB0 (N + 1) t6 SDOUT (AD7849A) DB13 (N) DB0 (N) t7 01008-019 LDAC, CLR NOTES 1. DCEN IS TIED PERMANENTLY HIGH. Figure 18. Timing Diagram (Daisy-Chain Mode) Serial Data Loading Format (Daisy-Chain Mode) Clear Function (CLR) By connecting DCEN high, daisy-chain mode is enabled. This mode of operation is designed for multiDAC systems where several AD7849s can be connected in cascade. In this mode, the internal gating circuitry on SCLK is disabled, and a serial data output facility is enabled. The internal gating signal is permanently active (low) so that the SCLK signal is continuously applied to the input shift register when SYNC is low. The data is clocked into the register on each falling SCLK edge after SYNC goes low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDOUT line. By connecting this line to the SDIN input on the next AD7849 in the chain, a multiDAC interface can be constructed. Sixteen SCLK pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16 x N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC is taken high, which prevents any further data from being clocked into the input register. The clear function bypasses the input shift register and loads the DAC latch with all 0s. It is activated by taking CLR low. In all ranges, except the offset binary bipolar range (-5 V to +5 V), the output voltage is reset to 0 V. In the offset binary bipolar range, the output is set to VREF-. This clear function is distinct and separate from the automatic power-on reset feature of the device. APPLYING THE AD7849 Power Supply Sequencing and Decoupling In the AD7849, VCC should not exceed VDD by more than 0.4 V. If this happens, then an internal diode is turned on, and it produces latch-up in the device. Care should be taken to employ the following power supply sequence: VDD, VSS, and then VCC. In systems where it is possible to have an incorrect power sequence (for example, if VCC is greater than 0.4 V while VDD is still 0 V), the circuit shown in Figure 19 can be used to ensure that the Absolute Maximum Ratings are not exceeded. When the transfer to all input registers is complete, a common LDAC signal updates all DAC latches with the data in each input register. All analog outputs are therefore updated simultaneously, 5 s after the falling edge of LDAC. Rev. C | Page 13 of 20 VDD VCC SD103C 1N5711 1N5712 1N4148 VDD AD7849 VCC 01008-020 A continuous SCLK source can be used if SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles can be used and SYNC taken high some time later. Figure 19. Power Supply Protection AD7849 Unipolar Configuration Bipolar Configuration Figure 20 shows the AD7849 in the unipolar binary circuit configuration. The DAC is driven by the AD586, 5 V reference. Because ROFS is tied to 0 V, the output amplifier has a gain of x2, and the output range is 0 V to 10 V. If a 0 V to 5 V range is required, ROFS should be tied to VOUT, configuring the output stage for a gain of x1. Table 7 gives the code table for the circuit shown in Figure 20. Figure 21 shows the AD7849 set up for 10 V bipolar operation. The AD588 provides precision 5 V tracking outputs that are fed to the VREF+ and VREF- inputs of the AD7849.The code table for the circuit shown in Figure 21 is shown in Table 8. VCC VOUT R1 10k 5 R1 39k VOUT (0V TO 10V) ROFS 4 AD7849* 4 VREF- SIGNAL GND *ADDITIONAL PINS OMITTED FOR CLARITY. C1 1F AGND VSS -15V R2 100k R3 100k Figure 20. Unipolar Binary Operation Table 7. Code Table for Figure 20 Binary Number in DAC Latch MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 VDD VCC VOUT 2 3 9 5 +5V 6 7 DGND +15V 1 AD588 15 11 16 12 8 ROFS VREF+ AD7849* AGND 14 10 VOUT (-10V TO +10V) VREF- DGND VSS SIGNAL GND 13 *ADDITIONAL PINS OMITTED FOR CLARITY -15V Figure 21. Bipolar 10 V Operation Analog Output (VOUT) 10 (65,535/65,536) V 10 (32,768/65,536) V 10 (1/65,536) V 0V Table 8. Code Table for Figure 21 Offset and gain can be adjusted in Figure 20 as follows: Binary Number in DAC Latch MSB LSB 1111 1111 1111 1111 1000 0000 0000 0001 1000 0000 0000 0001 0111 1111 1111 1111 0000 0000 0000 0000 * Table 8 assumes a 16-bit resolution; 1 LSB = 20 V/216 = 305 V. Table 7 assumes a 16-bit resolution; 1 LSB = 10 V/216 = 10 V/65,536 = 152 V. * To adjust offset, disconnect the VREF- input from 0 V, load the DAC with all 0s, and adjust the VREF- voltage until VOUT = 0 V. To adjust gain, load the AD7849 with all 1s and adjust R1 until VOUT = 10 (65,535/65,536) = 9.9998474 V for the 16-bit, B and C versions. For the 14-bit A version, VOUT should be 10 (16,383/16,384) = 9.9993896 V. If a simple resistor divider is used to vary the VREF- voltage, it is important that the temperature coefficients of these resistors match that of the DAC input resistance (-300 ppm/C). Otherwise, extra offset errors will be introduced over temperature. Many circuits do not require these offset and gain adjustments. In these circuits, R1 can be omitted. Pin 5 of the AD586 may be left open circuit, and Pin 2 (VREF-) of the AD7849 tied to 0 V. Analog Output (VOUT) +10 (32,767/32,768) V +10 (1/32,768) V 0V -10 (1/32,768) V -10 (32,768/32,768) V For bipolar-zero adjustment on the AD7849, load the DAC with 100 ... 000 and adjust R3 until VOUT = 0 V. Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until VOUT = 9.999694 V. When bipolar-zero and full-scale adjustment are not needed, omit R2 and R3, connect Pin 11 to Pin 12 on the AD588 and leave Pin 5 on the AD588 floating. If a 5 V output range is desired with the circuit shown in Figure 21, tie Pin 20 (ROFS) to Pin 19 (VOUT), thus reducing the output gain stage to unity and giving an output range of 5 V. Rev. C | Page 14 of 20 01008-022 VDD VREF+ 6 AD586 C1 1nF +5V 01008-021 2 8 +15V Full-scale and bipolar-zero adjustment are provided by varying the gain and balance on the AD588. R2 varies the gain on the AD588, while R3 adjusts the +5 V and -5 V outputs together with respect to ground. AD7849 Other Output Voltage Ranges MICROPROCESSOR INTERFACING In some cases, users may require output voltage ranges other than those already mentioned. One example is systems that need the output voltage to be a whole number of millivolts (that is,1 mV or 2 mV). If the circuit shown in Figure 22 is used, then the LSB size is 125 V. This makes it possible to program whole millivolt values at the output. Table 9 shows the code table for the circuit shown in Figure 22. Microprocessor interfacing to the AD7849 is via a serial bus that uses standard protocol compatible with DSP processors and microcontrollers. The communications channel requires a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD7849 requires a 16-bit data-word with data valid on the falling edge of SCLK. For all the interfaces, the DAC update can be done automatically when all data is clocked in, or it can be done under control of LDAC. +5V VDD 8 R1 1 ROFS VREF+ 8.192V AD584 VOUT AD7849* R2 Figure 24 through Figure 27 show the AD7849 configured for interfacing to a number of popular DSP processors and microcontrollers. VCC VOUT (0V TO 8.192V) AD7849-to-DSP56000 Interface DGND 4 VREF- AGND 01008-023 SIGNAL GND *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 22. 0 V to 8.192 V Output Range Table 9. Code Table for Figure 22 Binary Number in DAC Latch MSB LSB 1111 1111 1111 1111 1000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0100 0000 0000 0000 0010 0000 0000 0000 0001 Analog Output (VOUT) 8.192 V (65,535/65,536) = 8.1919 V 8.192 V (32,768/65,536) = 4.096 V 8.192 V (8/65,536) = 0.001 V 8.192 V (4/65,536) = 0.0005 V 8.192 V (2/65,536) = 0.00025 V 8.192 V (1/65,536) = 0.000125 V A serial interface between the AD7849 and the DSP56000 is shown in Figure 24. The DSP56000 is configured for normal mode asynchronous operation with a gated clock. It is also setup for a 16-bit word with SCK and SC2 as outputs and the FSL control bit set to 0. SCK is internally generated on the DSP56000 and applied to the AD7849 SCLK input. Data from the DSP56000 is valid on the falling edge of SCK. The SC2 output provides the framing pulse for valid data. This line must be inverted before being applied to the SYNC input of the AD7849. In this interface, an LDAC pulse generated from an external timer is used to update the outputs of the DAC. This update can also be produced using a bit programmable control line from the DSP56000. LDAC Table 9 assumes a 16-bit resolution; 1 LSB = 8.192 V/216 = 125 V. SCK Generating a 5 V Output Range from a Single +5 V Reference Figure 23 shows how to generate a 5 V output range when using a single +5 V reference. VREF- is connected to 0 V, and ROFS is connected to VREF+. The 5 V reference input is applied to these pins. With all 0s loaded to the DAC, the noninverting terminal of the output stage amplifier is at 0 V, and VOUT is the inverse of VREF+. With all 1s loaded to the DAC, the noninverting terminal of the output stage amplifier is 5 V and, therefore, VOUT is also 5 V. 2 VDD VCC ROFS 6 AD586 C1 1nF +5V 5 VOUT VREF+ R1 10k VOUT (-5V TO +5V) AD7849* 4 DGND VREF- SIGNAL GND *ADDITIONAL PINS OMITTED FOR CLARITY. VSS AGND -15V 01008-024 8 +15V TIMER Figure 23. Generating a 5 V Output Range from a Single +5 V Rev. C | Page 15 of 20 SCLK STD SDIN SC2 SYNC DSP56000 AD7849* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 24. AD7849-to-DSP56000 Interface 01008-029 +15V AD7849 Figure 25 shows a serial interface between the AD7849 and the TMS320C2x DSP processor. In this interface, the CLKX and FSX signals for the TMS320C2x should be generated using external clock/timer circuitry. The FSX pin of the TMS320C2x must be configured as an input. Data from the TMS320C2x is valid on the falling edge of CLKX. Figure 26 shows the LDAC input of the AD7849 being driven from another bit programmable port line (PC1). As a result, the DAC can be updated by taking LDAC low after the DAC input register has been loaded. PC1 PC0 SYNC SCK SCLK MOSI SDIN CLOCK/TIMER LDAC SYNC CLKX SCLK TMS320C2x *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 26. AD7849-to-68HC11 Interface SDIN AD7849* *ADDITIONAL PINS OMITTED FOR CLARITY. AD7849-to-87C51 Interface 01008-030 DX AD7849* 68HC11* Figure 25. AD7849-to-TMS320C2x Interface The clock/timer circuitry generates the LDAC signal for the AD7849 to synchronize the update of the output with the serial transmission. Alternatively, the automatic update mode can be selected by connecting LDAC to DGND. AD7849-to-68HC11 Interface Figure 26 shows a serial interface between the AD7849 and the 68HC11 microcontroller. SCK of the 68HC11 drives SCLK of the AD7849, while the MOSI output drives the serial data line of the AD7849. The SYNC signal is derived from a port line (PC0 shown). For correct operation of this interface, the 68HC11 should be configured such that its CPOL bit is a 0 and its CPHA bit is a 1. When data is transmitted to the part, PC0 is taken low. When the 68HC11 is configured like this, data on MOSI is valid on the falling edge of SCK. The 68HC11 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7849, PC0 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the AD7849. When the second serial transfer is complete, the PC0 line is taken high. A serial interface between the AD7849 and the 87C51 microcontroller is shown in Figure 27. TXD of the 87C51 drives SCLK of the AD7849, while RXD drives the serial data line of the part. The SYNC signal is derived from the P3.3 port line, and the LDAC line is driven from the P3.2 port line. The 87C51 provides the LSB of its SBUF register as the first bit in the serial data stream. Therefore, ensure that the data in the SBUF register is arranged correctly so that the most significant bits are the first to be transmitted to the AD7849, and the last bit to be sent is the LSB of the word to be loaded to the AD7849. When data is transmitted to the part, P3.3 is taken low. Data on RXD is valid on the falling edge of TXD. The 87C51 transmits its serial data in 8-bit bytes, with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7849, P3.3 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the AD7849. When the second serial transfer is complete, the P3.3 line is taken high. Figure 27 shows the LDAC input of the AD7849 driven from the bit programmable P3.2 port line. As a result, the DAC output can be updated by taking the LDAC line low following the completion of the write cycle. Alternatively, LDAC can be hardwired low, and the analog output is updated on the 16th falling edge of TXD after the SYNC signal for the DAC goes low. P3.2 LDAC P3.3 SYNC TXD SCLK RXD SDIN AD7849* 87C51* *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 27. AD7849-to-87C51 Interface Rev. C | Page 16 of 20 01008-026 FSX LDAC 01008-025 AD7849-to-TMS320C2x Interface AD7849 APPLICATIONS INFORMATION OPTO-ISOLATED INTERFACE In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD7849 makes it ideal for opto-isolated interfaces because the number of interface lines is kept to a minimum. Figure 28 shows a 4-channel isolated interface using the AD7849. The DCEN pin must be connected high to enable the daisy-chain facility. Four channels with 14-bit or 16-bit resolution are provided in the circuit shown, but this can be expanded to accommodate any number of DAC channels without any extra isolation circuitry. The only limitation is the output update rate. For example, if an output update rate of 10 kHz is required, then all DACs must be loaded and updated in 100 s. Operating at the maximum clock rate of 5 MHz means that it takes 3.2 s to load a DAC. This means that the total number of channels for this update rate is 31, which leaves 800 ns for the LDAC pulse. Of course, as the update rate requirement decreases, the number of possible channels increases. The sequence of events to program the output channels in Figure 28 is as follows: 1. 2. 3. 4. Take the SYNC line low. Transmit the data as four 16-bit words. A total of 64 clock pulses is required to clock the data through the chain. Take the SYNC line high. Pulse the LDAC line low. This updates all output channels simultaneously on the falling edge of LDAC. To reduce the number of optocouplers, the LDAC line can be driven from one shot that is triggered by the rising edge on the SYNC line. A low level pulse of 100 ns duration or greater is all that is required to update the outputs. VDD DATA OUT VDD SDIN CLOCK OUT SCLK VDD VOUT VOUTA SYNC AD7849* SYNC OUT LDAC VDD DCEN 5V SDOUT CONTROL OUT CONTROLLER SDIN VOUT SCLK QUAD OPTO-COUPLER VOUTB SYNC AD7849* LDAC DCEN 5V SDOUT SDIN VOUT SCLK VOUTC SYNC AD7849* LDAC DCEN 5V SDOUT SDIN SCLK VOUT VOUTD SYNC AD7849* DCEN SDOUT *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 28. 4-Channel Opto-Isolated Interface Rev. C | Page 17 of 20 5V 01008-031 LDAC AD7849 OUTLINE DIMENSIONS 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) 20 11 1 10 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) SEATING PLANE 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 070706-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 29. 20-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-20) Dimensions shown in inches and (millimeters) 13.00 (0.5118) 12.60 (0.4961) 20 11 7.60 (0.2992) 7.40 (0.2913) 10 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45 0.25 (0.0098) 8 0 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 30. 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-20) Dimensions shown in millimeters and (inches) Rev. C | Page 18 of 20 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A 1 AD7849 ORDERING GUIDE Model 1 AD7849ANZ AD7849BNZ AD7849CNZ AD7849AR AD7849AR-REEL AD7849ARZ AD7849ARZ-REEL AD7849BR AD7849BR-REEL AD7849BRZ AD7849BRZ-REEL AD7849CR AD7849CR-REEL AD7849CRZ AD7849CRZ-REEL 1 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Resolution (Bits) 14 16 16 14 14 14 14 16 16 16 16 16 16 16 16 Bipolar INL (LSB) 3 8 4 3 3 3 3 8 8 8 8 4 4 4 4 Z = RoHS Compliant Part. Rev. C | Page 19 of 20 Package Description 20-Lead PDIP 20-Lead PDIP 20-Lead PDIP 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W 20-Lead SOIC_W Package Option N-20 N-20 N-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 RW-20 AD7849 NOTES (c)1995-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01008-0-3/11(C) Rev. C | Page 20 of 20