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CMI-8738/PCI-SX AUDIO Specificatio n
3
DIGITAL PIN DESCRIPTION
Name Number PIN
Type Definition
XA31-XA0 126-128,1-2,5-7,12-16,19-21,32
-35,38-41,43-44,47-52 I/O PCI bus address and data lines
XINTA 117 O Interrupt request , activ e-low.
XPRST 119 I Reset
XCLK33 120 I PCI bus clock.
XGNT 121 I Bus master grant, activ e-low.
XREQ 122 O Bus master request, tri-state
output, active-low.
XIDSEL 9 I ID select, active-high.
XFRAME 23 I/O Cycle frame, active-low.
XIRDY 24 I/O Initiator ready, active-low. The bus
master device is ready to transmit
or receive data
XTRDY 25 I/O Target ready, active-low. The target
device is ready to transmit or
receive data
XDEVSEL 26 I/O Device select, active-low. The
target device has dec o ded the
address of the current transaction
as its own chip select range.
XSTOP 29 I/O Stop transaction, active-low. The
target device reque st to the master
to stop the current transaction.
XPAR 30 I/O Parity. The pin indicates even parity
across XA31-XA9 and XCBE3-0 for
both address and data phases.
XCBE3,2,1,0 8,22,31,42 I/O Multiplexed command/byte enable.
These pins indicate cycle type
during the address phase of a
transaction.
VDD 4,10,18,27,37,45,54,115,124 +5V Digital and PCI I/O power pin
GND 3,11,17,28,36,46,53,114,116,12
5 GND Digital and PCI I/O ground
XIN 55 I 14.318Mhz cry stal, or external clock
input
XOUT 56 O 14.318Mhz crystal
XGD7-XGD4 97-94 I Game port switch input pin.
Switch D to switch A
XGD3-XGD0 93-90 I/O Game port resistor input pin.
RC3 to RC0
XTXD 88 O MIDI transmit data
XRXD 89 I MIDI receive data
XBIO3-XBIO
0 109-112 I/O General purpose I/O
VDD5V 83 +5V Digital and PCI I/O power pin
VDDM 100 +5V Digital and PCI I/O power pin
DGND 99 GND Digital and PCI I/O ground
XEECS 84 O EEPROM chip select
PIN DESCRIPTION