EN5335QI-E - ALTERA - Datasheet.Live

00846 September 12, 2012 Rev: G

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EN5335QI

3A Voltage Mode Synchronous Buck PWM

DC-DC Converter with Integrated Inductor

3-Pin Programmable Output

Description

The EN5335QI is a Power System on a Chip

(PowerSoC). It is specifically designed to meet

the precise voltage and fast transient

requirements of present and future high-

performance, low-power processor, DSP, FPGA,

memory boards and system level applications in

a distributed power architecture. Advanced circuit

techniques, ultra high switching frequency, and

very advanced, high-density, integrated circuit

and proprietary inductor technology deliver high-

quality, ultra compact, non-isolated DC-DC

conversion. Operating this converter requires as

few as three external components that include

small value input and output ceramic capacitors

and a soft-start capacitor.

The Enpirion solution significantly helps in

system design and productivity by offering greatly

simplified board design, layout and

manufacturing requirements. In addition, a

reduction in the number of vendors required for

the complete power solution helps to enable an

overall system cost savings.

All Enpirion products are RoHS compliant and

lead-free manufacturing environment compatible.

Typical Application Circuit

VID Output

Voltage Select

VOUT

VIN

VSENSE

47μF

15nF

VOUT

VS0

VS1

VS2

POK

PGNDAGND

PVIN

AVIN

22μF

Figure 1. Simple Layout.

Features

• Integrated INDUCTOR, MOSFETS, Controller

• Footprint 1/3rd that of competing solutions.

• Low Part Count: only 3 MLC Capacitors.

• Up to 10W continuous output power.

• 5MHz operating frequency.

• High efficiency, up to 93%.

• V

OUT accuracy 3% over line, load and temp.

• Wide input voltage range of 2.375V to 6.6V.

• 3-pin VID output voltage select to choose one

of 7 pre-programmed voltage levels.

• Output enable pin and Power OK signal.

• Programmable soft-start time.

• Programmable over-current protection.

• Thermal shutdown, short circuit, and UVLO

• RoHS compliant, MSL level 3, 260C reflow.

Applications

• Point of load regulation for low-power

processors, network processors, DSPs,

FPGAs, and ASICs

• Notebook computers, servers, workstations

• Broadband, networking, LAN/WAN, optical

• Low voltage, distributed power architectures

with 2.5V, 3.3V or 5V rails

• DSL, STB, DVR, DTV, iPC

• Ripple sensitive applications

Ordering Information

Part Number Temp Rating

(°C) Package

EN5335QI -40 to +85 44-pin QFN T&R

EN5335QI-E QFN Evaluation Board

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EN5335QI

Pin Configuration

Below is a top view diagram of the EN5335QI package.

NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or

voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in

part malfunction or damage.

Figure 2. Pin-out diagram, top view.

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Pin Descriptions

PIN NAME FUNCTION

1-3 NC

NO CONNECT – Do not electrically connect these pins to each other or to

PCB.

4-6 NC(SW)

No Connect. These pins are internally connected to the switch node of the

internal MOSFETs. NC(SW) pins are not to be electrically connected to any

external signal, ground, or voltage.

7 NC No connect – Do not electrically connect these pins to each other or to PCB.

8-14 VOUT

Regulated converter output. Connect these pins to the load and place output

capacitor from these pins the PGND pins 17-18

15 NC(SW)

No Connect. These pins are internally connected to the switch node of the

internal MOSFETs. NC(SW) pins are not to be electrically connected to any

external signal, ground, or voltage.

16 NC No connect – Do not electrically connect these pins to each other or to PCB.

17-20 PGND

Output power ground. Connect these pins to the ground electrode of the

output filter capacitors. Refer to layout guideline section.

21-24 PVIN

Input power supply. Connect to input power supply. Decouple with input

capacitor to PGND (pins 19-20).

25-26 NC No connect – Do not electrically connect these pins to each other or to PCB.

27 ROCP

Optional Over Current Protection adjust pin. Place ROCP resistor between

this pin and AGND (pin 40) to increase the over current trip point by 50%.

28 AVIN

Analog voltage input for the controller circuits. Connect this pin to the input

power supply.

29 AGND Analog ground for the controller circuits.

30-31 NC No connect – Do not electrically connect these pins to each other or to PCB.

32 VS2 Voltage select line 2 input. See Table 1.

33 VS1 Voltage select line 1 input. See Table 1.

34 VS0 Voltage select line 0 input. See Table 1.

35 POK

Power OK is an open drain transistor for power system state indication. POK

is a logic high when VOUT is with -10% to +20% of VOUT nominal.

36 VSENSE

Remote voltage sense input. Connect this pin to the load voltage at the point

to be regulated.

37 SS

Soft-Start node. The soft-start capacitor is connected between this pin and

AGND. The value of this resistor determines the startup timing.

38 EAIN Optional Error Amplifier input. Allows for customization of the control loop.

39 EAOUT Optional Error Amplifier output. Allows for customization of the control loop.

40 COMP

Optional Error Amplifier Buffer output. Allows for customization of the control

loop.

41 ENABLE

Input Enable. Applying a logic high, enables the output and initiates a soft-

start. Applying a logic low disables the output.

42-44 NC No connect – Do not electrically connect these pins to each other or to PCB.

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EN5335QI

Block Diagram

(+)

(-)

Error

Amp

VOUT

P-Drive

N-Drive

UVLO

Thermal Limit

Current Limit

Soft Start

Sawtooth

Generator

(+)

(-)

PWM

Comp

PVIN

ENABLE

Compensation

Network

Bandgap

Reference

PGND

Voltage

Selector

VS0

VS1

VS2

VSENSE

EAIN

EAOUT

ROCP

Reference

Voltage

selector

COMP

Over Voltage

power

Good

Logic

Over

Voltage VOUT

POK

Figure 3. System block diagram.

Absolute Maximum Rati ngs

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond

recommended operating conditions is not implied. Stress beyond Absolute maximum ratings may

cause permanent damage to the device. Exposure to absolute maximum rated conditions for

extended periods may affect device reliability.

Maximum Electrical Ratings Min Max

Voltages on: VIN, VOUT -0.3V 7.0V

Voltages on: VSENSE -0.3V VIN + 0.3V

Voltages on: VS0-VS2 (Note 1) -0.3V VIN + 0.3V

Voltages on: ENABLE -0.3V VIN + 0.3V

Maximum Thermal Ratings

Ambient operating range -40°C +85°C

Storage Temperature Range -65°C +150°C

Reflow Peak Body Temperature MSL3 (10 Sec) +260°C

Note 1: VS0-VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as required.

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Recommended Operating Conditions

PARAMETER SYMBOL MIN MAX UNITS

Input Voltage Range (for output voltages < 1.2V) VIN 2.375 5.5 V

Input Voltage Range (for output voltages ≥ 1.2V) VIN 2.375 6.6 V

EN5335QI Operating Ambient Temperature TA -40 +85 °C

Operating Junction Temperature TJ -40 +125 °C

Thermal Characteristics

PARAMETER SYMBOL TYP UNITS

Thermal Shutdown TSD 150 °C

Thermal Shutdown Hysteresis TSDH 15 °C

Thermal Resistance: Junction to Case (0 LFM) (Note 2)

JC 3 °C/W

Thermal Resistance: Junction to Ambient (0 LFM)

JA 25 °C/W

Note 2: Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.

Electrical Characteristics

NOTE: VIN=5.5V over operating temperature range unless otherwise noted. Typical values are at TA =

25°C.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Input

Voltage (for output

voltages < 1.2V)

VIN 2.375 5.5 V

Operating Input

Voltage (for output

voltages ≥ 1.2V)

VIN 2.375 6.6 V

VOUT Initial Accuracy ΔVOUT_INIT

TA = 25C, VIN = 5.0V, ILOAD = 0A;

• All VID Settings except 0.8V

• 0.8V

-2

-3

VID Output Voltage

Settings VOUT

VS2 VS1 VS0

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

3.3

2.5

1.8

1.5

1.25

1.2

0.8

reserved

Drop out voltage VIN - VOUT Drop out voltage at full load 600 mV

Shut-Down Supply

Current IS ENABLE=0V 100 μA

Switching Frequency FOSC 5 MHz

VOUT

Output Voltage

Regulation VOUT

Over line, load and temperature

VID Output Voltage Setting (V):

1.2, 1.25, 1.5, 1.8, 2.5, 3.3

0.8V

-3.0

-4.0

3.0

4.0

Maximum Continuous Output Current

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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Over Current Trip

Piont IOCP 4.5 A

Enable Operation

Disable Threshold VDISABLE Max voltage to ensure the converter is

disabled 0.8 V

Enable Threshold VENABLE 2.375V ≤ VIN ≤ 5.5V

5.5V < VIN

1.8

2.0 V

Enable Pin Current IENABLE V

IN = 5.5V 50

Voltage Select Operation

VSX Logic Low

Threshold VSX-Low Threshold voltage for Logic Low 0.8 V

VSX Logic High

Threshold VSX-High

Threshold voltage for Logic High

(internally pulled high; can be left

floating to achieve logic high)

1.8 VIN V

VSX Pin Current IVSX

(VIN = 5.5V)

VSx = GND

VSx = VIN

VSx = Open

μA

Power OK Operation

POK low voltage VPOK I

POK = 4mA (sink current) 0.4 V

Max POK Voltage VPOK V

IN V

Typical Performance Characteristics

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

Lo a d C urre nt ( A)

E ffici e n cy (%)

=5.0V

OUT

= 3.3V

OUT

= 2.5V

OUT

= 1.8V

OUT

= 1.5V

OUT

= 1.2V

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

Lo a d C urre nt ( A)

E ffici e n cy (%)

=5.0V

OUT

= 3.3V

OUT

= 2.5V

OUT

= 1.8V

OUT

= 1.5V

OUT

= 1.2V

Efficiency versus Load, VIN = 5.0V Efficiency versus Load, VIN = 3.3V

Load transient, 0 – 3A, VIN/VOUT = 5.5V/1.2V Load transient, 0 – 3A, VIN/VOUT = 5.5V/3.3V

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

Lo a d Cu rren t ( A )

Efficiency (%)

=3.3V

OUT

= 0.8V

OUT

= 2.5V

OUT

= 1.8V

OUT

= 1.5V

OUT

= 1.2V

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9

Lo a d Cu rren t ( A )

Efficiency (%)

=3.3V

OUT

= 0.8V

OUT

= 2.5V

OUT

= 1.8V

OUT

= 1.5V

OUT

= 1.2V

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Start-up waveform, VIN/VOUT = 5.5V/1.2V Shut-down waveform, VIN/VOUT = 5.5V/1.2V

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EN5335QI

Theory of Operation

Synchronous Buck Converter

The EN5335QI is a synchronous, pin

programmable power supply with integrated

power MOSFET switches and integrated

inductor. The nominal input voltage range is 2.4-

5.0V. The output can be set to common pre-set

voltages by connecting appropriate combinations

of 3 voltage selection pins to ground. The

feedback control loop is a type III voltage-mode

and the part uses a low-noise PWM topology. Up

to 3A of output current can be drawn from this

converter. The 5MHz operating frequency

enables the use of small-size output capacitors.

The power supply has the following protection

features:

• Over-current protection (to protect the IC

from excessive load current)

• Thermal shutdown with hysteresis

• Over-voltage protection

• Under-voltage lockout circuit to disable the

converter output when the input voltage is

less than approximately 2.2V

Additional features include:

• Soft-start circuit, limiting the in-rush

current when the converter is powered up

• Power good circuit indicating whether the

output voltage is within 90% - 120% of the

programmed voltage

Output Voltage Programming

The EN5335QI output voltage is programmed

using a 3-pin voltage-ID or VID selector. Three

binary VID pins allow the user to choose one of

seven pre-set voltages. Refer to Table 1 for the

proper VID pin settings to choose VOUT.

The voltage select pins, VS0, VS1, and VS2, are

pulled-up internally and so will default to a logic

high, or “1”, if left “open”. Connecting the voltage

select pin to ground will result in a logic “0”.

Table 1: Output Voltage Select Table:

VS2* VS1* VS0* Output Voltage

0 0 0 3.3V

0 0 1 2.5V

0 1 0 1.8V

0 1 1 1.5V

1 0 0 1.25V

1 0 1 1.2V

1 1 0 0.8V

1 1 1 Reserved

Input Capacitor Selection

The EN5335QI requires about 20uF of input

capacitance. Low-cost, low-ESR ceramic

capacitors should be used as input capacitors for

this converter. The dielectric must be X5R or

X7R rated. In some applications, lower value

capacitors are needed in parallel with the larger,

capacitors in order to provide high frequency

decoupling. It is recommended to use 10V rated

MLCC capacitors.

Table 2. Recommended input capacitors.

Description MFG P/N

10uF, 10V, 10%

X7R, 1206

(2 capacitors needed)

Murata

Taiyo Yuden

GRM31CR71A106KA01L

LMK316B7106KL-T

22uF, 10V, 10%

X7R, 1210

(1 capacitor needed)

Murata

Taiyo Yuden

GRM32ER71A226KE20L

LMK325B7226KM-T

Output Capacitor Selection

The EN5335QI has been optimized for use with

approximately 50μF of output capacitance. Low

ESR ceramic capacitors are required with X5R or

X7R rated dielectric formulation. Y5V or

equivalent dielectric formulations must not be

used as these lose capacitance with frequency,

temperature and bias voltage.

Output ripple voltage is determined by the

aggregate output capacitor impedance. Output

impedance, denoted as Z, is comprised of

effective series resistance, ESR, and effective

series inductance, ESL:

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EN5335QI

Z = ESR + ESL.

Placing output capacitors in parallel reduces the

impedance and will hence result in lower ripple

voltage.

nTotal ZZZZ 1

...

111

+++=

Typical ripple versus capacitance is given below:

Output Capacitor

Configuration

Typical Outp ut Ripple (mVp-p)

(as measured on EN5335QI

Evaluation Board)

1 x 47 uF 30

3 x 22 uF 15

Table 3. Recommended output capacitors.

Description MFG P/N

22uF, 6.3V, 10%

X5R, 1206

(3 capacitors needed)

Murata

Taiyo Yuden

GRM31CR60J226KE19L

JMK316BJ226KL-T

47uF, 10V, 10%

X5R, 1210

47uF, 6.3V, 10%

X5R, 1210

(1 capacitor needed)

Murata

AVX

GRM32ER61A476KE20L

12106D476KAT2A

Enable Operation

The ENABLE pin provides a means to shut down

the device, or enable normal operation. A logic

high will enable the converter into normal

operation. When the ENABLE pin is asserted,

the device will undergo a normal soft start. A

logic low will disable the converter and cause it to

shut down. When Enable goes low, circuitry

internal to the device continue to operate to

ensure the output voltage is gradually returned to

zero and the circuits turn off subsequently. A

short low going pulse on Enable is ignored.

Soft-Start Operation

Soft start is a method to reduce in-rush current

when the device is enabled. The output voltage

is ramped up slowly upon start-up. The output

rise time is controlled by choice of a soft-start

capacitor, which is placed between the SS pin

(pin 37) and the AGND pin (pin 29).

Rise Time: TR = Css* 75KΩ

During start-up of the converter, the reference

voltage to the error amplifier is gradually

increased from zero to its final level by an

internal current source of typically 10uA. Typical

soft-start rise time is 1mS to 3mS. The rise time

is measured from the time when AVIN > VUVLO

and the Enable signal crosses its logic high

threshold. Typical SS capacitor values are in the

range of 15nF to 50 nF.

Power-Up/Down Sequencing

During power-up, ENABLE should not be

asserted before PVIN, and PVIN should not be

asserted before AVIN. The PVIN should never

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements.

Pre-Bias Start-up

The EN5335QI does not support startup into a

pre-biased condition. Be sure the output

capacitors are not charged or the output of the

EN5335QI is not pre-biased when the EN5335QI

is first enabled.

POK Operation

The POK signal is an open drain signal from the

converter indicating the output voltage is within

the specified range. The POK signal will be a

logic high when the output voltage is within 90% -

120% of the programmed output voltage. If the

output voltage goes outside of this range, the

POK signal will be a logic low until the output

voltage has returned to within this range. In the

event of an over-voltage condition the POK

signal will go low and will remain in this condition

until the output voltage has dropped to 95% of

the programmed output voltage before returning

to the high state (see also: Over Voltage

Protection).

Over-Current Protection

The current limit function is achieved by sensing

the current flowing through the sense P-

MOSFET. When the sensed current exceeds the

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EN5335QI

current limit, both NFET and PFET switches are

turned off. If the over-current condition is

removed, the over-current protection circuit will

enable the PWM operation. This circuit is

designed to provide high noise immunity.

The nominal over current trip point is set to 4.5A.

It is possible to increase the over-current set

point by about 50% by connecting a 7.5kΩ

resistor between ROCP (pin 27) and GND. The

typical voltage at the ROCP pin is 0.75V.

In some cases, such as the start-up of FPGA

devices, it is desirable to blank the over-current

protection feature. In order to disable over-

current protection, the ROCP pin should be tied

to any voltage between 2.5V and PVIN.

Over-Voltage Protection

When the output voltage exceeds 120% of the

programmed output voltage, the PWM operation

stops, the lower N-MOSFET is turned on and the

POK signal goes low. When the output voltage

drops below 95% of the programmed output

voltage, normal PWM operation resumes and

POK returns to its high state.

Thermal Overload Protection

Thermal shutdown will disable operation once

the Junction temperature exceeds approximately

150ºC. Once the junction temperature drops by

approx 25ºC, the converter will re-start with a

normal soft-start.

Input Under-voltage Lock-out

Circuitry is provided to ensure that when the

input voltage is below the specified voltage

range, the converter will not start-up. Circuits for

hysteresis, input de-glitch and output leading

edge blanking are included to ensure high noise

immunity and prevent false tripping.

Compensation

The EN5335QI is internally compensated

through the use of a type 3 compensation

network and is optimized for use with about 50μF

of output capacitance and will provide excellent

loop bandwidth and transient performance for

most applications. (See the section on Capacitor

Selection for details on recommended capacitor

types.) Voltage mode operation provides high

noise immunity at light load.

In some cases modifications to the compensation

may be required. For more information, contact

Enpirion Applications Engineering support.

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Design Considerations for Lead-Frame Based Modules

Exposed Metal on Bottom of Pac ka ge

Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance,

and in overall foot print. However, they do require some special considerations.

In the assembly process lead frame construction requires that, for mechanical support, some of the

lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.

This results in several small pads being exposed on the bottom of the package.

Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to

the PC board. The PCB top layer under the EN5335QI should be clear of any metal except for the

large thermal pad. The “grayed-out” area in Figure 4 represents the area that should be clear of any

metal (traces, vias, or planes), on the top layer of the PCB. Figure 5 shows the recommended PCB

footprint for this device.

Figure 4. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or

electrically connected to the PCB.

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EN5335QI

Figure 5. Recommended PCB footprint.

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EN5335QI

Package Dimensions

Figure 6. Package dimensions.

Contact Information

Enpirion, Inc.

Perryville III

53 Frontage Road, Suite 210

Hampton, NJ 08827

USA

Phone: 908-894-6000

Fax: 908-894-6090

Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is

believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party righ ts, which may

result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment

used in hazardous environment without the express written authority from Enpirion.