www.nuvoton.com 4 Revision 1.2
WPCN381U
Table of Contents
Revision Record ................................................................................................................................................ 3
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM ........................................................................................................... 8
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY ...................................................................... 9
1.3 PIN MULTIPLEXING ................................................................................................................... 9
1.4 DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 10
1.4.1 LPC Bus Interface ....................................................................................................... 10
1.4.2 Clocks .......................................................................................................................... 10
1.4.3 Infrared (IR) ................................................................................................................ 10
1.4.4 Serial Ports (SP1, SP2) ............................................................................................... 10
1.4.5 General-Purpose Input/Output (GPIO) Ports ............................................................... 11
1.4.6 Power and Ground ..................................................................................................... 11
1.4.7 Strap Configuration ...................................................................................................... 12
1.4.8 Test and Miscellaneous ............................................................................................... 12
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS ............................................................ 13
2.0 Power, Reset and Clocks
2.1 POWER ..................................................................................................................................... 14
2.1.1 Power Planes ..............................................................................................................14
2.1.2 Power States ............................................................................................................... 14
2.1.3 Power Connection and Layout Guidelines .................................................................. 14
2.2 RESET SOURCES AND TYPES ............................................................................................... 15
2.2.1 VDD Power-Up Reset .................................................................................................. 15
2.2.2 Hardware Reset ........................................................................................................... 15
2.3 CLOCK DOMAINS ..................................................................................................................... 15
2.3.1 LPC Domain ................................................................................................................15
2.3.2 48 MHz Domain ........................................................................................................... 15
2.3.3 WPCN381U Power-Up ................................................................................................ 16
2.3.4 Specifications .............................................................................................................. 16
2.4 TESTABILITY SUPPORT .......................................................................................................... 17
2.4.1 ICT ............................................................................................................................... 17
2.4.2 XOR Tree Testing ........................................................................................................ 17
2.4.3 Test Mode Entry Sequence ......................................................................................... 17
3.0 Device Architecture and Configuration
3.1 OVERVIEW ............................................................................................................................... 18
3.2 CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 19
3.2.1 The Index-Data Register Pair ...................................................................................... 19
3.2.2 Banked Logical Device Registers Structure ................................................................ 19
3.2.3 Standard Configuration Register Definitions ............................................................... 20
3.2.4 Standard Configuration Registers ............................................................................... 22
3.2.5 Default Configuration Setup ........................................................................................ 23