IS64LP12832 IS64LP12836 ISSI (R) 128K x 32, 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM FEATURES * Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-pin TQFP and 119-pin PBGA package * Power-down snooze mode * Power Supply + 3.3V VDD + 3.3V OR 2.5V VDDQ (I/O) * Temperature offerings Option A2: -400 C to +1050 C Option A3: -400 C to +1250 C PRELIMINARY INFORMATION JULY 2004 DESCRIPTION The ISSI IS64LP12832 and IS64LP12836 are high-speed synchronous static RAMs designed to provide high-performance memory with burst for high-speed networking and communication applications. IS64LP12832 is organized as 131,072 words by 32 bits. IS64LP12836 is organized as 131,072 words by 36 bits. The IS64LP12832 and IS64LP12836 are fabricated with ISSI's advanced CMOS technology. These devices integrate a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. BW1 controls DQa, BW2 controls DQb, BW3 controls DQc, BW4 controls DQd, conditioned by BWE being LOW. A LOW on GW input would cause all bytes to be written. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -150 4.3 6.7 150 Units ns ns MHz Copyright (c) 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 1 IS64LP12832 IS64LP12836 ISSI (R) BLOCK DIAGRAM MODE Q0 CLK CLK A0' A0 BINARY COUNTER CE ADV ADSC ADSP Q1 A1' A1 128K x 32/128K x 36 MEMORY ARRAY CLR 17 A D Q 15 17 ADDRESS REGISTER CE CLK 32 or 36 GW BWE BW4 (x32/ x36) D 32 or 36 Q DQd BYTE WRITE REGISTERS CLK BW3 (x32/ x36) D DQc Q BYTE WRITE REGISTERS CLK D Q DQb BYTE WRITE REGISTERS BW2 (x32/ x36) CLK BW1 (x32/ x36) D DQa Q BYTE WRITE REGISTERS CLK CE 32 or 36 4 D CE2 CE2 Q ENABLE REGISTER INPUT REGISTERS CLK OUTPUT REGISTERS CLK DQa-d OE CE CLK D Q ENABLE DELAY REGISTER CLK OE 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI (R) PIN CONFIGURATION A A CE CE2 BW4 BW3 BW2 BW1 CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A NC DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd NC 128K x 32 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BW1-BW4 BWE Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 GW CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable 3 IS64LP12832 IS64LP12836 ISSI (R) PIN CONFIGURATION 1 2 3 4 5 VDDQ 6 A6 4 A4 ADSP 8 A8 NC CE2 A3 3 ADSC A9 9 NC A7 7 A2 2 VDD DQc1 1 DQPc GND NC GND DQPb 8 DQb8 DQc2 2 DQc3 3 GND CE GND DQb6 6 DQb7 7 VDDQ DQc4 4 GND OE GND DQb5 5 VDDQ 5 DQc5 DQc6 6 BW3 ADV BW2 DQb4 4 3 DQb3 DQc7 7 DQc8 8 GND GW GND DQb2 2 DQb1 1 VDDQ VDD NC VDD NC VDD VDDQ DQd1 1 DQd2 2 GND CLK GND DQa7 7 DQa8 8 DQd4 4 DQd3 3 BW4 NC BW1 DQa5 5 DQa6 6 VDDQ DQd5 5 GND BWE GND DQa4 4 VDDQ DQd6 6 DQd7 7 GND A1 GND DQa3 3 DQa2 2 DQd8 8 DQPd GND A0 GND DQPa DQa1 1 NC A5 5 MODE VDD NC NC NC A10 10 11 A11 VDDQ NC NC NC A B 6 100-Pin TQFP 16 A16 CE2 7 VDDQ NC C A12 12 A15 15 NC D E F G H J K L M N P R A13 13 NC T A14 14 A A CE CE2 BW4 BW3 BW2 BW1 CE2 VDD GND CLK GW BWE OE ADSC ADSP ADV A A 119-pin PBGA (Top View) NC ZZ NC VDDQ DQPc DQc DQc VDDQ GND DQc DQc DQc DQc GND VDDQ DQc DQc NC VDD NC GND DQd DQd VDDQ GND DQd DQd DQd DQd GND VDDQ DQd DQd DQPd U DQPb DQb DQb VDDQ GND DQb DQb DQb DQb GND VDDQ DQb DQb GND NC VDD ZZ DQa DQa VDDQ GND DQa DQa DQa DQa GND VDDQ DQa DQa DQPa MODE A A A A A1 A0 NC NC GND VDD NC NC A A A A A A A NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 128K x 36 PIN DESCRIPTIONS A0, A1 A CLK ADSP ADSC ADV BW1-BW4 BWE 4 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VDD GND VDDQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI (R) TRUTH TABLE Operation Address Used Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L X X L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L X L X H L H L L X H L H L H H H H X H X H H H X H H H H H X H X H H H X H ADV WRITE X X X X X X X X X X X X X Read X Write L Read L Read L Read L Read L Write L Write H Read H Read H Read H Read H Write H Write OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BW1 X H L L X BW2 X H H L X Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 BW3 X H H L X BW4 X H H L X 5 IS64LP12832 IS64LP12836 ISSI (R) INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = GND) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN VDD Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on VDD Supply Relative to GND Value -55 to +150 1.6 100 -0.5 to VDDQ + 0.3 -0.5 to VDD + 0.5 Unit C W mA V V -0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. 6 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI (R) OPERATING RANGE Range Ambient Temperature VDD 3.3V (I/O) VDDQ 2.5V (I/O) VDDQ A2 -40C to +105C 3.3V, +10%, -5% 3.3V, +10%, -5% 2.5V + 5% A3 -40C to +125C 3.3V, +10%, -5% 3.3V, +10%, -5% 2.5V + 5% DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range) Symbol VOH Parameter OutputHIGHVoltage VOL OutputLOWVoltage VIH VIL ILI ILO Input HIGH Voltage Input LOW Voltage InputLeakageCurrent OutputLeakageCurrent Test Conditions IOH = -4.0 mA (3.3V) IOH = 1.0 mA (2.5V) IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) GND VIN VDD GND VOUT VDDQ, OE = VI 2.5V (I/O) Min. Max. 2.0 -- 3.3V (I/O) Min. Max. 2.4 -- Unit V -- 0.4 -- 0.4 V 1.7 -0.3 -5 -5 VDD + 0.3 0.7 5 5 2.0 -0.3 -5 -5 VDD + 0.3 0.8 5 5 V V A A POWER SUPPLY CHARACTERISTICS (Over Operating Range) Symbol ICC Parameter AC Operating Supply Current ISB Standby Current IZZ Power-down Mode Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, VDD = Max. Cycle Time tKC min. Device Deselected, VDD = Max., All Inputs = VIH or VIL CLK Cycle Time tKC min. ZZ = VDD Clock Running All Inputs GND + 0.2V or VDD - 0.2V A2 A3 -150 Max. 280 290 Unit mA mA A2 A3 80 90 mA mA A2 A3 20 25 mA mA Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VDD. 2. The MODE pin should be tied to VDD or GND. It exhibits 10 A maximum leakage current when tied to GND + 0.2V or VDD - 0.2V. Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 7 IS64LP12832 IS64LP12836 ISSI (R) CAPACITANCE(1,2) Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, VDD = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 ZO = 50 +3.3V Output OUTPUT 50 351 1.5V Figure 1 8 5 pF Including jig and scope Figure 2 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 ZO = 50 +2.5V Output OUTPUT 50 1538 1.25V Figure 3 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 5 pF Including jig and scope Figure 4 9 (R) IS64LP12832 IS64LP12836 ISSI (R) READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol (3) fMAX tKC(3) tKH tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tWS(3) tCES(3) tAVS(3) tAH(3) tSH(3) tWH(3) tCEH(3) tAVH(3) Parameter -150 Min. Max. Unit Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -- 6.7 2.6 2.6 -- 3.0 0 1.5 -- 0 0 2.0 2.0 1.5 1.5 2.0 1.5 1.0 1.0 1.0 1.0 1.0 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 150 -- -- -- 4.3 -- -- 3.5 4.2 -- -- 3.5 -- -- -- -- -- -- -- -- -- -- Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2. 3. Tested with load in Figure 1. 10 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI (R) READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC initiate read ADSC tAVH tAVS Suspend Burst ADV tAS A tAH RD1 RD3 RD2 tWS tWH tWS tWH GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 tOEHZ tOEQ OE DATAOUT tKQX tOEQX tOELZ High-Z 1a 2a 2b 2c 2d tKQLZ 3a tKQHZ tKQ DATAIN High-Z Pipelined Read Single Read Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 Burst Read Unselected 11 IS64LP12832 IS64LP12836 ISSI (R) WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(1) tKH(1) tKL(1) tAS(1) tSS(1) tWS(1) tDS(1) tCES(1) tAVS(1) tAH(1) tSH(1) tDH(1) tWH(1) tCEH(1) tAVH(1) Parameter Cycle Time Clock High Time Clock Low Time Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -150 Min. Max. 6.7 -- 2.6 -- 2.6 -- 2.0 -- 1.5 -- 1.5 -- 1.5 -- 2.0 -- 1.5 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- 1.0 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note: 1. Tested with load in Figure 1. 12 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP ADSC initiate Write ADSC tAVH ADV must be inactive for ADSP Write tAVS ADV tAS A tAH WR1 WR2 tWS tWH tWS tWH tWS tWH WR3 GW BWE BW4-BW1 WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE Masks ADSP CE Unselected with CE2 CE2 and CE2 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b Burst Write Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 2c 2d 3a Write Unselected 13 (R) IS64LP12832 IS64LP12836 ISSI (R) SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) Symbol tKC(3) tKH(3) tKL(3) tKQ(3) tKQX(1) tKQLZ(1,2) tKQHZ(1,2) tOEQ(3) tOEQX(1) tOELZ(1,2) tOEHZ(1,2) tAS(3) tSS(3) tCES(3) tAH(3) tSH(3) tCEH(3) tZZS tZZREC -150 Min. 6.7 2.6 2.6 -- 3.0 0 1.5 -- 0 0 2 2.0 1.5 2.0 1.0 1.0 1.0 2 2 Parameter Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Disable to Output Invalid Output Enable to Output Low-Z Output Disable to Output High-Z Address Setup Time Address Status Setup Time Chip Enable Setup Time Address Hold Time Address Status Hold Time Chip Enable Hold Time ZZ Standby ZZ Recovery Max. -- -- -- 4.3 -- -- 3.5 4.2 -- -- 3.5 -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Notes: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 14 Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 IS64LP12832 IS64LP12836 ISSI SNOOZE AND RECOVERY CYCLE TIMING tKC CLK tSS tSH tAS tAH tKH tKL ADSP ADSC ADV A RD2 RD1 GW BWE BW4-BW1 tCES tCEH tCES tCEH tCES tCEH CE CE2 CE2 tOEHZ tOEQ OE tOEQX tOELZ DATAOUT High-Z 1a tKQLZ tKQ DATAIN tKQX tKQHZ High-Z tZZS tZZREC ZZ Single Read Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 Snooze with Data Retention Read 15 (R) IS64LP12832 IS64LP12836 ISSI (R) ORDERING INFORMATION Temperature Range (A2): -40C to +105C Speed Order Part No. 150 MHz IS64LP12832-150TQA2 IS64LP12836-150TQA2 Organization 128Kx32 128Kx36 Package TQFP TQFP Temperature Range (A3): -40C to +125C 16 Speed Order Part No. 150 MHz IS64LP12832-150TQA3 IS64LP12836-150TQA3 IS64LP12836-150BA3 Organization Package 128Kx32 128Kx36 128Kx36 TQFP TQFP PBGA Integrated Silicon Solution, Inc. -- 1-800-379-4774 Rev. 00C 07/12/04 ISSI PACKAGING INFORMATION (R) Plastic Ball Grid Array Package Code: B (119-pin) b (119X) E A 7 6 5 4 D2 D1 e A2 A3 E2 Sym. Min. N0. Leads Max. SEATING PLANE INCHES Min. Max. Notes: 119 A -- 2.41 -- 0.095 A1 0.50 0.70 0.020 0.028 A2 0.80 1.00 0.032 0.039 A3 1.30 1.70 0.051 0.067 A4 0.56 BSC 0.60 0.90 0.024 0.035 D 21.80 22.20 0.858 0.874 20.32 BSC 0.800 BSC D2 19.40 19.60 0.764 0.772 E 13.80 14.20 0.543 0.559 E1 E2 e 7.62 BSC 11.90 12.10 1.27 BSC 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.022 BSC b D1 E1 A1 A4 MILLIMETERS 1 A B C D E F G H J K L M N P R T U 30 D 3 2 0.300 BSC 0.469 0.476 0.050 BSC Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774 Rev. B 02/12/03 ISSI PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A -- 1.60 -- 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o 128 -- 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. -- 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max -- 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. (R)