FemtoClock(R) Crystal-to-3.3V, 2.5V LVPECL 400MHz Frequency Synthesizer ICS843801I-24 DATA SHEET General Description Features The ICS843801I-24 is a 400MHz Frequency Synthesizer. The ICS843801I-24 uses an 18pF parallel resonant crystal over the range of 21.5625MHz - 25.3125MHz. The ICS843801I-24 has excellent <1ps phase jitter performance, over the 12kHz - 20MHz integration range. The ICS843801I-24 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * * One differential 3.3V, 2.5V LVPECL output * Output frequency range: 172.5MHz - 202.5MHz, and 345MHz - 405MHz * * VCO range: 690MHz - 810MHz * * * Full 3.3V or 2.5V operating supply modes Crystal oscillator interface, 18pF parallel resonant crystal (21.5625MHz - 25.3125MHz) RMS phase jitter at 400MHz, using a 25MHz crystal (12kHz - 20MHz): 0.88ps (typical), @ 3.3V -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package Common Configuration Table Inputs Crystal Frequency (MHz) FREQ_SEL M N Multiplication Value M/N Output Frequency (MHz) 25 0 32 2 16 400 25 1 (default) 32 4 8 200 Pin Assignment Block Diagram FREQ_SEL Pullup XTAL_IN OSC XTAL_OUT Phase Detector VCO 690MHz - 810MHz FREQ_SEL N 0 /2 1 (default) /4 M = /32 (fixed) ICS843801AGI-24 REVISION A AUGUST 10, 2011 1 Q VCCA XTAL_OUT XTAL_IN VEE 1 2 3 4 8 7 6 5 VCC Q nQ FREQ_SEL nQ ICS843801I-24 8 Lead TSSOP 4.40mm x 3.0mm x 0.925 package body G Package Top View (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name 1 VCCA Power Type Analog supply pin Description 2, 3 XTAL_OUT XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 4 VEE Power Negative supply pin. 5 FREQ_SEL Input 6, 7 nQ, Q Output Pullup Differential output pair. LVPECL interface levels. Frequency select pin, LVCMOS/LVTTL interface levels. 8 VCC Power Core supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k ICS843801AGI-24 REVISION A AUGUST 10, 2011 Test Conditions Minimum 2 Typical Maximum Units (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI XTAL_IN Other Inputs 0V to VCC -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Package Thermal Impedance, JA 129.5C/W (0 mps) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCC - 0.09 3.3 VCC V Power Supply Current 66 mA ICCA Analog Supply Current 9 mA IEE Power Supply Current 72 mA Table 3B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICC Minimum Typical Maximum Units 2.375 2.5 2.625 V VCC - 0.09 2.5 VCC V Power Supply Current 60 mA ICCA Analog Supply Current 9 mA IEE Power Supply Current 72 mA ICS843801AGI-24 REVISION A AUGUST 10, 2011 Test Conditions 3 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Table 3C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum VIH Input High Voltage VCC = 3.3V VIL Input Low Voltage IIH Input High Current VCC = VIN = 3.465V or 2.625V IIL Input Low Current VCC = 3.465V or 2.625V, VIN = 0V Typical Maximum Units 2 VCC + 0.3 V VCC = 2.5V 1.7 VCC + 0.3 V VCC = 3.3V -0.3 0.8 V VCC = 2.5V -0.3 0.7 V 5 A -150 A Table 3D. LVPECL DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.6 1.0 V Maximum Units NOTE 1: Outputs termination with 50 to VCC - 2V. Table 3E. LVPECL DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.5 V VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V Maximum Units 25.3125 MHz Equivalent Series Resistance (ESR) 50 Shunt Capacitance 7 pF NOTE 1: Outputs termination with 50 to VCC - 2V. Table 4. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Fundamental Frequency ICS843801AGI-24 REVISION A AUGUST 10, 2011 Typical 21.5625 4 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER AC Electrical Characteristics Table 5A. AC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40C to 85 Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter, Random; NOTE 1 tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 tjit(per) RMS Period Jitter tL PLL Lock Time tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum Units 172.5 202.5 MHz 345 405 MHz 200MHz, Integration Range: 12kHz - 20MHz 0.87 1.02 ps 400MHz, Integration Range: 12kHz - 20MHz 0.88 0.98 ps 13 ps 2.1 ps 10 ms 200 500 ps 48 52 % 0.18 20% to 80% NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. Table 5B. AC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40C to 85 Symbol Parameter fOUT Output Frequency tjit(O) RMS Phase Jitter, Random; NOTE 1 tjit(cc) Test Conditions Minimum Maximum Units 172.5 Typical 202.5 MHz 345 405 MHz 200MHz, Integration Range: 12kHz - 20MHz 0.87 1.05 ps 400MHz, Integration Range: 12kHz - 20MHz 0.89 1.06 ps 16 ps Cycle-to-Cycle Jitter; NOTE 2 tjit(per) RMS Period Jitter tL PLL Lock Time tR / tF Output Rise/Fall Time odc Output Duty Cycle 0.20 20% to 80% 2.6 ps 10 ms 200 500 ps 48 52 % NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE 1: Refer to Phase Noise Plots. NOTE 2: These parameters are guaranteed by characterization. Not tested in production. ICS843801AGI-24 REVISION A AUGUST 10, 2011 5 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 200MHz, (3.3V) Noise Power dBc Hz 200MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.87ps (typical) Offset Frequency (Hz) ICS843801AGI-24 REVISION A AUGUST 10, 2011 6 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 400MHz, (3.3V) Noise Power dBc Hz 400MHz RMS Phase Jitter (Random) 12kHz to 20MHz = 0.88ps (typical) Offset Frequency (Hz) ICS843801AGI-24 REVISION A AUGUST 10, 2011 7 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2V 2V 2V 2V VCC Qx SCOPE VCC VCCA LVPECL Qx SCOPE VCCA LVPECL nQx nQx VEE VEE -1.3V 0.165V -0.5V 0.125V 2.5V LVPECL Output Load AC Test Circuit 3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit Phase Noise Plot Noise Power nQ Q tcycle n tcycle n+1 tjit(cc) = |tcycle n - tcycle n+1| 1000 Cycles Offset Frequency f1 f2 RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers RMS Phase Jitter Cycle-to-Cycle Jitter VOH nQ VREF (Trigger Edge) t PW VOL 1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements Reference Point Q t odc = PERIOD t PW x 100% t PERIOD Histogram Mean Period (First edge after trigger) Output Duty Cycle/Pulse Width/Period Period Jitter ICS843801AGI-24 REVISION A AUGUST 10, 2011 8 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information, continued nQ 80% 80% VSW I N G Q 20% 20% tR tF PLL Lock Time Output Rise/Fall Time ICS843801AGI-24 REVISION A AUGUST 10, 2011 9 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Applications Information Overdriving the XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 1A. The XTAL_OUT pin can be left floating. The maximum amplitude of the input signal should not exceed 2V and the input edge rate can be as slow as 10ns. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. By overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. 3.3V 3.3V R1 100 Ro ~ 7 Ohm C1 Zo = 50 Ohm XTAL_IN RS 43 R2 100 Driv er_LVCMOS 0.1uF XTAL_OUT Cry stal Input Interf ace Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface VCC=3.3V C1 Zo = 50 Ohm XTAL_IN R1 50 Zo = 50 Ohm 0.1uF XTAL_OUT LVPECL Cry stal Input Interf ace R2 50 R3 50 Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface ICS843801AGI-24 REVISION A AUGUST 10, 2011 10 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The differential outputs are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 R3 125 3.3V 3.3V Zo = 50 3.3V R4 125 3.3V 3.3V + Zo = 50 + _ LVPECL Input Zo = 50 R1 50 _ LVPECL R2 50 R1 84 VCC - 2V RTT = 1 * Zo ((VOH + VOL) / (VCC - 2)) - 2 R2 84 RTT Figure 2A. 3.3V LVPECL Output Termination ICS843801AGI-24 REVISION A AUGUST 10, 2011 Input Zo = 50 Figure 2B. 3.3V LVPECL Output Termination 11 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Termination for 2.5V LVPECL Outputs level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCO - 2V. For VCC= 2.5V, the VCC- 2V is very close to ground 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 50 R3 250 + 50 50 + - 50 2.5V LVPECL Driver R1 50 - R2 50 2.5V LVPECL Driver R2 62.5 R4 62.5 R3 18 Figure 3A. 2.5V LVPECL Driver Termination Example Figure 3B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 3C. 2.5V LVPECL Driver Termination Example ICS843801AGI-24 REVISION A AUGUST 10, 2011 12 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Schematic Example Figure 4 shows an example of ICS843801I-24 application schematic. In this example, the device is operated at VCC = VCCA = 3.3V. The 18pF parallel resonant 25MHz crystal is used. The load capacitance C1 = 22pF and C2 = 22pF are recommended for frequency accuracy. Depending on the parasitic of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load capacitance specifications can be used. This will require adjusting C1 and C2 device side of the PCB and the other components can be placed on the opposite side. Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. The filter performance is designed for wide range of noise frequency. This low-pass filter starts to attenuate noise at approximately 10kHz. If a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. Additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843801I-24 provides separate power supplies to isolate any high switching noise from coupling into the internal PLL. The schematic example focuses on functional connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB as close to the power pins as possible. If space is limited, the 0.1F capacitor in each power pin filter should be placed on the 3. 3V 3.3V FB1 R9 133 VCC R10 133 Zo = 50 Ohm muR ata, BLM18BB221SN 1 C13 + C12 0.1uF VCC 10uF Zo = 50 Ohm R1 VDDA 10 C2 10u R12 82.5 C3 0.1u XTAL_OU T XTAL_IN R 13 82.5 C1 0.1u LVPECL Term ination U1 1 2 3 4 VCCA XTAL_OUT XTAL_IN VEE VCC Q nQ F REQ_SEL 8 7 6 5 Q nQ FR EQ_SEL VCC = 3.3V 25MHz F p 8 1 X1 - VCC C1 22pF C2 Logic Input Pin Examples 22pF Set Logic Input to '1' VCC RU1 1K Set Logic Input to '0' VC C Zo = 50 Ohm + Zo = 50 Ohm - RU2 Not Inst all To Logic Input pins RD1 Not Install R15 50 To Logic Input pins LVPECL Optional Y-Termination RD2 1K R16 50 R18 50 Figure 4. ICS843801I-24 Schematic Example ICS843801AGI-24 REVISION A AUGUST 10, 2011 13 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843801I-24. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843801I-24 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 72mA = 249.48mW * Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 249.48mW + 30mW = 279.48mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 129.5C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.279W * 129.5C/W = 121.2C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resitance JA for 8 Lead TSSOP, Forced Convection JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards ICS843801AGI-24 REVISION A AUGUST 10, 2011 0 1 2.5 129.5C/W 125.5C/W 123.5C/W 14 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the LVPECL output pair. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW ICS843801AGI-24 REVISION A AUGUST 10, 2011 15 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 7. JA vs. Air Flow Table for a 8 Lead TSSOP JA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 129.5C/W 125.5C/W 123.5C/W Transistor Count The transistor count for ICS843801I-24 is: 1649 Package Outline and Package Dimensions Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS843801AGI-24 REVISION A AUGUST 10, 2011 16 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 9. Ordering Information Part/Order Number 843801AGI-24LF 843801AGI-24LFT Marking AI24L AI24L Package "Lead-Free" 8 Lead TSSOP "Lead-Free" 8 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring e high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS843801AGI-24 REVISION A AUGUST 10, 2011 17 (c)2011 Integrated Device Technology, Inc. ICS843801I-24 Data Sheet FEMTOCLOCK(R) CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. 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