ICS843801AGI-24LFT - Integrated Device Technology

DATA SHEET

FemtoClock® Crystal-to-3.3V, 2.5V

LVPECL 400MHz Frequency Synthesizer

ICS843801I-24

General Description

The ICS843801I-24 is a 400MHz Frequency Synthesizer. The

ICS843801I-24 uses an 18pF parallel resonant crystal over the

range of 21.5625MHz - 25.3125MHz. The ICS843801I-24 has

excellent <1ps phase jitter performance, over the 12kHz - 20MHz

integration range. The ICS843801I-24 is packaged in a small 8-pin

TSSOP, making it ideal for use in systems with limited board space.

Features

•One differential 3.3V, 2.5V LVPECL output

•Crystal oscillator interface, 18pF parallel resonant crystal

(21.5625MHz - 25.3125MHz)

•Output frequency range: 172.5MHz - 202.5MHz, and

345MHz - 405MHz

•VCO range: 690MHz – 810MHz

•RMS phase jitter at 400MHz, using a 25MHz crystal

(12kHz – 20MHz): 0.88ps (typical), @ 3.3V

•Full 3.3V or 2.5V operating supply modes

•-40°C to 85°C ambient operating temperature

•Available in lead-free (RoHS 6) package

Common Configuration Table

Inputs

Output Frequency (MHz)Crystal Frequency (MHz) FREQ_SEL M N

Multiplication Value

M/N

25 0 32 2 16 400

25 1 (default) 32 4 8 200

VCCA

XTAL_OUT

XTAL_IN

VEE

VCC

FREQ_SEL

Pin Assignment

ICS843801I-24

8 Lead TSSOP

4.40mm x 3.0mm x 0.925 package body

G Package

Top View

OSC Phase

Detector

VCO

690MHz - 810MHz

M = ÷32 (fixed)

FREQ_SEL N

0 ÷2

1 (default) ÷4

Pullup

FREQ_SEL

XTAL_IN

XTAL_OUT

Block Diagram

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Table 1. Pin Descriptions

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

CCA Power Analog supply pin

XTAL_OUT

XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.

EE Power Negative supply pin.

5 FREQ_SEL Input Pullup Frequency select pin, LVCMOS/LVTTL interface levels.

6, 7 nQ, Q Output Differential output pair. LVPECL interface levels.

CC Power Core supply pin.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 3A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C

Table 3B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

Item Rating

Supply Voltage, VCC 4.6V

Inputs, VI

XTAL_IN

Other Inputs

0V to VCC

-0.5V to VCC + 0.5V

Outputs, IO

Continuos Current

Surge Current

50mA

100mA

Package Thermal Impedance, θJA 129.5°C/W (0 mps)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Core Supply Voltage 3.135 3.3 3.465 V

VCCA Analog Supply Voltage VCC – 0.09 3.3 VCC V

ICC Power Supply Current 66 mA

ICCA Analog Supply Current 9mA

IEE Power Supply Current 72 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VCC Core Supply Voltage 2.375 2.5 2.625 V

VCCA Analog Supply Voltage VCC – 0.09 2.5 VCC V

ICC Power Supply Current 60 mA

ICCA Analog Supply Current 9mA

IEE Power Supply Current 72 mA

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Table 3C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

Table 3D. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs termination with 50Ω to VCC – 2V.

Table 3E. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C

NOTE 1: Outputs termination with 50Ω to VCC – 2V.

Table 4. Crystal Characteristics

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage VCC = 3.3V 2 VCC + 0.3 V

VCC = 2.5V 1.7 VCC + 0.3 V

VIL Input Low Voltage VCC = 3.3V -0.3 0.8 V

VCC = 2.5V -0.3 0.7 V

IIH Input High Current VCC = VIN = 3.465V or 2.625V 5 µA

IIL Input Low Current VCC = 3.465V or 2.625V, VIN = 0V -150 µA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.7 V

VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH Output High Voltage; NOTE 1 VCC – 1.4 VCC – 0.9 V

VOL Output Low Voltage; NOTE 1 VCC – 2.0 VCC – 1.5 V

VSWING Peak-to-Peak Output Voltage Swing 0.4 1.0 V

Parameter Test Conditions Minimum Typical Maximum Units

Mode of Oscillation Fundamental

Frequency 21.5625 25.3125 MHz

Equivalent Series Resistance (ESR) 50 Ω

Shunt Capacitance 7pF

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

AC Electrical Characteristics

Table 5A. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Refer to Phase Noise Plots.

NOTE 2: These parameters are guaranteed by characterization. Not tested in production.

Table 5B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Refer to Phase Noise Plots.

NOTE 2: These parameters are guaranteed by characterization. Not tested in production.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 172.5 202.5 MHz

345 405 MHz

tjit(Ø) RMS Phase Jitter, Random;

NOTE 1

200MHz,

Integration Range: 12kHz – 20MHz 0.87 1.02 ps

400MHz,

Integration Range: 12kHz – 20MHz 0.88 0.98 ps

tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 13 ps

tjit(per) RMS Period Jitter 0.18 2.1 ps

tLPLL Lock Time 10 ms

tR / tFOutput Rise/Fall Time 20% to 80% 200 500 ps

odc Output Duty Cycle 48 52 %

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 172.5 202.5 MHz

345 405 MHz

tjit(Ø) RMS Phase Jitter, Random;

NOTE 1

200MHz,

Integration Range: 12kHz – 20MHz 0.87 1.05 ps

400MHz,

Integration Range: 12kHz – 20MHz 0.89 1.06 ps

tjit(cc) Cycle-to-Cycle Jitter; NOTE 2 16 ps

tjit(per) RMS Period Jitter 0.20 2.6 ps

tLPLL Lock Time 10 ms

tR / tFOutput Rise/Fall Time 20% to 80% 200 500 ps

odc Output Duty Cycle 48 52 %

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Typical Phase Noise at 200MHz, (3.3V)

Noise Power dBc

200MHz

RMS Phase Jitter (Random)

12kHz to 20MHz = 0.87ps (typical)

Offset Frequency (Hz)

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Typical Phase Noise at 400MHz, (3.3V)

Noise Power dBc

400MHz

RMS Phase Jitter (Random)

12kHz to 20MHz = 0.88ps (typical)

Offset Frequency (Hz)

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Parameter Measurement Information

3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit

Cycle-to-Cycle Jitter

Period Jitter

2.5V LVPECL Output Load AC Test Circuit

RMS Phase Jitter

Output Duty Cycle/Pulse Width/Period

SCOPE

nQx

LVPECL

VEE

VCC

VCCA

-1.3V ± 0.165V

➤

tcycle n tcycle n+1

tjit(cc) =

tcycle n – tcycle n+1

1000 Cycles

VOH

VRE

VOL

Mean Period

(First edge after trigger)

Reference Point

(Trigger Edge)

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10-7)% of all measurements

Histogram

SCOPE

nQx

LVPECL

VEE

VCC

VCCA

-0.5V ± 0.125V

Offset Frequency

f1f2

Phase Noise Plot

RMS Jitter = Area Under Curve Defined by the Offset Frequency Markers

Noise Power

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Parameter Measurement Information, continued

Output Rise/Fall Time PLL Lock Time

20%

80% 80%

20%

tRtF

VSWING

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Applications Information

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 1A. The XTAL_OUT pin can be left floating. The

maximum amplitude of the input signal should not exceed 2V and the

input edge rate can be as slow as 10ns. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in

half. This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50Ω

applications, R1 and R2 can be 100Ω. This can also be

accomplished by removing R1 and making R2 50Ω. By overdriving

the crystal oscillator, the device will be functional, but note, the device

performance is guaranteed by using a quartz crystal.

Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface

Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface

100

RS 43

Ro ~ 7 Ohm

Driv er_LVCMOS

Zo = 50 Ohm C1

0.1uF

3.3V

Crystal Input Interface

XTA L _ I N

XTA L _ O U T

Crystal Input Interface

XTAL_IN

XTAL_OUT

0.1uF

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

VCC=3.3V

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

The differential outputs are low impedance follower outputs that

generate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50Ω

transmission lines. Matched impedance techniques should be used

to maximize operating frequency and minimize signal distortion.

Figures 2A and 2B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts may

exist and it would be recommended that the board designers

simulate to guarantee compatibility across all printed circuit and clock

component process variations.

Figure 2A. 3.3V LVPECL Output Termination Figure 2B. 3.3V LVPECL Output Termination

3.3V

VCC - 2V

50Ω

RTT

Zo = 50Ω

RTT = * Zo

((VOH + VOL) / (VCC – 2)) – 2

3.3V

LVPECL Input

84Ω

3.3V

125Ω

Zo = 50Ω

LVPECL Input

3.3V

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Termination for 2.5V LVPECL Outputs

Figure 3A and Figure 3B show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating 50Ω

to VCO – 2V. For VCC= 2.5V, the VCC– 2V is very close to ground

level. The R3 in Figure 3B can be eliminated and the termination is

shown in Figure 3C.

Figure 3A. 2.5V LVPECL Driver Termination Example

Figure 3C. 2.5V LVPECL Driver Termination Example

Figure 3B. 2.5V LVPECL Driver Termination Example

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

250Ω

62.5Ω

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

–

2.5V LVPECL Driver

VCC = 2.5V

2.5V

50Ω

18Ω

–

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Schematic Example

Figure 4 shows an example of ICS843801I-24 application schematic.

In this example, the device is operated at VCC = VCCA = 3.3V. The

18pF parallel resonant 25MHz crystal is used. The load capacitance

C1 = 22pF and C2 = 22pF are recommended for frequency accuracy.

Depending on the parasitic of the printed circuit board layout, these

values might require a slight adjustment to optimize the frequency

accuracy. Crystals with other load capacitance specifications can be

used. This will require adjusting C1 and C2

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS843801I-24 provides

separate power supplies to isolate any high switching noise from

coupling into the internal PLL.

In order to achieve the best possible filtering, it is recommended that

the placement of the filter components be on the device side of the

PCB as close to the power pins as possible. If space is limited, the

0.1µF capacitor in each power pin filter should be placed on the

device side of the PCB and the other components can be placed on

the opposite side.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices. The

filter performance is designed for wide range of noise frequency. This

low-pass filter starts to attenuate noise at approximately 10kHz. If a

specific frequency noise component with high amplitude interference

is known, such as switching power supplies frequencies, it is

recommended that component values be adjusted and if required,

additional filtering be added. Additionally general design practice for

power plane voltage stability suggests adding bulk capacitances in

the general area of all devices.

The schematic example focuses on functional connections and is not

configuration specific. Refer to the pin description and functional

tables in the datasheet to ensure the logic control inputs are properly

set.

Figure 4. ICS843801I-24 Schematic Example

XTAL_OU T

Zo = 50 Ohm

RU1

RU2

Not Inst all

RD2

XTAL_IN

VC CVCC

VCCA

XT A L _ O U T

XT A L _ I N

VEE

VCC

FREQ_SEL

LVP ECL

Term ination

To Lo gic

In pu t

pins

R10

133

VC C = 3. 3V

VCC

LVPE CL

Optional

Y-Termi nation

VDDA

Set Logic

Input to

'1'

10 u

3.3V

To Lo gic

Input

pins

Zo = 50 Ohm

C12

0.1uF

Logic Input Pin E xampl es

13 3

R15

22 p F

Set Logic

Input to

'0'

R18

m uR ata , BL M18 B B2 21SN 1

FB1

R13

82.5

22pF

3. 3V

C13

10uF

0.1u

VCC

18pF

FR EQ_SEL

RD1

Not Install

0.1u

VCC

R12

82.5

X1 25MHz

Zo = 50 Ohm

R16

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS843801I-24.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS843801I-24 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 72mA = 249.48mW

• Power (outputs)MAX = 30mW/Loaded Output pair

Total Power_MAX (3.465V, with all outputs switching) = 249.48mW + 30mW = 279.48mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 129.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.279W * 129.5°C/W = 121.2°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resitance θJA for 8 Lead TSSOP, Forced Convection

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 5.

Figure 5. LVPECL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of

VCC – 2V.

• For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V

(VCC_MAX – VOH_MAX) = 0.9V

• For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V

(VCC_MAX – VOL_MAX) = 1.7V

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =

[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW

Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =

[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW

VOUT

VCC

VCC - 2V

50Ω

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Reliability Information

Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP

Transistor Count

The transistor count for ICS843801I-24 is: 1649

Package Outline and Package Dimensions

Package Outline - G Suffix for 8 Lead TSSOP Table 8. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA vs. Air Flow

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 129.5°C/W 125.5°C/W 123.5°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

A1.20

A1 0.5 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D2.90 3.10

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

Ordering Information

Table 9. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

843801AGI-24LF AI24L “Lead-Free” 8 Lead TSSOP Tube -40°C to 85°C

843801AGI-24LFT AI24L “Lead-Free” 8 Lead TSSOP 2500 Tape & Reel -40°C to 85°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial and industrial applications. Any other applications, such as those requiring e high reliability or other extraordinary environmental requirements are not recommended without

additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support

devices or critical medical instruments.

ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER

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including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

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