ICS843801I-24 Data Sheet FEMTOCLOCK® CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ICS843801AGI-24 REVISION A AUGUST 10, 2011 13 ©2011 Integrated Device Technology, Inc.
Schematic Example
Figure 4 shows an example of ICS843801I-24 application schematic.
In this example, the device is operated at VCC = VCCA = 3.3V. The
18pF parallel resonant 25MHz crystal is used. The load capacitance
C1 = 22pF and C2 = 22pF are recommended for frequency accuracy.
Depending on the parasitic of the printed circuit board layout, these
values might require a slight adjustment to optimize the frequency
accuracy. Crystals with other load capacitance specifications can be
used. This will require adjusting C1 and C2
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843801I-24 provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
Figure 4. ICS843801I-24 Schematic Example
XTAL_OU T
Zo = 50 Ohm
RU1
1K
RU2
Not Inst all
RD2
1K
XTAL_IN
R1
10
VC CVCC
U1
1
2
3
4
8
7
6
5
VCCA
XT A L _ O U T
XT A L _ I N
VEE
VCC
Q
nQ
FREQ_SEL
+
-
LVP ECL
Term ination
nQ
To Lo gic
In pu t
pins
R10
133
VC C = 3. 3V
VCC
LVPE CL
Optional
Y-Termi nation
VDDA
Set Logic
Input to
'1'
C2
10 u
3.3V
To Lo gic
Input
pins
Zo = 50 Ohm
C12
0.1uF
+
-
Q
Logic Input Pin E xampl es
R9
13 3
R15
50
C1
22 p F
Set Logic
Input to
'0'
R18
50
m uR ata , BL M18 B B2 21SN 1
FB1
R13
82.5
C2
22pF
3. 3V
C13
10uF
C3
0.1u
VCC
18pF
FR EQ_SEL
RD1
Not Install
C1
0.1u
VCC
R12
82.5
X1 25MHz
Zo = 50 Ohm
Zo = 50 Ohm
R16
50