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FEATURES
DESCRIPTION
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
SN55LVDS31 ... J OR W
SN65LVDS31 . . . D OR PW
(Marked as LVDS31 or 65LVDS31)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1
2
3
4
8
7
6
5
VCC
1A
2A
GND
1Y
1Z
2Y
2Z
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
SN65LVDS9638DGK (Marked as AXG)
(TOP VIEW)
192013 2
17
18
16
15
14
1312119 10
5
4
6
7
8
4Y
4Z
NC
G
3Z
1Z
G
NC
2Z
2Y
1Y
1A
NC
V
4A
GND
NC
3A
3Y
2A
SN55LVDS31FK
(TOP VIEW)
CC
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
•Meet or Exceed the Requirements of ANSITIA/EIA-644 Standard•Low-Voltage Differential Signaling WithTypical Output Voltage of 350 mV and 100- ΩLoad
•Typical Output Voltage Rise and Fall Times of500 ps (400 Mbps)•Typical Propagation Delay Times of 1.7 ns•Operate From a Single 3.3-V Supply•Power Dissipation 25 mW Typical Per Driverat 200 MHz•Driver at High Impedance When Disabled orWith V
CC
= 0•Bus-Terminal ESD Protection Exceeds 8 kV•Low-Voltage TTL (LVTTL) Logic Input Levels•Pin Compatible With AM26LS31, MC3487, andμA9638
•Cold Sparing for Space and High ReliabilityApplications Requiring Redundancy
The SN55LVDS31, SN65LVDS31, SN65LVDS3487,and SN65LVDS9638 are differential line drivers thatimplement the electrical characteristics of low-voltagedifferential signaling (LVDS). This signalingtechnique lowers the output voltage levels of 5-Vdifferential standard levels (such as TIA/EIA-422B) toreduce the power, increase the switching speeds,and allow operation with a 3.3-V supply rail. Any ofthe four current-mode drivers will deliver a minimumdifferential output voltage magnitude of 247 mV intoa 100- Ωload when enabled.
The intended application of these devices andsignaling technique is both point-to-point andmultidrop (one driver and multiple receivers) datatransmission over controlled impedance media ofapproximately 100 Ω. The transmission media maybe printed-circuit board traces, backplanes, orcables. The ultimate rate and distance of datatransfer is dependent upon the attenuationcharacteristics of the media and the noise couplingto the environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1997–2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION (CONTINUED)
’LVDS31 logic diagram (positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
13
14
11
10
5
6
3
2
4A
3A
2A
1A
G
G
15
9
7
1
12
4
logic symbol†
SN55LVDS31, SN65LVDS31
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A
G
G
13
14
11
10
5
6
3
2
15
9
7
1
12
4≥ 1
EN
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
The SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are characterized for operation from –40 °C to 85 °C.The SN55LVDS31 is characterized for operation from –55 °C to 125 °C.
AVAILABLE OPTIONS
PACKAGE
(1)
T
A
SMALL OUTLINE
CHIP CARRIER CERAMIC DIP FLAT PACKMSOP
(FK) (J) (W)(D) (PW)
SN65LVDS31D SN65LVDS31PW — — — —
SN65LVDS3487D — — — — —–40 °C to 85 °C
SN65LVDS9638D — SN65LVDS9638DGN — — —
— — SN65LVDS9638DGK — — —
SNJ55LVDS31W–55 °C to 125 °C — — — SNJ55LVDS31FK SNJ55LVDS31J
SN55LVDS31W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
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SN65LVDS3487 logic diagram
(positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
13
14
11
10
5
6
3
2
4A
3A
2A
1A
15
9
1
4
7
12
3,4EN
1,2EN
logic symbol†
EN
EN
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
15
9
12
7
1
4
4A
3A
3,4EN
2A
1A
1,2EN
13
14
11
10
5
6
3
2
SN65LVDS3487
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
SN65LVDS9638 logic diagram
(positive logic)
2Z
2Y
1Z
1Y
5
6
7
8
2A
1A 2
3
logic symbol†
2Z
2Y
1Z
1Y
3
2
2A
1A
5
6
7
8
SN65LVDS9638
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
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FUNCTION TABLES
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
SN55LVDS31, SN65LVDS31
(1)
ENABLES OUTPUTSINPUT
A
G G Y Z
H H X H LL H X L HH X L H LL X L L HX L H Z ZOpen H X L HOpen X L L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance(off)
SN65LVDS3487
(1)
OUTPUTSINPUT A ENABLE EN
Y Z
H H H LL H L HX L Z ZOpen H L H
(1) H = high level, L = low level, X = irrelevant, Z = high impedance(off)
SN65LVDS9638
(1)
OUTPUTSINPUT A
Y Z
H H LL L HOpen L H
(1) H = high level, L = low level
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
7 V
300 kΩ
50 Ω
VCC
Input
VCC
5 Ω
7 V
Y or Z
Output
EQUIVALENT OF EACH A INPUT EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS TYPICAL OF ALL OUTPUTS
7 V
50 Ω
VCC
Input 10 kΩ
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATING TABLE
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
Supply voltage range
(2)
–0.5 V to 4 VV
I
Input voltage range –0.5 V to V
CC
+ 0.5 VContinuous total power dissipation See Dissipation Rating TableLead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °CT
stg
Storage temperature range –65 °C to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
T
A
≤25 °C DERATING FACTOR
(1)
T
A
= 70 °C T
A
= 85 °C T
A
= 125 °CPACKAGE
POWER RATING ABOVE T
A
= 25 °C POWER RATING POWER RATING POWER RATING
D (8) 725 mW 5.8 mW/ °C 464 mW 377 mW —D (16) 950 mW 7.6 mW/ °C 608 mW 494 mW —DGK 425 mW 3.4 mW/ °C 272 mW 221 mW —DGN
(2)
2.14 W 17.1 mW/ °C 1.37 W 1.11 W —FK 1375 mW 11.0 mW/ °C 880 mW 715 mW 275 mWJ 1375 mW 11.0 mW/ °C 880 mW 715 mW 275 mWPW (16) 774 mW 6.2 mW/ °C 496 mW 402 mW —W 1000 mW 8.0 mW/ °C 640 mW 520 mW 200 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.(2) The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD ThermallyEnhanced Package (SLMA002 ).
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RECOMMENDED OPERATING CONDITIONS
SN55LVDS31 ELECTRICAL CHARACTERISTICS
SN55LVDS31 SWITCHING CHARACTERISTICS
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
MIN NOM MAX UNIT
V
CC
Supply voltage 3 3.3 3.6 VV
IH
High-level input voltage 2 VV
IL
Low-level input voltage 0.8 VSN65 prefix –40 85T
A
Operating free-air temperature °CSN55 prefix –55 125
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OD
Differential output voltage magnitude R
L
= 100 Ω, See Figure 2 247 340 454 mV
ΔV
OD
Change in differential output voltage R
L
= 100 Ω, See Figure 2 –50 50 mVmagnitude between logic statesV
OC(SS)
Steady-state common-mode output voltage See Figure 3 1.125 1.2 1.375 VChange in steady-state common-mode outputΔV
OC(SS)
See Figure 3 –50 50 mVvoltage between logic statesV
OC(PP)
Peak-to-peak common-mode output voltage See Figure 3 50 150 mVV
I
= 0.8 V or 2 V, Enabled, No load 9 20I
CC
Supply current V
I
= 0.8 or 2 V, R
L
= 100 Ω, Enabled 25 35 mAV
I
= 0 or V
CC
, Disabled 0.25 1I
IH
High-level input current V
IH
= 2 4 20 μAI
IL
Low-level input current V
IL
= 0.8 V 0.1 10 μAV
O(Y)
or V
O(Z)
= 0 –4 –24I
OS
Short-circuit output current mAV
OD
= 0 ±12I
OZ
High-impedance output current V
O
= 0 or 2.4 V ±1μAI
O(OFF)
Power-off output current V
CC
= 0, V
O
= 2.4 V ±4μAC
i
Input capacitance 3 pF
(1) All typical values are at T
A
= 25 °C and with V
CC
= 3.3 V.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 0.5 1.4 4 nst
PHL
Propagation delay time, high-to-low-level output 1 1.7 4.5 nst
r
Differential output signal rise time (20% to 80%) 0.4 0.5 1 nsR
L
= 100 Ω, C
L
= 10 pF,See Figure 2t
f
Differential output signal fall time (80% to 20%) 0.4 0.5 1 nst
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) 0.3 0.6 nst
sk(o)
Channel-to-channel output skew
(2)
0.3 0.6 nst
PZH
Propagation delay time, high-impedance-to-high-level output 5.4 15 nst
PZL
Propagation delay time, high-impedance-to-low-level output 2.5 15 nsSee Figure 4t
PHZ
Propagation delay time, high-level-to-high-impedance output 8.1 17 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 7.3 15 ns
(1) All typical values are at T
A
= 25 °C and with V
CC
= 3.3 V.(2) t
sk(o)
is the maximum delay time difference between drivers on the same device.
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SN65LVDSxxxx ELECTRICAL CHARACTERISTICS
SN65LVDSxxxx SWITCHING CHARACTERISTICS
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
over recommended operating conditions (unless otherwise noted)
SN65LVDS31
SN65LVDS3487PARAMETER TEST CONDITIONS UNITSN65LVDS9638
MIN TYP
(1)
MAX
V
OD
Differential output voltage magnitude R
L
= 100 Ω, See Figure 2 247 340 454 mVChange in differential output voltageΔV
OD
R
L
= 100 Ω, See Figure 2 –50 50 mVmagnitude between logic states
1.37V
OC(SS)
Steady-state common-mode output voltage See Figure 3 1.125 1.2 V5
ΔV
OC(S
Change in steady-state common-mode output
See Figure 3 –50 50 mVS)
voltage between logic statesV
OC(PP)
Peak-to-peak common-mode output voltage See Figure 3 50 150 mVV
I
= 0.8 V or 2 V, Enabled, No load 9 20SN65LVDS31,
V
I
= 0.8 or 2 V, R
L
= 100 Ω, Enabled 25 35 mASN65LVDS3487I
CC
Supply current V
I
= 0 or V
CC
, Disabled 0.25 1No load 4.7 8SN65LVDS9638 V
I
= 0.8 V or 2 V mAR
L
= 100 Ω9 13I
IH
High-level input current V
IH
= 2 4 20 μAI
IL
Low-level input current V
IL
= 0.8 V 0.1 10 μAV
O(Y)
or V
O(Z)
= 0 –4 –24I
OS
Short-circuit output current mAV
OD
= 0 ±12I
OZ
High-impedance output current V
O
= 0 or 2.4 V ±1μAI
O(OFF)
Power-off output current V
CC
= 0, V
O
= 2.4 V ±1μAC
i
Input capacitance 3 pF
(1) All typical values are at T
A
= 25 °C and with V
CC
= 3.3 V.
over recommended operating conditions (unless otherwise noted)
SN65LVDS31
SN65LVDS3487PARAMETER TEST CONDITIONS UNITSN65LVDS9638
MIN TYP
(1)
MAX
t
PLH
Propagation delay time, low-to-high-level output 0.5 1.4 2 nst
PHL
Propagation delay time, high-to-low-level output 1 1.7 2.5 nst
r
Differential output signal rise time (20% to 80%) 0.4 0.5 0.6 nsR
L
= 100 Ω, C
L
= 10 pF,See Figure 2t
f
Differential output signal fall time (80% to 20%) 0.4 0.5 0.6 nst
sk(p)
Pulse skew (|t
PHL
– t
PLH
|) 0.3 0.6 nst
sk(o)
Channel-to-channel output skew
(2)
0 0.3 nst
sk(pp)
Part-to-part skew
(3)
800 pst
PZH
Propagation delay time, high-impedance-to-high-level output 5.4 15 nst
PZL
Propagation delay time, high-impedance-to-low-level output 2.5 15 nsSee Figure 4t
PHZ
Propagation delay time, high-level-to-high-impedance output 8.1 15 nst
PLZ
Propagation delay time, low-level-to-high-impedance output 7.3 15 ns
(1) All typical values are at T
A
= 25 °C and with V
CC
= 3.3 V.(2) t
sk(o)
is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads.(3) t
sk(pp)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devicesoperate with the same supply voltages, same temperature, and have identical packages and test circuits.
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PARAMETER MEASUREMENT INFORMATION
Y
ZVOD
Input
(see Note A)
CL = 10 pF
(2 Places)
(see Note B)
100 Ω
± 1%
2 V
1.4 V
0.8 V
tPLH tPHL
100%
80%
20%
0%
Input
VOD
0
tftr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t r or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Y
Z
Input
(see Note A)
CL = 10 pF
(2 Places)
(see Note B)
49.9 Ω ± 1% (2 Places)
VOC
AA
VOC
VOC(PP)
(see Note C) VOC(SS)
0
3 V
NOTES: A. All input pulses are supplied by a generator having the following characteristics: t r or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
Figure 1. Voltage and Current Definitions
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
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Y
Z
Inputs
(see Note A)
CL = 10 pF
(2 Places)
(see Note B)
49.9 Ω ± 1% (2 Places)
G
G
1.2 V
tPZH tPHZ
tPZL tPLZ
2 V
1.4 V
0.8 V
100%, ≅1.4 V
1.4 V
2 V
0.8 V
50%
0%, 1.2 V
0%, ≅1 V
100%, 1.2 V
50%
G, 1,2EN,
OR 3,4EN
G
VOY
or
VOZ
VOZ
or
VOY
A at 2 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
A at 0.8 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
VOY VOZ
0.8 V or 2 V
1,2EN or 3,4EN
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Enable-/Disable-Time Circuit and Definitions
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TYPICAL CHARACTERISTICS
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously
29
27
19
1550 100
− Supply Current − mA
31
33
f − Frequency − MHz
35
150 200
21
VCC = 3.6 V
ICC
VCC = 3.3 V
25
23
17
VCC = 3 V
1.5
1.4
1.2
1
1.7
1.9
−40 −20 0 20 40
TA − Free-Air Temperature − °C
VCC = 3 V
VCC = 3.6 V
1.8
1.6
1.3
1.1
60 80 100
VCC = 3.3 V
− Low-to-High Propagation Delay T ime − ns
tPLH
1.5
1.4
1.2
1
1.7
1.9
−40 −20 0 20 40
TA − Free-Air Temperature − °C
VCC = 3 V
1.8
1.6
1.3
1.1
60 80 100
VCC = 3.3 V
VCC = 3.6 V
tPHL − High-to-Low Propagation Delay T ime − ns
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
SN55LVDS31, SN65LVDS31
SUPPLY CURRENT LOW-TO-HIGH PROPAGATION DELAY TIMEvs vsFREQUENCY FREE-AIR TEMPERATURE
Figure 5. Figure 6.
HIGH-TO-LOW PROPAGATION DELAY TIMEvsFREE-AIR TEMPERATURE
Figure 7.
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APPLICATION INFORMATION
10
1
0.1
Transmission Distance − m
100
Signaling Rate − Mbps
TRANSMISSION DISTANCE
vs
SIGNALING RATE
10 100 1000
5% Jitter
(see Note A)
30% Jitter
(see Note A)
24 AWG UTP 96 Ω
(PVC Dielectric)
1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ZO = 100 Ω
ZO = 100 Ω
ZO = 100 Ω
ZO = 100 Ω
3.3 V
0.1 µF
(see Note A) 0.001 µF
(see Note A)
VCC
See Note B
NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to VCC or GND, as appropriate.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
The devices are generally used as building blocks for high-speed point-to-point data transmission where grounddifferences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receiversapproach ECL speeds without the power and dual supply requirements.
A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
Figure 9. Typical Application Circuit Schematic
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1/4 ’LVDS31
’LVDS32
500 Ω
500 Ω
20 kΩ
20 kΩ
3.3 V
500 Ω
500 Ω
20 kΩ
20 kΩ
3.3 V
7 kΩ7 kΩ10 kΩ
3.3 kΩ
Twisted-Pair B Only
Strb/Data_TX
Strb/Data_Enable
Data/Strobe
1 Arb_RX
2 Arb_RX
Port_Status
Tp Bias on
Twisted-Pair A
55 Ω
55 Ω
5 kΩ
VG on
Twisted-Pair B
TP
TP
3.3 V
NOTES: A. Resistors are leadless, thick film (0603), 5% tolerance.
B. Decoupling capacitance is not shown, but recommended.
C. VCC is 3 V to 3.6 V.
D. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
Figure 10. 100-Mbps IEEE 1394 Transceiver
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1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ZO = 100 Ω
ZO = 100 Ω
ZO = 100 Ω
ZO = 100 Ω
≈3.6 V
0.1 µF
(see Note A)
VCC
See Note B
1N645
(2 places)
0.01 µF
5 V
COLD SPARING
RELATED INFORMATION
SN55LVDS31, SN65LVDS31SN65LVDS3487, SN65LVDS9638
SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
A. Place a 0.1- μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between V
CC
and the groundplane. The capacitor should be located as close as possible to the device terminals.B. Unused enable inputs should be tied to V
CC
or GND, as appropriate.
Figure 11. Operation With 5-V Supply
Systems using cold sparing have a redundant device electrically connected without power supplied. To supportthis configuration, the spare must present a high-input impedance to the system so that it does not drawappreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.When the device is powered off, V
CC
must be clamped to ground and the I/O voltages applied must be within thespecified recommended operating conditions.
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com formore information.
For more application guidelines, see the following documents:•Low-Voltage Differential Signaling Design Notes (SLLA014 )•Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038 )•Reducing EMI With LVDS (SLLA030 )•Slew Rate Control of LVDS Circuits (SLLA034 )•Using an LVDS Receiver With RS-422 Data (SLLA031 )•Evaluating the LVDS EVM (SLLA033 )
13Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9762101Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9762101QEA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-9762101QFA ACTIVE CFP W 16 1 TBD Call TI Call TI
5962-9762101VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
SN55LVDS31W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
SN65LVDS31D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31NSR ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31NSRG4 ACTIVE SO NS 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS31QPWQ1 OBSOLETE TSSOP PW 16 TBD Call TI Call TI
SN65LVDS31QPWRQ1 OBSOLETE TSSOP PW 16 TBD Call TI Call TI
SN65LVDS3487D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3487DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS3487DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN65LVDS3487DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGK ACTIVE MSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LVDS9638DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ55LVDS31FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ55LVDS31J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
SNJ55LVDS31W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type
SNLVDS9638DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55LVDS31, SN55LVDS31-SP :
•Catalog: SN75LVDS31, SN55LVDS31
•Space: SN55LVDS31-SP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LVDS31DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS31NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN65LVDS31PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN65LVDS3487DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN65LVDS9638DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65LVDS9638DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
SN65LVDS9638DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65LVDS9638DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Dec-2010
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LVDS31DR SOIC D 16 2500 333.2 345.9 28.6
SN65LVDS31NSR SO NS 16 2000 346.0 346.0 33.0
SN65LVDS31PWR TSSOP PW 16 2000 346.0 346.0 29.0
SN65LVDS3487DR SOIC D 16 2500 346.0 346.0 33.0
SN65LVDS9638DGKR MSOP DGK 8 2500 358.0 335.0 35.0
SN65LVDS9638DGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
SN65LVDS9638DR SOIC D 8 2500 340.5 338.1 20.6
SN65LVDS9638DR SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 13-Dec-2010
Pack Materials-Page 2
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