Acts! Preliminary vi.1 54SX Family FPGAs Features High Performance * 320 MHz Internal Performance * 4.0 ns Clock-to-Out (Pin-to-Pin) * 0.5 ns Input Set-Up * 0.25 ns Clock Skew High Density * 8,000 to 32,000 Available Logic Gates * 246 User-Programmable I/O * 1,980 Flip-Flops Easy Logic Integration * ASIC Design Methodology Support Using Synthesis Tools for Performance-Intensive Designs * 100% Resource Utilization with 100%Pin Locking SX Product Profile 3.3V Operation with 5.0V Input Tolerance Low Power Consumption Deterministic, User-Controllable Timing Unique, In-System Diagnostic and Debug Facility with Silicon Explorer JTAG Boundary Scan Testing in Compliance with IEEE Standard 1149.1 Actel Designer Series Design Tools, Supported by Cadence, Exemplar, IST, Mentor Graphics, Model Tech, Synopsys, Synplicity, and Viewlogic Design Entry and Simulation Tools Permanently Programmed for Instantaneous Operation on Power-Up Secure Programming Technology Prevents Reverse Engineering and Design Theft A54SX08 A54SX16 A54SX16P A54SX32 Gate Capacity 8,000 16,000 16,000 32,000 Logic Modules 768 1,452 1,452 2,880 Register Cells 256 528 528 1,080 Combinatorial Cells 512 924 924 1,800 Maximum Flip-Flops 512 990 990 1,980 User I/Os (Maximum) 129 177 177 246 Clocks 3 3 3 3 JTAG Yes Yes Yes Yes PCI _ _ Yes _ Clock-to-Out 4.0 ns 4.3 ns 4.4 ns* 4.9 ns Input Set-Up (External) 0.8 ns 0.5 ns 0.5 ns 0.1 ns Speed Grades Std, -1, -2 Std, -1, -2 Std, -1, -2 Std, -1, -2 Temperature Grades C, | C,1,M, B C, | C,1,M,B Packages (by pin count) PQFP 208 208 208 208 PLCC 84 84 84 VQFP 100 100 100 TQFP 144, 176 176 144,176 144,176 CQFP _ 208, 256 _ 208, 256 PBGA 329 329 313, 329 * Clock-to-Out for PCI. September 1998 1998 Actel Corporation(el Preliminary General Description The New SX Family of FPGAs Actels SX Family of FPGAs features a revolutionary new sea-of-modules architecture that delivers next-generation device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further speed time-to-market for performance-intensive applications. Fast and Flexible New Architecture Actels SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell) , each optimized for fast and efficient mapping of synthesized logic functions. Optimal use of the silicon is made by locating the routing and interconnect resources in the metal layers above the logic modules, enabling the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, | synthesis-friendly logic modules (or sea-of-modules) which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local Ordering Information routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (typically 90% of connections use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100% pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with a minimum of effort. Further complementing the SXs flexible routing structure, a hard-wired, constantly-loaded clock network has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clock-to-out or fast input set-up times. SX devices have easy-to-use I/O cells which do not require HDL instantiation, facilitating design re-use and reducing design and debugging time. A54SX16 P - 2 PQ 208 E Application (Temperature Range) Blank = Commercial (0 to +70C) | = Industrial (40 to +85C) M = Military (-55 to +125C) B = MIL-STD-883 PP = Pre-production Package Lead Count Package Type BG = Ball Grid Array CQ = Ceramic Quad Flat Pack PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack " Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard - Blank = Not PCI Compliant P= PCI Compliant L___ Part Number A54SX08 = 8,000 Gates Ab4SX16 = 16,000 Gates Ab4SX16P = 16,000 Gates Ad4SX32 = 32,000 GatesPreliminary54SX Family FPGAs Product Plan Speed Grade Application Std -1* -2* Cc I M B A54SX08 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) P P P P P _ _ 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) vf vf vf P P 144-Pin Thin Quad Flat Pack (TQFP) P P P P P _ _ 176-Pin Thin Quad Flat Pack (TQFP) P P P P P _ _ 208-Pin Plastic Quad Flat Pack (PQFP) v7 7 7 P P 329-Pin Plastic Ball Grid Array (PBGA) P P P P P _ A54SX16 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) P P P P P _ _ 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) vf vf vf P P 176-Pin Thin Quad Flat Pack (TQFP) 7 7 7 P P 208-Pin Plastic Quad Flat Pack (PQFP) v7 7 7 P P 208-Pin Ceramic Quad Flat Pack (CQFP) P P _ P _ P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P _ P _ P P 329-Pin Plastic Ball Grid Array (PBGA) P P P P P _ A54SX16P Device 100-Pin Very Thin Plastic Quad Flat Pack (VQFP) 7 7 7 P P _ _ 144-Pin Thin Quad Flat Pack (TQFP) P P P P P _ _ 176-Pin Thin Quad Flat Pack (TQFP) 7 7 P P P _ 208-Pin Plastic Quad Flat Pack (PQFP) v7 7 7 P P A54SX32 Device 84-Pin Plastic Leaded Chip Carrier (PLCC) P P P P P _ _ 144-Pin Thin Quad Flat Pack (TQFP) P P P P P _ _ 176-Pin Thin Quad Flat Pack (TQFP) P P P P P _ _ 208-Pin Plastic Quad Flat Pack (PQFP) v7 7 7 P P 208-Pin Ceramic Quad Flat Pack (CQFP) P P _ P _ P P 256-Pin Ceramic Quad Flat Pack (CQFP) P P _ P _ P P 313-Pin Plastic Ball Grid Array (PBGA) 7 7 7 P P 329-Pin Plastic Ball Grid Array (PBGA) P P P P P _ Consult your local Actel sales representative for product availability. Applications; C = Commercial Availability: & = Available * Speed Grade: -1 = Approx. 15%Faster than Standard | = Industrial P = Planned -2 = Approx. 25%Faster than Standard M = Military = Not Planned B = MIL-STD-883(el Preliminary Plastic Device Resources User I/Os PLCC VQFP PQFP TQFP TQFP PBGA PBGA Device 84-Pin 100-Pin 208-Pin 144-Pin 176-Pin 313-Pin 329-Pin A54SX08 66 78 129 112 129 129 A54SX16 66 78 172 144 177 A54SX16P 78 172 112 144 A54SX32 66 171 112 144 246 246 Package Definitions (Consult your local Actel sales representative for product availability.) PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array Ceramic Device Resources User I/Os CQFP CQFP Device 208-Pin 256-Pin A54SX16 172 177 A54SX32 171 225 Package Definitions (Consult your local Actel sales reor esentative for product availability.) COQFP = Ceramic Quad Flat PackPreliminary54SX Family FPGAs Pin Description CLKA Clock A (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. CLKB Clock B (Input) TTL clock input for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. TCK Test Clock (Input) Test clock input for diagnostic probe and device programming. In flexible mode (refer to the JTAG pins functionality table), TCK becomes active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. 1/0 Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bi-directional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tri-stated by the Designer Series software. TMS Test Mode Select (Input) The TMS pin controls the use of JTAG pins (TCK, TDI, TDO). In flexible mode (refer to the JTAG pins functionality table), when the TMS pin is set LOW, the TCK, TDI, and TDO pins are JTAG pins. Once the JTAG pins are in JTAG mode they will remain in JTAG mode until the internal JTAG state machine reaches the logic reset state. At this point the JTAG pins will be released and will function as regular I/O pins. The logic reset state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated JTAG mode, TMS functions as specified in the IEEE 499.1 JTAG Specifications. JTAG operation is further described on page 11. NC No Connection This pin is not connected to circuitry within the device. PRA ActionProbe A (Output) The ActionProbe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the ActionProbe B pin to allow real-time diagnostic output of any signal path within the device. The ActionProbe A pin can be used as a user-defined I/O when debugging has been completed. PRB ActionProbe B (Output) The ActionProbe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the ActionProbe A pin to allow real-time diagnostic output of any signal path within the device. The ActionProbe B pin can be used as a user-defined I/O when debugging has been completed. TDI Test Data Input (Input) Serial input for JTAG and diagnostic probe. In flexible mode, (refer to the JTAG pins functionality table), TDI is active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. TDO Test Data Output (output) Serial output for JTAG. In flexible mode (Refer to the JTAG pins functionality table), TDO is active when the TMS pin is set LOW. This pin functions as an I/O when the JTAG state machine reaches the logic reset state. Vecl Supply Voltage Supply voltage for 1/Os. Veca Supply Voltage Supply voltage for Array. Vecr Supply Voltage Supply voltage for input tolerance (required for internal biasing). Table 1 + Supply Voltages A54SX08 A54SX16 A54SX32 A54SX16P Veca 3.3V | 33V ] 3.3V | 3.3V | 3.3V Vecl 3.3V | 33V ] 3.3V | 3.3V | 5.0V Vecr 5.0V | 5.0V | 3.3V | 5.0V | 5.0V Input Tolerance | 3.3V | 5.0V | 3.3V |] 5.0V | 5.0V Output Drive 3.3V | 33V |] 33V / 3.3V |] 5.0V(el Preliminary SX Family Architecture The SX Family architecture was designed to satisfy next-generation performance and integration requirements for production-volume designs in a broad range of applications. Programmable Interconnect Element Actels new SX Family provides much more efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (see Figure 1). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs) , and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Interconnection between these logic modules is achieved using Actels patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX Family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible as it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Additionally, the interconnect (i.e. the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Routing Tracks J} fo Metal 3 q Amprphous Silicon/ <<____ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Tungsten Plug Contact _> Metal 1 Figure? + SX Family Interconnect ElementsPreliminary54SX Family FPGAs Logic Module Design The SX Family architecture has been called a sea-of-modules architecture because the entire floor of the device is covered with agrid of logic modules with virtually no chip area lost to interconnect elements or routing (see Figure 2). Actel provides two types of logic modules, the R-cell and the C-cell. Channelled Array Architecture Sea-of-Modules Architecture Figure 2 + Channeled Array and Sea-of-Modules Architectures The Rell (or register cell) contains a flip-flop featuring more control signals than in previous Actel architectures, including asynchronous clear, asynchronous preset, and clock enable (using the SO and S1 lines). The R-cell (Figure 3) registers feature programmable clock polarity, selectable on a register-by-register basis. This provides the designer with additional flexibility while allowing mapping of synthesized functions into the SX FGPA. The clock source for the R-cell can be chosen from the hard-wired clock or the routed clock. The C-cell (or combinatorial cell, Figure 4) implements a range of combinatorial functions up to 5-inputs. Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions which can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility enabled by the inversion capability isthe ability tointegrate a 3input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis-friendly, simplifying the overall design and reducing synthesis time. Chip Architecture The SX Familys chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications.(el Preliminary Routed Data Input S1 PSETB Direct Connect D Q Y Input HCOLK | CLKA, CLRB CLKB, Internal Logic CKS CKP Figure3 + R-Cell DO D1 l Y D2 D3 l Sa Sb DB > AO! |IBO All |Bt1 Figure4 + C-Cell Module Organization Actel has arranged all C-cell and R-cell logic modules into horizontal banks called Clusters. There are two types of Clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. To increase design efficiency and device performance, Actel has further organized these modules into Super Clusters (see Figure 5). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX devices feature significantly more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flip-flops. Routing Resources Clusters and SuperClusters can be connected through the use of two innovative new local routing resources called FastConnect and DirectConnect which enable extremely fast and predictable interconnection of modules within Clusters and SuperClusters (see Figure 6 and Figure 7). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance.Preliminary54SX Family FPGAs R-Cell C-Cell Cluster 1 Cluster 2 Cluster 2 Cluster 1 Type 1 SuperCluster Type 2 SuperCluster Figure5 + Cluster Organization A Direct Connect *No antifuses * 0.1 ns routing delay > Fast Connect * One antifuse * 0.4 ns routing delay > Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 1 SuperClusters Figure6 + DirectConnect and FastConnect for Type 1 Super Clusters(el Preliminary > Direct Connect * No antifuses * 0.1 ns routing delay > Fast Connect * One antifuse * 0.4 ns routing delay p> Routing Segments * Typically 2 antifuses * Max. 5 antifuses Type 2 SuperClusters Figure 7 + DirectConnect and FastConnect for Type 2 SuperClusters DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring R-cell in a given SuperCluster. DirectConnect uses a hard-wired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster, and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.4 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally-oriented routing resources known as segmented routing and high-drive routing. Actels segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100% automatic place and route software to minimize signal propagation delays. Actels high-drive routing structure provides three clock networks. The first clock, called HCLK, is hard-wired from the HCLK buffer to the clock select MUX in each R-cell. This provides a fast propagation path for the clock signal, enabling the 4.0 ns clock-to-out (pin-to-pin) performance of the SX devices. The hard-wired clock is tuned to provide clock skew as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal signal logic within the SX device. Other Architecture Features Technology Actels SX Family of FPGAs is implemented in high-voltage twin-well CMOS using three layers of metal and 0.35 micron design rules (moving quickly to 0.25 micron). The M2/M3 antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals, and has a programmed (on state) resistance of 25 ohms with capacitance of 1.6 fF for low signal impedance. Performance The combination of architectural features described above enables SX devices to operate with internal clock frequencies exceeding 300 MHz, enabling very fast execution of even complex logic functions. Thus, the Actel SX Family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs which previously would have required a gate array to meet performance goals can now be integrated into an SX device with dramatic improvements in cost and time-to-market. Using timing-driven place and route tools, designers can achieve highly deterministic device performance. 10Preliminary54SX Family FPGAs With SX devices, designers can achieve a higher level of performance without recourse to complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macrosin HDL code. 1/O Modules Each I/O on an SX device can be configured as an input, an output, a tri-state output, or a bi-directional pin. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 4.0 ns, and external set-up time as low as 0.6 ns. I/O cells including embedded latches and flip-flops require instantiation in HDL code, a complication not required by SX FPGAs. Fast pin-to-pin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reducing overall design time. Power Requirements The SX Family supports 3.3-volt operation and is designed to tolerate 5-volt inputs. Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced due to the small number of antifusesin the path, and because of the low resistance properties of the antifuses. The antifuse architecture does not require active circuitry to hold a charge (as an SRAM or EPROM does), thereby makingit the lowest-power architecture on the market. JTAG All SX devices feature hard-wired IEEE 1149.1 JTAG Boundary Scan Test circuitry. Figure 8 is a block diagram of the 54SX JTAG Circuity. SX devices offer superior diagnostic and testing capabilities by providing JTAG and probing capabilities. These functions are controlled through the special JTAG pins in conjunction with the program fuse. The functionality of each pin is described in Table 2. Table2 + JTAG Program Fuse Blown (Dedicated JTAG Mode) Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible JTAG pins and may be used as I/Os No need for pull-up resistor Use a pull-up resistor of 10K for TMS ohm on TMS In the dedicated JTAG mode, TCK, TDI and TDO are dedicated JTAG pins and cannot be used as regular |/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10K ohm. TMS can be pulled LOW to initiate the JTAG sequence. The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. -------Aa Data Registers (DRs) r--- | I I output stage |_f TDO =) Instruction Register (IR) clocks and/or controls Tr TMS wi TcK E#>} TAP Controller Powerup Reset Figure8 + 54SX JTAG Test Logic 11(el Preliminary Design Tool Support As with all Actel FPGAs, the new SX Family is fully supported by Actels Designer Series development tools, which include: * DirectTime for automated, timing-driven place and route; * ACTgen for fast development using a wide range of macro functions; and * ACTmap for logic synthesis. Designer Series supports industry-leading VHDL and Verilog-based design tools, including synthesis tools from industry leaders such as Exemplar Logic, Synplicity, and Synopsys. In addition, the SX Family is supported by Actels new Silicon Explorer diagnostic and debugging tool kit. Silicon Explorer dramatically reduces verification time from several hours per 3.3V/5V Operating Conditions Absolute Maximum Ratings Symbol Parameter Limits Units Vocr DC Supply Voltage? -0.3 to +6.0 Vv Voc? DC Supply Voltage -0.3 to +4.0 Vv DC Supply Voltage Voc (A54SX08, A54SX16, -0.3 to +4.0 Vv A548X32) 2 DC Supply Voltage _ Vecl (A54SX1 6P) 0.3 to +6.0 Vv Vi Input Voltage 0.5 to +5.5 Vv Vo Output Voltage 0.5 to +3.6 Vv 1/0 Source Sink lio 3 30 to +5.0 mA Current Tsta Storage Temperature 40 to +125 C Notes: 1. Stresses beyond thoselisted under AbsoluteMaximum Ratings may cause permanent damage to the device Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Vecr in the 54SX16P must be greater than or equal to Vor during power-up and power-down sequences and during normal operation. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than Veo + 0.5V or less than GND 0.5V, theinternal protection diodes will forward-bias and can draw excessive current. cycle to a few seconds by enabling real-time, in-circuit debugging. Silicon Explorer includes: * Probe Pilot, a high-speed signal acquisition and control tool that samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Probe Pilot features 18 probing channels and connects to the users PC via a standard serial port connection. * Diagnostic software, which turns the PC into a fully-featured, 100 MHz logic analyzer for easy graphical analysis of waveforms. Silicon Explorer probes 100 percent of the device circuitry using Probe Pilots powerful, 18-channel signal acquisition capability. Individual bugs are then isolated and passed to the user interface, providing the user with complete waveform data. Recommended Operating Conditions Parameter Commercial Industrial Military Units Temperature 0 to -40to --55to C Range! +70 +85 +125 3.3V Power + + + % Supply Tolerance +10 +10 +10 Voc 5V Power Supply Tolerance +5 +10 +10 Voc Note: I. Ambient temperature (T,4) is used for commercial and industrial; case temperature (Tc) is used for military. 12Preliminary54SX Family FPGAs Electrical Specifications Commercial Industrial Symbol Parameter Min. Max. Min. Max. Units (lo = -20uA) (CMOS) (Veci- 9-1) Veer (Veci- 9.1) Vec! Vou (loy = -8mA) (TTL) 2.4 Vecl V (loy = -6mA) (TTL) 2.4 Vecl (Io_= 20uA) (CMOS) 0.10 VoL (Io, = 12mA) (TTL) 0.50 V (lo, = 8mA) (TTL) 0.50 Vit 0.8 0.8 V Vin 2.0 2.0 V tp, te Input Transition Time tp, tp 50 50 ns Cio Cig VO Capacitance 10 10 pF loc Standby Current, loc 4.0 4.0 mA lec(D) loc(D) !bynamic Vec Supply Current See Power Dissipation for 54SX Family on page 15. Note: See/EEE PCI specification for A54SX16P 3.3V and 5.0V PCI operation. Power-Up Sequencing Veca Vocr Vec Power-Up Sequence Comments A54SX08, A54SX16, A54SX32 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 3.3V 33V Enel . irs . . 5.0V Second No possible damage to device. A54SX16P 3.3V 3.3V 3.3V 3.3V Only No possible damage to device. 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 3.3V 33VE . irst . . 5.0V Second Possible damage to device. 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 5.0V 33VE . irst . . 5.0V Second No possible damage to device. 13(el Preliminary Power-Down Sequencing Voca Vocr Vecl Power-Down Sequence Comments A54SX08, A54SX16, A54SX32 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 3.3V 33VE . irst . . 5.0V Second No possible damage to device. A54SX16P 3.3V 3.3V 3.3V 3.3V Only No possible damage to device. 5.0V First . . 3.3V Second Possible damage to device. 3.3V 5.0V 3.3V av Enel . irs . . 5.0V Second No possible damage to device. 5.0V First . . 3.3V Second No possible damage to device. 3.3V 5.0V 5.0V av Enel . irs . . 5.0V Second No possible damage to device. 14Preliminary54SX Family FPGAs Package Thermal Characteristics The device junction to case thermal characteristic is 8,,, and the junction to ambient air characteristic is 8. The thermal characteristics for 0; are shown with two different air flow rates. Max. junction temp. (C) Max. ambient temp. (C) _ 150C 70C Absolute maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follows: Absolute Maximum Power Allowed = on CCIW) 28C]W = 2.86W Sia Gia Package Type Pin Count Vic Still Air 300 ft/min Units Plastic Leaded Chip Carrier (PLCC) 84 12 32 22 CAN Thin Quad Flatpack (TQFP) 144 10 32 24 C/W Thin Quad Flatpack (TQFP) 176 11 28 21 C/W Very Thin Quad Flatpack (VQFP) 100 11 38 32 CAN Plastic Quad Flatpack (PQFP) with Heat Spreader 208 18 14 C/W Plastic Ball Grid Array (PBGA) 329 18 13 C/W Plastic Ball Grid Array (PBGA) 313 8 25 21 C/W Juntion Temperature (Tj) Junction Temperature = AT + T, Where: T, = Ambient Temperature AT = j,* Power = Temperature gradient between juntion (silicon) and ambient Power = Power calculated from Power Dissipaction section Oj, = Juntion to ambient of package. Power Dissipation for 545X Family P= [locstandby + lecactive] * Voca + lo. * Vo. * N+ lou (Voca - Vou) * M Where: lecstandby is the current flowing when no inputs or outputs are changing. Iocactive is the current flowing due to CMOS switching. lo, loy are TTL sink/source currents. Vor, Voy are TTL level output voltages. N equals the number of outputs driving TTL loads to Vo, . M equals the number of outputs driving TTL loads to Voy. An accurate determination of N and M is problematical because their values depend on the design and on the system 1/0. The power can be divided into two components: static and active. Static Power Component The power due to standby current is typically a small component of the overall power. Standby power is shown below for commercial, worst case conditions (70C). Power 14.4mW loc Voc 4mA 3.6V Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency-dependent, a function of the logic and the external 1/0. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totempole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. 15(el Preliminary Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power (uW) = Ceq* Voca?* F (1) Where: Ceqis the equivalent capacitance expressed in pF. Veca is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring I cactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of Voca. Equivalent capacitance is frequency-independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. Ceg Values A54SX08 A54SX16 A54SX16P A54SX32 Cou (PF) 3.9 3.9 3.9 3.9 Ceqy (DF) 1.0 1.0 1.0 1.0 Crago (pF) 5.0 5.0 5.0 5.0 Ceacr (PF) 0.08 0.2 0.2 0.3 Crap (PF) 0.06 0.15 0.15 0.23 r, (pF) 32 60 60 107 > (pF) 32 60 60 107 Sy 206 928 928 1,080 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power =Vocq?* [(m * Ceqy * frm) modules + (n* Ceqi * fr) inputst (P * (Ceo + CL) * fp) outputst 0.5* (44 * Cegor * fyt)routed_cikt + (14 * ft) routed_cikt + 0.5* (do Cegor * fg2) routed_cik2t (2 * foe) routed_cik2 + 0.5* (81 * Geen * fs) dedicated_CLKI (2) Where: m = Number of logic modules switching at f,, n = Number of input buffers switching at f, p = Number of output buffers switching at f, qs = Number of clock loads on the first routed array clock Qo = Number of clock loads on the second routed array clock ry = Fixed capacitance due to first routed array clock fo = Fixed capacitance due to second routed array clock Sy = Fixed number of clock loads on the dedicated array clock= (528 for A54SX16) Ceqy = Equivalent capacitance of logic modules in pF Ceq = Equivalent capacitance of input buffers in pF Ceqgg = = _- Equivalent capacitance of output buffers in pF Cegcr = Equivalent capacitance of routed array clock in pF Cegep = Equivalent capacitance of dedicated array clock in pF CL = Output lead capacitance in pF fin = Average logic module switching rate in MHz f, = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fot = Average first routed array clock rate in MHz foe = Average second routed array clock ratein MHz Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) 80% of modules Inputs Switching (n) = #inputs/4 Outputs Switching (p) = #output/4 First Routed Array Clock Loads(q,) = 40%of sequential modules Second Routed ArrayClock Loads = 40%of sequential (Qo) modules Load Capacitance (C,) = 85pF Average Logic Module Switching = F/10 Rate (f,,) Average Input Switching Rate(f,) = F/5 Average Output Switching Rate (f,) = F/10 Average First Routed ArrayClock = F/2 Rate (f,1) Average Second Routed ArrayClock = F/2 Rate (fyo) Average Dedicated Array Clock Rate = =F (fs) 16Preliminary54SX Family FPGAs Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, Ty = 70C, Veca = 3.0V) Junction Temperature (T,) Veca 40 0 25 70 85 125 3.0 0.78 0.87 0.89 1.00 1.04 1.16 3.3 0.73 0.82 0.83 0.93 0.97 1.08 3.6 0.69 0.77 0.78 0.87 0.92 1.02 5435xX Timing Model Input Delays Internal Delays Predicted Output Delays Routing Delays r/O Module |] Combinatorial [ 70 Moduie | ih =1.7N8 | taps = 0.7 ns | | \ tpHL = 2-1 ns ! DHL = <: 1 1 : | a L__ tpp =0.7 ns vot = 3 ne nn RD4 = !- traps = 2.2 ns - 1/0 Module 4 toHL =2.1ns Register Register | ell Cell | | D D | wt | | Q | trot = 0.4 ns| Q | trot = 0.4 ns tx] | teENZH = 2.7 ns | tsup =0.6 ns | | | tup = 0.0 ns | | taco 2 658 incon 05 ns L___ _ tackH =2.2ns (1 00% Load) FMax = 250 MHz Hard-Wired Clock tucKH =1.3ns FumMax = 320 MHz *Values shown for AS4SX16-2, worst-case commercial conditions. Hard-Wired Clock External Set-Up = tiny + tirps + tsup - tueKH = 17+ 04+ 06-13= 1.4ns Clock-to-Out (Pin-to-Pin) = tuckH+ trcot trpi + tpHL = 13+0.5+04+21=43ns Routed Clock External Set-Up = tinyt tino + tsup trekH = 17+ 04+ 06-22=0.5ns Clock-to-Out (Pin-to-Pin) = trex + trco+ tapi + tox = 22+ 0.5+0.4+21=52ns 17(el Preliminary Output Buffer Delays tENHZ AC Test Loads Load 1 (Used to measure propagation delay) To the output under Ny == 35 pF Load 2 (Used to measure enable delays) Voc GND e e R to Vec for tpzi To the output R to GND for tpzy Load 3 (Used to measure disable delays) Voc GND e R to Vec for tpLz R to GND for tpyz R=1kQ To the output under test input Buffer Delays PAD 3V under test R=1kQ rl rT C-Cell Delays Y Voc S,AorBy50% 50%N__GND_ Voc Out 50% 50% GND tpp Out 50% tiny tep 18Preliminary54SX Family FPGAs Register Cell Timing Characteristics Flip-Flops D __| PRESETF- @ CLK+ CLR (Positive edge triggered) | tuo k= D_ OX e tsup tupwH -->| |}< typ +| CLK 1 tRewH | 1 rT 4 . l typwi, >| taco | tRewL Q Z X / torr tereser | CLR | twasyn PRESET | Timing Characteristics Timing characteristics for 54SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all 54SX family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the users design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout del ays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the netsin adesign are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6%of netsin a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO=24) routing delays in the data sheet specifications section. Timing Derating 54SX devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 19(el Preliminary A54SXK16 Timing Characteristics (Worst-Case Commercial Conditions, Voecr= 4.75 V, Voca Voc; = 3.0 V, Ty = 70C) C-Cell Propagation Delays! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units tpp Internal Array Module 0.7 0.8 0.9 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 ns tec FO=1 Routing Delay, Fast Connect 0.4 0.4 0.5 ns tap1 FO=1 Routing Delay 0.4 0.4 0.5 ns tape FO=2 Routing Delay 0.7 0.8 0.9 ns taps FO=3 Routing Delay 0.9 1.0 1.2 ns trp4 FO=4 Routing Delay 1.2 1.4 1.6 ns taps FO=8 Routing Delay 2.2 2.5 2.9 ns tap12 FO=12 Routing Delay 3.2 3.7 4.3 ns tapis FO=18 Routing Delay 4.8 5.4 6.4 ns tape FO=24 Routing Delay 6.3 7.1 8.4 ns R-Cell Timing trco Sequential Clock-to-Q 0.5 0.6 0.7 ns tcLr Asynchronous Clear-to-Q 0.5 0.6 0.7 ns tpRESET Asynchronous Preset-to-Q 0.5 0.6 0.7 ns tsup Flip-Flop Data Input Set-Up 0.6 0.7 0.8 ns tup Flip-Flop Data Input Hold 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.1 2.5 ns Notes: 1. For dual-module macros, use tpp + tapi + tppn. trcot tani + tepp or tppy + tany + tsup. whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance Post-routetiming analysis or simulation is required to determine actual worst-case performance. Post-routetiming is based on actual routing delay measurements per for med on the device prior to shipment. 20Preliminary54SX Family FPGAs A54SX16 Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays -2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tINYH Input Data Pad-to-Y HIGH 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.7 1.9 2.2 ns Predicted Input Routing Delays tiap1 FO=1 Routing Delay 0.4 0.4 0.5 ns tinp2 FO=2 Routing Delay 0.7 0.8 0.9 ns tiaps FO=3 Routing Delay 0.9 1.0 1.2 ns tinp4 FO=4 Routing Delay 1.2 1.4 1.6 ns tirnps FO=8 Routing Delay 2.2 2.5 2.9 ns tiapt12 FO=12 Routing Delay 3.2 3.7 4.3 ns tinD18 FO=18 Routing Delay 4.8 5.4 6.4 ns tinpe4 FO=24 Routing Delay 6.3 7.4 8.4 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 21(el Preliminary A54SX16 Timing Charateristics (continued) (Worst-Case Commercial Conditions) 1/O Module TTL Output Timing! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 2.1 2.4 2.8 ns toHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 ns teENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 ns tENZH Enable-to-Pad, Z to H 2.7 3.1 3.6 ns tENLZ Enable-to-Pad, L to Z 1.7 1.9 2.2 ns teNHz Enable-to-Pad, H to Z 1.5 1.7 2.0 ns Note: 1. Delays based on 35pF loading, except tey7 and teyzy. For teyz and teyzy theloading is 5pF. 22Preliminary54SX Family FPGAs A54SX16 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) Array Clock Network 2 Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.3 1.5 1.8 ns tHcKL Input HIGH to LOW (Pad to R-Cell Input) 1.4 1.7 1.9 ns tHPWH Minimum Pulse Width HIGH 1.6 1.8 2.1 ns tuPWL Minimum Pulse Width LOW 1.6 1.8 2.1 ns tucksw Maximum Skew 0.2 0.3 0.3 ns tup Minimum Period 3.1 3.6 4.2 ns fuMax Maximum Frequency 320 280 240 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.8 2.1 2.5 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.0 2.3 2.7 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.1 2.5 2.8 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.2 2.5 3.0 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.1 2.4 2.8 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.2 2.5 3.0 ns tRPWH Min. Pulse Width HIGH 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.4 2.7 3.2 ns tracKksw Maximum Skew (Light Load) 0.5 0.5 0.7 ns tacksw Maximum Skew (50% Load) 0.6 0.7 0.8 ns tacksw Maximum Skew (100% Load) 0.6 0.7 0.8 ns 23(el Preliminary A54SK16P Timing Characteristics (Worst-Case Commercial Conditions, Voecr= 4.75 V, Voca Voc; = 3.0 V, Ty = 70C) C-Cell Propagation Delays! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units tpp Internal Array Module 0.7 0.8 0.9 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 ns tec FO=1 Routing Delay, Fast Connect 0.4 0.4 0.5 ns tap1 FO=1 Routing Delay 0.4 0.4 0.5 ns tape FO=2 Routing Delay 0.7 0.8 0.9 ns taps FO=3 Routing Delay 0.9 1.0 1.2 ns trp4 FO=4 Routing Delay 1.2 1.4 1.6 ns taps FO=8 Routing Delay 2.2 2.5 2.9 ns tap12 FO=12 Routing Delay 3.2 3.7 4.3 ns tapis FO=18 Routing Delay 4.8 5.4 6.4 ns tape FO=24 Routing Delay 6.3 7.1 8.4 ns R-Cell Timing trco Sequential Clock-to-Q 0.5 0.6 0.7 ns tcLr Asynchronous Clear-to-Q 0.5 0.6 0.7 ns tpRESET Asynchronous Preset-to-Q 0.5 0.6 0.7 ns tsup Flip-Flop Data Input Set-Up 0.6 0.7 0.8 ns tup Flip-Flop Data Input Hold 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.1 2.5 ns Notes: 1. For dual-module macros, use tpp + tapi + tppn. trcot tani + tepp or tppy + tany + tsup. whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance Post-routetiming analysis or simulation is required to determine actual worst-case performance. Post-routetiming is based on actual routing delay measurements per for med on the device prior to shipment. 24Preliminary54SX Family FPGAs A54SX16P Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays -2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tINYH Input Data Pad-to-Y HIGH 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.7 1.9 2.2 ns Predicted Input Routing Delays tiap1 FO=1 Routing Delay 0.4 0.4 0.5 ns tinp2 FO=2 Routing Delay 0.7 0.8 0.9 ns tiaps FO=3 Routing Delay 0.9 1.0 1.2 ns tinp4 FO=4 Routing Delay 1.2 1.4 1.6 ns tirnps FO=8 Routing Delay 2.2 2.5 2.9 ns tiapt12 FO=12 Routing Delay 3.2 3.7 4.3 ns tinD18 FO=18 Routing Delay 4.8 5.4 6.4 ns tinpe4 FO=24 Routing Delay 6.3 7.4 8.4 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 25S9chte/ Preliminary A54SX16P Timing Charateristics (continued) (Worst-Case Commercial Conditions Vocr = 3.0 V, Veca, Veco; = 3.0 V, Ty = 70C) 1/0 Module PCI Output Timing! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 2.0 2.3 2.7 ns toHL Data-to-Pad HIGH to LOW 2.0 2.2 2.6 ns teENZL Enable-to-Pad, Z to L 1.0 1.4 1.3 ns teNZH Enable-to-Pad, Z to H 1.2 1.5 1.8 ns tENLZ Enable-to-Pad, L to Z 1.1 1.3 1.5 ns teNHz Enable-to-Pad, H to Z 1.3 1.5 1.7 ns Note: 1. Delays based on 10pF loading. (Worst-Case Commercial Conditions Voor = 3.0 V, Voca, Voc, = 3.0 V, Ty = 70C) 1/0 Module TTL Output Timing 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 2.5 2.8 3.3 ns tpHL Data-to-Pad HIGH to LOW 2.3 2.6 3.1 ns tENZL Enable-to-Pad, Z to L 2.9 3.2 3.8 ns tENZH Enable-to-Pad, Z to H 3.5 3.9 4.6 ns tENLZ Enable-to-Pad, L to Z 2.7 3.1 3.6 ns tENHZ Enable-to-Pad, H to Z 3.3 3.7 4.4 ns 26Preliminary54SX Family FPGAs A54SX16P Timing Charateristics (continued) (Worst-Case Commercial Conditions Vocr = 4.75 V, Voca, Voc; = 3.0 V, Ty = 70C) 1/0 Module TTL Output Timing 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 2.8 3.1 3.7 ns toHL Data-to-Pad HIGH to LOW 2.9 3.2 3.8 ns teENZL Enable-to-Pad, Z to L 3.4 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 3.8 4.3 5.0 ns tENLZ Enable-to-Pad, L to Z 27 3.0 3.5 ns tENHZ Enable-to-Pad, H to Z 3.2 3.7 43 ns (Worst-Case Commercial Conditions Voce = 4.75 V, Voca, Voc, = 4.75 V, Ty = 70C) 1/0 Module TTL/PCI Output Timing -2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 1.7 2.0 2.3 ns tpHL Data-to-Pad HIGH to LOW 2.2 2.4 2.9 ns tenZL Enable-to-Pad, Z to L 2.6 3.0 3.5 ns teNZH Enable-to-Pad, Z to H 1.7 1.9 2.3 ns tENLZ Enable-to-Pad, L to Z 3.1 3.5 4.1 ns tENHZ Enable-to-Pad, H to Z 3.3 3.7 4.4 ns 27S9chte/ Preliminary A54SX16P Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) Array Clock Network 2 Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tHCKH Input LOW to HIGH (Pad to R-Cell Input) 1.3 1.5 1.8 ns tHcKL Input HIGH to LOW (Pad to R-Cell Input) 1.4 1.7 1.9 ns tHPWH Minimum Pulse Width HIGH 1.6 1.8 2.1 ns tuPWL Minimum Pulse Width LOW 1.6 1.8 2.1 ns tucksw Maximum Skew 0.2 0.3 0.3 ns tup Minimum Period 3.1 3.6 4.2 ns fuMax Maximum Frequency 320 280 240 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 1.8 2.1 2.5 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 2.0 2.3 2.7 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.1 2.5 2.8 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.2 2.5 3.0 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.1 2.4 2.8 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.2 2.5 3.0 ns tRPWH Min. Pulse Width HIGH 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.4 2.7 3.2 ns tracKksw Maximum Skew (Light Load) 0.5 0.5 0.7 ns tacksw Maximum Skew (50% Load) 0.6 0.7 0.8 ns tacksw Maximum Skew (100% Load) 0.6 0.7 0.8 ns 28Preliminary54SX Family FPGAs A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, Voecr= 4.75 V, Voca Voc; = 3.0 V, Ty = 70C) C-Cell Propagation Delays! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units tpp Internal Array Module 0.7 0.8 0.9 ns Predicted Routing Delays? toc FO=1 Routing Delay, Direct Connect 0.1 0.1 0.1 ns tec FO=1 Routing Delay, Fast Connect 0.4 0.4 0.5 ns tap1 FO=1 Routing Delay 0.4 0.4 0.5 ns tape FO=2 Routing Delay 0.8 0.9 1.0 ns taps FO=3 Routing Delay 1.2 1.4 1.6 ns trp4 FO=4 Routing Delay 1.6 1.8 2.1 ns tapos FO=8 Routing Delay 3.1 3.5 4.1 ns tap12 FO=12 Routing Delay 4.7 5.3 6.2 ns trois FO=18 Routing Delay 7.0 7.9 9.3 ns tape FO=24 Routing Delay 9.3 10.5 12.4 ns R-Cell Timing trco Sequential Clock-to-Q 0.5 0.6 0.7 ns tcLr Asynchronous Clear-to-Q 0.5 0.6 0.7 ns tpRESET Asynchronous Preset-to-Q 0.5 0.6 0.7 ns tsup Flip-Flop Data Input Set-Up 0.6 0.7 0.8 ns tup Flip-Flop Data Input Hold 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.9 2.1 2.5 ns Notes: 1. For dual-module macros, use tpp + tapi + tppn. trcot tani + tepp or tppy + tany + tsup. whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance Post-routetiming analysis or simulation is required to determine actual worst-case performance. Post-routetiming is based on actual routing delay measurements per for med on the device prior to shipment. 29S9chte/ Preliminary A54SX32 Timing Characteristics (continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays -2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tINYH Input Data Pad-to-Y HIGH 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.7 1.9 2.2 ns Predicted Input Routing Delays tirnp4 FO=1 Routing Delay 0.4 0.4 0.5 ns tinp2 FO=2 Routing Delay 0.8 0.9 1.0 ns tiaps FO=3 Routing Delay 1.2 1.4 1.6 ns tirnpa FO=4 Routing Delay 1.6 1.8 2.1 ns tirnps FO=8 Routing Delay 3.1 3.5 4.1 ns tiapt12 FO=12 Routing Delay 4.7 5.3 6.2 ns tirnpis FO=18 Routing Delay 7.0 7.9 9.3 ns tinpe4 FO=24 Routing Delay 9.3 10.5 12.4 ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements per for med on the device prior to shipment. 30Preliminary54SX Family FPGAs A54SX32 Timing Charateristics (continued) (Worst-Case Commercial Conditions) 1/O Module TTL Output Timing! 2 Speed 1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units toLH Data-to-Pad LOW to HIGH 2.1 2.4 2.8 ns toHL Data-to-Pad HIGH to LOW 2.1 2.4 2.8 ns teENZL Enable-to-Pad, Z to L 2.4 2.8 3.2 ns tENZH Enable-to-Pad, Z to H 2.7 3.1 3.6 ns tENLZ Enable-to-Pad, L to Z 1.7 1.9 2.2 ns teNHz Enable-to-Pad, H to Z 1.5 1.7 2.0 ns Note: 1. Delays based on 35pF loading, except teyz and teyzy. For teyz and teyz, theloading is 5pF. 31S9chte/ Preliminary A54SX32 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) Array Clock Network 2 Speed -1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. | Units tuckH Input LOW to HIGH (Pad to R-Cell Input) 1.9 2.1 2.5 ns tHCKL Input HIGH to LOW (Pad to R-Cell Input) 1.9 2.1 2.5 ns tHPWH Minimum Pulse Width HIGH 1.6 1.8 2.1 ns tuPWL Minimum Pulse Width LOW 1.6 1.8 2.1 ns tucksw Maximum Skew 0.2 0.3 0.3 ns tup Minimum Period 3.1 3.6 4.2 ns fuMax Maximum Frequency 320 280 240 MHz Routed Array Clock Networks tRcKH Input LOW to HIGH (Light Load) (Pad to R-Cell Input) 2.1 2.4 2.8 ns tRCKL Input HIGH to LOW (Light Load) (Pad to R-Cell Input) 1.5 2.6 3.0 ns tackH Input LOW to HIGH (50% Load) (Pad to R-Cell Input) 2.5 2.8 3.3 ns tRcKL Input HIGH to LOW (50% Load) (Pad to R-Cell Input) 2.6 2.9 3.4 ns tackH Input LOW to HIGH (100% Load) (Pad to R-Cell Input) 2.5 2.8 3.3 ns tRcKL Input HIGH to LOW (100% Load) (Pad to R-Cell Input) 2.6 2.9 3.4 ns tRPWH Min. Pulse Width HIGH 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.4 2.7 3.2 ns tracKksw Maximum Skew (Light Load) 0.6 0.7 0.8 ns tacksw Maximum Skew (50% Load) 0.9 1.0 1.2 ns tacksw Maximum Skew (100% Load) 0.9 1.0 1.2 ns 32Preliminary54SX Family FPGAs Package Pin Assignments 208-Pin PQFP 208-Pin PQFP 33(el Preliminary 208-Pin PQFP A54SX16, A54SX16, A54SX08 A54SX16P A54SX32 A54SX08 A54SX16P A54SX32 Pin Number Function Function Function Pin Number Function Function Function 1 GND GND GND 54 VO VO VO 2 TDI, /O TDI, /O TDI, Oo 55 VO VO VO 3 VO VO VO 56 VO VO VO 4 NC VO VO 57 VO VO VO 5 VO VO VO 58 VO VO VO 6 NC VO VO 59 VO VO VO 7 VO VO VO 60 Veci Vecl Veci 8 VO VO VO 61 NC VO VO 9 VO VO VO 62 VO VO VO 10 VO VO VO 63 VO VO VO 11 TMS TMS TMS 64 NC VO VO 12 Vecl Voc Vecl 65* VO VO Nc* 13 VO VO VO 66 VO VO VO 14 NC VO VO 67 NC VO VO 15 VO VO VO 68 VO VO VO 16 VO VO VO 69 VO VO VO 17 NC VO VO 70 NC VO VO 18 VO VO VO 71 VO VO VO 19 VO VO VO 72 VO VO VO 20 NC VO VO 73 NC VO VO 21 VO VO VO 74 VO VO VO 22 VO VO VO 75 NC VO VO 23 NC VO VO 76 PRB, I/O PRB, I/O PRB, I/O 24 VO VO VO 77 GND GND GND 25 Vecr Vecr Voecr 78 Veca Veca Veca 26 GND GND GND 79 GND GND GND 27 Veca Veca Veca 80 Voecr Vecr Vecr 28 GND GND GND 81 VO VO VO 29 VO VO VO 82 HCLK HCLK HCLK 30 VO VO VO 83 VO VO VO 31 NC VO VO 84 VO VO VO 32 VO VO VO 85 NC VO VO 33 VO VO VO 86 VO VO VO 34 VO VO VO 87 VO VO VO 35 NC VO VO 88 NC VO VO 36 VO VO VO 89 VO VO VO 37 VO VO VO 90 VO VO VO 38 VO VO VO 91 NC VO VO 39 NC VO VO 92 VO VO VO 40 Voc Voc Vecl 93 VO VO VO 41 Voca Voca Voca 94 NC VO VO 42 VO VO VO 95 VO VO VO 43 VO VO VO 96 VO VO VO 44 VO VO VO 97 NC VO VO 45 VO VO VO 98 Veci Vecl Veci 46 VO VO VO 99 VO VO VO 47 VO VO VO 100 VO VO VO 48 NC VO VO 101 VO VO VO 49 VO VO VO 102 VO VO VO 50 NC VO VO 103 TDO, I/O TDO, I/O TDO, I/O 54 VO VO VO 104 VO VO VO 52 GND GND GND 105 GND GND GND 53 VO VO VO 106 NC VO VO * Please note that Pin 65 in the A54SX32 PQ208 is a no connect (NC). 34Preliminary54SX Family FPGAs 208-Pin PQFP (Continued) A54SX16, A54SX16, A54SX08 A54SX16P A54SX32 A54SX08 A54SX16P A54SX32 Pin Number Function Function Function Pin Number Function Function Function 107 VO VO VO 158 VO VO VO 108 NC VO VO 159 VO VO VO 109 VO VO VO 160 VO VO VO 110 VO VO VO 161 VO VO VO 111 VO VO VO 162 VO VO VO 112 VO VO VO 163 VO VO VO 113 VO VO VO 164 Veci Vecl Veci 114 Voca Voeca Veca 165 VO VO VO 115 Veci Veci Veci 166 VO VO VO 116 NC VO VO 167 NC VO VO 117 VO VO VO 168 VO VO VO 118 VO VO VO 169 VO VO VO 119 NC VO VO 170 NC VO VO 120 VO VO VO 171 VO VO VO 121 VO VO VO 172 VO VO VO 122 NC VO VO 173 NC VO VO 123 VO VO VO 174 VO VO VO 124 VO VO VO 175 VO VO VO 125 NC VO VO 176 NC VO VO 126 VO VO VO 177 VO VO VO 127 VO VO VO 178 VO VO VO 128 VO VO VO 179 VO VO VO 129 GND GND GND 180 CLKA CLKA CLKA 130 Voca Voeca Veca 181 CLKB CLKB CLKB 131 GND GND GND 182 Vocr Vecr Voecr 132 Voecr Vocr Vecr 183 GND GND GND 133 VO VO VO 184 Voca Veca Voca 134 VO VO VO 185 GND GND GND 135 NC VO VO 186 PRA, I/O PRA, I/O PRA, I/O 136 VO VO VO 187 VO VO VO 137 VO VO VO 188 VO VO VO 138 NC VO VO 189 NC VO VO 139 VO VO VO 190 VO VO VO 140 VO VO VO 191 VO VO VO 144 NC VO VO 192 NC VO VO 142 VO VO VO 193 VO VO VO 143 NC VO VO 194 VO VO VO 144 VO VO VO 195 NC VO VO 145 Voca Voca Voca 196 VO VO VO 146 GND GND GND 197 VO VO VO 147 VO VO VO 198 NC VO VO 148 Veci Veci Veci 199 VO VO VO 149 VO VO VO 200 VO VO VO 150 VO VO VO 201 Veci Vecl Veci 151 VO VO VO 202 NC VO VO 152 VO VO VO 203 NC VO VO 153 VO VO VO 204 VO VO VO 154 VO VO VO 205 NC VO VO 155 NC VO VO 206 VO VO VO 156 NC VO VO 207 VO VO VO 157 GND GND GND 208 TCK, I/O TCK, I/O TCK, I/O * Please note that Pin 65 in the A54SX32 PQ208 is a no connect (NC). 35(el Preliminary Package Pin Assignments (continued) 144-Pin TQFP (Top View) 36Preliminary54SX Family FPGAs 144-Pin TQEP A54SX08 A54SX16P A54SX32 A54SX08 A54SX16P A54SX32 Pin Number = Function Function Function Pin Number _ Function Function Function 1 GND GND GND At VO VO VO 2 TDI, I/O TDI, I/O TDI, I/O 42 VO VO VO 3 VO VO VO 43 VO VO VO 4 VO VO VO 44 Vecl Vecl Vecl 5 VO VO VO 45 VO VO VO 6 VO VO VO 46 VO VO VO 7 VO VO VO 47 VO VO VO 8 VO VO VO 48 VO VO VO 9 TMS TMS TMS 49 VO VO VO 10 Vecl Vecl Vecl 50 VO VO VO 11 GND GND GND 51 VO VO VO 12 VO VO VO 52 VO VO VO 13 VO VO VO 53 VO VO VO 14 VO VO VO 54 PRB, I/O PRB, I/O PRB, I/O 15 VO VO VO 55 VO VO VO 16 VO VO VO 56 Voca Voca Voca 17 VO VO VO 57 GND GND GND 18 VO VO VO 58 Vocr Vocr Vocr 19 Vocr Vocr Vocr 59 VO VO VO 20 Voca Voca Voca 60 HCLK HCLK HCLK 21 VO VO VO 61 VO VO VO 22 VO VO VO 62 VO VO VO 23 VO VO VO 63 VO VO VO 24 VO VO VO 64 VO VO VO 25 VO VO VO 65 VO VO VO 26 VO VO VO 66 VO VO VO 27 VO VO VO 67 VO VO VO 28 GND GND GND 68 Vecl Vecl Vecl 29 Vecl Vecl Vecl 69 VO VO VO 30 Voca Voca Voca 70 VO VO VO 31 VO VO VO 71 TDO, I/O TDO, I/O TDO, I/O 32 VO VO VO 72 VO VO VO 33 VO VO VO 73 GND GND GND 34 VO VO VO 74 VO VO VO 35 VO VO VO 75 VO VO VO 36 GND GND GND 76 VO VO VO 37 VO VO VO 77 VO VO VO 38 VO VO VO 78 VO VO VO 39 VO VO VO 79 Voca Voca Voca 40 VO VO VO 80 Vecl Vecl Vecl 37(el Preliminary 144-Pin TQFP (Continued) A54SX08 A54SX16P A54SX32 A54SX08 A54SX16P A54SX32 Pin Number = Function Function Function Pin Number _ Function Function Function 81 GND GND GND 113 VO VO /O 82 VO VO VO 114 VO VO VO 83 VO VO VO 115 Voc! Voc! Voc! 84 VO VO VO 116 VO VO VO 85 VO VO VO 117 VO VO VO 86 VO VO VO 118 VO VO VO 87 VO VO VO 119 VO VO VO 88 VO VO VO 120 VO VO VO 89 Voca Voca Voca 121 VO VO VO 90 Vocr Vocr Vocr 122 VO VO VO 91 VO VO VO 123 VO VO VO 92 VO VO VO 124 VO VO VO 93 VO VO VO 125 CLKA CLKA CLKA 94 VO VO VO 126 CLKB CLKB CLKB 95 VO VO VO 127 Vocr Vocr Vocr 96 VO VO VO 128 GND GND GND 97 VO VO VO 129 Voca Voca Voca 98 Voca Voca Voca 130 VO VO VO 99 GND GND GND 131 PRA, I/O PRA, I/O PRA, I/O 100 VO VO VO 132 VO VO VO 101 GND GND GND 133 VO VO VO 102 Vecl Vecl Vecl 134 VO VO VO 103 VO VO VO 135 VO VO VO 104 VO VO VO 136 VO VO VO 105 VO VO VO 137 VO VO VO 106 VO VO VO 138 VO VO VO 107 VO VO VO 139 VO VO VO 108 VO VO VO 140 Vecl Vecl Vecl 109 GND GND GND 141 VO VO /O 110 VO VO VO 142 VO VO VO 111 VO VO VO 143 VO VO VO 112 VO VO VO 144 TCK, I/O TCK, I/O TCK, I/O 113 VO VO VO 38Preliminary54SX Family FPGAs Package Pin Assignments (continued) 176-Pin TQFP (Top View) 176-Pin TQFP 39(el Preliminary 176-Pin TQFP A54SX08 A54SX16 A54SX32 A54SX08 A54SX16 A54SX32 Pin Number Function Function Function Pin Number Function Function Function 1 GND GND GND 45 /O /O /O 2 TDI, /O TDI, /O TDI, /O 46 /O /O /O 3 NC /O /O 47 /O /O /O 4 /O /O /O 48 /O /O /O 5 /O /O /O 49 /O /O /O 6 /O /O /O 50 /O /O /O 7 /O /O /O 51 /O /O /O 8 /O /O /O 52 Vecl Vecl Vecl 9 /O /O /O 53 /O /O /O 10 TMS TMS TMS 54 NC /O /O 11 Vecl Vecl Vecl 55 /O /O /O 12 NC /O /O 56 /O /O /O 13 /O /O /O 57 NC /O /O 14 /O /O /O 58 /O /O /O 15 /O /O /O 59 /O /O /O 16 /O /O /O 60 /O /O /O 17 /O /O /O 61 /O /O /O 18 /O /O /O 62 /O /O /O 19 /O /O /O 63 /O /O /O 20 /O /O /O 64 PRB, I/O PRB, I/O PRB, I/O 21 GND GND GND 65 GND GND GND 22 Veca Veca Veca 66 Veca Veca Veca 23 GND GND GND 67 Vocr Vocr Vocr 24 /O /O /O 68 /O /O /O 25 /O /O /O 69 HCLK HCLK HCLK 26 /O /O /O 70 /O /O /O 27 /O /O /O 71 /O /O /O 28 /O /O /O 72 /O /O /O 29 /O /O /O 73 /O /O /O 30 /O /O /O 74 /O /O /O 31 /O /O /O 75 /O /O /O 32 Vecl Vecl Vecl 76 /O /O /O 33 Voca Voca Voca 77 /O /O /O 34 /O /O /O 78 /O /O /O 35 /O /O /O 79 NC /O /O 36 /O /O /O 80 /O /O /O 37 /O /O /O 81 NC /O /O 38 /O /O /O 82 Vecl Vecl Vecl 39 /O /O /O 83 /O /O /O 40 NC /O /O 84 /O /O /O A1 /O /O /O 85 /O /O /O 42 NC /O /O 86 /O /O /O 43 /O /O /O 87 TDO, I/O TDO, I/O TDO, I/O 44 GND GND GND 88 /O /O ie) 40Preliminary54SX Family FPGAs 176-Pin TQFP (Continued) A54SX08 A54SX16 A54SX32 A54SX08 A54SX16 A54SX32 Pin Number Function Function Function Pin Number Function Function Function 89 GND GND GND 133 GND GND GND 90 NC /O /O 134 /O /O /O 91 NC /O /O 135 /O /O /O 92 /O /O /O 136 /O /O /O 93 /O /O /O 137 /O /O /O 94 /O /O /O 138 /O /O /O 95 /O /O /O 139 /O /O /O 96 /O /O /O 140 Vecl Vecl Vecl 97 /O /O /O 141 /O /O /O 98 Voca Voca Voca 142 /O /O /O 99 Vecl Vecl Vecl 143 /O /O /O 100 /O /O /O 144 /O /O /O 101 /O /O /O 145 /O /O /O 102 /O /O /O 146 /O /O /O 103 /O /O /O 147 /O /O /O 104 /O /O /O 148 /O /O /O 105 /O /O /O 149 /O /O /O 106 /O /O /O 150 /O /O /O 107 /O /O /O 151 /O /O /O 108 GND GND GND 152 CLKA CLKA CLKA 109 Voca Voca Voca 153 CLKB CLKB CLKB 110 GND GND GND 154 Vocr Vocr Vocr 111 /O /O /O 155 GND GND GND 112 /O /O /O 156 Voca Voca Voca 113 /O /O /O 157 PRA, I/O PRA, I/O PRA, I/O 114 /O /O /O 158 /O /O /O 115 /O /O /O 159 /O /O /O 116 /O /O /O 160 /O /O /O 117 /O /O /O 161 /O /O /O 118 NC /O /O 162 /O /O /O 119 /O /O /O 163 /O /O /O 120 NC /O /O 164 /O /O /O 121 NC /O /O 165 /O /O /O 122 Voca Voca Voca 166 /O /O /O 123 GND GND GND 167 /O /O /O 124 Vecl Vecl Vecl 168 NC /O /O 125 /O /O /O 169 Vecl Vecl Vecl 126 /O /O /O 170 /O /O /O 127 /O /O /O 171 NC /O /O 128 /O /O /O 172 NC /O /O 129 /O /O /O 173 NC /O /O 130 /O /O /O 174 /O /O /O 131 NC /O /O 175 /O /O /O 132 NC /O /O 176 TCK, I/O TCK, I/O TCK, I/O 41(el Preliminary Package Pin Assignments (continued) 100-Pin VQFP (Top View) CUPP UATE CUA EE TT CUE 100 ,O 100-Pin VQFP UUUUUUUUUUUUUUUUU UU UUUUUUUUUUUUUUUUUUUUUUUa 42Preliminary54SX Family FPGAs 100-VQFP A54SX16 , A54SX16 , A54SX08 A54SX16P A54SX08 A54SX16P Pin Number Function Function Pin Number Function Function 1 GND GND 54 GND GND 2 TDI, /O TDI, /O 52 VO VO 3 VO VO 53 VO VO 4 VO VO 54 VO VO 5 VO VO 55 VO VO 6 VO VO 56 VO VO 7 TMS TMS 57 Voca Voca 8 Vecl Vecl 58 Vecl Vecl 9 GND GND 59 VO VO 10 VO VO 60 VO VO 11 VO VO 61 VO VO 12 VO VO 62 VO VO 13 VO VO 63 VO VO 14 VO VO 64 VO VO 15 VO VO 65 VO VO 16 VO VO 66 VO VO 17 VO VO 67 Voca Voca 18 VO VO 68 GND GND 19 VO VO 69 GND GND 20 Veci Veci 70 VO VO 21 VO VO 71 VO VO 22 VO VO 72 VO VO 23 VO VO 73 VO VO 24 VO VO 74 VO VO 25 VO VO 75 VO VO 26 VO VO 76 VO VO 27 VO VO 77 VO VO 28 VO VO 78 VO VO 29 VO VO 79 VO VO 30 VO VO 80 VO VO 31 VO VO 81 VO VO 32 VO VO 82 Voc Vecl 33 VO VO 83 VO VO 34 PRB, I/O PRB, I/O 84 VO VO 35 Voeca Voca 85 VO VO 36 GND GND 86 VO VO 37 Vocr Voecr 87 CLKA CLKA 38 VO VO 88 CLKB CLKB 39 HCLK HCLK 89 Vocr Vocr 40 VO VO 90 Voca Voca 41 VO VO 91 GND GND 42 VO VO 92 PRA, I/O PRA, I/O 43 VO VO 93 VO VO 44 Veci Veci 94 VO ie) 45 VO VO 95 VO VO 46 VO VO 96 VO VO 47 VO VO 97 VO VO 48 VO VO 98 VO VO 49 TDO, I/O TDO, I/O 99 VO VO 50 VO VO 100 TCK, I/O TCK, I/O 43(el Preliminary Package Pin Assignments (continued) 313-Pin PBGA (Top View) $< Sec cHomvnvzt=- Re LToOmAmMmIOD>D 123 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 N O_O O_O O_O 0 0 0 0 0 0 O O_O 0 OO 0 0 0 0 0 0 O O_O 0.0 0.0 0.0 0 0 0 0 0 O_O 0 0 0 0.0.0 0.0 0 O O_O O_O 0 0 0 0 0 0 0 0 O O_O 0 OO 0 0 0 0 0 0 O OOo POOP OOO? OPPO 00 OOOO OOP OOM Moo 6 POP OPO 6? Oooo meme mememen OOO 66 OPO OOO? OOo 6 POP 0806? eee tode ome memememen OOOO 66 OPO OOO? Oooo meme memememen OOWOWWWOWAOAOO00 0 123 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NS Ya Bex es CtrwmvzeET ACTH 7M OOD > > oO > > m 0 44Preliminary54SX Family FPGAs 313-Pin PBGA Pin Number A54SX32 Pin Number A54SX32 Pin Number A54SX32 Pin Number A54SX32 C1 TDI, /O T8 /O AB12 ie) W25 /O D2 ie) U3 /O U13 ie) U21 /O H8 ie) T6 /O AA13 ie) T20 /O K10 ie) U9 /O Vv14 ie) U23 /O F1 ie) v4 /O R15 ie) R17 /O F4 ie) W1 /O AD14 ie) U25 /O G5 ie) U7 /O AB14 ie) T22 /O F2 ie) W3 /O Y14 ie) R19 /O H6 ie) V6 /O AE15 ie) T24 /O G3 TMS W5 /O U15 ie) R21 /O G1 ie) Y2 /O AC15 ie) P16 /O H4 ie) AAI /O W15 ie) R23 /O H2 ie) Y4 /O AA15 ie) P18 /O J5 ie) AA3 /O AD16 ie) R25 /O K6 ie) AC3 1/0 AB16 ie) P22 /O J3 ie) AC1 /O AE17 ie) P24 /O L9 ie) AE3 /O AC17 ie) N17 /O J1 ie) AD4 /O Y16 ie) N19 /O K4 ie) Y6 /O AA17 ie) N21 /O L7 ie) V8 /O AD18 ie) M18 /O K2 ie) AC5 /O U17 ie) L15 /O L5 ie) T10 /O AE19 ie) M24 /O M10 ie) AE5 /O W17 ie) M22 /O L3 ie) AB6 /O AC19 ie) M20 /O M8 ie) AA7 /O Y18 ie) L25 /O L1 ie) Y8 /O AA19 ie) L17 /O M6 ie) Ww9 /O AD20 ie) L23 /O M4 ie) AC7 /O W19 ie) L19 /O M2 ie) V10 /O AE21 ie) L21 /O N7 ie) AE7 /O AA21 ie) K24 /O N1 ie) AB8 /O AC21 ie) K22 /O P10 ie) AD8 /O AC23 ie) J25 /O P8 ie) Y10 /O AE23 TDO, I/O K18 /O R11 ie) AC9 /O AD24 ie) J23 /O P2 ie) U11 /O AB22 ie) H24 /O P4 ie) AE9 /O AB24 ie) J17 /O P6 ie) AB10 /O V18 ie) G25 /O R1 ie) Wwi1 /O T16 ie) J19 /O R9 ie) AD10 /O AA25 ie) G23 /O R3 ie) AA11 /O Y22 ie) H20 /O R7 ie) T12 /O We ie) Get /O R5 ie) AC11 /O V20 ie) F24 /O T2 ie) V12 /O U19 ie) G19 /O T4 ie) AE11 /O W23 ie) E25 /O U1 ie) Y12 /O T18 ie) F22 /O 45(el Preliminary 313-Pin PBGA (Continued) Pin Number A54SX32 Pin Number A54SX32 Pin Number A54SX32 E21 ie) C11 /O F10 NC E23 ie) G11 /O C5 NC C23 ie) E11 /O J7 NC B24 ie) B10 /O F6 NC D22 ie) D10 /O Y24 NC B22 ie) AQ /O A3 NC F20 ie) H10 /O Al GND C21 ie) cg /O AD2 GND K16 ie) E9 /O AE25 GND A21 ie) B8& /O J21 GND D20 ie) J9 /O A25 GND E19 ie) D8 /O N11 GND B20 ie) A7 /O N13 GND F18 ie) C7 /O R13 GND G17 ie) F8 /O M14 GND H16 ie) E7 /O P14 GND A19 ie) B6 /O M12 GND D18 ie) G7 /O P12 GND B18 ie) A5 /O L13 GND E17 ie) D6 /O N15 GND C17 ie) E5 /O N3 Voca J15 ie) B4 /O v2 Voca A17 ie) C3 /O AE13 Voca D16 ie) B2 TCK, I/O V22 Voca G15 ie) AD12 PRB, I/O N25 Voca B16 ie) D4 NC K20 Voca E15 ie) E3 NC E13 Voca K14 ie) W7 NC N5 Vocr C15 ie) AA5 NC AC13 Vocr H14 ie) AB2 NC N23 Vocr A15 ie) AE1 NC A13 Vocr F14 ie) AB4 NC AD6 Vecl D14 ie) AAQ NC C13 Vecl B14 ie) V16 NC G9 Vecl J13 CLKA AB20 NC U5 Vecl G13 CLKB AD22 NC M16 Vecl T14 HCLK AC25 NC K8& Vecl K12 ie) Y20 NC C19 Vecl H12 PRA, I/O AA23 NC H22 Vecl L11 ie) P20 NC N9 Vecl B12 ie) D24 NC V24 Vecl D12 ie) C25 NC W13 Vecl Fi2 ie) A23 NC AB18 Vecl Alt ie) H18 NC J11 ie) F16 NC 46Preliminary54SX Family FPGAs Package Mechanical Drawings Plastic Quad Flat Pack (PQFP, TQFP, VQFP) A A E1 E Vv Vv ba D1 > he D > See Detail A a f_\ \ | A A2 |p A, ccc |e Detail A 10 Typ A 0.20 RAD \ Theta >| > 0.20 RAD Typ F 47(el Preliminary Plastic Quad Flat Packages (PQFP) JEDEC PQFP208 Equivalent MO-143 Dimension Min. Nom. Max. A 4.10 Al 0.25 A2 3.17 3.37 3.67 b 0.15 0.30 c 0.13 0.23 D 30.35 30.60 30.85 D1 27.90 28.00 28.10 E 30.35 30.60 30.85 E1 27.90 28.00 28.10 e 0.50 BSC L 0.50 0.75 ccc 0.10 Theta 0 7 deg Notes: 7. All dimensions arein millimeters. 2. BSCBasic Spacing between Centers. Thin Quad Flat Packs (TQFP and VQFP) JEDEC TQFP144 TQFP176 VQFP100 Equivalent MO0-136 MO0-136 MO-136 Dimension Min. Nom. Max. Min. Nom. Max. Min. Nom. Max. A 1.60 1.60 1.20 Al 0.05 0.15 0.05 0.15 0.05 0.15 A2 1.35 1.45 1.35 1.45 0.95 1.05 b 0.17 0.27 0.17 0.27 0.17 0.27 c 0.09 0.20 0.09 0.20 0.09 0.20 D/E 21.90 22.00 22.10 25.75 26.00 26.25 15.75 16.00 16.25 D1/E1 19.90 20.00 20.10 23.9 24.00 24.10 13.90 14.00 14.10 e 0.50 BSC 0.50 BSC 0.50 BSC L 0.45 0.75 0.45 0.75 0.45 0.75 ccc 0.10 0.10 0.10 Theta 0 7 deg 0 7 deg 0 7 deg Notes: 7. All dimensions arein millimeters. 2. BSCBasic Spacing between Centers. 48Preliminary54SX Family FPGAs Package Mechanical Drawings (continued) Ball Grid Array (PBGA) Top View Pe D < D1 > Y Side View y Y L [ l A ed * a2 At Bottom View 313 PBGA vt (dia.) e \ enon O 6 PP C5Po O GP 666? 0.00.00, 0 0.0, 07> O_O _ 0 _ O; O O O O O O O 0. of. of O. o. O O O O sl oe OOP 0000 07200000 0500050050-00050-050 000986 %6 0.0.0.0 0.0 0.0.0.0 C0000 000C0C00M O O O O O O O O O O70 2060005050405 05 00 4 0-000"0 00"0'00'000 | 12345 6 7 8 9 1011121314 15 16 17 1819 20 21 22 23 24 25 pwoumnOrtexrzz0uD4C< SKB Pin One Corner 49(el Preliminary Plastic Ball Grid Array (PBGA) PBGA 313 JEDEC Equivalent MO-151 Dimension Min. Nom. Max. A2 1.12 1.22 Al 0.50 0.60 0.70 c 0.56 REF. A 2.12 2.33 2.52 D/E 34.80 35.00 35.20 D1/E1 29.50 30.00 30.70 e 1.27 BSC r (diameter) 0.60 0.76 0.90 Notes: 7. All dimensions arein millimeters. 2. BSCBasic Spacing between Centers. 50Preliminary54SX Family FPGAs 51(el Preliminary 52Preliminary54SX Family FPGAs 53(el Preliminary 54Preliminary54SX Family FPGAs 55Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. ICTS] Take it to a higher level. http:/Awww.actel.com Actel Europe Ltd. Actel Corporation Actel Asia-Pacific Daneshill House, Lutyens Close 955 East Arques Avenue EXOS Ebisu Bldg. 4F Basingstoke, Hampshire RG24 8AG Sunnyvale, California 94086 1-24-14 Ebisu Shibuya-ku United Kingdom USA Tokyo 150 Japan Tel: +44.(0)1256.305600 Tel: 408.739.1010 Tel: +81.(0)3.3445.7671 Fax: +44.(0)1256.355420 Fax: 408.739.1540 Fax: +81.(0)3.3445.7668 5172137-1/9.98