CAT28C16AGI-90T - ON Semiconductor

October, 2009 − Rev. 6

1Publication Order Number:

CAT28C16A/D

CAT28C16A

16 kb CMOS Parallel

EEPROM

Description

The CAT28C16A is a fast, low power, 5V−only CMOS Parallel

EEPROM organized as 2K x 8−bits. It requires a simple interface for

in−system programming. On−chip address and data latches,

self−timed write cycle with auto−clear and VCC power up/down write

protection eliminate additional timing and protection hardware. DATA

Polling signals the start and end of the self−timed write cycle.

Additionally, the CAT28C16A features hardware write protection.

The CAT28C16A is manufactured using ON Semiconductor’s

advanced CMOS floating gate technology. It is designed to endure

100,000 program/erase cycles and has a data retention of 100 years.

The device is available in JEDEC approved 24−pin DIP and SOIC or

32−pin PLCC packages.

Features

•Fast Read Access Times: 90 ns, 120 ns, 200 ns

•Low Power CMOS Dissipation:

– Active: 25 mA Max.

– Standby: 100 mA Max.

•Simple Write Operation:

– On−chip Address and Data Latches

– Self−timed Write Cycle with Auto−clear

•Fast Write Cycle Time: 10 ms Max

•End of Write Detection: DATA Polling

•Hardware Write Protection

•CMOS and TTL Compatible I/O

•100,000 Program/Erase Cycles

•100 Year Data Retention

•Commercial, Industrial and Automotive Temperature Ranges

PIN CONFIGURATION

TOP VIEW

PLCC Package (N, G)

DIP Package (L)

SOIC Package (J, K, W, X)

VCC

A10

I/O7

I/O6

I/O5

I/O4

I/O3

I/O0

I/O1

I/O2

VSS

14 15 16 17 18 19 20

4 3 2 1 32 31 30

A10

I/O7

I/O6

VCC

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

VSS

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See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

PDIP−24

L SUFFIX

CASE 646AD

PLCC−32

N, G SUFFIX

CASE 776AK

Address InputsA0−A10

Data Inputs/OutputsI/O0−I/O7

Chip EnableCE

Output EnableOE

Write EnableWE

5 V SupplyVCC

FunctionPin Name

PIN FUNCTION

SOIC−24

J, K, W, X SUFFIX

CASE 751BK

GroundVSS

No ConnectNC

CAT28C16A

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Figure 1. Block Diagram

ADDR. BUFFER

& LATCHES

ADDR. BUFFER

& LATCHES

INADVERTENT

CONTROL

LOGIC

TIMER

HIGH VOLTAGE

GENERATOR

I/O BUFFERS

2,048 x 8

EEPROM

ARRAY

VCC

A0−A3

A4−A10

WRITE

PROTECTION

COLUMN

DECODER

ROW

DECODER

DATA POLLING

I/O0−I/O7

Table 1. MODE SELECTION

Mode CE WE OE I/O Power

Read L H L DOUT ACTIVE

Byte Write (WE Controlled) L H DIN ACTIVE

Byte Write (CE Controlled) L H DIN ACTIVE

Standby, and Write Inhibit H X X High−Z STANDBY

Read and Write Inhibit X H H High−Z ACTIVE

Table 2. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V)

Symbol Test Max Conditions Units

CI/O (Note 1) Input/Output Capacitance 10 VI/O = 0 V pF

CIN (Note 1) Input Capacitance 6 VIN = 0 V pF

1. This parameter is tested initially and after a design or process change that affects the parameter.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameters Ratings Units

Temperature Under Bias –55 to +125 °C

Storage Temperature –65 to +150 °C

Voltage on Any Pin with Respect to Ground (Note 2) –2.0 V to +VCC + 2.0 V V

VCC with Respect to Ground −2.0 to +7.0 V

Package Power Dissipation Capability (TA = 25°C) 1.0 W

Lead Soldering Temperature (10 secs) 300 °C

Output Short Circuit Current (Note 3) 100 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

CAT28C16A

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Table 4. RELIABILITY CHARACTERISTICS (Note 4)

Symbol Parameter Min Max Units

NEND (Note 5) Endurance 100,000 Cycles/Byte

TDR (Notes 5) Data Retention 100 Years

VZAP ESD Susceptibility 2,000 V

ILTH (Note 6) Latch−Up 100 mA

4. This parameter is tested initially and after a design or process change that affects the parameter.

5. For the CAT28C16A−20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years.

6. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V.

Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 5 V ±10%, unless otherwise specified.)

Symbol Parameter Test Conditions

Limits

Units

Min Typ Max

ICC VCC Current (Operating, TTL) CE = OE = VIL,

f = 1/tRC min, All I/O’s Open

35 mA

ICCC (Note 7) VCC Current (Operating, CMOS) CE = OE = VILC,

f = 1/tRC min, All I/O’s Open

25 mA

ISB VCC Current (Standby, TTL) CE = VIH, All I/O’s Open 1 mA

ISBC (Note 8) VCC Current (Standby, CMOS) CE = VIHC, All I/O’s Open 100 mA

ILI Input Leakage Current VIN = GND to VCC −10 10 mA

ILO Output Leakage Current VOUT = GND to VCC,

CE = VIH

−10 10 mA

VIH (Note 8) High Level Input Voltage 2 VCC + 0.3 V

VIL (Note 7) Low Level Input Voltage −0.3 0.8 V

VOH High Level Output Voltage IOH = −400 mA2.4 V

VOL Low Level Output Voltage IOL = 2.1 mA 0.4 V

VWI Write Inhibit Voltage 3.0 V

7. VILC = −0.3 V to +0.3 V

8. VIHC = VCC − 0.3 V to VCC + 0.3 V

Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 5 V ±10%, unless otherwise specified.)

Symbol Parameter

28C16A−90 28C16A−12 28C16A−20

Units

Min Max Min Max Min Max

tRC Read Cycle Time 90 120 200 ns

tCE CE Access Time 90 120 200 ns

tAA Address Access Time 90 120 200 ns

tOE OE Access Time 50 60 80 ns

tLZ (Note 9) CE Low to Active Output 0 0 0 ns

tOLZ (Note 9) OE Low to Active Output 0 0 0 ns

tHZ (Notes 9, 10) CE High to High−Z Output 50 50 55 ns

tOHZ (Notes 9,

10)

OE High to High−Z Output 50 50 55 ns

tOH (Note 9) Output Hold from Address Change 0 0 0 ns

9. This parameter is tested initially and after a design or process change that affects the parameter.

10.Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.

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Figure 2. A.C. Testing Input/Output Waveform (Note 11)

INPUT PULSE LEVELS REFERENCE POINTS

2.0 V

0.8 V

2.4 V

0.45 V

11. Input rise and fall times (10% and 90%) < 10 ns.

Figure 3. A.C. Testing Load Circuit (example)

1.3V

DEVICE

UNDER

TEST

1N914

3.3K

OUT

CL = 100 pF

CL INCLUDES JIG CAPACITANCE

Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 5 V ±10%, unless otherwise specified.)

Symbol Parameter

28C16A−90 28C16A−12 28C16A−20

Units

Min Max Min Max Min Max

tWC Write Cycle Time 5 5 10 ms

tAS Address Setup Time 0 0 10 ns

tAH Address Hold Time 100 100 100 ns

tCS CE Setup Time 0 0 0 ns

tCH CE Hold Time 0 0 0 ns

tCW (Note 12) CE Pulse Time 110 110 150 ns

tOES OE Setup Time 0 0 15 ns

tOEH OE Hold Time 0 0 15 ns

tWP (Note 12) WE Pulse Width 110 110 150 ns

tDS Data Setup Time 60 60 50 ns

tDH Data Hold Time 0 0 10 ns

tDL Data Latch Time 5 10 5 10 50 ns

tINIT (Note 13) Write Inhibit Period After Power−up 0.05 100 0.05 100 5 20 ms

12.A write pulse of less than 20 ns duration will not initiate a write cycle.

13.This parameter is tested initially and after a design or process change that affects the parameter.

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DEVICE OPERATION

Read

Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The

data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to

eliminate bus contention in a system environment.

Figure 4. Read Cycle

ADDRESS

DATA OUT DATA VALIDDATA VALID

HIGH−Z

tOHZ

tHZ

tAA

tOH

tOE

tOLZ

tCE

tLZ

tRC

VIH

Figure 5. Byte Write Cycle [WE Controlled]

ADDRESS

DATA OUT

DATA IN DATA VALID

HIGH−Z

tAH

tAS

tCS tCH

tWP

tOES tOEH

tDL

tDS tDH

tWC

Byte Write

A write cycle is executed when both CE and WE are low,

and OE is high. Write cycles can be initiated using either WE

or CE, with the address input being latched on the falling

edge of WE or CE, whichever occurs last. Data, conversely,

is latched on the rising edge of WE or CE, whichever occurs

first. Once initiated, a byte write cycle automatically erases

the addressed byte and the new data is written within 10 ms.

CAT28C16A

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DATA Polling

DATA polling is provided to indicate the completion of a

byte write cycle. Once a byte write cycle is initiated,

attempting to read the last byte written will output the

complement of that data on I/O7 (I/O0–I/O6 are

indeterminate) until the programming cycle is complete.

Upon completion of the self−timed byte write cycle, all I/O’s

will output true data during a read cycle.

Figure 6. Byte Write Cycle [CE Controlled]

ADDRESS

DATA OUT

DATA IN DATA VALID

HIGH−Z

tAS tAH

tCS

tOES

tCW

tOEH

tCH

tDL

tDS tDH

tWC

Figure 7. DATA Polling

ADDRESS

I/O7

DIN = X DOUT = X DOUT = X

tOEH tOE

tWC

tOES

Hardware Data Protection

The following is a list of hardware data protection features

that are incorporated into the CAT28C16A.

1. VCC sense provides for write protection when VCC

falls below 3.0 V min.

2. A power on delay mechanism, tINIT (see AC

characteristics), provides a 5 to 20 ms delay before

a write sequence, after VCC has reached 3.0 V

min.

3. Write inhibit is activated by holding any one of

OE low, CE high or WE high.

4. Noise pulses of less than 20 ns on the WE or CE

inputs will not result in a write cycle.

CAT28C16A

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PACKAGE DIMENSIONS

PLCC 32

CASE 776AK−01

ISSUE O

E1 E2E

PIN#1 IDENTIFICATION

SIDE VIEW

TOP VIEW END VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-016.

SYMBOL MIN NOM MAX

2.54

0.33

0.66

12.32

12.10

11.36

9.56

14.86

0.38

2.80

0.54

0.82

12.57

13.86

11.50

11.32

15.11

1.27 BSC

13.90 14.04

CAT28C16A

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PACKAGE DIMENSIONS

SOIC−24, 300 mils

CASE 751BK−01

ISSUE O

E1 E

PIN#1 IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-013.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.31

0.20

0.25

15.20

10.11

7.34

1.27 BSC

2.65

0.30

0.51

0.33

0.75

15.40

10.51

7.60

L0.40 1.27

2.35

A2 2.05 2.55

θ1 5º 15º

CAT28C16A

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PACKAGE DIMENSIONS

PDIP−24, 600 mils

CASE 646AD−01

ISSUE A

ebb1 eB

SIDE VIEW

TOP VIEW

END VIEW

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-011.

A2 A

A1 L

SYMBOL MIN NOM MAX

0.39

3.18

0.36

12.32

0.77

0.21

31.50

2.54 BSC

6.35

4.95

0.55

14.73

1.77

0.38

32.25

eB 15.24 17.78

E 15.24 15.87

2.93 5.08

CAT28C16A

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Example of Ordering Information

Prefix Device # Suffix

Company ID

CAT 28C16A N

Product Number

28C16A

I− 20 T

Package

Blank = Commercial (0°C to +70°C)

I = Industrial (−40°C to +85°C)

A = Automotive (−40°C to +105°C)

Temperature Range

N: PLCC

J: SOIC (JEDEC)

K: SOIC (EIAJ)

L: PDIP (Lead Free, Halogen Free)

G: PLCC (Lead Free, Halogen Free)

W: SOIC (JEDEC) (Lead Free, Halogen Free)

X: SOIC (EIAJ) (Lead Free, Halogen Free)

T: Tape & Reel

Speed

−90: 90 ns

−12: 120 ns

−20: 200 ns

Tape & Reel (Note 15)

(Optional)

14.The device used in the above example is a CAT28C16ANI−20T (PLCC, Industrial Temperature, 200 ns Access Time, Tape & Reel).

15.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

CAT28C16A/D

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