TLV320AIC23B-Q1
Stereo Audio Codec, 8- to 96-kHz, With Integrated
Headphone Amplifier
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SGLS240C
March 2004–Revised June 2012
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone
Amplifier
Check for Samples: TLV320AIC23B-Q1
1 1 Introduction
1.1 Features
1
• Qualified for Automotive Applications • Integrated Total Electret-Microphone Biasing
and Buffering Solution
• High-Performance Stereo Codec – Low-Noise MICBIAS pin at 3/4 AVDD for
– 90-dB SNR Multibit Sigma-Delta ADC (A- Biasing of Electret Capsules
weighted at 48 kHz) – Integrated Buffer Amplifier With Tunable
– 100-dB SNR Multibit Sigma-Delta DAC (A- Fixed Gain of 1 to 5
weighted at 48 kHz) – Additional Control-Register Selectable Buffer
– 1.42 V – 3.6 V Core Digital Supply: Gain of 0 dB or 20 dB
Compatible With TI C54x DSP Core Voltages • Stereo-Line Inputs
– 2.7 V – 3.6 V Buffer and Analog Supply:
Compatible Both TI C54x DSP Buffer – Integrated Programmable Gain Amplifier
Voltages – Analog Bypass Path of Codec
– 8-kHz – 96-kHz Sampling-Frequency Support • ADC Multiplexed Input for Stereo-Line Inputs
• Software Control Via TI McBSP-Compatible and Microphone
Multiprotocol Serial Port • Stereo-Line Outputs
– 2-wire-Compatible and SPI-Compatible – Analog Stereo Mixer for DAC and Analog
Serial-Port Protocols Bypass Path
– Glueless Interface to TI McBSPs • Volume Control With Mute on Input and Output
• Audio-Data Input/Output Via TI McBSP- • Highly Efficient Linear Headphone Amplifier
Compatible Programmable Audio Interface – 30 mW into 32 ΩFrom a 3.3-V Analog Supply
– I2S-Compatible Interface Requiring Only One Voltage
McBSP for both ADC and DAC • Flexible Power Management Under Total
– Standard I2S, MSB, or LSB Justified-Data Software Control
Transfers – 23-mW Power Consumption During Playback
– 16/20/24/32-Bit Word Lengths Mode
– Audio Master/Slave Timing Capability – Standby Power Consumption < 150 µW
Optimized for TI DSPs (250/272 fs), USB – Power-Down Power Consumption < 15 µW
mode • 28-Pin TSSOP (62 mm2Total Board Area)
– Industry-Standard Master/Slave Support • Ideally Suitable for Portable Solid-State Audio
Provided Also (256/384 fs), Normal mode Players and Recorders
– Glueless Interface to TI McBSPs
1.2 Description
The TLV320AIC23B-Q1 is a high-performance stereo audio codec with highly integrated analog
functionality. The analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) within the
TLV320AIC23B-Q1 use multibit sigma-delta technology with integrated oversampling digital interpolation
filters. Data-transfer word lengths of 16, 20, 24, and 32 bits, with sample rates from 8 kHz to 96 kHz, are
supported. The ADC sigma-delta modulator features third-order multibit architecture with up to 90-dBA
signal-to-noise ratio (SNR) at audio sampling rates up to 96 kHz, enabling high-fidelity audio recording in a
compact, power-saving design. The DAC sigma-delta modulator features a second-order multibit
architecture with up to 100-dBA SNR at audio sampling rates up to 96 kHz, enabling high-quality digital
audio-playback capability, while consuming less than 23 mW during playback only. The TLV320AIC23B-
Q1 is the ideal analog input/output (I/O) choice for portable digital audio-player and recorder applications,
such as MP3 digital audio players.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2004–2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
Integrated analog features consist of stereo-line inputs with an analog bypass path, a stereo headphone
amplifier, with analog volume control and mute, and a complete electret-microphone-capsule biasing and
buffering solution. The headphone amplifier is capable of delivering 30 mW per channel into 32 Ω. The
analog bypass path allows use of the stereo-line inputs and the headphone amplifier with analog volume
control, while completely bypassing the codec, thus enabling further design flexibility, such as integrated
FM tuners. A microphone bias-voltage output provides a low-noise current source for electret-capsule
biasing. The AIC23B has an integrated adjustable microphone amplifier (gain adjustable from 1 to 5) and
a programmable gain microphone amplifier (0 dB or 20 dB). The microphone signal can be mixed with the
output signals if a sidetone is required.
While the TLV320AIC23B-Q1 supports the industry-standard oversampling rates of 256 fsand 384 fs,
unique oversampling rates of 250 fsand 272 fsare provided, which optimize interface considerations in
designs using TI C54x digital signal processors (DSPs) and universal serial bus (USB) data interfaces. A
single 12-MHz crystal can supply clocking to the DSP, USB, and codec. The TLV320AIC23B-Q1 features
an internal oscillator that, when connected to a 12-MHz external crystal, provides a system clock to the
DSP and other peripherals at either 12 MHz or 6 MHz, using an internal clock buffer and selectable
divider. Audio sample rates of 48 kHz and compact-disc (CD) standard 44.1 kHz are supported directly
from a 12-MHz master clock with 250 fsand 272 fsoversampling rates.
Low power consumption and flexible power management allow selective shutdown of codec functions,
thus extending battery life in portable applications. This design solution makes powerful portable stereo
audio designs easily realizable in a cost-effective, space-saving total analog I/O solution: the
TLV320AIC23B-Q1.
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Σ
Σ−∆
DAC
Σ
OSC
SDIN
SCLK
MODE
DVDD
BVDD
DGND
LRCIN
DIN
LRCOUT
DOUT
BCLK
B0486-01
AVDD
VMID
AGND
RLINEIN
LLINEIN
HPVDD
HPGND
RHPOUT
ROUT
LOUT
LHPOUT
XTI/MCLK
XTO
CLKOUT
1.0X
1.0X
VADC
VMID
50 kΩ
VDAC
Σ−∆
ADC
VMID
50 kΩ
10 kΩ
VADC
1.0X
1.5X
VDAC
MICBIAS
MICIN
Sidetone
Mute
NOTE: MCLK, BCLK, and SCLK are all asynchronous to each other.
50 kΩ
DSPcodec
TLV320AIC23B
Mute,
0 dB, 20 dB
Bypass
Mute
Line
Mute
2:1
MUX
Σ−∆
ADC
12 to 34.5 dB,
1.5-dB Steps
–
CS
Control
Interface
12 to 34 dB,
1.5-dB Steps
–
6 to 73 dB,
1-dB Steps
–
Σ−∆
DAC
Bypass
Mute
6 to 73 dB,
1-dB Steps
–
Headphone
Driver
Headphone
Driver
CLKIN
Divider
(1x, x)½
CLKOUT
Divider
(1x, x)½
Digital
Audio
Interface
Digital
Filters
2:1
MUX
Line
Mute
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1.3 Functional Block Diagram
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1
2
3
4
5
6
7
11
8
12
9
13
10
14
21
28
27
26
25
24
23
22
18
17
20
16
19
15
BVDD
CLKOUT
BCLK
DIN
LRCIN
DOUT
LRCOUT
HPGND
HPVDD
LOUT
LHPOUT
ROUT
RHPOUT
AVDD
DGND
DVDD
XTO
XTI/MCLK
SCLK
SDIN
MODE
MICIN
CS
MICBIAS
LLINEIN
VMID
RLINEIN
AGND
P0043-05
PW Package
(Top View)
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1.4 Pin Assignments
1.5 Ordering Information
TAPACKAGE REEL ORDERABLE PART NUMBER TOP-SIDE MARKING
−40°C to 85°C TSSOP 2000 TLV320AIC23BIPWRQ1 AIC23BIQ1
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1.6 Pin Functions
Table 1-1. Pin Functions
PIN I/O DESCRIPTION
NAME NO.
AGND 15 Analog supply return
AVDD 14 Analog supply input. Voltage level is 3.3 V nominal.
I2S serial-bit clock. In audio master mode, the AIC23B generates this signal and sends it to the DSP. In
BCLK 3 I/O audio slave mode, the signal is generated by the DSP.
BVDD 1 Buffer supply input. Voltage range is from 2.7 V to 3.6 V.
Clock output. This is a buffered version of the XTI input and is available in 1X or 1/2X frequencies of
CLKOUT 2 O XTI. Bit 07 in the sample rate control register controls frequency selection.
Control port input latch/address select. For SPI control mode this input acts as the data latch control.
CS 21 I For 2-wire control mode this input defines the seventh bit in the device address field. See Section 3.1 for
details.
DIN 4 I I2S format serial data input to the sigma-delta stereo DAC
DGND 28 Digital supply return
DOUT 6 O I2S format serial data output from the sigma-delta stereo ADC
DVDD 27 Digital supply input. Voltage range is 1.4 V to 3.6 V.
HPGND 11 Analog headphone amplifier supply return
HPVDD 8 Analog headphone amplifier supply input. Voltage level is 3.3 V nominal.
Left stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of
LHPOUT 9 O –73 dB to 6 dB is provided in 1-dB steps.
Left stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
LLINEIN 20 I provided in 1.5-dB steps.
LOUT 12 O Left stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
I2S DAC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends
LRCIN 5 I/O it to the DSP. In audio slave mode, the signal is generated by the DSP.
I2S ADC-word clock signal. In audio master mode, the AIC23B generates this framing signal and sends
LRCOUT 7 I/O it to the DSP. In audio slave mode, the signal is generated by the DSP.
Buffered low-noise-voltage output suitable for electret-microphone-capsule biasing. Voltage level is 3/4
MICBIAS 17 O AVDD nominal.
Buffered amplifier input suitable for use with electret-microphone capsules. Without external resistors a
MICIN 18 I default gain of 5 is provided. See Section 2.3.1.2 for details.
MODE 22 I Serial-interface-mode input. See Section 3.1 for details.
NC Not Used—No internal connection
Right stereo mixer-channel amplified headphone output. Nominal 0-dB output level is 1 VRMS. Gain of
RHPOUT 10 O −73 dB to 6 dB is provided in 1-dB steps.
Right stereo-line input channel. Nominal 0-dB input level is 1 VRMS. Gain of –34.5 dB to 12 dB is
RLINEIN 19 I provided in 1.5-dB steps.
ROUT 13 O Right stereo mixer-channel line output. Nominal output level is 1.0 VRMS.
Control-port serial-data clock. For SPI and 2-wire control modes this is the serial-clock input. See
SCLK 24 I Section 3.1 for details.
Control-port serial-data input. For SPI and 2-wire control modes this is the serial-data input and also is
SDIN 23 I used to select the control protocol after reset. See Section 3.1 for details.
Midrail voltage decoupling input. 10-μF and 0.1-μF capacitors should be connected in parallel to this
VMID 16 I terminal for noise filtering. Voltage level is 1/2 AVDD nominal.
XTI/MCLK 25 I Crystal or external-clock input. Used for derivation of all internal clocks on the AIC23B.
Crystal output. Connect to external crystal for applications where the AIC23B is the audio timing master.
XTO 26 O Not used in applications where external clock source is used.
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2 Electrical Specifications
2.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
AVDD to AGND, DVDD to DGND,
Supply voltage range(2) –0.3 to 3.63 V
BVDD to DGND, HPVDD to HPGND
Analog supply return to digital supply return AGND to DGND –0.3 to 3 .63 V
Digital –0.3 to DVDD V
Input voltage range, all input signals Analog –0.3 to AVDD V
Case temperature for 10 seconds 240 °C
Operating free-air temperature range: Industrial, TA–40 to 85 °C
Storage temperature range, Tstg –65 to 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) DVDD may not exceed BVDD 0.3 V; BVDD may not exceed AVDD 0.3 V or HPVDD 0.3.
2.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
Analog supply voltage, AVDD, HPVDD (1) 2.7 3.3 3.6 V
Digital buffer supply voltage, BVDD (1) 2.7 3.3 3.6 V
Digital core supply voltage, DVDD(1) 1.42 1.5 3.6 V
Analog input voltage, full scale −0 dB (AVDD = 3.3 V) 1 VRMS
Stereo-line output load resistance 10 kΩ
Headphone-amplifier output load resistance 0 Ω
CLKOUT digital output load capacitance 20 pF
All other digital output load capacitance 10 pF
Stereo-line output load capacitance 50 pF
XTI master clock Input 18.43 MHz
ADC or DAC conversion rate 96 kHz
Operating free-air temperature, TAIndustrial –40 85 °C
(1) Digital voltage values are with respect to DGND; analog voltage values are with respect to AGND.
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2.3 Electrical Characteristics
over recommended operating conditions, AVDD, HPVDD, BVDD = 3.3 V, DVDD = 1.5 V, slave mode, XTI/MCLK = 256 fs, fs= 48
kHz (unless otherwise stated)
2.3.1 ADC
2.3.1.1 Line Input to ADC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1 VRMS
fs= 48 kHz (3.3 V) 85 90
Signal-to-noise ratio, A-weighted, 0-dB gain (1)(2) dB
fs= 48 kHz (2.7 V) 90
AVDD = 3.3 V 85 90
Dynamic range, A-weighted, –60-dB full-scale input (2) dB
AVDD = 2.7 V 90
AVDD = 3.3 V –80
Total harmonic distortion, –1-dB input, 0-dB gain dB
AVDD = 2.7 V 80
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
ADC channel separation 1 kHz input tone 90 dB
Programmable gain 1 kHz input tone, RSOURCE < 50 Ω–34.5 12 dB
Programmable gain step size Monotonic 1.5 dB
Mute attenuation 0 dB, 1 kHz input tone 80 dB
12 dB input gain 10 20
Input resistance kΩ
0 dB input gain 28 35
Input capacitance 10 pF
(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.1.2 Microphone Input to ADC
0-dB Gain, fs= 8 kHz (40-KΩsource impedance, see Section 1.3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input signal level (0 dB) 1 VRMS
AVDD = 3.3 V 77 85
Signal-to-noise ratio, A-weighted, 0-dB gain(1)(2) dB
AVDD = 2.7 V 84
AVDD = 3.3 V 77 85
Dynamic range, A-weighted, –60-dB full-scale input(2) dB
AVDD = 2.7 V 84
AVDD = 3.3 V –60
Total harmonic distortion, –1-dB input, 0-dB gain dB
AVDD = 2.7 V –60
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain boost 1 kHz input tone, RSOURCE < 50 Ω20 dB
Microphone-path gain MICBOOST = 0, RSOURCE < 50 Ω14 dB
Mute attenuation 0 dB, 1 kHz input tone 60 80 dB
Input resistance 8 14 kΩ
Input capacitance 10 pF
(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
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2.3.1.3 Microphone Bias
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bias voltage 3/4 AVDD −100 m 3/4 AVDD 3/4 AVDD + 100 m V
Bias-current source 3 mA
Output noise voltage 1 kHz to 20 kHz 25 nV/√Hz
2.3.2 DAC
Line output, load = 10 kΩ, 50 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage (FFFFFF) 1 VRMS
AVDD = 3.3 V fs= 48kHz 90 100
Signal-to-noise ratio, A-weighted, 0-dB gain(1)(2)(3) dB
AVDD = 2.7 V fs= 48 kHz 100
AVDD = 3.3 V 85 90
Dynamic range, A-weighted(2) dB
AVDD = 2.7 V TBD
1 kHz, 0 dB –88 –80
AVDD = 3.3 V dB
1 kHz, –3 dB –92 –86
Total harmonic distortion 1 kHz, 0 dB –85
AVDD = 2.7 V dB
1 kHz, –3 dB –88
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation 100 dB
(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Ratio of output level with 1-kHz full-scale input, to the output level with all zeros into the digital input, measured A-weighted over a 20-Hz
to 20-kHz bandwidth.
2.3.3 Analog Line Input to Line Output (Bypass)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1 VRMS
AVDD = 3.3 V 90 95
Signal-to-noise ratio, A-weighted, 0-dB gain(1)(2) dB
AVDD = 2.7 V 95
1 kHz, 0 dB –86 –80
AVDD = 3.3 V dB
1 kHz, –3 dB –92 –86
Total harmonic distortion 1 kHz, 0 dB –86
AVDD = 2.7 V dB
1 kHz, –3 dB –92
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
DAC channel separation (left to right) 1 kHz, 0 dB 80 dB
(1) Ratio of output level with 1-kHz full-scale input, to the output level with the input short circuited, measured A-weighted over a 20-Hz to
20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
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2.3.4 Stereo Headphone Output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0-dB full-scale output voltage 1 VRMS
RL = 32 Ω30
Maximum output power, POmW
RL = 16 Ω40
Signal-to-noise ratio, A-weighted (1) AVDD = 3.3 V 88 97 dB
PO = 10 mW 0.1
AVDD = 3.3 V,
Total harmonic distortion %
1 kHz output PO = 20 mW 1
Power supply rejection ratio 1 kHz, 100 mVpp 50 dB
Programmable gain 1 kHz output −73 6 dB
Programmable-gain step size 1 dB
Mute attenuation 1 kHz output 80 dB
(1) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter results in
higher THD + N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes
out-of-band noise, which, although not audible, may affect dynamic specification values.
2.3.5 Analog Reference Levels
PARAMETER MIN TYP MAX UNIT
Reference voltage AVDD/2 −50 mV AVDD/2 + 50 mV V
Divider resistance 40 50 60 kΩ
2.3.6 Digital I/O
PARAMETER MIN TYP MAX UNIT
VIL Input low level 0.3 × BVDD V
VIH Input high level 0.7 × BVDD V
VOL Output low level 0.1 × BVDD V
VOH Output high level 0.9 × BVDD V
2.3.7 Supply Current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Record and playback (all active) 20 24 26
Record and playback (osc, clk, and MIC output powered down) 16 18 20
Line playback only 6 7.5 9
Total supply current, Record only 11 13.5 15 mA
No input signal ITOT Analog bypass (line in to line out) 4 4.5 6
Power down, DVDD = 1.5 V, Oscillator enabled 0.8 1.5 3
AVDD Oscillator disabled 0.01
= BVDD = HPVDD = 3.3 V
2.4 Digital-Interface Timing
PARAMETER MIN TYP MAX UNIT
tw(1) High 18 ns
System-clock pulse duration, MCLK/XTI
tw(2) Low 18
tc(1) System-clock period, MCLK/XTI 54 ns
Duty cycle, MCLK/XTI 40/60 60/40 %
tpd(1) Propagation delay, CLKOUT 0 10 ns
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BCLK
LRCIN
DIN
DOUT
LRCOUT
tsu(1) th(1)
tpd(2)
tpd(3)
T0548-01
tpd(1)
MCLK/XTI
CLKOUT
CLKOUT
(Div 2)
tc(1)
tw(1) tw(2)
T0547-01
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Figure 2-1. System-Clock Timing Requirements
2.4.1 Audio Interface (Master Mode)
PARAMETER MIN TYP MAX UNIT
tpd(2) Propagation delay, LRCIN/LRCOUT 0 10 ns
tpd(3) Propagation delay, DOUT 0 10 ns
tsu(1) Setup time, DIN 10 ns
th(1) Hold time, DIN 10 ns
Figure 2-2. Master-Mode Timing Requirements
2.4.2 Audio Interface (Slave-Mode)
PARAMETER MIN TYP MAX UNIT
tw(3) High 20
Pulse duration, BCLK ns
tw(4) Low 20
tc(2) Clock period, BCLK 50 ns
tpd(4) Propagation delay, DOUT 0 10 ns
tsu(2) Setup time, DIN 10 ns
th(2) Hold time, DIN 10 ns
tsu(3) Setup time, LRCIN 10 ns
th(3) Hold time, LRCIN 10 ns
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LSB
tw(8)
tw(5) tw(6)
tc(3)
tsu(5)
tsu(4)
th(4)
CS
SCLK
DIN
T0550-01
BCLK
LRCIN
DIN
DOUT
LRCOUT
tc(2)
tw(4) tw(3)
tsu(2) th(3)
th(2)
tsu(3)
tpd(2)
T0549-01
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Figure 2-3. Slave-Mode Timing Requirements
2.4.3 3-Wire Control Interface (SDIN)
PARAMETER MIN TYP MAX UNIT
tw(5) High 20
Clock pulse duration, SCLK ns
tw(6) Low 20
tc(3) Clock period, SCLK 80 ns
tsu(4) Clock rising edge to CS rising edge, SCLK 60 ns
tsu(5) Setup time, SDIN to SCLK 20 ns
th(4) Hold time, SCLK to SDIN 20 ns
tw(7) High 20
Pulse duration, CS ns
tw(8) Low 20
Figure 2-4. 3-Wire Control Interface Timing Requirements
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SCLK
DIN
tw(9) tw(10) tsp
th(5) th(6) tsu(7) tsu(8)
T0551-01
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2.4.4 2-Wire Control Interface
PARAMETER MIN TYP MAX UNIT
tw(9) High 1.3 µs
Clock pulse duration, SCLK
tw(10) Low 600 ns
f(sf) Clock frequency, SCLK 0 400 kHz
th(5) Hold time (start condition) 600 ns
tsu(6) Setup time (start condition) 600 ns
th(6) Data hold time 900 ns
tsu(7) Data setup time 100 ns
tr Rise time, SDIN, SCLK 300 ns
tf Fall time, SDIN, SCLK 300 ns
tsu(8) Setup time (stop condition) 600 ns
tsp Pulse width of spikes suppressed by input filter 0 50 ns
Figure 2-5. 2-Wire Control Interface Timing Requirements
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MSB LSB
CS
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SCLK
SDIN
T0552-01
TLV320AIC23B-Q1
SGLS240C –MARCH 2004–REVISED JUNE 2012
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3 How to Use the TLV320AIC23B-Q1
3.1 Control Interfaces
The TLV320AIC23B-Q1 has many programmable features. The control interface is used to program the
registers of the device. The control interface complies with SPI (3-wire operation) and 2-wire operation
specifications. The state of the MODE terminal selects the control interface type. The MODE pin must be
hardwired to the required level.
MODE INTERFACE
0 2-wire
1 SPI
3.1.1 SPI
In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320AIC23B-Q1. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of
SCLK. A rising edge on CS after the 16th rising clock edge latches the data word into the AIC (see
Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data
block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
Figure 3-1. SPI Timing
3.1.2 2-Wire
In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start
condition is a falling edge on SDIN while SCLK is high. The seven bits following the start condition
determine which device on the 2-wire bus receives the data. R/W determines the direction of the data
transfer. The TLV320AIC23B-Q1 is a write only device and responds only if R/W is 0. The device operates
only as a slave device whose address is selected by setting the state of the CS pin as follows.
CS STATE ADDRESS
(Default = 0)
0 0011010
1 0011011
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The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle,
acknowledging the data transfer. The control follows in the next two eight-bit blocks. The stop condition
after the data transfer is a rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the
data block:
B[15:9] Control Address Bits
B[8:0] Control Data Bits
Figure 3-2. 2-Wire Compatible Timing
3.1.3 Register Map
The TLV320AIC23B-Q1 has the following set of registers, which are used to program the modes of
operation. To minimize corruption and potential noise injection due to improper sequencing, program the
registers while the device is powered down (Register 0x06, value 0x80). After the registers are
programmed, power on the device (Register 0x06, value 0x28).
ADDRESS REGISTER
0000000 Left line input channel volume control
0000001 Right line input channel volume control
0000010 Left channel headphone volume control
0000011 Right channel headphone volume control
0000100 Analog audio path control
0000101 Digital audio path control
0000110 Power down control
0000111 Digital audio interface format
0001000 Sample rate control
0001001 Digital interface activation
0001111 Reset register
Table 3-1. Left Line Input Channel Volume Control (Address: 0000000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LIM X X LIV4 LIV3 LIV2 LIV1 LIV0
Default 0 1 0 0 1 0 1 1 1
LRS Left/right line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LIM Left line input mute 0 = Normal 1 = Muted
LIV[4:0] Left line input volume control (10111 = 0 dB default)
11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
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Table 3-2. Right Line Input Channel Volume Control (Address: 0000001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RIM X X RIV4 RIV3 RIV2 RIV1 RIV0
Default 0 1 0 0 1 0 1 1 1
RLS Right/left line simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
RIM Right line input mute 0 = Normal 1 = Muted
RIV[4:0] Right line input volume control (10111 = 0 dB default)
11111 = 12 dB down to 00000 = –34.5 dB in 1.5-dB steps
X Reserved
Table 3-3. Left Channel Headphone Volume Control (Address: 0000010)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function LRS LZC LHV6 LHV5 LHV4 LHV3 LHV2 LHV1 LHV0
Default 0 1 1 1 1 1 0 0 1
LRS Left/right headphone channel simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
LZC Left channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
LHV[6:0] Left Headphone volume control (1111001 = 0 dB default)
1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), anything below 0110000 does nothing −
you are still muted
Table 3-4. Right Channel Headphone Volume Control (Address: 0000011)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RLS RZC RHV6 RHV5 RHV4 RHV3 RHV2 RHV1 RHV0
Default 0 1 1 1 1 1 0 0 1
LRS Right/left headphone channel simultaneous volume/mute update
Simultaneous update 0 = Disabled 1 = Enabled
RZC Right channel zero-cross detect
Zero-cross detect 0 = Off 1 = On
RHV[6:0] Right headphone volume control (1111001 = 0 dB default)
1111111 = 6 dB, 79 steps between 6 dB and −73 dB (mute), 0110000 = −73 dB (mute), any thing below 0110000 does
nothing −you are still muted
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Table 3-5. Analog Audio Path Control (Address: 0000100)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function STA2 STA1 STA0 STE DAC BYP INSEL MICM MICB
Default 0 0 0 0 1 1 0 1 0
STA[2:0] and STE
STE STA2 STA1 STA0 ADDED SIDETONE
1 1 X X 0 dB
1 0 0 0 -6 dB
1 0 0 1 -9 dB
1 0 1 0 -12 dB
1 0 1 1 -18 dB
0 X X X Disabled
DAC DAC select 0 = DAC off 1 = DAC selected
BYP Bypass 0 = Disabled 1 = Enabled
INSEL Input select for ADC 0 = Line 1 = Microphone
MICM Microphone mute 0 = Normal 1 = Muted
MICB Microphone boost 0 = dB 1 = 20 dB
X Reserved
Table 3-6. Digital Audio Path Control (Address: 0000101)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X X X X DACM DEEMP1 DEEMP0 ADCHP
Default 0 0 0 0 0 0 1 0 0
DACM DAC soft mute 0 = Disabled 1 = Enabled
DEEMP[1:0] De-emphasis control 00 = Disabled 01 = 32 kHz 10 = 44.1 kHz 11 = 48 kHz
ADCHP ADC high-pass filter 1 = Disabled 0 = Enabled
X Reserved
Table 3-7. Power Down Control (Address: 0000110)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X OFF CLK OSC OUT DAC ADC MIC LINE
Default 0 0 0 0 0 0 1 1 1
OFF Device power 0 = On 1 = Off
CLK Clock 0 = On 1 = Off
OSC Oscillator 0 = On 1 = Off
OUT Outputs 0 = On 1 = Off
DAC DAC 0 = On 1 = Off
ADC ADC 0 = On 1 = Off
MIC Microphone input 0 = On 1 = Off
LINE Line input 0 = On 1 = Off
X Reserved
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Table 3-8. Digital Audio Interface Format (Address: 0000111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X X MS LRSWAP LRP IWL1 IWL0 FOR1 FOR0
Default 0 0 0 0 0 0 0 0 1
MS Maser/slave mode 0 = Slave 1 = Master
LRSWAP DAC left/right swap 0 = Disabled 1 = Enabled
LRP DAC left/right phase 0 = Right channel on, LRCIN high
1 = Right channel on, LRCIN low
DSP mode
1 = MSB is available on second BCLK rising edge after LRCIN rising edge
0 = MSB is available on first BCLK rising edge after LRCIN rising edge
IWL[1:0] Input bit length 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = 32 bit
FOR[1:0] Data format 11 = DSP format, frame sync followed by two data words
10 = I2S format, MSB first, left – 1 aligned
01 = MSB first, left aligned
00 = MSB first, right aligned
X Reserved
NOTES: 1. In master mode, the TLV320AIC23B-Q1 supplies the BCLK, LRCOUT, and LRCIN. In slave mode, BCLK, LRCOUT, and
LRCIN are supplied to the TLV320AIC23B-Q1.
2. In normal mode, BCLK = MCLK/4 for all sample rates except for 88.2 kHz and 96 kHz. For 88.2 kHz and 96 kHz sample rate,
BCLK = MCLK.
3. In USB mode, bit BCLK = MCLK
Table 3-9. Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Norma
l
Default 0 0 0 1 0 0 0 0 0
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Section 3.3.2.1 and Section 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs1 = 272 fs
Normal mode: 0 = 256 fs1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
Table 3-10. Digital Interface Activation (Address: 0001001)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X RES RES X X X X X ACT
Default 0 0 0 0 0 0 0 0 0
ACT Activate interface 0 = Inactive 1 = Active
X Reserved
Table 3-11. Reset Register (Address: 0001111)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function RES RES RES RES RES RES RES RES RES
Default 0 0 0 0 0 0 0 0 0
RES Write 000000000 to this register triggers reset
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50 kΩ
10 kΩ
VMID
0 dB/20 dB
To ADC
MICIN
S0527-01
R2
R1
C1
C2 +
CDIN LINEIN
S0526-01
AGND
Where:
R1 = 5 kΩ
R2 = 5 kΩ
C1 = 47 pF
C2 = 470 nF
TLV320AIC23B-Q1
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3.2 Analog Interface
3.2.1 Line Inputs
The TLV320AIC23B-Q1 has line inputs for the left and the right audio channels (RLINEIN and LLINEIN).
Both line inputs have independently programmable volume controls and mutes. Active and passive filters
for the two channels prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-
scale range is 1 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with analog supply voltage
AVDD. To avoid distortions, it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of
software write cycles required. Both channels can be locked to the same value by setting the RLS and
LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to
standby mode, the line inputs are kept biased to VMID using special antithump circuitry. This reduces
audible clicks that otherwise might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 VRMS to avoid clipping, using the circuit
shown in Figure 3-3.
Figure 3-3. Analog Line Input Circuit
R1 and R2 divide the input signal by two, reducing the 2 VRMS from the CD player to the nominal 1 VRMS of
the AIC23B inputs. The C1 filters high-frequency noise, and C2 removes any dc component from the
signal.
3.2.2 Microphone Input
MICIN is a high-impedance, low-capacitance input that is compatible with a wide range of microphones. It
has a programmable volume control and a mute function. Active and passive filters prevent high
frequencies from folding back into the audio band.
The MICIN signal path has two gain stages. The first stage has a nominal gain of G1 = 50 k/10 k = 5. By
adding an external resistor (RMIC) in series with MICIN, the gain of the first stage can be adjusted by G1 =
50 k/(10 k + RMIC). For example, RMIC = 40 k gives a gain of 0 dB. The second stage has a software
programmable gain of 0 dB or 20 dB (see Section 3.1.3).
Figure 3-4. Microphone Input Circuit
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The microphone input is biased internally to VMID. When the line inputs are muted, the MICIN input is
kept biased to VMID using special antithump circuitry. This reduces audible clicks that may otherwise be
heard when reactivating the input.
The MICBIAS output provides a low-noise reference voltage suitable for biasing electret type microphones
and the associated external resistor biasing network. The maximum source current capability is 3 mA.
This limits the smallest value of external biasing resistors that safely can be used.
The MICBIAS output is not active in standby mode.
3.2.3 Line Outputs
The TLV320AIC23B-Q1 has two low-impedance line outputs (LLINEOUT and RLINEOUT) capable of
driving line loads with 10-kΩand 50-pF impedances.
The DAC full-scale output voltage is 1 VRMS at AVDD = 3.3 V. The full-scale range tracks linearly with the
analog supply voltage AVDD. The DAC is connected to the line outputs via a low-pass filter that removes
out-of-band components. No further external filtering is required in most applications.
The DAC outputs, line inputs, and the microphone signal are summed into the line outputs. These sources
can be switched off independently. For example, in bypass mode, the line inputs are routed to the line
outputs, bypassing the ADC and the DAC. If sidetone is enabled, the microphone signal is routed to both
line outputs via a four-step programmable attenuation circuit.
The line outputs are muted by either muting the DAC (analog) or soft muting (digital) and disabling the
bypass and sidetone paths (see Section 3.1.3).
3.2.4 Headphone Output
The TLV320AIC23B-Q1 has stereo headphone outputs (LHPOUT and RHPOUT), and is designed to drive
16-Ωor 32-Ωheadphones. The headphone output includes a high-quality volume control and mute
function.
The headphone volume is logarithmically adjustable from 6 dB to –73 dB in 1-dB steps. Writing 000000 to
the volume-control registers (see Section 3.1.3) mutes the headphone output. When the headphone
output is muted or the device is placed in standby mode, the dc voltage is maintained at the outputs to
prevent audible clicks.
A zero-cross detection circuit is provided under the control of the LZC and RZC bits. If this circuit is
enabled, the volume-control values are updated only when the input signal to the gain stage is close to the
analog ground level.
This minimizes audible clicks as the volume is changed or the device is muted. This circuit has no time-
out, so, if only dc levels are being applied to the gain stage input of more than 20 mV, the gain is not
updated.
The gain is independently programmable on the left and right channels. Both channels can be locked to
the same value by setting the RLS and LRS bits (see Section 3.1.3).
3.2.5 Analog Bypass Mode
The TLV320AIC23B-Q1 includes a bypass mode in which the analog line inputs are directly routed to the
analog line outputs, bypassing the ADC and DAC. This is enabled by selecting the bypass bit in the
analog audio path control register (see Section 3.1.3).
For a true bypass mode, the output from the DAC and the sidetone should be disabled. The line input and
headphone output volume controls and mutes are still operational in bypass mode. Therefore the line
inputs, DAC output, and microphone input can be summed together. The maximum signal at any point in
the bypass path must be no greater than 1 VRMS at AVDD = 3.3 V to avoid clipping and distortion. This
amplitude tracks linearly with AVDD.
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nn−1 0
1 n−1
n
1/fs
100
MSB LSB
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
Left Channel Right Channel
T0554-01
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3.2.6 Sidetone Insertion
The TLV320AIC23B-Q1 has a sidetone insertion made where the microphone input is routed to the line
and headphone outputs. This is useful for telephony and headset applications. The attenuation of the
sidetone signal may be set to −6 dB, −9 dB, −12 dB, −15 dB, or 0 dB, by software selection (see
Section 3.1.3). If this mode is used to sum the microphone input with the DAC output and line inputs, care
must be taken not to exceed signal level to avoid clipping and distortion.
3.3 Digital Audio Interface
3.3.1 Digital Audio-Interface Modes
The TLV320AIC23B-Q1 supports four audio-interface modes.
• Right justified
• Left justified
• I2S mode
• DSP mode
The four modes are MSB first and operate with a variable word width between 16 to 32 bits (except right-
justified mode, which does not support 32 bits).
The digital audio interface consists of clock signal BCLK, data signals DIN and DOUT, and
synchronization signals LRCIN and LRCOUT. BCLK is an output in master mode and an input in slave
mode.
3.3.1.1 Right-Justified Mode
In right-justified mode, the LSB is available on the rising edge of BCLK, preceding a falling edge on LRCIN
or LRCOUT (see Figure 3-5).
Figure 3-5. Right-Justified Mode Timing
3.3.1.2 Left-Justified Mode
In left-justified mode, the MSB is available on the rising edge of BCLK, following a rising edge on LRCIN
or LRCOUT (see Figure 3-6).
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nn−1 0
1 n−1
n10
MSB LSB
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
Left Channel Right Channel
MSB LSB
T0557-01
nn−1 0
1 n−1
n
1/fs
10
MSB LSB
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
Left Channel Right Channel
1BCLK
T0556-01
nn−1 0
1 n−1
n
1/fs
10
MSB LSB
LRCIN/
LRCOUT
BCLK
DIN/
DOUT
Left Channel Right Channel
n
T0555-01
TLV320AIC23B-Q1
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Figure 3-6. Left-Justified Mode Timing
3.3.1.3 I2S Mode
In I2S mode, the MSB is available on the second rising edge of BCLK, after the falling edge on LRCIN or
LRCOUT (see Figure 3-7).
Figure 3-7. I2S Mode Timing
3.3.1.4 DSP Mode
The DSP mode is compatible with the McBSP ports of TI DSPs. LRCIN and LRCOUT must be connected
to the Frame Sync signal of the McBSP. A falling edge on LRCIN or LRCOUT starts the data transfer. The
left-channel data consists of the first data word, which is immediately followed by the right channel data
word (see Figure 3-8). Input word length is defined by the IWL register. Figure 3-8 shows LRP = 1 (default
LRP = 0).
Figure 3-8. DSP Mode Timing
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3.3.2 Audio Sampling Rates
The TLV320AIC23B-Q1 can operate in master or slave clock mode. In the master mode, the
TLV320AIC23B-Q1 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock
signal is compatible with the USB specification. The TLV320AIC23B-Q1 can be used directly in a USB
system.
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings
control the TLV320AIC23B-Q1 clock and sampling rates.
The settings in the sample rate control register control the clock mode and sampling rates.
Table 3-12. Sample Rate Control (Address: 0001000)
BIT D8 D7 D6 D5 D4 D3 D2 D1 D0
Function X CLKOUT CLKIN SR3 SR2 SR1 SR0 BOSR USB/Normal
Default 0 0 0 1 0 0 0 0 0
CLKIN Clock input divider 0 = MCLK 1 = MCLK/2
CLKOUT Clock output divider 0 = MCLK 1 = MCLK/2
SR[3:0] Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
BOSR Base oversampling rate
USB mode: 0 = 250 fs1 = 272 fs
Normal mode: 0 = 256 fs1 = 384 fs
USB/Normal Clock mode select: 0 = Normal 1 = USB
X Reserved
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the
sampling-rate generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT
terminal. By setting CLKIN to 1, the entire codec is clocked with half the frequency, effectively dividing the
resulting sampling rates by two. The following sampling-rate tables are based on CLKIN = MCLK.
3.3.2.1 USB-Mode Sampling Rates (MCLK = 12 MHz)
In the USB mode, the following ADC and DAC sampling rates are available:
SAMPLING RATE(1) SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR
96 96 3 0 1 1 1 0
88.2 88.2 2 1 1 1 1 1
48 48 0 0 0 0 0 0
44.1 44.1 1 1 0 0 0 1
32 32 0 0 1 1 0 0
8.021 8.021 1 1 0 1 1 1
88000110
488000010
44.1 8.021 1 1 0 0 1 1
848000100
8.021 44.1 1 1 0 1 0 1
(1) The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-
kHz, and 88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figure 3-9 through Figure 3-26 for
filter responses.
3.3.2.2 Normal-Mode Sampling Rates
In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are
available:
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MCLK = 12.288 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 0
48 48 1 0 0 0 0 0
32 32 1 0 1 1 0 0
88100110
488100010
848100100
MCLK = 11.2896 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 0
44.1 44.1 1 1 0 0 0 0
8.021 8.021 1 1 0 1 1 0
44.1 8.021 1 1 0 0 1 0
8.021 44.1 1 1 0 1 0 0
MCLK = 18.432 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR
96 96 2 0 1 1 1 1
48 48 1 0 0 0 0 1
32 32 1 0 1 1 0 1
88100111
488100011
848100101
MCLK = 16.9344 MHz
SAMPLING RATE SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz) DAC (kHz) SR3 SR2 SR1 SR0 BOSR
88.2 88.2 2 1 1 1 1 1
44.1 44.1 1 1 0 0 0 1
8.021 8.021 1 1 0 1 1 1
44.1 8.021 1 1 0 0 1 1
8.021 44.1 1 1 0 1 0 1
3.3.3 Digital Filter Characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC Filter Characteristics (TI DSP 250 fsMode Operation)
Passband ±0.05 dB 0.416 fsHz
Stopband –6 dB 0.5 fsHz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.584 fs–60 dB
ADC Filter Characteristics (TI DSP 272 fsand Normal Mode Operation)
Passband ±0.05 dB 0.4535 fsHz
Stopband –6 dB 0.5 fsHz
Passband ripple ±0.05 dB
Stopband attenuation f > 0.5465 fs–60 dB
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−10
−8
−6
−4
−2
0
0 0.1 0.2 0.3 0.4 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G001
−10
−8
−6
−4
−2
0
0 0.1 0.2 0.3 0.4 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G002
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PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ADC High-Pass Filter Characteristics
Corner frequency –3 dB, fs= 44.1 kHz 3.7 Hz
–3 dB, fs= 48 kHz 4 Hz
–0.5 dB, fs= 44.1 kHz 10.4 Hz
–0.5 dB, fs= 48 kHz 11.3 Hz
–0.1 dB fs= 44.1 kHz 21.6 Hz
–0.1 dB, fs= 48 kHz 23.5 Hz
DAC Filter Characteristics (48-kHz Sampling Rate)
Passband ±0.03 dB 0.416 fsHz
Stopband –6 dB 0.5 fsHz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.584 fs–50 dB
DAC Filter Characteristics (44.1-kHz Sampling Rate)
Passband ±0.03 dB 0.4535 fsHz
Stopband –6 dB 0.5 fsHz
Passband ripple ±0.03 dB
Stopband attenuation f > 0.5465 fs–50 dB
SPACE SPACE
SPACE SPACE
SPACE SPACE
FILTER RESPONSE FILTER RESPONSE
vs vs
NORMALIZED AUDIO SAMPLING FREQUENCY NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-9. Digital De-Emphasis Filter Response −Figure 3-10. Digital De-Emphasis Filter Response −
44.1 kHz Sampling 48 kHz Sampling
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−0.1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G004
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G003
TLV320AIC23B-Q1
SGLS240C –MARCH 2004–REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-11. ADC Digital Filter Response 0: USB Mode (Group Delay = 12 Output Samples)
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-12. ADC Digital Filter Ripple 0: USB (Group Delay = 20 Output Samples)
26 How to Use the TLV320AIC23B-Q1 Copyright © 2004–2012, Texas Instruments Incorporated
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−0.1
−0.1
−0.1
0
0
0
0
0
0.1
0.1
0.1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G006
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G005
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-13. ADC Digital Filter Response 1: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-14. ADC Digital Filter Ripple 1: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated How to Use the TLV320AIC23B-Q1 27
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−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G008
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G007
TLV320AIC23B-Q1
SGLS240C –MARCH 2004–REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-15. ADC Digital Filter Response 2: USB Mode and Normal Modes (Group Delay = 3 Output
Samples)
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-16. ADC Digital Filter Ripple 2: USB Mode and Normal Modes
28 How to Use the TLV320AIC23B-Q1 Copyright © 2004–2012, Texas Instruments Incorporated
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−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G010
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G009
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-17. ADC Digital Filter Response 3: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-18. ADC Digital Filter Ripple 3: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated How to Use the TLV320AIC23B-Q1 29
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−0.1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G012
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G011
TLV320AIC23B-Q1
SGLS240C –MARCH 2004–REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-19. DAC Digital Filter Response 0: USB Mode
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-20. DAC Digital Filter Ripple 0: USB Mode
30 How to Use the TLV320AIC23B-Q1 Copyright © 2004–2012, Texas Instruments Incorporated
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−0.1
−0.08
−0.06
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G014
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G013
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-21. DAC Digital Filter Response 1: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-22. DAC Digital Filter Ripple 1: USB Mode Only
Copyright © 2004–2012, Texas Instruments Incorporated How to Use the TLV320AIC23B-Q1 31
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−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G016
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G015
TLV320AIC23B-Q1
SGLS240C –MARCH 2004–REVISED JUNE 2012
www.ti.com
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-23. DAC Digital Filter Response 2: USB Mode and Normal Modes
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-24. DAC Digital Filter Ripple 2: USB Mode and Normal Modes
32 How to Use the TLV320AIC23B-Q1 Copyright © 2004–2012, Texas Instruments Incorporated
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−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Normalized Audio Sampling Frequency
Filter Response (dB)
G018
−90
−70
−50
−30
−10
10
0 0.5 1 1.5 2 2.5 3
Normalized Audio Sampling Frequency
Filter Response (dB)
G017
TLV320AIC23B-Q1
www.ti.com
SGLS240C –MARCH 2004–REVISED JUNE 2012
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-25. DAC Digital Filter Response 3: USB Mode Only
SPACE
SPACE
SPACE
FILTER RESPONSE
vs
NORMALIZED AUDIO SAMPLING FREQUENCY
Figure 3-26. DAC Digital Filter Ripple 3: USB Mode Only
The delay between the converter is a function of the sample rate. The group delays for the AIC23B are
shown in the following table. Each delay is one LR clock (1/sample rate).
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TLV320AIC23B-Q1
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www.ti.com
Table 3-13. Group Delays
FILTER GROUP DELAY
DAC type 0 11
DAC type 1 18
DAC type 2 5
DAC type 3 5
ADC type 0 12
ADC type 1 20
ADC type 2 3
ADC type 3 6
34 How to Use the TLV320AIC23B-Q1 Copyright © 2004–2012, Texas Instruments Incorporated
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TLV320AIC23B-Q1
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SGLS240C –MARCH 2004–REVISED JUNE 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June 2008) to Revision C Page
• Added sentences after: The TLV320AIC23B-Q1 has the following set of registers, which are used to
program the modes of operation, in the Register Map section. ......................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
6PAIC23BIPWRG4Q1 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV320AIC23BIPWRQ1 ACTIVE TSSOP PW 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV320AIC23B-Q1 :
•Catalog: TLV320AIC23B
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2012
Addendum-Page 2
•Catalog - TI's standard catalog product
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