Revised April 2000 DM74LS169A Synchronous 4-Bit Up/Down Binary Counter General Description This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs all change at the same time when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four masterslave flip-flops on the rising edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count-enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the UP/DOWN input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA output when counting DOWN. This lowlevel overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, UP/ DOWN), which modify the operating mode, have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. Features Fully synchronous operation for counting and programming. Internal look-ahead for fast counting. Carry output for n-bit cascading. Fully independent clock circuit Ordering Code: Order Number Package Number Package Description DM74LS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram (c) 2000 Fairchild Semiconductor Corporation DS006401 www.fairchildsemi.com DM74LS169A Synchronous 4-Bit Up/Down Binary Counter August 1986 DM74LS169A Logic Diagram www.fairchildsemi.com 2 DM74LS169A Timing Diagram Typical Load, Count, and Inhibit Sequences 3 www.fairchildsemi.com DM74LS169A Absolute Maximum Ratings(Note 1) Supply Voltage Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage 7V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V LOW Level Input Voltage 0.8 V mA VCC Supply Voltage VIH HIGH Level Input Voltage VIL 2 V IOH HIGH Level Output Current -0.4 IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 0 25 MHz 20 MHz Clock Frequency (Note 3) 0 tW Clock Pulse Width (Note 4) 25 tSU Setup Time Data (Note 4) Enable ns 20 20 T or P Load 25 U/D 30 tH Hold Time (Note 4) 0 TA Free Air Operating Temperature 0 ns ns C 70 Note 2: CL = 15 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 4: TA = 25C and V CC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = -18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min VOL Min 2.7 IOL = 4 mA, VCC = Min II IIH IIL Typ (Note 5) Max Units -1.5 V 3.4 V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max Enable T 0.2 Input Voltage VI = 7V Others 0.1 HIGH Level VCC = Max Enable T 40 Input Current VI = 2.7V Others 20 LOW Level VCC = Max Enable T -0.8 Input Current VI = 0.4V Others -0.4 IOS Short Circuit Output Current VCC = Max (Note 6) ICC Supply Current VCC = Max (Note 7) -20 20 A mA mA 34 mA Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: ICC is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs OPEN. 4 mA -100 Note 5: All typicals are at VCC = 5V and TA = 25C. www.fairchildsemi.com V at VCC = 5V and TA = 25C RL = 2 k From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPLH Ripple Carry Clock to Ripple Carry Clock to Any Q Clock to Any Q Propagation Delay Time Enable T to Ripple Carry Propagation Delay Time Enable T to HIGH-to-LOW Level Output Ripple Carry LOW-to-HIGH Level Output tPHL 25 Clock to LOW-to-HIGH Level Output Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output Max Up/Down to Ripple Carry (Note 8) Up/Down to Ripple Carry (Note 8) CL = 50 pF Min Units Max 20 MHz 35 39 ns 35 44 ns 20 24 ns 23 32 ns 18 24 ns 18 28 ns 25 30 ns 29 38 ns Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level of the UP/DOWN input is changed, the ripple carry output will follow. If the count is minimum, the RIPPLE CARRY output transition will be in phase. If the count is maximum, the RIPPLE CARRY output will be out of phase. 5 www.fairchildsemi.com DM74LS169A Switching Characteristic DM74LS169A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 6 DM74LS169A Synchronous 4-Bit Up/Down Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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