DM74LS169 - Fairchild Semiconductor

August 1986

Revised April 2000

DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

DM74LS169A

Synchronous 4-Bit Up/Down Binary Counter

General Descript ion

This synchronous p resettable counter features an internal

carry look-ahead for cascading in high-speed counting

applicatio ns. Synchro nous operat ion is provide d by having

all flip-f lops clocked simult aneously, so that the outputs al l

change at the sa me time whe n so instructed by the c ount-

enable inputs and internal gating. This mode of operation

helps eliminate the output counting spikes that are nor-

mally associated with asynchronous (ripple clock)

counters. A buffered clock input triggers the four master-

slave flip-flops on the rising edge of the clock waveform.

This counter is fully programmable; that is, the outputs may

each be preset either HIGH or LOW. The load input cir-

cuitry allows loading with the carry-enable output of cas-

caded counters. As loading is synchronous, setting up a

low level a t th e load inp ut disab l es the cou nte r a nd cau ses

the outputs to agree with the data inputs after the next

clock pulse.

The carr y look-ahead circuitr y permits casca ding counters

for n-bit synchronous applications without additional gating.

Both count- ena ble inp uts (P and T) must be LOW to count.

The dir ection o f the co unt is det erm ined b y the leve l of t he

UP/DOWN input. When the input is HIGH, the counter

counts UP; when LOW, it counts DOWN. Input T is fe d fo r-

ward to enable the carry outputs. The carry output thus

enabled will produce a low-level output pulse with a dura-

tion a pproximate ly equal to the high portio n of the QA out-

put w hen c ounting UP, and a pproxim atel y equ al to the lo w

portion of the QA output when counting DOWN. This low-

level overflow carry pulse can be used to enable succes-

sively cascaded stages. Transitions at the enable P or T

inputs are allowed regardless of the level of the clock input.

All inp uts are dio de clamped to minimi ze transmi ssion-line

effects, thereby simplifying system design.

This counter features a fully independent clock circuit.

Changes at control inputs (enable P, enable T, load, UP/

DOWN), w hich modify the ope rating mode, hav e no effect

until c locking o ccurs. Th e function of the counter (whether

enabled, disabled, loading, or counting) will be dictated

solely by th e conditio ns meeting th e stable setup and hold

times.

Features

■Fully synchronous operation for counting and

programming.

■Internal look-ahead for fast counting.

■Carry output for n-bit cascading.

■Fully indepe nde nt cl ock circui t

Ordering Code:

Devices also available in Tape and R eel. Spe ci fy by append ing the suffix let t er “X” to the orderin g c ode.

Connection Diagram

Order Number Package Number Package Description

DM74LS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

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DM74LS169A

Logic Diagram

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DM74LS169A

Timing Diagram

Typical Load, Count, and Inhibit Sequences

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DM74LS169A

Absolute Maximum Ratings(Note 1) Note 1: The “Abs olute Maxim um Ratings ” are those values beyond whic h

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are no t gua rant eed at the absolute maximu m rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.

Note 4: TA = 25°C an d VCC = 5V.

Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted)

Note 5: All typic als are at VCC = 5V an d TA = 25°C.

Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Note 7: ICC is meas ured aft er a m omen t ary 4. 5V, then ground, is applie d t o t he CLO C K w it h all other inputs gro unded and all the out puts OPEN.

Supply Voltage 7V

Input Voltage 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 2) 0 25 MHz

Clock Frequency (Note 3) 0 20 MHz

tWClock Puls e Wid th (Note 4) 25 ns

tSU Setup Time Data 20

(Note 4) Enable 20

T or P ns

Load 25

U/D 30

tHHold Time (Note 4) 0 ns

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 5)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V

Output Voltage VIL = Max, VIH = Min

VOL LOW Level VCC = Min, IOL = Max 0.35 0.5

Output Voltage VIL = Max, VIH = Min V

IOL = 4 mA, VCC = Min 0.25 0.4

IIInput Current @ Max VCC = Max Enable T 0.2 mA

Input Voltage VI = 7V Others 0.1

IIH HIGH Level VCC = Max Enable T 40 µA

Input Current VI = 2.7V Others 20

IIL LOW Level VCC = Max Enable T −0.8 mA

Input Current VI = 0.4V Others −0.4

IOS Short Circuit Output Current VCC = Max (Note 6) −20 −100 mA

ICC Supply Curre nt VCC = Max (Note 7) 20 34 mA

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DM74LS169A

Switching Charact eristic

at VCC = 5V and TA = 25°C

Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the

logic leve l of the UP/DO WN input is cha nged, the ripple carr y output will fo llow. If the count is minimum, the RIPPLE CA RRY output transition w ill be in

phase. If t he coun t is m ax imum, th e R I PPLE C AR RY output will be out of phase.

From (Input) RL = 2 kΩ

Symbol Paramete r To (Output) CL = 15 pF CL = 50 pF Units

Min Max Min Max

fMAX Maximum Clock Frequency 25 20 MHz

tPLH Propagation Delay Time Clock to 35 39 ns

LOW-to-HIGH Level Output Ripple Carry

tPHL Propagation Delay Time Clock to 35 44 ns

HIGH-to-LOW Level Output Ripple Carry

tPLH Propagation Delay Time Clock to 20 24 ns

LOW-to-HIGH Level Output Any Q

tPHL Propagation Delay Time Clock to 23 32 ns

HIGH-to-LOW Level Output Any Q

tPLH Propagation Delay Time Enable T to 18 24 ns

LOW-to-HIGH Level Output Ripple Carry

tPHL Propagation Delay Time Enable T to 18 28 ns

HIGH-to-LOW Level Output Ripple Carry

tPLH Propagation Delay Time Up/Down to 25 30 ns

LOW-to-HIGH Level Output Ripple Carry (Note 8)

tPHL Propagation Delay Time Up/Down to 29 38 ns

HIGH-to-LOW Level Output Ripple Carry (Note 8)

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DM74LS169A

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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