PIC18F87J72-I/PT - MICROCHIP

 2010 Microchip Technology Inc. Preliminary DS39979A

PIC18F87J72 Family

Data Sheet

80-Pin, High-Performance

Microcontrollers with Dual Channel AFE,

LCD Driver and nanoWatt Technology

DS39979A-page 2 Preliminary  2010 Microchip Technology Inc.

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ISBN: 978-1-60932-314-1

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

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• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

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analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 3

Analog Features:

• Dual-Channel, 24-Bit Analog Front End (AFE):

- 90 dB SINAD, -101 dBc THD (to 35th harmonic),

103 dB SFDR for each channel

- 10 ppm INL

- Differential voltage input pins

- Low drift internal voltage reference (12 ppm/°C)

- Programmable data rate to 64 ksps

- High-gain PGA on each channel (up to 32 V/V)

- Phase delay compensation between channels

(1 µs resolution)

• 12-Bit, 12-Channel SAR A/D Converter:

- Auto-acquisition

- Conversion available during Sleep

• Two Analog Comparators

• Programmable Reference Voltage for Comparators

• Charge Time Measurement Unit (CTMU):

- Capacitance measurement

- Time measurement with 1 ns typical resolution

- Temperature sensing

LCD Driver and Keypad Interface

Features:

• Direct LCD Panel Drive Capability:

- Can drive LCD panel while in Sleep mode

- Wake-up from interrupt

• Up to 33 Segments and 132 Pixels: Software Selectable

• Programmable LCD Timing module:

- Multiple LCD timing sources available

- Up to four commons: static, 1/2, 1/3 or

1/4 multiplex

- Static, 1/2 or 1/3 bias configuration

• On-Chip LCD Boost Voltage Regulator for

Contrast Control

• CTMU for Capacitive Touch Sensing

• ADC for Resistive Touch Sensing

Flexible Oscillator Structure:

• External Crystal and Clock modes, with operation

up to 48 MHz

• 4x Phase Lock Loop (PLL)

• Internal Oscillator Block with PLL:

- Eight user-selectable frequencies from 31.25 kHz

to 8 MHz

• Secondary Oscillator using Timer1 at 32 kHz

• Fail-Safe Clock Monitor (FSCM):

- Allows for safe shutdown if peripheral clock fails

Low-Power Features:

• Power-Managed modes:

- Run: CPU on, peripherals on

- Idle: CPU off, peripherals on

- Sleep: CPU off, peripherals off

• Two-Speed Oscillator Start-up

Peripheral Highlights:

• High-Current Sink/Source 25 mA/25 mA

(PORTB and PORTC)

• Up to Four External Interrupts

• Four 8-Bit/16-Bit Timer/Counter modules

• Two Capture/Compare/PWM (CCP) modules

• Master Synchronous Serial Port (MSSP) module with

Two Modes of Operation:

- 3-wire/4-wire SPI (supports all four SPI modes)

-I

2C™ Master and Slave mode

• One Addressable USART module

• One Enhanced Addressable USART module:

- LIN/J2602 support

- Auto-wake-up on Start bit and Break character

- Auto-Baud Detect (ABD)

• Hardware Real-Time Clock and Calendar (RTCC) with

Clock, Calendar and Alarm Functions

Special Microcontroller Features:

• 10,000 Erase/Write Cycle Flash Program

Memory, Typical

• Flash Retention 20 Years, Minimum

• Self-Programmable under Software Control

• Word Write Capability for Flash Program Memory for

Data EEPROM Emulators

• Priority Levels for Interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

• Extended Watchdog Timer (WDT):

- Programmable period from 4 ms to 131s

• Selectable Open-Drain Configuration for Serial

Communication and CCP pins for Driving Outputs up to 5V

• In-Circuit Serial Programming™ (ICSP™) via Two Pins

• In-Circuit Debug via Two Pins

• Operating Voltage Range: 4.5V to 5.5V (ADC), 2.0V

to 3.6V (digital and SAR ADC)

• 5.5V Tolerant Input (digital pins only)

• On-Chip 2.5V Regulator

Target Applications:

• Energy Metering

• Power Measurement and Monitoring

• Portable Instrumentation

• Medical Monitoring

PIC18F87J72 FAMILY

80-Pin, High-Performance Microcontrollers with

Dual-Channel AFE, LCD Driver and nanoWatt Technology

PIC18F87J72 FAMILY

DS39979A-page 4 Preliminary  2010 Microchip Technology Inc.

Pin Diagram

Device

Flash

Program

Memory

(bytes)

SRAM

Data

Memory

(bytes)

LCD

(Pixels) I/O

A/D

Comparators

CCP

BOR/LVD

MSSP

A/EUSART

Timers

8-bit/16-bit

RTCC

CTMU

12-Bit SAR

(channels)

24-bit AFE

(channels)

PIC18F86J72 64K 3,923 132 51 12 2 2 2 Y 1 1/1 1/3 Y Y

PIC18F87J72 128K 3,923 132 51 12 2 2 2 Y 1 1/1 1/3 Y Y

PIC18F86J72

Note 1: Pinouts are subject to change.

2: The CCP2 pin placement depends on the setting of the CCP2MX Configuration bit.

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

33 34 35 36 38

68 67 66 6572 71 70 6974 73

78 77 76 75

RD7/SEG7

RD6/SEG6

RD5/SEG5

RD4/SEG4

RD3/SEG3

RD2/SEG2

RD1/SEG1

SVDD

VSS

RD0/SEG0/CTPLS

RE7/CCP2(2)/SEG31

RE6/COM3

RE5/COM2

RE4/COM1

RE3/COM0

RE2/LCDBIAS3

RE1/LCDBIAS2

RE0/LCDBIAS1

RG0/LCDBIAS0

RG1/TX2/CK2

RG2/RX2/DT2/VLCAP1

RG3/VLCAP2

MCLR

RG4/SEG26/RTCC

VSS

VDDCORE/VCAP

RF7/AN5/SS/SEG25

RF6/AN11/SEG24/C1INA

RF5/AN10/CVREF/SEG23/C1INB

RF4/AN9/SEG22/C2INA

RF3/AN8/SEG21/C2INB

RF2/AN7/C1OUT/SEG20

RF1/AN6/C2OUT/SEG19

ENVREG

AVDD

AVSS

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1/SEG18

RA0/AN0

VSS

RA5/AN4/SEG15

RA4/T0CKI/SEG14

RC1/T1OSI/CCP2(2)I/SEG32

RC0/T1OSO/T13CKI

RC6/TX1/CK1/SEG27

RC7/RX1/DT1/SEG28

RC2/CCP1/SEG13

RC3/SCK/SCL/SEG17

RC4/SDI/SDA/SEG16

RC5/SDO/SEG12

RB7/KBI3/PGD

VDD

OSC1/CLKI/RA7

OSC2/CLKO/RA6

VSS

RB6/KBI2/PGC

RB5/KBI1/SEG29

RB4/KBI0/SEG11

RB3/INT3/SEG10/CTED2

RB2/INT2/SEG9/CTED1

RB1/INT1/SEG8

RB0/INT0/SEG30

SAVDD

VDD

ARESET

SDIA

CSA

SCKA

SDOA

CLKIA

SVSS

REFIN-

REFIN+/OUT

SAVSS

CH0+

CH0-

CH1-

CH1+

80-Pin TQFP(1)

Pins are tolerant up to 5.5 V Dedicated 24-bit AFE pins

PIC18F87J72

 2010 Microchip Technology Inc. Preliminary DS39979A-page 5

PIC18F87J72 FAMILY

Typical Application Circuit: Single-Phase Power Meter

LCD Glass

EEPROM

RS-485

RF/PLC

Current

Sensor(s)(1) SEG/COM

SPI/I2C™

CTMU

CH0+

CH0-

CH1+

CH1-

UART1 UART2

Touc h

Keypad

Temperature

Sensor

Up to 33 SEG/4 COM

24-Bit

AFE with

PGA

PIC18F87J72(2)

Low-Voltage

Detect

12-Bit A/D

H/W RTCC

32 kHz

10 MHz

Note 1: Generic current sense configuration shown. Many circuit configurations using current and/or voltage

sensing are possible, including the use of shunts, transformers or Rogowski coils.

2: Power metering, with the measurement of active and reactive power, is done with the power metering

firmware application available through Microchip Technology.

Line Voltage

Measurement

Digital I/O

Indicator LEDs

Anti-tamper sensors

MAIN OSC

PIC18F87J72 FAMILY

DS39979A-page 6 Preliminary  2010 Microchip Technology Inc.

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 21

3.0 Oscillator Configurations ............................................................................................................................................................ 25

4.0 Power-Managed Modes ............................................................................................................................................................. 35

5.0 Reset .......................................................................................................................................................................................... 43

6.0 Memory Organization ................................................................................................................................................................. 55

7.0 Flash Program Memory.............................................................................................................................................................. 77

8.0 8 x 8 Hardware Multiplier............................................................................................................................................................ 87

9.0 Interrupts .................................................................................................................................................................................... 89

10.0 I/O Ports ................................................................................................................................................................................... 105

11.0 Timer0 Module ......................................................................................................................................................................... 123

12.0 Timer1 Module ......................................................................................................................................................................... 127

13.0 Timer2 Module ......................................................................................................................................................................... 133

14.0 Timer3 Module ......................................................................................................................................................................... 135

15.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 139

16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 157

17.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 167

18.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 195

19.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 239

20.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) ........................................................... 259

21.0 12-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 273

22.0 Dual-Channel, 24-Bit Analog Front End (AFE)......................................................................................................................... 283

23.0 Comparator Module.................................................................................................................................................................. 293

24.0 Comparator Voltage Reference Module................................................................................................................................... 299

25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 303

26.0 Special Features of the CPU.................................................................................................................................................... 319

27.0 Instruction Set Summary .......................................................................................................................................................... 333

28.0 Development Support............................................................................................................................................................... 385

29.0 Electrical Characteristics .......................................................................................................................................................... 389

30.0 Packaging Information.............................................................................................................................................................. 429

Appendix A: Revision History............................................................................................................................................................. 433

Appendix B: Dual-Channel, 24-Bit AFE Reference............................................................................................................................ 434

The Microchip Web Site..................................................................................................................................................................... 477

Customer Change Notification Service .............................................................................................................................................. 477

Customer Support .............................................................................................................................................................................. 477

Reader Response .............................................................................................................................................................................. 478

Product Identification System............................................................................................................................................................. 479

 2010 Microchip Technology Inc. Preliminary DS39979A-page 7

PIC18F87J72 FAMILY

TO OUR VALUED CUSTOMERS

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Customer Notification System

PIC18F87J72 FAMILY

DS39979A-page 8 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 9

PIC18F87J72 FAMILY

1.0 DEVICE OVERVIEW

This document contains device-specific information for

the following devices:

• PIC18F86J72

• PIC18F87J72

This family combines the traditional advantages of all

PIC18 microcontrollers – namely, high computational

performance and a rich feature set – with a versatile

on-chip LCD driver and a high-performance,

high-accuracy analog front end. These features make

the PIC18F87J72 family a logical choice for many

high-performance power and metering applications

where price is a primary consideration.

1.1 Core Features

1.1.1 nanoWatt TECHNOLOGY

All of the devices in the PIC18F87J72 family incorporate

a range of features that can significantly reduce power

consumption during operation. Key items include:

•Alternate Run Modes: By clocking the controller

from the Timer1 source or the internal RC

oscillator, power consumption during code

execution can be reduced by as much as 90%.

•Multiple Idle Modes: The controller can also run

with its CPU core disabled but the peripherals still

active. In these states, power consumption can be

reduced even further, to as little as 4% of normal

operation requirements.

•On-the-Fly Mode Switching: The power-managed

modes are invoked by user code during operation,

allowing the user to incorporate power-saving ideas

into their application’s software design.

1.1.2 OSCILLATOR OPTIONS AND

FEATURES

All of the devices in the PIC18F87J72 family offer six

different oscillator options, allowing users a range of

choices in developing application hardware. These

include:

• Two Crystal modes using crystals or ceramic

resonators.

• Two External Clock modes offering the option of a

divide-by-4 clock output.

• A Phase Lock Loop (PLL) frequency multiplier,

available to the external oscillator modes which

allows clock speeds of up to 40 MHz. PLL can

also be used with the internal oscillator.

• An internal oscillator block which provides an

8 MHz clock (±2% accuracy) and an INTRC source

(approximately 31 kHz, stable over temperature

and VDD), as well as a range of six user-selectable

clock frequencies, between 125 kHz to 4 MHz, for a

total of eight clock frequencies. This option frees the

two oscillator pins for use as additional general

purpose I/O.

The internal oscillator block provides a stable reference

source that gives the family additional features for

robust operation:

•Fail-Safe Clock Monitor: This option constantly

monitors the main clock source against a reference

signal provided by the internal oscillator. If a clock

failure occurs, the controller is switched to the

internal oscillator, allowing for continued low-speed

operation or a safe application shutdown.

•Two-Speed Start-up: This option allows the

internal oscillator to serve as the clock source

from Power-on Reset, or wake-up from Sleep

mode, until the primary clock source is available.

1.1.3 MEMORY OPTIONS

The PIC18F87J72 family provides ample room for

application code with 128 Kbytes of code space. The

Flash cells for program memory are rated to last up to

10,000 erase/write cycles. Data retention without

refresh is conservatively estimated to be greater than

20 years.

The Flash program memory is readable and writable.

During normal operation, the PIC18F87J72 family also

provides plenty of room for dynamic application data

with up to 3,923 bytes of data RAM.

1.1.4 EXTENDED INSTRUCTION SET

The PIC18F87J72 family implements the optional

extension to the PIC18 instruction set, adding 8 new

instructions and an Indexed Addressing mode.

Enabled as a device configuration option, the extension

has been specifically designed to optimize re-entrant

application code originally developed in high-level

languages, such as ‘C’.

1.1.5 EASY MIGRATION

Regardless of the memory size, all devices share the

same rich set of peripherals, allowing for a smooth

migration path as applications grow and evolve.

The consistent pinout scheme used throughout the

entire family also aids in migrating to the next larger

device.

The PIC18F87J72 family is also largely pin compatible

with other PIC18 families, such as the PIC18F8720 and

PIC18F8722, the PIC18F85J11, and the PIC18F8490

and PIC18F85J90 families of microcontrollers with

LCD drivers. This allows a new dimension to the

evolution of applications, allowing developers to select

different price points within Microchip’s PIC18 portfolio,

while maintaining a similar feature set.

PIC18F87J72 FAMILY

DS39979A-page 10 Preliminary  2010 Microchip Technology Inc.

1.2 Analog Features

•Dual-Channel, 24-Bit ADC Front End (AFE):

This module contains two synchronous sampling,

 Analog-to-Digital (A/D) Converters, plus sup-

porting Programmable Gain Amplifiers (PGAs)

and an internal voltage reference, to perform

high-accuracy and low noise analog conversions.

The AFE is controlled, and its data read, through

a dedicated, high-speed (20 MHz) SPI interface.

•12-Bit A/D Converter: In addition to the AFE,

PIC18F87J72 family devices also include a stan-

dard SAR A/D Converter with 12 independent

analog inputs. The module incorporates program-

mable acquisition time, allowing for a channel to

be selected and a conversion to be initiated

without waiting for a sampling period and thus,

reducing code overhead.

•Charge Time Measurement Unit (CTMU): The

CTMU is a flexible analog module that provides

accurate differential time measurement between

pulse sources, as well as asynchronous pulse

generation.

Together with other on-chip analog modules, the

CTMU can precisely measure time, measure

capacitance or relative changes in capacitance, or

generate output pulses that are independent of

the system clock.

1.3 LCD Driver

The on-chip LCD driver includes many features that

make the integration of displays in low-power

applications easier. These include an integrated volt-

age regulator with charge pump that allows contrast

control in software and display operation above device

VDD.

1.4 Other Special Features

•Communications: The PIC18F87J72 family

incorporates a range of serial communication

peripherals, including an Addressable USART, a

separate Enhanced USART that supports

LIN/J2602 specification 1.2, and one Master SSP

module capable of both SPI and I2C™ (Master and

Slave) modes of operation.

•CCP Modules: All devices in the family incorporate

two Capture/Compare/PWM (CCP) modules. Up to

four different time bases may be used to perform

several different operations at once.

•Extended Watchdog Timer (WDT): This

enhanced version incorporates a 16-bit prescaler,

allowing an extended time-out range that is stable

across operating voltage and temperature. See

Section 29.0 “Electrical Characteristics” for

time-out periods.

•Real Time Clock and Calendar Module (RTCC):

The RTCC module is intended for applications

requiring that accurate time be maintained for

extended periods of time with minimum to no

intervention from the CPU.

The module is a 100-year clock and calendar with

automatic leap year detection. The range of the

clock is from 00:00:00 (midnight) on January 1,

2000 to 23:59:59 on December 31, 2099.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 11

PIC18F87J72 FAMILY

1.5 Details on Individual Family

Members

Devices in the PIC18F87J72 family are available in

80-pin packages. Block diagrams for the two groups

are shown in Figure 1-1.

The devices are differentiated in that PIC18F86J72

devices have a Flash program memory of 64 Kbytes

and PIC18F87J72 devices memory is 128 Kbytes

All other features for the devices are identical. These

are summarized in Table 1-1.

The pinouts for all devices are listed in Table 1-2.

TABLE 1-1: DEVICE FEATURES FOR THE PIC18F8XJ72 (80-PIN DEVICES)

Features PIC18F86J72 PIC18F87J72

Operating Frequency DC – 48 MHz

Program Memory (Bytes) 64K 128K

Program Memory (Instructions) 32,768 65,536

Data Memory (Bytes) 3,923 3,923

Interrupt Sources 29

I/O Ports Ports A, B, C, D, E, F, G

LCD Driver (available pixels to drive) 132 (33 SEGs x 4 COMs)

Timers 4

Comparators 2

CTMU Yes

RTCC Yes

Capture/Compare/PWM Modules 2

Serial Communications MSSP, Addressable USART, Enhanced USART

12-Bit Analog-to-Digital Module 12 Input Channels

Dual-Channel 24-Bit Analog Front End Yes

Resets (and Delays) POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR,

WDT (PWRT, OST)

Instruction Set 75 Instructions, 83 with Extended Instruction Set Enabled

Packages 80-Pin TQFP

PIC18F87J72 FAMILY

DS39979A-page 12 Preliminary  2010 Microchip Technology Inc.

FIGURE 1-1: PIC18F8XJ72 (80-PIN) BLOCK DIAGRAM

Instruction

Decode and

Control

PORTA

Data Latch

Data Memory

(2.0, 3.9

Address Latch

Data Address<12>

Access

BSR FSR0

FSR1

FSR2

inc/dec

logic

Address

412 4

PCH PCL

PCLATH

31-Level Stack

Program Counter

PRODLPRODH

8 x 8 Multiply

BITOP

ALU<8>

Address Latch

Program Memory

(96 Kbytes)

Data Latch

Table Pointer<21>

inc/dec logic

Data Bus<8>

Table Latch

PCLATU

PCU

Note 1: See Table 1-2 for I/O port pin descriptions.

2: RA6 and RA7 are only available as digital I/O in select oscillator modes. See Section 3.0 “Oscillator Configurations” for more

information

3: Brown-out Reset and Low-Voltage Detect functions are provided when the on-board voltage regulator is enabled.

AUSART

Comparators

MSSP

Timer3Timer2 CTMUTimer1

CCP2

ADC

12-Bit

Instruction Bus <16>

STKPTR Bank

State Machine

Control Signals

Decode

EUSART

ROM Latch

LCD

PORTC

PORTD

PORTE

PORTF

PORTG

RA0:RA7(1,2)

RC0:RC7(1)

RD0:RD7(1)

RE0:RE1,

RF1:RF7(1)

RG0:RG4(1)

PORTB

RB0:RB7(1)

OSC1/CLKI

OSC2/CLKO

VDD,

Timing

Generation

VSS MCLR

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

BOR and

LVD(3)

Precision

Reference

Band Gap

INTRC

Oscillator

Regulator

Voltage

VDDCORE/VCAP

ENVREG

Kbytes)

Driver

8 MHz

Oscillator

RE3:RE7(1)

Timer0

CCP1 RTCC

Dual-Channel

SDIA

AFE

SDOA

CSA DR

CLKIA

CHn+

CHn-

SVDD

SVSS

ARESET

SAVDD

SAVSS

 2010 Microchip Technology Inc. Preliminary DS39979A-page 13

PIC18F87J72 FAMILY

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

MCLR 9 I ST Master Clear (input) or programming voltage (input). This pin

is an active-low Reset to the device.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

I/O

CMOS

TTL

Oscillator crystal or external clock input.

Oscillator crystal input.

External clock source input. Always associated

with pin function, OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

I/O

—

TTL

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In EC modes, OSC2 pin outputs CLKO, which has

1/4 the frequency of OSC1 and denotes the

instruction cycle rate.

General purpose I/O pin.

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

I/O

TTL

Analog

Digital I/O.

Analog Input 0.

RA1/AN1/SEG18

RA1

AN1

SEG18

I/O

TTL

Analog

Digital I/O.

Analog Input 1.

SEG18 output for LCD.

RA2/AN2/VREF-

RA2

AN2

VREF-

I/O

TTL

Analog

Digital I/O.

Analog Input 2.

A/D reference voltage (low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

I/O

TTL

Analog

Digital I/O.

Analog Input 3.

A/D reference voltage (high) input.

RA4/T0CKI/SEG14

RA4

T0CKI

SEG14

I/O

Analog

Digital I/O.

Timer0 external clock input.

SEG14 output for LCD.

RA5/AN4/SEG15

RA5

AN4

SEG15

I/O

TTL

Analog

Digital I/O.

Analog Input 4.

SEG15 output for LCD.

RA6 See the OSC2/CLKO/RA6 pin.

RA7 See the OSC1/CLKI/RA7 pin.

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

PIC18F87J72 FAMILY

DS39979A-page 14 Preliminary  2010 Microchip Technology Inc.

PORTB is a bidirectional I/O port. PORTB can be software

programmed for internal weak pull-ups on all inputs.

RB0/INT0/SEG30

RB0

INT0

SEG30

I/O

TTL

Analog

Digital I/O.

External Interrupt 0.

SEG30 output for LCD.

RB1/INT1/SEG8

RB1

INT1

SEG8

I/O

TTL

Analog

Digital I/O.

External Interrupt 1.

SEG8 output for LCD.

RB2/INT2/SEG9/

CTED1

RB2

INT2

CTED1

SEG9

I/O

TTL

Analog

Digital I/O.

External Interrupt 2.

CTMU Edge 1 input.

SEG9 output for LCD.

RB3/INT3/SEG10/

CTED2

RB3

INT3

SEG10

CTED2

I/O

TTL

Analog

Digital I/O.

External Interrupt 3.

SEG10 output for LCD.

CTMU Edge 2 input.

RB4/KBI0/SEG11

RB4

KBI0

SEG11

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

SEG11 output for LCD.

RB5/KBI1/SEG29

RB5

KBI1

SEG29

I/O

TTL

Analog

Digital I/O.

Interrupt-on-change pin.

SEG29 output for LCD.

RB6/KBI2/PGC

RB6

KBI2

PGC

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP™ programming clock pin.

RB7/KBI3/PGD

RB7

KBI3

PGD

I/O

TTL

Digital I/O.

Interrupt-on-change pin.

In-Circuit Debugger and ICSP programming data pin.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 15

PIC18F87J72 FAMILY

PORTC is a bidirectional I/O port.

RC0/T1OSO/T13CKI

RC0

T1OSO

T13CKI

I/O

—

Digital I/O.

Timer1 oscillator output.

Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2/

SEG32

RC1

T1OSI

CCP2(1)

SEG32

I/O

CMOS

Analog

Digital I/O.

Timer1 oscillator input.

Capture 2 input/Compare 2 output/PWM2 output.

SEG32 output for LCD.

RC2/CCP1/SEG13

RC2

CCP1

SEG13

I/O

Analog

Digital I/O.

Capture 1 input/Compare 1 output/PWM1 output.

SEG13 output for LCD.

RC3/SCK/SCL/SEG17

RC3

SCK

SCL

SEG17

I/O

I2C

Analog

Digital I/O.

Synchronous serial clock input/output for SPI mode.

Synchronous serial clock input/output for I2C™ mode.

SEG17 output for LCD.

RC4/SDI/SDA/SEG16

RC4

SDI

SDA

SEG16

I/O

I2C

Analog

Digital I/O.

SPI data in.

I2C data I/O.

SEG16 output for LCD.

RC5/SDO/SEG12

RC5

SDO

SEG12

I/O

—

Analog

Digital I/O.

SPI data out.

SEG12 output for LCD.

RC6/TX1/CK1/SEG27

RC6

TX1

CK1

SEG27

I/O

—

Analog

Digital I/O.

EUSART asynchronous transmit.

EUSART synchronous clock (see related RX1/DT1).

SEG27 output for LCD.

RC7/RX1/DT1/SEG28

RC7

RX1

DT1

SEG28

I/O

Analog

Digital I/O.

EUSART asynchronous receive.

EUSART synchronous data (see related TX1/CK1).

SEG28 output for LCD.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

PIC18F87J72 FAMILY

DS39979A-page 16 Preliminary  2010 Microchip Technology Inc.

PORTD is a bidirectional I/O port.

RD0/SEG0/CTPLS

RD0

SEG0

CTPLS

I/O

Analog

—

Digital I/O.

SEG0 output for LCD.

CTMU pulse generator output.

RD1/SEG1

RD1

SEG1

I/O

Analog

Digital I/O.

SEG1 output for LCD.

RD2/SEG2

RD2

SEG2

I/O

Analog

Digital I/O.

SEG2 output for LCD.

RD3/SEG3

RD3

SEG3

I/O

Analog

Digital I/O.

SEG3 output for LCD.

RD4/SEG4

RD4

SEG4

I/O

Analog

Digital I/O.

SEG4 output for LCD.

RD5/SEG5

RD5

SEG5

I/O

Analog

Digital I/O.

SEG5 output for LCD.

RD6/SEG6

RD6

SEG6

I/O

Analog

Digital I/O.

SEG6 output for LCD.

RD7/SEG7

RD7

SEG7

I/O

Analog

Digital I/O.

SEG7 output for LCD.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 17

PIC18F87J72 FAMILY

PORTE is a bidirectional I/O port.

RE0/LCDBIAS1

RE0

LCDBIAS1

I/O

Analog

Digital I/O.

BIAS1 input for LCD.

RE1/LCDBIAS2

RE1

LCDBIAS2

I/O

Analog

Digital I/O.

BIAS2 input for LCD.

RE2/LCDBIAS3

RE2

LCDBIAS3

I/O

Analog

Digital I/O.

BIAS3 input for LCD.

RE3/COM0

RE3

COM0

I/O

Analog

Digital I/O.

COM0 output for LCD.

RE4/COM1

RE4

COM1

I/O

Analog

Digital I/O.

COM1 output for LCD.

RE5/COM2

RE5

COM2

I/O

Analog

Digital I/O.

COM2 output for LCD.

RE6/COM3

RE6

COM3

I/O

Analog

Digital I/O.

COM3 output for LCD.

RE7/CCP2/SEG31

RE7

CCP2(2)

SEG31

I/O

Analog

Digital I/O.

Capture 2 input/Compare 2 output/PWM2 output.

SEG31 output for LCD.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

PIC18F87J72 FAMILY

DS39979A-page 18 Preliminary  2010 Microchip Technology Inc.

PORTF is a bidirectional I/O port.

RF1/AN6/C2OUT/

SEG19

RF1

AN6

C2OUT

SEG19

I/O

Analog

—

Analog

Digital I/O.

Analog Input 6.

Comparator 2 output.

SEG19 output for LCD.

RF2/AN7/C1OUT/

SEG20

RF2

AN7

C1OUT

SEG20

I/O

Analog

—

Analog

Digital I/O.

Analog Input 7.

Comparator 1 output.

SEG20 output for LCD.

RF3/AN8/SEG21/

C2INB

RF3

AN8

SEG21

C2INB

I/O

Analog

Digital I/O.

Analog Input 8.

SEG21 output for LCD.

Comparator 2 Input B.

RF4/AN9/SEG22/

C2INA

RF4

AN9

SEG22

C2INA

I/O

Analog

Digital I/O.

Analog Input 9.

SEG22 output for LCD

Comparator 2 Input A.

RF5/AN10/CVREF/

SEG23/C1INB

RF5

AN10

CVREF

SEG23

C1INB

I/O

Analog

Digital I/O.

Analog Input 10.

Comparator reference voltage output.

SEG23 output for LCD.

Comparator 1 Input B.

RF6/AN11/SEG24/

C1INA

RF6

AN11

SEG24

C1INA

I/O

Analog

Digital I/O.

Analog Input 11.

SEG24 output for LCD

Comparator 1 Input A.

RF7/AN5/SS/SEG25

RF7

AN5

SEG25

I/O

Analog

TTL

Analog

Digital I/O.

Analog Input 5.

SPI slave select input.

SEG25 output for LCD.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 19

PIC18F87J72 FAMILY

PORTG is a bidirectional I/O port.

RG0/LCDBIAS0

RG0

LCDBIAS0

I/O

Analog

Digital I/O.

BIAS0 input for LCD.

RG1/TX2/CK2

RG1

TX2

CK2

I/O

—

Digital I/O.

AUSART asynchronous transmit.

AUSART synchronous clock (see related RX2/DT2).

RG2/RX2/DT2/VLCAP1

RG2

RX2

DT2

VLCAP1

I/O

Analog

Digital I/O.

AUSART asynchronous receive.

AUSART synchronous data (see related TX2/CK2).

LCD charge pump capacitor input.

RG3/VLCAP2

RG3

VLCAP2

I/O

Analog

Digital I/O.

LCD charge pump capacitor input.

RG4/SEG26/RTCC

RG4

SEG26

RTCC

I/O

Analog

—

Digital I/O.

SEG26 output for LCD.

RTCC output.

VSS 11,32,50, 71 P — Ground reference for logic and I/O pins.

VDD 47, 72 P — Positive supply for logic and I/O pins.

AVSS 24 P — Ground reference for analog modules.

AVDD 23 P — Positive supply for analog modules.

ENVREG 22 I ST Enable for on-chip voltage regulator.

VDDCORE/VCAP

VDDCORE

VCAP

—

Core logic power or external filter capacitor connection.

Positive supply for microcontroller core logic

(regulator disabled).

External filter capacitor connection (regulator enabled).

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

PIC18F87J72 FAMILY

DS39979A-page 20 Preliminary  2010 Microchip Technology Inc.

RESET 69 I ST AFE Master Reset logic input pin.

SVDD 70 P — AFE digital power supply pin.

SAVDD 74 P — AFE analog power supply reference pin.

CH0+ 1 I Analog Channel 0 non-inverting analog input pin.

CH0- 2 I Analog Channel 0 inverting analog input pin.

CH1- 19 I Analog Channel 1 inverting analog input pin.

CH1+ 20 I Analog Channel 1 Non-Inverting Analog Input Pin

SAVSS 26 P — AFE analog ground pin (return path for analog circuitry).

REFIN+/OUT

REFIN+

REFOUT

Analog

AFE non-inverting voltage reference input.

Internal reference output pin.

REFIN- 29 I Analog Inverting voltage reference input pin.

SVSS 36 P — AFE digital ground pin (return path for digital circuitry).

DR 40 — AFE data ready signal output pin.

CLKIA 41 I CMOS AFE oscillator crystal connection pin or external clock input pin.

CSA 58 I TTL AFE serial interface chip select pin.

SCKA 59 I TTL AFE serial interface clock pin.

SDOA 60 O TTL AFE serial interface data output pin.

SDIA 64 I TTL AFE serial interface data input pin.

TABLE 1-2: PIC18F8XJ72 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number Pin

Type

Buffer

Type Description

TQFP

Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels Analog = Analog input

I2C = I2C/SMBus compatible input OD = Open-Drain (no P diode to VDD)

I = Input O = Output

P= Power

Note 1: Default assignment for CCP2 when the CCP2MX Configuration bit is set.

2: Alternate assignment for CCP2 when the CCP2MX Configuration bit is cleared.

 2010 Microchip Technology Inc. DS39979A-page 21

PIC18F87J72 FAMILY

2.0 GUIDELINES FOR GETTING

STARTED WITH PIC18FJ

MICROCONTROLLERS

2.1 Basic Connection Requirements

Getting started with the PIC18F87J72 family family of

8-bit microcontrollers requires attention to a minimal

set of device pin connections before proceeding with

development.

The following pins must always be connected:

•All V

DD and VSS pins

(see Section 2.2 “Power Supply Pins”)

•All AV

DD and AVSS pins, regardless of whether or

not the analog device features are used

(see Section 2.2 “Power Supply Pins”)

•MCLR

(see Section 2.3 “Master Clear (MCLR) Pin”)

• ENVREG (if implemented) and VCAP/VDDCORE pins

(see Section 2.4 “Voltage Regulator Pins

(ENVREG and VCAP/VDDCORE)”)

These pins must also be connected if they are being

used in the end application:

• PGC/PGD pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.5 “ICSP Pins”)

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.6 “External Oscillator Pins”)

Additionally, the following pins may be required:

•V

REF+/VREF- pins are used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

FIGURE 2-1: RECOMMENDED MINIMUM

CONNECTIONS

Note: The AVDD and AVSS pins must always be

connected, regardless of whether any of

the analog modules are being used.

PIC18FXXJXX

VDD

VSS

VDD

VSS

VDD

AVDD

AVSS

VDD

VSS

VDD

MCLR

VCAP/VDDCORE

R2 ENVREG

(1)

C2(2)

C3(2)

C4(2)

C5(2)

C6(2)

Key (all values are recommendations):

C1 through C6: 0.1 F, 20V ceramic

C7: 10 F, 6.3V or greater, tantalum or ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

Note 1: See Section 2.4 “Voltage Regulator Pins

(ENVREG and VCAP/VDDCORE)” for

explanation of ENVREG pin connections.

2: The example shown is for a PIC18F device

with five VDD/VSS and AVDD/AVSS pairs.

Other devices may have more or less pairs;

adjust the number of decoupling capacitors

appropriately.

(1)

PIC18F87J72 FAMILY

DS39979A-page 22  2010 Microchip Technology Inc.

2.2 Power Supply Pins

2.2.1 DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS, is required.

Consider the following criteria when using decoupling

capacitors:

•Value and type of capacitor: A 0.1 F (100 nF),

10-20V capacitor is recommended. The capacitor

should be a low-ESR device, with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

•Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

•Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

•Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

inductance.

2.2.2 TANK CAPACITORS

On boards with power traces running longer than

six inches in length, it is suggested to use a tank capac-

itor for integrated circuits, including microcontrollers, to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

2.3 Master Clear (MCLR) Pin

The MCLR pin provides two specific device

functions: Device Reset, and Device Programming

and Debugging. If programming and debugging are

not required in the end application, a direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

voltage sags, may be beneficial. A typical

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN

CONNECTIONS

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

VDD

MCLR

PIC18FXXJXX

 2010 Microchip Technology Inc. DS39979A-page 23

PIC18F87J72 FAMILY

2.4 Voltage Regulator Pins (ENVREG

and VCAP/VDDCORE)

The on-chip voltage regulator enable pin, ENVREG,

must always be connected directly to either a supply

voltage or to ground. Tying ENVREG to VDD enables

the regulator, while tying it to ground disables the

regulator. Refer to Section 26.3 “On-Chip Voltage

Regulator” for details on connecting and using the

on-chip regulator.

When the regulator is enabled, a low-ESR (< 5Ω)

capacitor is required on the VCAP/VDDCORE pin to

stabilize the voltage regulator output voltage. The

VCAP/VDDCORE pin must not be connected to VDD and

must use a capacitor of 10 F connected to ground. The

type can be ceramic or tantalum. A suitable example is

the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or

equivalent. Designers may use Figure 2-3 to evaluate

ESR equivalence of candidate devices.

It is recommended that the trace length not exceed

0.25 inch (6 mm). Refer to Section 29.0 “Electrical

Characteristics” for additional information.

When the regulator is disabled, the VCAP/VDDCORE pin

must be tied to a voltage supply at the VDDCORE level.

Refer to Section 29.0 “Electrical Characteristics” for

information on VDD and VDDCORE.

Note that the “LF” versions of some low pin count

PIC18FJ parts (e.g., the PIC18LF45J10) do not have

the ENVREG pin. These devices are provided with the

voltage regulator permanently disabled; they must

always be provided with a supply voltage on the

VDDCORE pin.

FIGURE 2-3: FREQUENCY vs. ESR

PERFORMANCE FOR

SUGGESTED VCAP

2.5 ICSP Pins

The PGC and PGD pins are used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes. It

is recommended to keep the trace length between the

ICSP connector and the ICSP pins on the device as

short as possible. If the ICSP connector is expected to

experience an ESD event, a series resistor is recom-

mended, with the value in the range of a few tens of

ohms, not to exceed 100Ω.

Pull-up resistors, series diodes, and capacitors on the

PGC and PGD pins are not recommended as they will

interfere with the programmer/debugger communica-

tions to the device. If such discrete components are an

application requirement, they should be removed from

the circuit during programming and debugging. Alter-

natively, refer to the AC/DC characteristics and timing

requirements information in the respective device

Flash programming specification for information on

capacitive loading limits, and pin input voltage high

(VIH) and input low (VIL) requirements.

For device emulation, ensure that the “Communication

Channel Select” (i.e., PGCx/PGDx pins) programmed

into the device matches the physical connections for

the ICSP to the Microchip debugger/emulator tool.

For more information on available Microchip

development tools connection requirements, refer to

Section 28.0 “Development Support”.

0.1

0.01

0.001 0.01 0.1 1 10 100 1000 10,000

Frequency (MHz)

ESR ()

Note: Data for Murata GRM21BF50J106ZE01 shown.

Measurements at 25°C, 0V DC bias.

PIC18F87J72 FAMILY

DS39979A-page 24  2010 Microchip Technology Inc.

2.6 External Oscillator Pins

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

low-frequency secondary oscillator (refer to

Section 3.0 “Oscillator Configurations” for details).

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

Layout suggestions are shown in Figure 2-4. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins and other signals

in close proximity to the oscillator are benign (i.e., free

of high frequencies, short rise and fall times, and other

similar noise).

For additional information and design guidance on

oscillator circuits, please refer to these Microchip

Application Notes, available at the corporate web site

(www.microchip.com):

•AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro® Devices”

• AN849, “Basic PICmicro® Oscillator Design”

• AN943, “Practical PICmicro® Oscillator Analysis

and Design”

•AN949, “Making Your Oscillator Work”

2.7 Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

FIGURE 2-4: SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

GND

OSC1

OSC2

T1OSO

T1OS I

Copper Pour Primary Oscillator

Crystal

Timer1 Oscillator

Crystal

DEVICE PINS

Primary

Oscillator

T1 Oscillator: C1 T1 Oscillator: C2

(tied to ground)

Single-Sided and In-Line Layouts:

Fine-Pitch (Dual-Sided) Layouts:

GND

OSCO

OSCI

Bottom Layer

Copper Pour

Oscillator

Crystal

Top Layer Copper Pour

DEVICE PINS

(tied to ground)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 25

PIC18F87J72 FAMILY

3.0 OSCILLATOR

CONFIGURATIONS

3.1 Oscillator Types

The PIC18F87J72 family of devices can be operated in

eight different oscillator modes:

1. ECPLL OSC1/OSC2 as primary; ECPLL

oscillator with PLL enabled, CLKO on

RA6

2. EC OSC1/OSC2 as primary; external

clock with FOSC/4 output

3. HSPLL OSC1/OSC2 as primary; high-speed

crystal/resonator with software PLL

control

4. HS OSC1/OSC2 as primary; high-speed

crystal/resonator

5. INTPLL1 Internal oscillator block with software

PLL control, FOSC/4 output on RA6

and I/O on RA7

6. INTIO1 Internal oscillator block with FOSC/4

output on RA6 and I/O on RA7

7. INTPLL2 Internal oscillator block with software

PLL control and I/O on RA6 and RA7

8. INTIO2 Internal oscillator block with I/O on

RA6 and RA7

All of these modes are selected by the user by

programming the FOSC<2:0> Configuration bits.

In addition, PIC18F87J72 family devices can switch

between different clock sources, either under software

control or automatically under certain conditions. This

allows for additional power savings by managing

device clock speed in real time without resetting the

application.

The clock sources for the PIC18F87J72 family of

devices are shown in Figure 3-1.

FIGURE 3-1: PIC18F87J72 FAMILY CLOCK DIAGRAM

4 x PLL

FOSC<2:0>

Secondary Oscillator

T1OSCEN

Enable

Oscillator

T1OSO

T1OSI

Clock Source Option

for Other Modules

OSC1

OSC2

Sleep HSPLL, ECPLL, INTPLL

HS, EC

T1OSC

CPU

Peripherals

IDLEN

Postscaler

MUX

8 MHz

4 MHz

2 MHz

1 MHz

500 kHz

125 kHz

250 kHz

OSCCON<6:4>

111

110

101

100

011

010

001

000

31 kHz

INTRC

Source

Internal

Oscillator

Block

WDT, PWRT, FSCM

8 MHz

Internal Oscillator

(INTOSC)

OSCCON<6:4>

Clock

Control

OSCCON<1:0>

Source

8 MHz

31 kHz (INTRC)

OSCTUNE<7>

and Two-Speed Start-up

Primary Oscillator

OSCTUNE<6>

PIC18F87J72 FAMILY

DS39979A-page 26 Preliminary  2010 Microchip Technology Inc.

3.2 Control Registers

The OSCCON register (Register 3-1) controls the main

aspects of the device clock’s operation. It selects the

oscillator type to be used, which of the power-managed

modes to invoke and the output frequency of the

INTOSC source. It also provides status on the oscillators.

The OSCTUNE register (Register 3-2) controls the

tuning and operation of the internal oscillator block. It

also implements the PLLEN bits which control the

operation of the Phase Locked Loop (PLL) (see

Section 3.4.3 “PLL Frequency Multiplier”).

R/W-0 R/W-1 R/W-1 R/W-0 R(2) R-0 R/W-0 R/W-0

IDLEN IRCF2(3) IRCF1(3) IRCF0(3) OSTS IOFS SCS1(5) SCS0(5)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IDLEN: Idle Enable bit

1 = Device enters an Idle mode when a SLEEP instruction is executed

0 = Device enters Sleep mode when a SLEEP instruction is executed

bit 6-4 IRCF<2:0>: INTOSC Source Frequency Select bits(3)

111 = 8 MHz (INTOSC drives clock directly)

110 = 4 MHz (default)

101 = 2 MHz

100 = 1 MHz

011 = 500 kHz

010 = 250 kHz

001 = 125 kHz

000 = 31 kHz (from either INTOSC/256 or INTRC)(4)

bit 3 OSTS: Oscillator Start-up Timer Time-out Status bit(2)

1 = Oscillator Start-up Timer (OST) time-out has expired; primary oscillator is running

0 = Oscillator Start-up Timer (OST) time-out is running; primary oscillator is not ready

bit 2 IOFS: INTOSC Frequency Stable bit

1 = Fast RC oscillator frequency is stable

0 = Fast RC oscillator frequency is not stable

bit 1-0 SCS<1:0>: System Clock Select bits(5)

11 = Internal oscillator block

10 = Primary oscillator

01 = Timer1 oscillator

00 = Default primary oscillator (as defined by FOSC<2:0> Configuration bits)

Note 1: Default (legacy) SFR at this address; available when WDTCON<4> = 0.

2: Reset state depends on the state of the IESO Configuration bit.

3: Modifying these bits will cause an immediate clock frequency switch if the internal oscillator is providing

the device clocks.

4: Source selected by the INTSRC bit (OSCTUNE<7>), see text.

5: Modifying these bits will cause an immediate clock source switch.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 27

PIC18F87J72 FAMILY

3.3 Clock Sources and

Oscillator Switching

Essentially, PIC18F87J72 family devices have three

independent clock sources:

• Primary oscillators

• Secondary oscillators

• Internal oscillator

The primary oscillators can be thought of as the main

device oscillators. These are any external oscillators

connected to the OSC1 and OSC2 pins, and include

the External Crystal and Resonator modes and the

External Clock modes. If selected by the FOSC<2:0>

Configuration bits, the internal oscillator block (either

the 31 kHz INTRC or the 8 MHz INTOSC source) may

be considered a primary oscillator. The particular mode

is defined by the FOSC Configuration bits. The details

of these modes are covered in Section 3.4 “External

Oscillator Modes”.

The secondary oscillators are external clock sources

that are not connected to the OSC1 or OSC2 pins.

These sources may continue to operate even after the

controller is placed in a power-managed mode.

PIC18F87J72 family devices offer the Timer1 oscillator

as a secondary oscillator source. This oscillator, in all

power-managed modes, is often the time base for

functions such as a Real-Time Clock (RTC). The

Timer1 oscillator is discussed in greater detail in

Section 12.0 “Timer1 Module”.

In addition to being a primary clock source in some

circumstances, the internal oscillator is available as a

power-managed mode clock source. The INTRC

source is also used as the clock source for several

special features, such as the WDT and Fail-Safe Clock

Monitor. The internal oscillator block is discussed in

more detail in Section 3.5 “Internal Oscillator

Block”.

The PIC18F87J72 family includes features that allow

the device clock source to be switched from the main

oscillator, chosen by device configuration, to one of the

alternate clock sources. When an alternate clock

source is enabled, various power-managed operating

modes are available.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit

1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled)

0 = 31 kHz device clock derived from INTRC 31 kHz oscillator

bit 6 PLLEN: Frequency Multiplier PLL Enable bit

1 = PLL is enabled

0 = PLL is disabled

bit 5-0 TUN<5:0>: Fast RC Oscillator (INTOSC) Frequency Tuning bits

011111 = Maximum frequency

• •

000001

000000 = Center frequency. Fast RC oscillator is running at the calibrated frequency.

111111

• •

100000 = Minimum frequency

PIC18F87J72 FAMILY

DS39979A-page 28 Preliminary  2010 Microchip Technology Inc.

3.3.1 CLOCK SOURCE SELECTION

The System Clock Select bits, SCS<1:0>

(OSCCON<1:0>), select the clock source. The avail-

able clock sources are the primary clock defined by the

FOSC<2:0> Configuration bits, the secondary clock

(Timer1 oscillator) and the internal oscillator. The clock

source changes after one or more of the bits is written

to, following a brief clock transition interval.

The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)

bits indicate which clock source is currently providing

the device clock. The OSTS bit indicates that the

Oscillator Start-up Timer (OST) has timed out and the

primary clock is providing the device clock in primary

clock modes. The T1RUN bit indicates when the

Timer1 oscillator is providing the device clock in sec-

ondary clock modes. In power-managed modes, only

one of these bits will be set at any time. If neither of

these bits is set, the INTRC is providing the clock or the

internal oscillator has just started and is not yet stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-Managed Modes”.

3.3.1.1 System Clock Selection and Device

Resets

Since the SCS bits are cleared on all forms of Reset,

this means the primary oscillator defined by the

FOSC<2:0> Configuration bits is used as the primary

clock source on device Resets. This could either be the

internal oscillator block by itself or one of the other

primary clock source (HS, EC, HSPLL, ECPLL1/2 or

INTPLL1/2).

In those cases, when the internal oscillator block with-

out PLL, is the default clock on Reset, the Fast RC

oscillator (INTOSC) will be used as the device clock

source. It will initially start at 1 MHz, which is the

postscaler selection that corresponds to the Reset

value of the IRCF<2:0> bits (‘100’).

Regardless of which primary oscillator is selected,

INTRC will always be enabled on device power-up. It

serves as the clock source until the device has loaded

its configuration values from memory. It is at this point

that the FOSC Configuration bits are read and the

oscillator selection of the operational mode is made.

Note that either the primary clock source, or the internal

oscillator, will have two bit setting options for the possible

values of the SCS<1:0> bits at any given time.

3.3.2 OSCILLATOR TRANSITIONS

PIC18F87J72 family devices contain circuitry to

prevent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock switch. The length of this pause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 4.1.2 “Entering Power-Managed Modes”.

Note 1: The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP instruction will be ignored.

2: It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction or a very

long delay may occur while the Timer1

oscillator starts.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 29

PIC18F87J72 FAMILY

3.4 External Oscillator Modes

3.4.1 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS (HS MODES)

In HS or HSPLL Oscillator modes, a crystal or ceramic

resonator is connected to the OSC1 and OSC2 pins to

establish oscillation. Figure 3-2 shows the pin

connections.

The oscillator design requires the use of a crystal rated

for parallel resonant operation.

TABLE 3-1: CAPACITOR SELECTION FOR

CERAMIC RESONATORS

TABLE 3-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

FIGURE 3-2: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS OR HSPLL

CONFIGURATION)

Note: Use of a crystal rated for series resonant

operation may give a frequency out of the

crystal manufacturer’s specifications.

Typical Capacitor Values Used:

Mode Freq. OSC1 OSC2

HS 8.0 MHz

16.0 MHz

27 pF

22 pF

27 pF

22 pF

Capacitor values are for design guidance only.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application. Refer

to the following application notes for oscillator specific

information:

• AN588, “PIC® Microcontroller Oscillator Design

Guide”

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC® and PIC® Devices”

• AN849, “Basic PIC® Oscillator Design”

• AN943, “Practical PIC® Oscillator Analysis and

Design”

• AN949, “Making Your Oscillator Work”

See the notes following Table 3-2 for additional

information.

Osc Type Crystal

Freq.

Typical Capacitor Values

Tested:

C1 C2

HS 4 MHz 27 pF 27 pF

8 MHz 22 pF 22 pF

20 MHz 15 pF 15 pF

Capacitor values are for design guidance only.

Different capacitor values may be required to produce

acceptable oscillator operation. The user should test

the performance of the oscillator over the expected

VDD and temperature range for the application.

Refer to the Microchip application notes cited in

Table 3-1 for oscillator specific information. Also see

the notes following this table for additional

information.

Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up

time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

3: Rs may be required to avoid overdriving

crystals with low drive level specification.

4: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

Note 1: See Table 3-1 and Table 3-2 for initial values of

C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

Sleep

Logic

RS(2)

Internal

PIC18F87J72

PIC18F87J72 FAMILY

DS39979A-page 30 Preliminary  2010 Microchip Technology Inc.

3.4.2 EXTERNAL CLOCK INPUT

(EC MODES)

The EC and ECPLL Oscillator modes require an

external clock source to be connected to the OSC1 pin.

There is no oscillator start-up time required after a

Power-on Reset or after an exit from Sleep mode.

In the EC Oscillator mode, the oscillator frequency

divided by 4 is available on the OSC2 pin. This signal

may be used for test purposes or to synchronize other

logic. Figure 3-3 shows the pin connections for the EC

Oscillator mode.

FIGURE 3-3: EXTERNAL CLOCK

INPUT OPERATION

(EC CONFIGURATION)

An external clock source may also be connected to the

OSC1 pin in the HS mode, as shown in Figure 3-4. In

this configuration, the divide-by-4 output on OSC2 is

not available. Current consumption in this configuration

will be somewhat higher than EC mode, as the internal

oscillator’s feedback circuitry will be enabled (in EC

mode, the feedback circuit is disabled).

FIGURE 3-4: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

3.4.3 PLL FREQUENCY MULTIPLIER

A Phase Locked Loop (PLL) circuit is provided as an

option for users who want to use a lower frequency

oscillator circuit, or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be

useful for customers who are concerned with EMI due

to high-frequency crystals, or users who require higher

clock speeds from an internal oscillator.

3.4.3.1 HSPLL and ECPLL Modes

The HSPLL and ECPLL modes provide the ability to

selectively run the device at 4 times the external

oscillating source to produce frequencies up to

40 MHz.

The PLL is enabled by programming the FOSC<2:0>

Configuration bits to either ‘111’ (for ECPLL) or ‘101’

(for HSPLL). In addition, the PLLEN bit

(OSCTUNE<6>) must also be set. Clearing PLLEN

disables the PLL, regardless of the chosen oscillator

configuration. It also allows additional flexibility for

controlling the application’s clock speed in software.

FIGURE 3-5: PLL BLOCK DIAGRAM

3.4.3.2 PLL and INTOSC

The PLL is also available to the internal oscillator block

when the internal oscillator block is configured as the

primary clock source. In this configuration, the PLL is

enabled in software and generates a clock output of up

to 32 MHz. The operation of INTOSC with the PLL is

described in Section 3.5.2 “INTPLL Modes”.

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System PIC18F87J72

OSC1

OSC2

Open

Clock from

Ext. System

(HS Mode)

PIC18F87J72

MUX

VCO

Loop

Filter

OSC2

OSC1

PLL Enable (OSCTUNE)

FIN

FOUT

SYSCLK

Phase

Comparator

HSPLL or ECPLL (CONFIG2L)

4

HS or EC

Mode

 2010 Microchip Technology Inc. Preliminary DS39979A-page 31

PIC18F87J72 FAMILY

3.5 Internal Oscillator Block

The PIC18F87J72 family of devices includes an

internal oscillator block which generates two different

clock signals; either can be used as the microcon-

troller’s clock source. This may eliminate the need for

an external oscillator circuit on the OSC1 and/or OSC2

pins.

The main output is the Fast RC oscillator, or INTOSC,

an 8 MHz clock source which can be used to directly

drive the device clock. It also drives a postscaler, which

can provide a range of clock frequencies from 31 kHz

to 4 MHz. INTOSC is enabled when a clock frequency

from 125 kHz to 8 MHz is selected. The INTOSC out-

put can also be enabled when 31 kHz is selected,

depending on the INTSRC bit (OSCTUNE<7>).

The other clock source is the Internal RC (INTRC)

oscillator, which provides a nominal 31 kHz output.

INTRC is enabled if it is selected as the device clock

source. It is also enabled automatically when any of the

following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 26.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTOSC

with postscaler or INTRC direct) is selected by config-

uring the IRCF bits of the OSCCON register. The

default frequency on device Resets is 4 MHz.

3.5.1 INTIO MODES

Using the internal oscillator as the clock source elimi-

nates the need for up to two external oscillator pins,

which can then be used for digital I/O. Two distinct

oscillator configurations, which are determined by the

FOSC Configuration bits, are available:

• In INTIO1 mode, the OSC2 pin outputs FOSC/4

while OSC1 functions as RA7 (see Figure 3-6) for

digital input and output.

• In INTIO2 mode, OSC1 functions as RA7 and

OSC2 functions as RA6 (see Figure 3-7), both for

digital input and output.

FIGURE 3-6: INTIO1 OSCILLATOR MODE

FIGURE 3-7: INTIO2 OSCILLATOR MODE

3.5.2 INTPLL MODES

The 4x Phase Locked Loop (PLL) can be used with the

internal oscillator block to produce faster device clock

speeds than are normally possible with the internal

oscillator sources. When enabled, the PLL produces a

clock speed of 16 MHz or 32 MHz.

PLL operation is controlled through software. The con-

trol bit, PLLEN (OSCTUNE<6>), is used to enable or

disable its operation. The PLL is available only to

INTOSC when the device is configured to use one of

the INTPLL modes as the primary clock source

(FOSC<2:0> = 011 or 001). Additionally, the PLL will

only function when the selected output frequency is

either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110).

Like the INTIO modes, there are two distinct INTPLL

modes available:

• In INTPLL1 mode, the OSC2 pin outputs FOSC/4,

while OSC1 functions as RA7 for digital input and

output. Externally, this is identical in appearance

to INTIO1 (Figure 3-6).

• In INTPLL2 mode, OSC1 functions as RA7 and

OSC2 functions as RA6, both for digital input and

output. Externally, this is identical to INTIO2

(Figure 3-7).

OSC2

FOSC/4

I/O (OSC1)

RA7

PIC18F87J72

I/O (OSC2)

RA6

I/O (OSC1)

RA7

PIC18F87J72

PIC18F87J72 FAMILY

DS39979A-page 32 Preliminary  2010 Microchip Technology Inc.

3.5.3 INTERNAL OSCILLATOR OUTPUT

FREQUENCY AND TUNING

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of 8 MHz. It

can be adjusted in the user’s application by writing to

TUN<5:0> (OSCTUNE<5:0>) in the OSCTUNE

When the OSCTUNE register is modified, the INTOSC

frequency will begin shifting to the new frequency. The

oscillator will stabilize within 1 ms. Code execution

continues during this shift and there is no indication that

the shift has occurred.

The INTRC oscillator operates independently of the

INTOSC source. Any changes in INTOSC across

voltage and temperature are not necessarily reflected

by changes in INTRC or vice versa. The frequency of

INTRC is not affected by OSCTUNE.

3.5.4 INTOSC FREQUENCY DRIFT

The INTOSC frequency may drift as VDD or tempera-

ture changes and can affect the controller operation in

a variety of ways. It is possible to adjust the INTOSC

frequency by modifying the value in the OSCTUNE

effect on the INTRC clock source frequency.

Tuning INTOSC requires knowing when to make the

adjustment, in which direction it should be made, and in

some cases, how large a change is needed. Three

compensation techniques are shown here.

3.5.4.1 Compensating with the EUSART

An adjustment may be required when the EUSART

begins to generate framing errors or receives data with

errors while in Asynchronous mode. Framing errors

indicate that the device clock frequency is too high. To

adjust for this, decrement the value in OSCTUNE to

reduce the clock frequency. On the other hand, errors

in data may suggest that the clock speed is too low. To

compensate, increment OSCTUNE to increase the

clock frequency.

3.5.4.2 Compensating with the Timers

This technique compares device clock speed to some

reference clock. Two timers may be used; one timer is

clocked by the peripheral clock, while the other is

clocked by a fixed reference source, such as the

Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is much greater than expected, then the internal

oscillator block is running too fast. To adjust for this,

decrement the OSCTUNE register.

3.5.4.3 Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (i.e., AC power

frequency). The time of the first event is captured in the

CCPRxH:CCPRxL registers and is recorded for use

later. When the second event causes a capture, the

time of the first event is subtracted from the time of the

second event. Since the period of the external event is

known, the time difference between events can be

calculated.

If the measured time is much greater than the

calculated time, the internal oscillator block is running

too fast. To compensate, decrement the OSCTUNE

calculated time, the internal oscillator block is running

too slow. To compensate, increment the OSCTUNE

 2010 Microchip Technology Inc. Preliminary DS39979A-page 33

PIC18F87J72 FAMILY

3.6 Effects of Power-Managed Modes

on the Various Clock Sources

When PRI_IDLE mode is selected, the designated pri-

mary oscillator continues to run without interruption.

For all other power-managed modes, the oscillator

using the OSC1 pin is disabled. The OSC1 pin (and

OSC2 pin if used by the oscillator) will stop oscillating.

In secondary clock modes (SEC_RUN and

SEC_IDLE), the Timer1 oscillator is operating and

providing the device clock. The Timer1 oscillator may

also run in all power-managed modes if required to

clock Timer1 or Timer3.

In RC_RUN and RC_IDLE modes, the internal

oscillator provides the device clock source. The 31 kHz

INTRC output can be used directly to provide the clock

and may be enabled to support various special

features, regardless of the power-managed mode (see

Section 26.2 “Watchdog Timer (WDT)” through

Section 26.5 “Fail-Safe Clock Monitor” for more

information on WDT, Fail-Safe Clock Monitor and

Two-Speed Start-up).

If the Sleep mode is selected, all clock sources are

stopped. Since all the transistor switching currents

have been stopped, Sleep mode achieves the lowest

current consumption of the device (only leakage

currents).

Enabling any on-chip feature that will operate during

Sleep will increase the current consumed during Sleep.

The INTRC is required to support WDT operation. The

Timer1 oscillator may be operating to support a Real-

Time Clock (RTC). Other features may be operating

that do not require a device clock source (i.e., MSSP

slave, INTx pins and others). Peripherals that may add

significant current consumption are listed in

Section 29.2 “DC Characteristics: Power-Down and

Supply Current PIC18F87J72 Family (Industrial)”.

3.7 Power-up Delays

Power-up delays are controlled by two timers, so that

no external Reset circuitry is required for most applica-

tions. The delays ensure that the device is kept in

Reset until the device power supply is stable under nor-

mal circumstances, and the primary clock is operating

and stable. For additional information on power-up

delays, see Section 5.6 “Power-up Timer (PWRT)”.

The first timer is the Power-up Timer (PWRT), which

provides a fixed delay on power-up (parameter 33,

Table 29-11); it is always enabled.

The second timer is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the

crystal oscillator is stable (HS modes). The OST does

this by counting 1024 oscillator cycles before allowing

the oscillator to clock the device.

There is a delay of interval, TCSD (parameter 38,

Table 29-11), following POR, while the controller

becomes ready to execute instructions.

TABLE 3-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE

Oscillator Mode OSC1 Pin OSC2 Pin

EC, ECPLL Floating, pulled by external clock At logic low (clock/4 output)

HS, HSPLL Feedback inverter disabled at quiescent

voltage level

Feedback inverter disabled at quiescent

voltage level

INTOSC, INTPLL1/2 I/O pin, RA6, direction controlled by

TRISA<6>

I/O pin, RA6, direction controlled by

TRISA<7>

Note: See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.

PIC18F87J72 FAMILY

DS39979A-page 34 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 35

PIC18F87J72 FAMILY

4.0 POWER-MANAGED MODES

The PIC18F87J72 family devices provide the ability to

manage power consumption by simply managing clock-

ing to the CPU and the peripherals. In general, a lower

clock frequency and a reduction in the number of circuits

being clocked constitutes lower consumed power. For

the sake of managing power in an application, there are

three primary modes of operation:

• Run mode

• Idle mode

• Sleep mode

These modes define which portions of the device are

clocked and at what speed. The Run and Idle modes

may use any of the three available clock sources

(primary, secondary or internal oscillator block); the

Sleep mode does not use a clock source.

The power-managed modes include several

power-saving features offered on previous PIC®

devices. One is the clock switching feature, offered in

other PIC18 devices, allowing the controller to use the

Timer1 oscillator in place of the primary oscillator. Also

included is the Sleep mode, offered by all PIC devices,

where all device clocks are stopped.

4.1 Selecting Power-Managed Modes

Selecting a power-managed mode requires two

decisions: if the CPU is to be clocked or not and which

clock source is to be used. The IDLEN bit

(OSCCON<7>) controls CPU clocking, while the

SCS<1:0> bits (OSCCON<1:0>) select the clock

source. The individual modes, bit settings, clock

sources and affected modules are summarized in

Table 4-1.

4.1.1 CLOCK SOURCES

The SCS<1:0> bits allow the selection of one of three

clock sources for power-managed modes. They are:

• the primary clock, as defined by the FOSC<2:0>

Configuration bits

• the secondary clock (Timer1 oscillator)

• the internal oscillator

4.1.2 ENTERING POWER-MANAGED

MODES

Switching from one power-managed mode to another

begins by loading the OSCCON register. The

SCS<1:0> bits select the clock source and determine

which Run or Idle mode is to be used. Changing these

bits causes an immediate switch to the new clock

source, assuming that it is running. The switch may

also be subject to clock transition delays. These are

discussed in Section 4.1.3 “Clock Transitions and

Status Indicators” and subsequent sections.

Entry to the power-managed Idle or Sleep modes is

triggered by the execution of a SLEEP instruction. The

actual mode that results depends on the status of the

IDLEN bit.

Depending on the current mode and the mode being

switched to, a change to a power-managed mode does

not always require setting all of these bits. Many

transitions may be done by changing the oscillator

select bits, or changing the IDLEN bit, prior to issuing a

SLEEP instruction. If the IDLEN bit is already

configured correctly, it may only be necessary to

perform a SLEEP instruction to switch to the desired

mode.

TABLE 4-1: POWER-MANAGED MODES

Mode

OSCCON Bits Module Clocking

Available Clock and Oscillator Source

IDLEN<7>(1) SCS<1:0> CPU Peripherals

Sleep 0N/A Off Off None – All clocks are disabled

PRI_RUN N/A 10 Clocked Clocked Primary – HS, EC, HSPLL, ECPLL;

this is the normal full-power execution mode

SEC_RUN N/A 01 Clocked Clocked Secondary – Timer1 Oscillator

RC_RUN N/A 11 Clocked Clocked Internal Oscillator

PRI_IDLE 110Off Clocked Primary – HS, EC, HSPLL, ECPLL

SEC_IDLE 101Off Clocked Secondary – Timer1 Oscillator

RC_IDLE 111Off Clocked Internal Oscillator

Note 1: IDLEN reflects its value when the SLEEP instruction is executed.

PIC18F87J72 FAMILY

DS39979A-page 36 Preliminary  2010 Microchip Technology Inc.

4.1.3 CLOCK TRANSITIONS AND STATUS

INDICATORS

The length of the transition between clock sources is

the sum of two cycles of the old clock source and three

to four cycles of the new clock source. This formula

assumes that the new clock source is stable.

Two bits indicate the current clock source and its

status: OSTS (OSCCON<3>) and T1RUN

(T1CON<6>). In general, only one of these bits will be

set while in a given power-managed mode. When the

OSTS bit is set, the primary clock is providing the

device clock. When the T1RUN bit is set, the Timer1

oscillator is providing the clock. If neither of these bits

is set, INTRC is clocking the device.

4.1.4 MULTIPLE SLEEP COMMANDS

The power-managed mode that is invoked with the

SLEEP instruction is determined by the setting of the

IDLEN bit at the time the instruction is executed. If

another SLEEP instruction is executed, the device will

enter the power-managed mode specified by IDLEN at

that time. If IDLEN has changed, the device will enter

the new power-managed mode specified by the new

setting.

4.2 Run Modes

In the Run modes, clocks to both the core and

peripherals are active. The difference between these

modes is the clock source.

4.2.1 PRI_RUN MODE

The PRI_RUN mode is the normal, full-power execu-

tion mode of the microcontroller. This is also the default

mode upon a device Reset unless Two-Speed Start-up

is enabled (see Section 26.4 “Two-Speed Start-up”

for details). In this mode, the OSTS bit is set (see

Section 3.2 “Control Registers”).

4.2.2 SEC_RUN MODE

The SEC_RUN mode is the compatible mode to the

“clock switching” feature offered in other PIC18

devices. In this mode, the CPU and peripherals are

clocked from the Timer1 oscillator. This gives users the

option of lower power consumption while still using a

high-accuracy clock source.

SEC_RUN mode is entered by setting the SCS<1:0>

bits to ‘01’. The device clock source is switched to the

Timer1 oscillator (see Figure 4-1), the primary oscilla-

tor is shut down, the T1RUN bit (T1CON<6>) is set and

the OSTS bit is cleared.

Note: Executing a SLEEP instruction does not

necessarily place the device into Sleep

mode. It acts as the trigger to place the

controller into either the Sleep mode, or

one of the Idle modes, depending on the

setting of the IDLEN bit.

Note: The Timer1 oscillator should already be

running prior to entering SEC_RUN mode.

If the T1OSCEN bit is not set when the

SCS<1:0> bits are set to ‘01’, entry to

SEC_RUN mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, device clocks will be delayed until

the oscillator has started. In such situa-

tions, initial oscillator operation is far from

stable and unpredictable operation may

result.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 37

PIC18F87J72 FAMILY

On transitions from SEC_RUN mode to PRI_RUN

mode, the peripherals and CPU continue to be clocked

from the Timer1 oscillator while the primary clock is

started. When the primary clock becomes ready, a

clock switch back to the primary clock occurs (see

Figure 4-2). When the clock switch is complete, the

T1RUN bit is cleared, the OSTS bit is set and the

primary clock is providing the clock. The IDLEN and

SCS bits are not affected by the wake-up; the Timer1

oscillator continues to run.

FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE

FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Program

T1OSI

Counter

Clock

CPU

Clock

PC + 2PC

123

n-1

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

T1OSI

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS<1:0> Bits Changed

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition

TOST(1)

PIC18F87J72 FAMILY

DS39979A-page 38 Preliminary  2010 Microchip Technology Inc.

4.2.3 RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator; the primary clock is

shut down. This mode provides the best power conser-

vation of all the Run modes while still executing code.

It works well for user applications which are not highly

timing-sensitive or do not require high-speed clocks at

all times.

This mode is entered by setting SCS bits to ‘11’. When

the clock source is switched to the INTRC (see

Figure 4-3), the primary oscillator is shut down and the

OSTS bit is cleared.

On transitions from RC_RUN mode to PRI_RUN mode,

the device continues to be clocked from the INTRC

while the primary clock is started. When the primary

clock becomes ready, a clock switch to the primary

clock occurs (see Figure 4-4). When the clock switch is

complete, the OSTS bit is set and the primary clock is

providing the device clock. The IDLEN and SCS bits

are not affected by the switch. The INTRC source will

continue to run if either the WDT or the Fail-Safe Clock

Monitor is enabled.

FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE

FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE

Q4Q3Q2

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2PC

123 n-1n

Clock Transition

Q4Q3Q2 Q1 Q3Q2

PC + 4

Q1 Q3 Q4

OSC1

Peripheral

Program PC

INTRC

PLL Clock

PC + 4

Output

Q3 Q4 Q1

CPU Clock

PC + 2

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

SCS<1:0> Bits Changed

TPLL(1)

12 n-1n

Clock

OSTS Bit Set

Transition

TOST(1)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 39

PIC18F87J72 FAMILY

4.3 Sleep Mode

The power-managed Sleep mode is identical to the leg-

acy Sleep mode offered in all other PIC devices. It is

entered by clearing the IDLEN bit (the default state on

device Reset) and executing the SLEEP instruction.

This shuts down the selected oscillator (Figure 4-5). All

clock source status bits are cleared.

Entering the Sleep mode from any other mode does not

require a clock switch. This is because no clocks are

needed once the controller has entered Sleep. If the

WDT is selected, the INTRC source will continue to

operate. If the Timer1 oscillator is enabled, it will also

continue to run.

When a wake event occurs in Sleep mode (by interrupt,

Reset or WDT time-out), the device will not be clocked

until the clock source selected by the SCS<1:0> bits

becomes ready (see Figure 4-6), or it will be clocked

from the internal oscillator if either the Two-Speed

Start-up or the Fail-Safe Clock Monitor is enabled (see

Section 26.0 “Special Features of the CPU”). In

either case, the OSTS bit is set when the primary clock

is providing the device clocks. The IDLEN and SCS bits

are not affected by the wake-up.

4.4 Idle Modes

The Idle modes allow the controller’s CPU to be

selectively shut down while the peripherals continue to

operate. Selecting a particular Idle mode allows users

to further manage power consumption.

If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is

executed, the peripherals will be clocked from the clock

source selected using the SCS<1:0> bits; however, the

CPU will not be clocked. The clock source status bits are

not affected. Setting IDLEN and executing a SLEEP

instruction provides a quick method of switching from a

given Run mode to its corresponding Idle mode.

If the WDT is selected, the INTRC source will continue

to operate. If the Timer1 oscillator is enabled, it will also

continue to run.

Since the CPU is not executing instructions, the only

exits from any of the Idle modes are by interrupt, WDT

time-out or a Reset. When a wake event occurs, CPU

execution is delayed by an interval of TCSD

(parameter 38, Table 29-11) while it becomes ready to

execute code. When the CPU begins executing code,

it resumes with the same clock source for the current

Idle mode. For example, when waking from RC_IDLE

mode, the internal oscillator block will clock the CPU

and peripherals (in other words, RC_RUN mode). The

IDLEN and SCS bits are not affected by the wake-up.

While in any Idle mode or the Sleep mode, a WDT

time-out will result in a WDT wake-up to the Run mode

currently specified by the SCS<1:0> bits.

FIGURE 4-5: TRANSITION TIMING FOR ENTRY TO SLEEP MODE

FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)

Q4Q3Q2

OSC1

Peripheral

Sleep

Program

Q1Q1

Counter

Clock

CPU

Clock

PC + 2PC

Q3 Q4 Q1 Q2

OSC1

Peripheral

Program PC

PLL Clock

Q3 Q4

Output

CPU Clock

Q1 Q2 Q3 Q4 Q1 Q2

Clock

Counter PC + 6PC + 4

Q1 Q2 Q3 Q4

Wake Event

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

TOST(1) TPLL(1)

OSTS Bit Set

PC + 2

PIC18F87J72 FAMILY

DS39979A-page 40 Preliminary  2010 Microchip Technology Inc.

4.4.1 PRI_IDLE MODE

This mode is unique among the three low-power Idle

modes, in that it does not disable the primary device

clock. For timing-sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm up” or transition from another

oscillator.

PRI_IDLE mode is entered from PRI_RUN mode by

setting the IDLEN bit and executing a SLEEP instruc-

tion. If the device is in another Run mode, set IDLEN

first, then set the SCS bits to ‘10’ and execute SLEEP.

Although the CPU is disabled, the peripherals continue

to be clocked from the primary clock source specified

by the FOSC<1:0> Configuration bits. The OSTS bit

remains set (see Figure 4-7).

When a wake event occurs, the CPU is clocked from the

primary clock source. A delay of interval, TCSD, is

required between the wake event and when code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the

wake-up, the OSTS bit remains set. The IDLEN and

SCS bits are not affected by the wake-up (see

Figure 4-8).

4.4.2 SEC_IDLE MODE

In SEC_IDLE mode, the CPU is disabled but the

peripherals continue to be clocked from the Timer1

oscillator. This mode is entered from SEC_RUN by set-

ting the IDLEN bit and executing a SLEEP instruction. If

the device is in another Run mode, set IDLEN first, then

set SCS<1:0> to ‘01’ and execute SLEEP. When the

clock source is switched to the Timer1 oscillator, the

primary oscillator is shut down, the OSTS bit is cleared

and the T1RUN bit is set.

When a wake event occurs, the peripherals continue to

be clocked from the Timer1 oscillator. After an interval

of TCSD, following the wake event, the CPU begins exe-

cuting code being clocked by the Timer1 oscillator. The

IDLEN and SCS bits are not affected by the wake-up;

the Timer1 oscillator continues to run (see Figure 4-8).

FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE

FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE

Note: The Timer1 oscillator should already be

running prior to entering SEC_IDLE mode.

If the T1OSCEN bit is not set when the

SLEEP instruction is executed, the SLEEP

instruction will be ignored and entry to

SEC_IDLE mode will not occur. If the

Timer1 oscillator is enabled, but not yet

running, peripheral clocks will be delayed

until the oscillator has started. In such

situations, initial oscillator operation is far

from stable and unpredictable operation

may result.

Peripheral

Program PC PC + 2

OSC1

Q3 Q4 Q1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program PC

CPU Clock

Q1 Q3 Q4

Clock

Counter

Wake Event

TCSD

 2010 Microchip Technology Inc. Preliminary DS39979A-page 41

PIC18F87J72 FAMILY

4.4.3 RC_IDLE MODE

In RC_IDLE mode, the CPU is disabled but the periph-

erals continue to be clocked from the internal oscillator.

This mode allows for controllable power conservation

during Idle periods.

From RC_RUN, this mode is entered by setting the

IDLEN bit and executing a SLEEP instruction. If the

device is in another Run mode, first set IDLEN, then

clear the SCS bits and execute SLEEP. When the clock

source is switched to the INTRC, the primary oscillator

is shut down and the OSTS bit is cleared.

When a wake event occurs, the peripherals continue to

be clocked from the INTOSC. After a delay of TCSD,

following the wake event, the CPU begins executing

code being clocked by the INTOSC. The IDLEN and

SCS bits are not affected by the wake-up. The INTOSC

source will continue to run if either the WDT or the

Fail-Safe Clock Monitor is enabled.

4.5 Exiting Idle and Sleep Modes

An exit from Sleep mode, or any of the Idle modes, is

triggered by an interrupt, a Reset or a WDT time-out.

This section discusses the triggers that cause exits

from power-managed modes. The clocking subsystem

actions are discussed in each of the power-managed

mode sections (see Section 4.2 “Run Modes”,

Section 4.3 “Sleep Mode” and Section 4.4 “Idle

Modes”).

4.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit from an Idle mode, or the Sleep mode, to

a Run mode. To enable this functionality, an interrupt

source must be enabled by setting its enable bit in one

of the INTCON or PIE registers. The exit sequence is

initiated when the corresponding interrupt flag bit is set.

On all exits from Idle or Sleep modes, by interrupt, code

execution branches to the interrupt vector if the

GIE/GIEH bit (INTCON<7>) is set. Otherwise, code

execution continues or resumes without branching

(see Section 9.0 “Interrupts”).

A fixed delay of interval, TCSD, following the wake event

is required when leaving Sleep and Idle modes. This

delay is required for the CPU to prepare for execution.

Instruction execution resumes on the first clock cycle

following this delay.

4.5.2 EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions depending

on which power-managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in an exit from the

power-managed mode (see Section 4.2 “Run

Modes” and Section 4.3 “Sleep Mode”). If the device

is executing code (all Run modes), the time-out will

result in a WDT Reset (see Section 26.2 “Watchdog

Timer (WDT)”).

The Watchdog Timer and postscaler are cleared by one

of the following events:

• executing a SLEEP or CLRWDT instruction

• the loss of a currently selected clock source (if the

Fail-Safe Clock Monitor is enabled)

4.5.3 EXIT BY RESET

Exiting an Idle or Sleep mode by Reset automatically

forces the device to run from the INTRC.

4.5.4 EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power-managed modes do not

invoke the OST at all. There are two cases:

• PRI_IDLE mode, where the primary clock source

is not stopped; and

• the primary clock source is either the EC or

ECPLL mode.

In these instances, the primary clock source either

does not require an oscillator start-up delay, since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (EC). However, a

fixed delay of interval, T

CSD, following the wake event

is still required when leaving Sleep and Idle modes to

allow the CPU to prepare for execution. Instruction

execution resumes on the first clock cycle following this

delay.

PIC18F87J72 FAMILY

DS39979A-page 42 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 43

PIC18F87J72 FAMILY

5.0 RESET

The PIC18F87J72 family of devices differentiates

between various kinds of Reset:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR Reset during power-managed modes

• Watchdog Timer (WDT) Reset (during

execution)

• Brown-out Reset (BOR)

• Configuration Mismatch (CM)

•RESET Instruction

• Stack Full Reset

• Stack Underflow Reset

This section discusses Resets generated by MCLR,

POR and BOR, and covers the operation of the various

start-up timers. Stack Reset events are covered in

Section 6.1.4.4 “Stack Full and Underflow Resets”.

WDT Resets are covered in Section 26.2 “Watchdog

Timer (WDT)”.

A simplified block diagram of the on-chip Reset circuit

is shown in Figure 5-1.

5.1 RCON Register

Device Reset events are tracked through the RCON

occurred. In most cases, these bits can only be set by

the event and must be cleared by the application after

the event. The state of these flag bits, taken together,

can be read to indicate the type of Reset that just

occurred. This is described in more detail in

Section 5.7 “Reset State of Registers”.

The RCON register also has a control bit for setting

interrupt priority (IPEN). Interrupt priority is discussed

in Section 9.0 “Interrupts”.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

VDD

WDT

Time-out

VDD Rise

Detect

PWRT

INTRC

POR Pulse

PWRT Chip_Reset

11-Bit Ripple Counter

Brown-out

Reset(1)

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

Sleep

IDLE

65.5 ms (typical)

Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip

voltage regulator when there is insufficient source voltage to maintain regulation.

Configuration Word

Mismatch

32 s (typical)

PIC18F87J72 FAMILY

DS39979A-page 44 Preliminary  2010 Microchip Technology Inc.

R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN —CMRI TO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16XXXX Compatibility mode)

bit 6 Unimplemented: Read as ‘0’

bit 5 CM: Configuration Mismatch (CM) Flag bit

1 = A Configuration Mismatch has not occurred

0 = A Configuration Mismatch has occurred (Must be set in software after a Configuration Mismatch

Reset occurs.)

bit 4 RI: RESET Instruction Flag bit

1 =The RESET instruction was not executed (set by firmware only)

0 =The RESET instruction was executed causing a device Reset (must be set in software after a

Brown-out Reset occurs)

bit 3 TO: Watchdog Time-out Flag bit

1 = Set by power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 2 PD: Power-Down Detection Flag bit

1 = Set by power-up or by the CLRWDT instruction

0 = Set by execution of the SLEEP instruction

bit 1 POR: Power-on Reset Status bit

1 = A Power-on Reset has not occurred (set by firmware only)

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = A Brown-out Reset has not occurred (set by firmware only)

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent

Power-on Resets may be detected.

2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting

BOR” for more information.

3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to

‘1’ by software immediately after a Power-on Reset).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 45

PIC18F87J72 FAMILY

5.2 Master Clear (MCLR)

The MCLR pin provides a method for triggering a hard

external Reset of the device. A Reset is generated by

holding the pin low. PIC18 extended microcontroller

devices have a noise filter in the MCLR Reset path

which detects and ignores small pulses.

The MCLR pin is not driven low by any internal Resets,

including the WDT.

5.3 Power-on Reset (POR)

A Power-on Reset condition is generated on-chip

whenever VDD rises above a certain threshold. This

allows the device to start in the initialized state when

VDD is adequate for operation.

To take advantage of the POR circuitry, tie the MCLR

pin through a resistor (1 k to 10 k) to VDD. This will

eliminate external RC components usually needed to

create a Power-on Reset delay. A minimum rise rate for

VDD is specified (parameter D004). For a slow rise

time, see Figure 5-2.

When the device starts normal operation (i.e., exits the

Reset condition), device operating parameters

(voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

Power-on Reset events are captured by the POR bit

(RCON<1>). The state of the bit is set to ‘0’ whenever

a Power-on Reset occurs; it does not change for any

other Reset event. POR is not reset to ‘1’ by any

hardware event. To capture multiple events, the user

manually resets the bit to ‘1’ in software following any

Power-on Reset.

5.4 Brown-out Reset (BOR)

The PIC18F87J72 family of devices incorporates a

simple BOR function when the internal regulator is

enabled (ENVREG pin is tied to VDD). The voltage reg-

ulator will trigger a Brown-out Reset when output of the

regulator to the device core approaches the voltage at

which the device is unable to run at full speed. The

BOR circuit also keeps the device in Reset as VDD

rises, until the regulator’s output level is sufficient for

full-speed operation.

Once a BOR has occurred, the Power-up Timer will

keep the chip in Reset for TPWRT (parameter 33). If

VDD drops below the threshold for full-speed operation

while the Power-up Timer is running, the chip will go

back into a Brown-out Reset and the Power-up Timer

will be initialized. Once VDD rises to the point where

regulator output is sufficient, the Power-up Timer will

execute the additional time delay.

FIGURE 5-2: EXTERNAL POWER-ON

RESET CIRCUIT (FOR

SLOW VDD POWER-UP)

5.4.1 DETECTING BOR

The BOR bit always resets to ‘0’ on any Brown-out

Reset or Power-on Reset event. This makes it difficult

to determine if a Brown-out Reset event has occurred

just by reading the state of BOR alone. A more reliable

method is to simultaneously check the state of both

POR and BOR. This assumes that the POR bit is reset

to ‘1’ in software immediately after any Power-on Reset

event. If BOR is ‘0’ while POR is ‘1’, it can be reliably

assumed that a Brown-out Reset event has occurred.

If the voltage regulator is disabled, Brown-out Reset

functionality is disabled. In this case, the BOR bit

cannot be used to determine a Brown-out Reset event.

The BOR bit is still cleared by a Power-on Reset event.

5.5 Configuration Mismatch (CM)

The Configuration Mismatch (CM) Reset is designed to

detect, and attempt to recover from, random memory

corrupting events. These include Electrostatic

Discharge (ESD) events that can cause widespread,

single bit changes throughout the device and result in

catastrophic failure.

In PIC18F87J72 family Flash devices, the device

Configuration registers (located in the configuration

memory space) are continuously monitored during

operation by comparing their values to complimentary

shadow registers. If a mismatch is detected between

the two sets of registers, a CM Reset automatically

occurs. These events are captured by the CM bit

(RCON<5>). The state of the bit is set to ‘0’ whenever

a CM event occurs. The bit does not change for any

other Reset event.

Note 1: External Power-on Reset circuit is required

only if the VDD power-up slope is too slow.

The diode, D, helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k is recommended to make sure that

the voltage drop across R does not violate

the device’s electrical specification.

3: R1  1 k will limit any current flowing into

MCLR from external capacitor, C, in the event

of MCLR/VPP pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

VDD

PIC18F87J72

PIC18F87J72 FAMILY

DS39979A-page 46 Preliminary  2010 Microchip Technology Inc.

5.6 Power-up Timer (PWRT)

PIC18F87J72 family devices incorporate an on-chip

Power-up Timer (PWRT) to help regulate the Power-on

Reset process. The PWRT is always enabled. The

main function is to ensure that the device voltage is

stable before code is executed.

The Power-up Timer (PWRT) of the PIC18F87J72 fam-

ily devices is an 11-bit counter which uses the INTRC

source as the clock input. This yields an approximate

time interval of 2048 x 32 s = 65.6 ms. While the

PWRT is counting, the device is held in Reset.

The power-up time delay depends on the INTRC clock

and will vary from chip to chip due to temperature and

process variation. See DC Parameter 33 for details.

5.6.1 TIME-OUT SEQUENCE

If enabled, the PWRT time-out is invoked after the POR

pulse has cleared. The total time-out will vary based on

the status of the PWRT. Figure 5-3, Figure 5-4,

Figure 5-5 and Figure 5-6 all depict time-out

sequences on power-up with the Power-up Timer

enabled.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the PWRT will expire. Bringing

MCLR high will begin execution immediately

(Figure 5-5). This is useful for testing purposes, or to

synchronize more than one PIC18FXXXX device

operating in parallel.

FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)

FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

 2010 Microchip Technology Inc. Preliminary DS39979A-page 47

PIC18F87J72 FAMILY

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

TPWRT

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

INTERNAL RESET

0V 1V

3.3V

TPWRT

PIC18F87J72 FAMILY

DS39979A-page 48 Preliminary  2010 Microchip Technology Inc.

5.7 Reset State of Registers

Most registers are unaffected by a Reset. Their status

is unknown on POR and unchanged by all other

Resets. The other registers are forced to a “Reset

state” depending on the type of Reset that occurred.

Most registers are not affected by a WDT wake-up,

since this is viewed as the resumption of normal

operation. Status bits from the RCON register, RI, TO,

PD, POR and BOR, are set or cleared differently in

different Reset situations, as indicated in Table 5-1.

These bits are used in software to determine the nature

of the Reset.

Table 5-2 describes the Reset states for all of the

Special Function Registers. These are categorized by

Power-on and Brown-out Resets, Master Clear and

WDT Resets and WDT wake-ups.

TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR

RCON REGISTER

Condition Program

Counter(1)

RCON Register STKPTR Register

RI TO PD POR BOR STKFUL STKUNF

Power-on Reset 0000h 11100 0 0

RESET Instruction 0000h 0uuuu u u

Brown-out Reset 0000h 111u0 u u

MCLR during power-managed

Run modes

0000h u1uuu u u

MCLR during power-managed

Idle modes and Sleep mode

0000h u10uu u u

WDT time-out during full power

or power-managed Run modes

0000h u0uuu u u

MCLR during full power

execution

0000h uuuuu u u

Stack Full Reset (STVREN = 1) 0000h uuuuu 1 u

Stack Underflow Reset

(STVREN = 1)

0000h uuuuu u 1

Stack Underflow Error (not an

actual Reset, STVREN = 0)

0000h uuuuu u 1

WDT time-out during

power-managed Idle or Sleep

modes

PC + 2 u00uu u u

Interrupt exit from

power-managed modes

PC + 2 uu0uu u u

Legend: u = unchanged

Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 49

PIC18F87J72 FAMILY

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

TOSU PIC18F8XJ72 ---0 0000 ---0 0000 ---0 uuuu(1)

TOSH PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu(1)

TOSL PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu(1)

STKPTR PIC18F8XJ72 uu-0 0000 00-0 0000 uu-u uuuu(1)

PCLATU PIC18F8XJ72 ---0 0000 ---0 0000 ---u uuuu

PCLATH PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

PCL PIC18F8XJ72 0000 0000 0000 0000 PC + 2(2)

TBLPTRU PIC18F8XJ72 --00 0000 --00 0000 --uu uuuu

TBLPTRH PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TBLPTRL PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TABLAT PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

PRODH PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

PRODL PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

INTCON PIC18F8XJ72 0000 000x 0000 000u uuuu uuuu(3)

INTCON2 PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu(3)

INTCON3 PIC18F8XJ72 1100 0000 1100 0000 uuuu uuuu(3)

INDF0 PIC18F8XJ72 N/A N/A N/A

POSTINC0 PIC18F8XJ72 N/A N/A N/A

POSTDEC0 PIC18F8XJ72 N/A N/A N/A

PREINC0 PIC18F8XJ72 N/A N/A N/A

PLUSW0 PIC18F8XJ72 N/A N/A N/A

FSR0H PIC18F8XJ72 ---- xxxx ---- uuuu ---- uuuu

FSR0L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

WREG PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

INDF1 PIC18F8XJ72 N/A N/A N/A

POSTINC1 PIC18F8XJ72 N/A N/A N/A

POSTDEC1 PIC18F8XJ72 N/A N/A N/A

PREINC1 PIC18F8XJ72 N/A N/A N/A

PLUSW1 PIC18F8XJ72 N/A N/A N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 50 Preliminary  2010 Microchip Technology Inc.

FSR1H PIC18F8XJ72 ---- xxxx ---- uuuu ---- uuuu

FSR1L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

BSR PIC18F8XJ72 ---- 0000 ---- 0000 ---- uuuu

INDF2 PIC18F8XJ72 N/A N/A N/A

POSTINC2 PIC18F8XJ72 N/A N/A N/A

POSTDEC2 PIC18F8XJ72 N/A N/A N/A

PREINC2 PIC18F8XJ72 N/A N/A N/A

PLUSW2 PIC18F8XJ72 N/A N/A N/A

FSR2H PIC18F8XJ72 ---- xxxx ---- uuuu ---- uuuu

FSR2L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

STATUS PIC18F8XJ72 ---x xxxx ---u uuuu ---u uuuu

TMR0H PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TMR0L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

T0CON PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu

OSCCON PIC18F8XJ72 0110 q000 0110 q000 uuuu quuu

LCDREG PIC18F8XJ72 -011 1100 -011 1000 -uuu uuuu

WDTCON PIC18F8XJ72 0--- ---0 0--- ---0 u--- ---u

RCON(4) PIC18F8XJ72 0-11 11q0 0-0q qquu u-uu qquu

TMR1H PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON PIC18F8XJ72 0000 0000 u0uu uuuu uuuu uuuu

TMR2 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

PR2 PIC18F8XJ72 1111 1111 1111 1111 1111 1111

T2CON PIC18F8XJ72 -000 0000 -000 0000 -uuu uuuu

SSPBUF PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

SSPADD PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

SSPSTAT PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

SSPCON1 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

SSPCON2 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 51

PIC18F87J72 FAMILY

ADRESH PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

ADRESL PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 PIC18F8XJ72 0-00 0000 0-00 0000 u-uu uuuu

ADCON1 PIC18F8XJ72 0-00 0000 0-00 0000 u-uu uuuu

ADCON2 PIC18F8XJ72 0-00 0000 0-00 0000 u-uu uuuu

LCDDATA4 PIC18F8XJ72 ---- ---x ---- ---u ---- ---u

LCDDATA3 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA2 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA1 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA0 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDSE4 PIC18F8XJ72 ---- ---0 ---- ---u ---- ---u

LCDSE3 PIC18F8XJ72 0000 0000 uuuu uuuu uuuu uuuu

LCDSE2 PIC18F8XJ72 0000 0000 uuuu uuuu uuuu uuuu

LCDSE1 PIC18F8XJ72 0000 0000 uuuu uuuu uuuu uuuu

CVRCON PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

CMCON PIC18F8XJ72 0000 0111 0000 0111 uuuu uuuu

TMR3H PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

T3CON PIC18F8XJ72 0000 0000 uuuu uuuu uuuu uuuu

SPBRG1 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

RCREG1 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TXREG1 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TXSTA1 PIC18F8XJ72 0000 0010 0000 0010 uuuu uuuu

RCSTA1 PIC18F8XJ72 0000 000x 0000 000x uuuu uuuu

LCDPS PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

LCDSE0 PIC18F8XJ72 0000 0000 uuuu uuuu uuuu uuuu

LCDCON PIC18F8XJ72 000- 0000 000- 0000 uuu- uuuu

EECON2 PIC18F8XJ72 ---- ---- ---- ---- ---- ----

EECON1 PIC18F8XJ72 ---0 x00- ---0 u00- ---0 u00-

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 52 Preliminary  2010 Microchip Technology Inc.

IPR3 PIC18F8XJ72 -111 1111 -111 1111 -uuu 1111

PIR3 PIC18F8XJ72 -000 0000 -000 0000 -uuu 0000(3)

PIE3 PIC18F8XJ72 -000 0000 -000 0000 -uuu 0000

IPR2 PIC18F8XJ72 11-- 111- 11-- 111- uu-- uuu-

PIR2 PIC18F8XJ72 00-- 000- 00-- 000- uu-- uuu-(3)

PIE2 PIC18F8XJ72 00-- 000- 00-- 000- uu-- uuu-

IPR1 PIC18F8XJ72 -111 1-11 -111 1-11 -uuu u-uu

PIR1 PIC18F8XJ72 -000 0-00 -000 0-00 -uuu u-uu(3)

PIE1 PIC18F8XJ72 -000 0-00 -000 0-00 -uuu u-uu

OSCTUNE PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TRISG PIC18F8XJ72 0001 1111 0001 1111 uuuu uuuu

TRISF PIC18F8XJ72 1111 111- 1111 111- uuuu uuu-

TRISE PIC18F8XJ72 1111 1-11 1111 1-11 uuuu u-uu

TRISD PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu

TRISC PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu

TRISB PIC18F8XJ72 1111 1111 1111 1111 uuuu uuuu

TRISA(5) PIC18F8XJ72 1111 1111(5) 1111 1111(5) uuuu uuuu(5)

LATG PIC18F8XJ72 00-x xxxx 00-u uuuu uu-u uuuu

LATF PIC18F8XJ72 xxxx xxx- uuuu uuu- uuuu uuu-

LATE PIC18F8XJ72 xxxx x-xx uuuu u-uu uuuu u-uu

LATD PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LATC PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LATB PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LATA(5) PIC18F8XJ72 xxxx xxxx(5) uuuu uuuu(5) uuuu uuuu(5)

PORTG PIC18F8XJ72 000x xxxx 000u uuuu 000u uuuu

PORTF PIC18F8XJ72 xxxx xxx- uuuu uuu- uuuu uuu-

PORTE PIC18F8XJ72 xxxx x-xx uuuu u-uu uuuu u-uu

PORTD PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

PORTB PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA(5) PIC18F8XJ72 xx0x 0000(5) uu0u 0000(5) uuuu uuuu(5)

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 53

PIC18F87J72 FAMILY

SPBRGH1 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

BAUDCON1 PIC18F8XJ72 0100 0-00 0100 0-00 uuuu u-uu

LCDDATA22 PIC18F8XJ72 ---- ---x ---- ---u ---- ---u

LCDDATA22 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA21 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA20 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA19 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA18 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA16 PIC18F8XJ72 ---- ---x ---- ---u ---- ---u

LCDDATA16 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA15 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA14 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA13 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA12 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA10 PIC18F8XJ72 ---- ---x ---- ---u ---- ---u

LCDDATA10 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA9 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA8 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA7 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

LCDDATA6 PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON PIC18F8XJ72 --00 0000 --00 0000 --uu uuuu

CCPR2H PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR2L PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CCP2CON PIC18F8XJ72 --00 0000 --00 0000 --uu uuuu

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 54 Preliminary  2010 Microchip Technology Inc.

SPBRG2 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

RCREG2 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TXREG2 PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

TXSTA2 PIC18F8XJ72 0000 -010 0000 -010 uuuu -uuu

RCSTA2 PIC18F8XJ72 0000 000x 0000 000x uuuu uuuu

RTCCFG PIC18F8XJ72 0-00 0000 0-00 0000 u-uu uuuu

RTCCAL PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

RTCVALH PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

RTCVALL PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

ALRMCFG PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

ALRMRPT PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

ALRMVALH PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

ALRMVALL PIC18F8XJ72 xxxx xxxx uuuu uuuu uuuu uuuu

CTMUCONH PIC18F8XJ72 0-00 0000 0-00 0000 u-uu uuuu

CTMUCONL PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

CTMUICONH PIC18F8XJ72 0000 0000 0000 0000 uuuu uuuu

PADCFG1 PIC18F8XJ72 ---- -00- ---- -00- ---- -uu-

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 55

PIC18F87J72 FAMILY

6.0 MEMORY ORGANIZATION

There are two types of memory in PIC18 Flash

microcontroller devices:

• Program Memory

• Data RAM

As Harvard architecture devices, the data and program

memories use separate busses; this allows for

concurrent access of the two memory spaces.

Additional detailed information on the operation of the

Flash program memory is provided in Section 7.0

“Flash Program Memory”.

6.1 Program Memory Organization

PIC18 microcontrollers implement a 21-bit program

counter which is capable of addressing a 2-Mbyte

program memory space. Accessing a location between

the upper boundary of the physically implemented

memory and the 2-Mbyte address will return all ‘0’s (a

NOP instruction).

The PIC18F87J72 family has a Flash program memory

size of 128 Kbytes (65,536 single-word instructions).

The program memory maps for individual family

members are shown in Figure 6-1.

FIGURE 6-1: MEMORY MAPS FOR PIC18F87J72 FAMILY DEVICES

Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.

Unimplemented

Read as ‘0’

Unimplemented

Read as ‘0’

000000h

1FFFFFh

01FFFFh

00FFFFh

PC<20:0>

Stack Level 1



Stack Level 31



CALL, CALLW, RCALL,

RETURN, RETFIE, RETLW,

User Memory Space

On-Chip

Memory

ADDULNK, SUBULNK

Config. Words

PIC18F86J72 PIC18F87J72

On-Chip

Memory

PIC18F87J72 FAMILY

DS39979A-page 56 Preliminary  2010 Microchip Technology Inc.

6.1.1 HARD MEMORY VECTORS

All PIC18 devices have a total of three hard-coded

return vectors in their program memory space. The

Reset vector address is the default value to which the

program counter returns on all device Resets; it is

located at 0000h.

PIC18 devices also have two interrupt vector

addresses for the handling of high-priority and

low-priority interrupts. The high-priority interrupt vector

is located at 0008h and the low-priority interrupt vector

is at 0018h. Their locations in relation to the program

memory map are shown in Figure 6-2.

FIGURE 6-2: HARD VECTOR AND

CONFIGURATION WORD

LOCATIONS FOR

PIC18F87J72 FAMILY

FAMILY DEVICES

6.1.2 FLASH CONFIGURATION WORDS

Because PIC18F87J72 family devices do not have per-

sistent configuration memory, the top four words of

on-chip program memory are reserved for configuration

information. On Reset, the configuration information is

copied into the Configuration registers.

The Configuration Words are stored in their program

memory location in numerical order, starting with the

lower byte of CONFIG1 at the lowest address and end-

ing with the upper byte of CONFIG4. For these devices,

only Configuration Words, CONFIG1 through

CONFIG3, are used; CONFIG4 is reserved. The actual

addresses of the Flash Configuration Word for devices

in the PIC18F87J72 family are shown in Table 6-1.

Their location in the memory map is shown with the

other memory vectors in Figure 6-2.

Additional details on the device Configuration Words

are provided in Section 26.1 “Configuration Bits”.

TABLE 6-1: FLASH CONFIGURATION

WORD FOR PIC18F87J72

FAMILY DEVICES

Reset Vector

Low-Priority Interrupt Vector

0000h

0018h

On-Chip

Program Memory

High-Priority Interrupt Vector 0008h

1FFFFFh

(Top of Memory)

(Top of Memory-7)

Flash Configuration Words

Read ‘0’

Legend: (Top of Memory) represents upper boundary

of on-chip program memory space (see

Figure 6-1 for device-specific values).

Shaded area represents unimplemented

memory. Areas are not shown to scale.

Device

Program

Memory

(Kbytes)

Configuration Word

Addresses

PIC18F86J72 64 FFF8h to FFFFh

PIC18F87J72 128 1FFF8h to 1FFFFh

 2010 Microchip Technology Inc. Preliminary DS39979A-page 57

PIC18F87J72 FAMILY

6.1.3 PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and is contained in three separate 8-bit registers. The

low byte, known as the PCL register, is both readable

and writable. The high byte, or PCH register, contains

the PC<15:8> bits; it is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is called PCU. This

directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes

PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 6.1.6.1 “Computed

GOTO”).

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit (LSb) of PCL is

fixed to a value of ‘0’. The PC increments by 2 to

address sequential instructions in the program

memory.

The CALL, RCALL, GOTO and program branch

instructions write to the program counter directly. For

these instructions, the contents of PCLATH and

PCLATU are not transferred to the program counter.

6.1.4 RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC is

pushed onto the stack when a CALL or RCALL instruc-

tion is executed, or an interrupt is Acknowledged. The

PC value is pulled off the stack on a RETURN, RETLW or

a RETFIE instruction (and on ADDULNK and SUBULNK

instructions if the extended instruction set is enabled).

PCLATU and PCLATH are not affected by any of the

RETURN or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, STKPTR. The stack space is not

part of either program or data space. The Stack Pointer

is readable and writable and the address on the top of

the stack is readable and writable through the

Top-of-Stack Special Function Registers. Data can also

be pushed to, or popped from the stack, using these

registers.

A CALL type instruction causes a push onto the stack.

The Stack Pointer is first incremented and the location

pointed to by the Stack Pointer is written with the

contents of the PC (already pointing to the instruction

following the CALL). A RETURN type instruction causes

a pop from the stack. The contents of the location

pointed to by the STKPTR are transferred to the PC

and then the Stack Pointer is decremented.

The Stack Pointer is initialized to ‘00000’ after all

Resets. There is no RAM associated with the location

corresponding to a Stack Pointer value of ‘00000’; this

is only a Reset value. Status bits indicate if the stack is

full, has overflowed or has underflowed.

6.1.4.1 Top-of-Stack Access

Only the top of the return address stack (TOS) is

readable and writable. A set of three registers,

TOSU:TOSH:TOSL, holds the contents of the stack

location pointed to by the STKPTR register

(Figure 6-3). This allows users to implement a software

stack if necessary. After a CALL, RCALL or interrupt

(and ADDULNK and SUBULNK instructions if the

extended instruction set is enabled), the software can

read the pushed value by reading the

TOSU:TOSH:TOSL registers. These values can be

placed on a user-defined software stack. At return time,

the software can return these values to

TOSU:TOSH:TOSL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

00011

001A34h

11111

11110

11101

00010

00001

00000

00010

Return Address Stack <20:0>

Top-of-Stack

000D58h

TOSLTOSHTOSU

34h1Ah00h

STKPTR<4:0>

Top-of-Stack Registers Stack Pointer

PIC18F87J72 FAMILY

DS39979A-page 58 Preliminary  2010 Microchip Technology Inc.

6.1.4.2 Return Stack Pointer (STKPTR)

The STKPTR register (Register 6-1) contains the Stack

Pointer value, the STKFUL (Stack Full) status bit and

the STKUNF (Stack Underflow) status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. On Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 26.1 “Configuration Bits” for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and the STKPTR will remain at 31.

When the stack has been popped enough times to

unload the stack, the next pop will return a value of zero

to the PC and set the STKUNF bit while the Stack

Pointer remains at zero. The STKUNF bit will remain

set until cleared by software or until a POR occurs.

6.1.4.3 PUSH and POP Instructions

Since the Top-of-Stack is readable and writable, the

ability to push values onto the stack and pull values off

the stack, without disturbing normal program execu-

tion, is a desirable feature. The PIC18 instruction set

includes two instructions, PUSH and POP, that permit

the TOS to be manipulated under software control.

TOSU, TOSH and TOSL can be modified to place data

or a return address on the stack.

The PUSH instruction places the current PC value onto

the stack. This increments the Stack Pointer and loads

the current PC value onto the stack.

The POP instruction discards the current TOS by

decrementing the Stack Pointer. The previous value

pushed onto the stack then becomes the TOS value.

Note: Returning a value of zero to the PC on an

underflow has the effect of vectoring the

program to the Reset vector, where the

stack conditions can be verified and

appropriate actions can be taken. This is

not the same as a Reset, as the contents

of the SFRs are not affected.

R/C-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

STKFUL(1) STKUNF(1) — SP4 SP3 SP2 SP1 SP0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 STKFUL: Stack Full Flag bit(1)

1 = Stack became full or overflowed

0 = Stack has not become full or overflowed

bit 6 STKUNF: Stack Underflow Flag bit(1)

1 = Stack underflow occurred

0 = Stack underflow did not occur

bit 5 Unimplemented: Read as ‘0’

bit 4-0 SP<4:0>: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 are cleared by user software or by a POR.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 59

PIC18F87J72 FAMILY

6.1.4.4 Stack Full and Underflow Resets

Device Resets on stack overflow and stack underflow

conditions are enabled by setting the STVREN bit in

Configuration Register 1L. When STVREN is set, a full

or underflow condition will set the appropriate STKFUL

or STKUNF bit and then cause a device Reset. When

STVREN is cleared, a full or underflow condition will set

the appropriate STKFUL or STKUNF bit, but not cause

a device Reset. The STKFUL or STKUNF bits are

cleared by the user software or a Power-on Reset.

6.1.5 FAST REGISTER STACK

A Fast Register Stack is provided for the STATUS,

WREG and BSR registers to provide a “fast return”

option for interrupts. This stack is only one level deep

and is neither readable nor writable. It is loaded with the

current value of the corresponding register when the

processor vectors for an interrupt. All interrupt sources

will push values into the Stack registers. The values in

the registers are then loaded back into the working

registers if the RETFIE,FAST instruction is used to

return from the interrupt.

If both low and high-priority interrupts are enabled, the

Stack registers cannot be used reliably to return from

low-priority interrupts. If a high-priority interrupt occurs

while servicing a low-priority interrupt, the Stack

be overwritten. In these cases, users must save the key

registers in software during a low-priority interrupt.

If interrupt priority is not used, all interrupts may use the

Fast Register Stack for returns from interrupt. If no

interrupts are used, the Fast Register Stack can be

used to restore the STATUS, WREG and BSR registers

at the end of a subroutine call. To use the Fast Register

Stack for a subroutine call, a CALL label,FAST

instruction must be executed to save the STATUS,

WREG and BSR registers to the Fast Register Stack. A

RETURN,FAST instruction is then executed to restore

these registers from the Fast Register Stack.

Example 6-1 shows a source code example that uses

the Fast Register Stack during a subroutine call and

return.

EXAMPLE 6-1: FAST REGISTER STACK

CODE EXAMPLE

6.1.6 LOOK-UP TABLES IN PROGRAM

MEMORY

There may be programming situations that require the

creation of data structures, or look-up tables, in

program memory. For PIC18 devices, look-up tables

can be implemented in two ways:

• Computed GOTO

• Table Reads

6.1.6.1 Computed GOTO

A computed GOTO is accomplished by adding an offset

to the program counter. An example is shown in

Example 6-2.

A look-up table can be formed with an ADDWF PCL

instruction and a group of RETLW nn instructions. The

W register is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW nn

instructions that returns the value ‘nn’ to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSb = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 6-2: COMPUTED GOTO USING

AN OFFSET VALUE

6.1.6.2 Table Reads

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

Look-up table data may be stored, two bytes per

program word, while programming. The Table Pointer

(TBLPTR) specifies the byte address and the Table

Latch (TABLAT) contains the data that is read from the

program memory. Data is transferred from program

memory, one byte at a time.

Table read operation is discussed further in

Section 7.1 “Table Reads and Table Writes”.

CALL SUB1, FAST ;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK



SUB1 



RETURN FAST ;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

MOVF OFFSET, W

CALL TABLE

ORG nn00h

TABLE ADDWF PCL

RETLW nnh

PIC18F87J72 FAMILY

DS39979A-page 60 Preliminary  2010 Microchip Technology Inc.

6.2 PIC18 Instruction Cycle

6.2.1 CLOCKING SCHEME

The microcontroller clock input, whether from an

internal or external source, is internally divided by four

to generate four non-overlapping quadrature clocks

(Q1, Q2, Q3 and Q4). Internally, the program counter is

incremented on every Q1; the instruction is fetched

from the program memory and latched into the

Instruction Register (IR) during Q4. The instruction is

decoded and executed during the following Q1 through

Q4. The clocks and instruction execution flow are

shown in Figure 6-4.

6.2.2 INSTRUCTION FLOW/PIPELINING

An “Instruction Cycle” consists of four Q cycles, Q1

through Q4. The instruction fetch and execute are pipe-

lined in such a manner that a fetch takes one instruction

cycle, while the decode and execute take another

instruction cycle. However, due to the pipelining, each

instruction effectively executes in one cycle. If an

instruction causes the program counter to change (e.g.,

GOTO), then two cycles are required to complete the

instruction (Example 6-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 6-4: CLOCK/INSTRUCTION CYCLE

EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKO

(RC mode)

PC PC + 2 PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2

3. BRA SUB_1 Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP) Fetch 4 Flush (NOP)

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

 2010 Microchip Technology Inc. Preliminary DS39979A-page 61

PIC18F87J72 FAMILY

6.2.3 INSTRUCTIONS IN PROGRAM

MEMORY

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte (LSB) of an

instruction word is always stored in a program memory

location with an even address (LSB = 0). To maintain

alignment with instruction boundaries, the PC incre-

ments in steps of 2 and the LSB will always read ‘0’

(see Section 6.1.3 “Program Counter”).

Figure 6-5 shows an example of how instruction words

are stored in the program memory.

The CALL and GOTO instructions have the absolute

program memory address embedded into the instruc-

tion. Since instructions are always stored on word

boundaries, the data contained in the instruction is a

word address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 6-5 shows how the

instruction, GOTO 0006h, is encoded in the program

memory. Program branch instructions, which encode a

relative address offset, operate in the same manner. The

offset value stored in a branch instruction represents the

number of single-word instructions that the PC will be

offset by. Section 27.0 “Instruction Set Summary”

provides further details of the instruction set.

FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY

6.2.4 TWO-WORD INSTRUCTIONS

The standard PIC18 instruction set has four two-word

instructions: CALL, MOVFF, GOTO and LSFR. In all

cases, the second word of the instructions always has

‘1111’ as its four Most Significant bits; the other 12 bits

are literal data, usually a data memory address.

The use of ‘1111’ in the 4 MSbs of an instruction

specifies a special form of NOP. If the instruction is

executed in proper sequence – immediately after the

first word – the data in the second word is accessed

and used by the instruction sequence. If the first word

is skipped for some reason and the second word is

executed by itself, a NOP is executed instead. This is

necessary for cases when the two-word instruction is

preceded by a conditional instruction that changes the

PC. Example 6-4 shows how this works.

EXAMPLE 6-4: TWO-WORD INSTRUCTIONS

Word Address

LSB = 1LSB = 0

Program Memory

Byte Locations 

000000h

000002h

000004h

000006h

Instruction 1: MOVLW 055h 0Fh 55h 000008h

Instruction 2: GOTO 0006h EFh 03h 00000Ah

F0h 00h 00000Ch

Instruction 3: MOVFF 123h, 456h C1h 23h 00000Eh

F4h 56h 000010h

000012h

000014h

Note: See Section 6.5 “Program Memory and

the Extended Instruction Set” for

information on two-word instructions in the

extended instruction set.

CASE 1:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; No, skip this word

1111 0100 0101 0110 ; Execute this word as a NOP

0010 0100 0000 0000 ADDWF REG3 ; continue code

CASE 2:

Object Code Source Code

0110 0110 0000 0000 TSTFSZ REG1 ; is RAM location 0?

1100 0001 0010 0011 MOVFF REG1, REG2 ; Yes, execute this word

1111 0100 0101 0110 ; 2nd word of instruction

0010 0100 0000 0000 ADDWF REG3 ; continue code

PIC18F87J72 FAMILY

DS39979A-page 62 Preliminary  2010 Microchip Technology Inc.

6.3 Data Memory Organization

The data memory in PIC18 devices is implemented as

static RAM. Each register in the data memory has a

12-bit address, allowing up to 4,096 bytes of data

memory. The memory space is divided into as many as

16 banks that contain 256 bytes each. PIC18F86J72

and PIC18F87J72 devices implement all 16 complete

banks, for a total of 4 Kbytes. Figure 6-6 and Figure 6-7

show the data memory organization for the devices.

The data memory contains Special Function Registers

(SFRs) and General Purpose Registers (GPRs). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratchpad operations in the user’s

application. Any read of an unimplemented location will

read as ‘0’s.

The instruction set and architecture allow operations

across all banks. The entire data memory may be

accessed by Direct, Indirect or Indexed Addressing

modes. Addressing modes are discussed later in this

section.

To ensure that commonly used registers (select SFRs

and select GPRs) can be accessed in a single cycle,

PIC18 devices implement an Access Bank. This is a

256-byte memory space that provides fast access to

select SFRs and the lower portion of GPR Bank 0 with-

out using the BSR. Section 6.3.2 “Access Bank”

provides a detailed description of the Access RAM.

6.3.1 BANK SELECT REGISTER

Large areas of data memory require an efficient

addressing scheme to make rapid access to any

address possible. Ideally, this means that an entire

address does not need to be provided for each read or

write operation. For PIC18 devices, this is accom-

plished with a RAM banking scheme. This divides the

memory space into 16 contiguous banks of 256 bytes.

Depending on the instruction, each location can be

addressed directly by its full 12-bit address, or an 8-bit

low-order address and a 4-bit Bank Pointer.

Most instructions in the PIC18 instruction set make use

of the Bank Pointer, known as the Bank Select Register

(BSR). This SFR holds the 4 Most Significant bits of a

location’s address; the instruction itself includes the

8 Least Significant bits. Only the four lower bits of the

BSR are implemented (BSR<3:0>). The upper four bits

are unused; they will always read ‘0’ and cannot be

written to. The BSR can be loaded directly by using the

MOVLB instruction.

The value of the BSR indicates the bank in data

memory. The 8 bits in the instruction show the location

in the bank and can be thought of as an offset from the

bank’s lower boundary. The relationship between the

BSR’s value and the bank division in data memory is

shown in Figure 6-7.

Since up to 16 registers may share the same low-order

address, the user must always be careful to ensure that

the proper bank is selected before performing a data

read or write. For example, writing what should be

program data to an 8-bit address of F9h while the BSR

is 0Fh, will end up resetting the program counter.

While any bank can be selected, only those banks that

are actually implemented can be read or written to.

Writes to unimplemented banks are ignored, while

reads from unimplemented banks will return ‘0’s. Even

so, the STATUS register will still be affected as if the

operation was successful. The data memory map in

Figure 6-6 indicates which banks are implemented.

In the core PIC18 instruction set, only the MOVFF

instruction fully specifies the 12-bit address of the

source and target registers. This instruction ignores the

BSR completely when it executes. All other instructions

include only the low-order address as an operand and

must use either the BSR or the Access Bank to locate

their target registers.

Note: The operation of some aspects of data

memory are changed when the PIC18

extended instruction set is enabled. See

Section 6.6 “Data Memory and the

Extended Instruction Set” for more

information.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 63

PIC18F87J72 FAMILY

FIGURE 6-6: DATA MEMORY MAP FOR PIC18F86J72 AND PIC18F87J72 DEVICES

00h

5Fh

60h

FFh

Access Bank

When a = 0:

The BSR is ignored and the

Access Bank is used.

The first 96 bytes are general

purpose RAM (from Bank 0).

The second 160 bytes are

Special Function Registers

(from Bank 15).

When a = 1:

The BSR specifies the bank

used by the instruction.

Access RAM High

Access RAM Low

(SFRs)

Bank 0

Bank 1

Bank 14

Bank 15

Data Memory Map

BSR<3:0>

= 0000

= 0001

= 1111

060h

05Fh

F60h

FFFh

F5Fh

F00h

EFFh

1FFh

100h

0FFh

000h

Access RAM

FFh

00h

FFh

00h

FFh

00h

GPR

SFR

Bank 2

= 0010

2FFh

200h

Bank 3

FFh

00h

GPR

FFh

= 0011

GPR(1)

GPR

4FFh

400h

5FFh

500h

3FFh

300h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

= 0110

= 0111

= 0101

= 0100 Bank 4

Bank 5

Bank 6

Bank 7

Bank 8

= 1110

6FFh

600h

7FFh

700h

800h

Bank 9

Bank 10

Bank 11

Bank 12

Bank 13

8FFh

900h

9FFh

A00h

AFFh

B00h

BFFh

C00h

CFFh

D00h

DFFh

E00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

GPR

Note 1: Addresses, F5Ah through F5Fh, are also used by SFRs, but are not part of the Access RAM. Users

must always use the complete address, or load the proper SBR value, to access these registers.

= 1000

= 1001

= 1010

= 1011

= 1100

= 1101

PIC18F87J72 FAMILY

DS39979A-page 64 Preliminary  2010 Microchip Technology Inc.

FIGURE 6-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)

6.3.2 ACCESS BANK

While the use of the BSR with an embedded 8-bit

address allows users to address the entire range of data

memory, it also means that the user must always ensure

that the correct bank is selected. Otherwise, data may

be read from, or written to, the wrong location. This can

be disastrous if a GPR is the intended target of an oper-

ation, but an SFR is written to instead. Verifying and/or

changing the BSR for each read or write to data memory

can become very inefficient.

To streamline access for the most commonly used data

memory locations, the data memory is configured with

an Access Bank, which allows users to access a

mapped block of memory without specifying a BSR.

The Access Bank consists of the first 96 bytes of

memory (00h-5Fh) in Bank 0 and the last 160 bytes of

memory (60h-FFh) in Bank 15. The lower half is known

as the “Access RAM” and is composed of GPRs. The

upper half is where the device’s SFRs are mapped.

These two areas are mapped contiguously in the

Access Bank and can be addressed in a linear fashion

by an 8-bit address (Figure 6-6).

The Access Bank is used by core PIC18 instructions

that include the Access RAM bit (the ‘a’ parameter in

the instruction). When ‘a’ is equal to ‘1’, the instruction

uses the BSR and the 8-bit address included in the

opcode for the data memory address. When ‘a’ is ‘0’,

however, the instruction is forced to use the Access

Bank address map; the current value of the BSR is

ignored entirely.

Using this “forced” addressing allows the instruction to

operate on a data address in a single cycle without

updating the BSR first. For 8-bit addresses of 60h and

above, this means that users can evaluate and operate

on SFRs more efficiently. The Access RAM below 60h

is a good place for data values that the user might need

to access rapidly, such as immediate computational

results or common program variables. Access RAM

also allows for faster and more code efficient context

saving and switching of variables.

The mapping of the Access Bank is slightly different

when the extended instruction set is enabled (XINST

Configuration bit = 1). This is discussed in more detail

in Section 6.6.3 “Mapping the Access Bank in

Indexed Literal Offset Mode”.

6.3.3 GENERAL PURPOSE

PIC18 devices may have banked memory in the GPR

area. This is data RAM which is available for use by all

instructions. GPRs start at the bottom of Bank 0

(address 000h) and grow upwards towards the bottom of

the SFR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>)

to the registers of the Access Bank.

2: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data Memory

Bank Select(2)

From Opcode(2)

0000

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

00h

FFh

Bank 3

through

Bank 13

0010 11111111

BSR(1)

11111111

 2010 Microchip Technology Inc. Preliminary DS39979A-page 65

PIC18F87J72 FAMILY

6.3.4 SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral modules for controlling

the desired operation of the device. These registers are

implemented as static RAM. SFRs start at the top of

data memory (FFFh) and extend downward to occupy

more than the top half of Bank 15 (F60h to FFFh). A list

of these registers is given in Table 6-2 and Table 6-3.

The SFRs can be classified into two sets: those

associated with the “core” device functionality (ALU,

Resets and interrupts) and those related to the

peripheral functions. The Reset and Interrupt registers

are described in their respective chapters, while the

ALU’s STATUS register is described later in this section.

Registers related to the operation of the peripheral

features are described in the chapter for that peripheral.

The SFRs are typically distributed among the

peripherals whose functions they control. Unused SFR

locations are unimplemented and read as ‘0’s.

TABLE 6-2: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J72 FAMILY DEVICES

Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name Addr. Name

FFFh TOSU FDFh INDF2(1) FBFh LCDDATA4 F9Fh IPR1 F7Fh SPBRGH1 F5Fh RTCCFG

FFEh TOSH FDEh POSTINC2(1) FBEh LCDDATA3 F9Eh PIR1 F7Eh BAUDCON1 F5Eh RTCCAL

FFDh TOSL FDDh POSTDEC2(1) FBDh LCDDATA2 F9Dh PIE1 F7Dh —(2) F5Dh RTCVALH

FFCh STKPTR FDCh PREINC2(1) FBCh LCDDATA1 F9Ch —(2) F7Ch

LCDDATA22

F5Ch RTCVALL

FFBh PCLATU FDBh PLUSW2(1) FBBh LCDDATA0 F9Bh OSCTUNE F7Bh

LCDDATA21

F5Bh ALRMCFG

FFAh PCLATH FDAh FSR2H FBAh —(2) F9Ah TRISJ F7Ah

LCDDATA20

F5Ah ALRMRPT

FF9h PCL FD9h FSR2L FB9h LCDSE4 F99h TRISH F79h

LCDDATA19

F59h ALRMVALH

FF8h TBLPTRU FD8h STATUS FB8h LCDSE3 F98h TRISG F78h

LCDDATA18

F58h ALRMVALL

FF7h TBLPTRH FD7h TMR0H FB7h LCDSE2 F97h TRISF F77h —(2) F57h CTMUCONH

FF6h TBLPTRL FD6h TMR0L FB6h LCDSE1 F96h TRISE F76h

LCDDATA16

F56h CTMUCONL

FF5h TABLAT FD5h T0CON FB5h CVRCON F95h TRISD F75h

LCDDATA15

F55h CTMUICONH

FF4h PRODH FD4h —(2) FB4h CMCON F94h TRISC F74h

LCDDATA14

F54h PADCFG1

FF3h PRODL FD3h OSCCON FB3h TMR3H F93h TRISB F73h

LCDDATA13

FF2h INTCON FD2h LCDREG FB2h TMR3L F92h TRISA F72h

LCDDATA12

FF1h INTCON2 FD1h WDTCON FB1h T3CON F91h LATJ F71h —(2)

FF0h INTCON3 FD0h RCON FB0h —(2) F90h LATH F70h

LCDDATA10

FEFh INDF0(1) FCFh TMR1H FAFh SPBRG1 F8Fh LATG F6Fh LCDDATA9

FEEh POSTINC0(1) FCEh TMR1L FAEh RCREG1 F8Eh LATF F6Eh LCDDATA8

FEDh POSTDEC0(1) FCDh T1CON FADh TXREG1 F8Dh LATE F6Dh LCDDATA7

FECh PREINC0(1) FCCh TMR2 FACh TXSTA1 F8Ch LATD F6Ch LCDDATA6

FEBh PLUSW0(1) FCBh PR2 FABh RCSTA1 F8Bh LATC F6Bh —(2)

FEAh FSR0H FCAh T2CON FAAh LCDPS F8Ah LATB F6Ah CCPR1H

FE9h FSR0L FC9h SSPBUF FA9h LCDSE0 F89h LATA F69h CCPR1L

FE8h WREG FC8h SSPADD FA8h LCDCON F88h PORTJ F68h CCP1CON

FE7h INDF1(1) FC7h SSPSTAT FA7h EECON2 F87h PORTH F67h CCPR2H

FE6h POSTINC1(1) FC6h SSPCON1 FA6h EECON1 F86h PORTG F66h CCPR2L

FE5h POSTDEC1(1) FC5h SSPCON2 FA5h IPR3 F85h PORTF F65h CCP2CON

FE4h PREINC1(1) FC4h ADRESH FA4h PIR3 F84h PORTE F64h SPBRG2

FE3h PLUSW1(1) FC3h ADRESL FA3h PIE3 F83h PORTD F63h RCREG2

FE2h FSR1H FC2h ADCON0 FA2h IPR2 F82h PORTC F62h TXREG2

FE1h FSR1L FC1h ADCON1 FA1h PIR2 F81h PORTB F61h TXSTA2

FE0h BSR FC0h ADCON2 FA0h PIE2 F80h PORTA F60h RCSTA2

Note 1: This is not a physical register.

2: Unimplemented registers are read as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 66 Preliminary  2010 Microchip Technology Inc.

TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Details on

page

TOSU — — — Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

49, 57

TOSH Top-of-Stack High Byte (TOS<15:8>)

0000 0000

49, 57

TOSL Top-of-Stack Low Byte (TOS<7:0>)

0000 0000

49, 57

STKPTR STKFUL STKUNF — Return Stack Pointer

uu-0 0000

49, 58

PCLATU ——bit 21

(1)

Holding Register for PC<20:16>

---0 0000

49, 57

PCLATH Holding Register for PC<15:8>

0000 0000

49, 57

PCL PC Low Byte (PC<7:0>)

0000 0000

49, 57

TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000

49, 80

TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

49, 80

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000

49, 80

TABLAT Program Memory Table Latch

0000 0000

49, 80

PRODH Product Register High Byte

xxxx xxxx

49, 87

PRODL Product Register Low Byte

xxxx xxxx

49, 87

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF

0000 000x

49, 91

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

1111 1111

49, 92

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

1100 0000

49, 93

INDF0 Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) N/A 49, 72

POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) N/A 49, 73

POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) N/A 49, 73

PREINC0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) N/A 49, 73

PLUSW0 Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –

value of FSR0 offset by W

N/A 49, 73

FSR0H ———— Indirect Data Memory Address Pointer 0 High Byte

---- xxxx

49, 72

FSR0L Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx

49, 72

WREG Working Register

xxxx xxxx

INDF1 Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) N/A 49, 72

POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) N/A 49, 73

POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) N/A 49, 73

PREINC1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) N/A 49, 73

PLUSW1 Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –

value of FSR1 offset by W

N/A 49, 73

FSR1H ———— Indirect Data Memory Address Pointer 1 High Byte

---- xxxx

50, 72

FSR1L Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

50, 72

BSR ———— Bank Select Register

---- 0000

50, 62

INDF2 Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) N/A 50, 72

POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) N/A 50, 73

POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) N/A 50, 73

PREINC2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) N/A 50, 73

PLUSW2 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –

value of FSR2 offset by W

N/A 50, 73

FSR2H ———— Indirect Data Memory Address Pointer 2 High Byte

---- xxxx

50, 72

FSR2L Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

50, 72

STATUS — — —NOVZDCC

---x xxxx

50, 70

Legend:

= unknown,

= unchanged,

= unimplemented,

= value depends on condition,

= reserved, do not modify

Note 1:

Bit 21 of the PC is only available in Test mode and Serial Programming modes.

Alternate names and definitions for these bits when the MSSP module is operating in I

C™ Slave mode. See

Section 18.4.3.2 “Address

Masking”

for details.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘

’. See

Section 3.4.3 “PLL

Frequency Multiplier”

for details.

RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default

clock source (FOSC2 Configuration bit =

); otherwise, they are disabled and these bits read as ‘

’.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 67

PIC18F87J72 FAMILY

TMR0H Timer0 Register High Byte

0000 0000

50, 125

TMR0L Timer0 Register Low Byte

xxxx xxxx

50, 125

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

1111 1111

50, 123

OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS IOFS SCS1 SCS0

0110 q000

26, 50

LCDREG — CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0

-011 1100

50, 173

WDTCON REGSLP ——————SWDTEN

0--- ---0

50, 326

RCON IPEN —CMRI TO PD POR BOR

0-11 11q0

44, 50

TMR1H Timer1 Register High Byte

xxxx xxxx

50, 131

TMR1L Timer1 Register Low Byte

xxxx xxxx

50, 131

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

0000 0000

50, 127

TMR2 Timer2 Register

0000 0000

50, 134

PR2 Timer2 Period Register

1111 1111

50, 134

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000

50, 133

SSPBUF MSSP Receive Buffer/Transmit Register

xxxx xxxx

50, 203,

238

SSPADD MSSP Address Register in I

C™ Slave mode. MSSP1 Baud Rate Reload Register in I

C Master mode.

0000 0000

50, 238

SSPSTAT SMP CKE D/A PSR/WUA BF

0000 0000

50, 196,

205

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000

50, 197,

206

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN

0000 0000

50, 207,

208

GCEN ACKSTAT ADMSK5

(2)

ADMSK4

(2)

ADMSK3

(2)

ADMSK2

(2)

ADMSK1

(2)

SEN

ADRESH A/D Result Register High Byte

xxxx xxxx

51, 281

ADRESL A/D Result Register Low Byte

xxxx xxxx

51, 281

ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

0-00 0000

51, 273

ADCON1 TRIGSEL — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

0-00 0000

51, 274

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

0-00 0000

51, 275

LCDDATA4 — — — — — — — S32C0

xxxx xxxx

51, 171

LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0

xxxx xxxx

51, 171

LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0

xxxx xxxx

51, 171

LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0

xxxx xxxx

51, 171

LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0

xxxx xxxx

51, 171

LCDSE4 — — — — — — —SE32

0000 0000

51, 171

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24

0000 0000

51, 171

LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16

0000 0000

51, 171

LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08

0000 0000

51, 171

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0

0000 0000

51, 299

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

0000 0111

51, 293

TMR3H Timer3 Register High Byte

xxxx xxxx

51, 137

TMR3L Timer3 Register Low Byte

xxxx xxxx

51, 137

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

0000 0000

51, 135

TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Details on

page

Legend:

= unknown,

= unchanged,

= unimplemented,

= value depends on condition,

= reserved, do not modify

Note 1:

Bit 21 of the PC is only available in Test mode and Serial Programming modes.

Alternate names and definitions for these bits when the MSSP module is operating in I

C™ Slave mode. See

Section 18.4.3.2 “Address

Masking”

for details.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘

’. See

Section 3.4.3 “PLL

Frequency Multiplier”

for details.

RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default

clock source (FOSC2 Configuration bit =

); otherwise, they are disabled and these bits read as ‘

’.

PIC18F87J72 FAMILY

DS39979A-page 68 Preliminary  2010 Microchip Technology Inc.

SPBRG1 EUSART Baud Rate Generator Low Byte

0000 0000

51, 243

RCREG1 EUSART Receive Register

0000 0000

51, 251

TXREG1 EUSART Transmit Register

0000 0000

51, 249

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

0000 0010

51, 240

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0000 000x

51, 241

LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0

0000 0000

51, 169

LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00

0000 0000

51, 170

LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0

000- 0000

51, 168

EECON2 EEPROM Control Register 2 (not a physical register)

---- ----

51, 78

EECON1 —— WPROG FREE WRERR WREN WR —

--00 x00-

51, 78

IPR3 — LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP

-111 1111

52, 102

PIR3 — LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF

-000 0000

52, 96

PIE3 — LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE

-000 0000

52, 99

IPR2 OSCFIP CMIP —— BCLIP LVDIP TMR3IP —

11-- 111-

52, 101

PIR2 OSCFIF CMIF ——BCLIFLVDIFTMR3IF—

00-- 000-

52, 95

PIE2 OSCFIE CMIE —— BCLIE LVDIE TMR3IE —

00-- 000-

52, 98

IPR1 — ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP

-111 1-11

52, 100

PIR1 — ADIF RC1IF TX1IF SSPIF — TMR2IF TMR1IF

-000 0-00

52, 94

PIE1 — ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE

-000 0-00

52, 97

OSCTUNE INTSRC PLLEN

(3)

TUN5 TUN4 TUN3 TUN2 TUN1 TUN0

0000 0000

27, 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0

0001 1111

52, 122

TRISF TRISF7TRISF6TRISF5TRISF4TRISF3TRISF2TRISF1 —

1111 111-

52, 120

TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 — TRISE1 TRISE0

1111 1-11

52, 117

TRISD TRISD7TRISD6TRISD5TRISD4TRISD3TRISD2TRISD1TRISD0

1111 1111

52, 115

TRISC TRISC7TRISC6TRISC5TRISC4TRISC3TRISC2TRISC1TRISC0

1111 1111

52, 113

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

1111 1111

52, 110

TRISA TRISA7

(4)

TRISA6

(4)

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

1111 1111

52, 107

LATG U2OD U1OD — LATG4 LATG3 LATG2 LATG1 LATG0

00-x xxxx

52, 122

LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —

xxxx xxx-

52, 120

LATE LATE7 LATE6 LATE5 LATE4 LATE3 —LATE1LATE0

xxxx x-xx

52, 117

LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0

xxxx xxxx

52, 115

LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

xxxx xxxx

52, 113

LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0

xxxx xxxx

52, 110

LATA LATA7

(4)

LATA6

(4)

LATA5 LATA4 LATA3 LATA2 LATA1 LATA0

xxxx xxxx

52, 107

PORTG RDPU REPU RJPU

(2)

RG4RG3RG2RG1RG0

000x xxxx

52, 122

PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —

xxxx xxx-

52, 120

PORTE RE7 RE6 RE5 RE4 RE3 —RE1RE0

xxxx x-xx

52, 117

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

xxxx xxxx

52, 115

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

xxxx xxxx

52, 113

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

xxxx xxxx

52, 110

PORTA RA7

(4)

RA6

(4)

RA5RA4RA3RA2RA1RA0

xx0x 0000

52, 107

TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Details on

page

Legend:

= unknown,

= unchanged,

= unimplemented,

= value depends on condition,

= reserved, do not modify

Note 1:

Bit 21 of the PC is only available in Test mode and Serial Programming modes.

Alternate names and definitions for these bits when the MSSP module is operating in I

C™ Slave mode. See

Section 18.4.3.2 “Address

Masking”

for details.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘

’. See

Section 3.4.3 “PLL

Frequency Multiplier”

for details.

RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default

clock source (FOSC2 Configuration bit =

); otherwise, they are disabled and these bits read as ‘

’.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 69

PIC18F87J72 FAMILY

SPBRGH1 EUSART Baud Rate Generator High Byte

0000 0000

53, 243

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUEABDEN

0100 0-00

53, 242

LCDDATA22 — — — — — — — S32C3

xxxx xxxx

53, 171

LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3

xxxx xxxx

53, 171

LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3

xxxx xxxx

53, 171

LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3

xxxx xxxx

53, 171

LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3

xxxx xxxx

53, 171

LCDDATA16 — — — — — — — S32C2

xxxx xxxx

53, 171

LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2

xxxx xxxx

53, 171

LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2

xxxx xxxx

53, 171

LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2

xxxx xxxx

53, 171

LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2

xxxx xxxx

53, 171

LCDDATA10 — — — — — — — S32C1

xxxx xxxx

53, 171

LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1

xxxx xxxx

53, 171

LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1

xxxx xxxx

53, 171

LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1

xxxx xxxx

53, 171

LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1

xxxx xxxx

53, 171

CCPR1H Capture/Compare/PWM Register 1 High Byte

xxxx xxxx

53, 158

CCPR1L Capture/Compare/PWM Register 1 Low Byte

xxxx xxxx

53, 158

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0

--00 0000

53, 157

CCPR2H Capture/Compare/PWM Register 2 High Byte

xxxx xxxx

53, 158

CCPR2L Capture/Compare/PWM Register 2 Low Byte

xxxx xxxx

53, 158

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0

--00 0000

53, 157

SPBRG2 AUSART Baud Rate Generator Register

0000 0000

54, 262

RCREG2 AUSART Receive Register

0000 0000

54, 267

TXREG2 AUSART Transmit Register

0000 0000

54, 265

TXSTA2 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

0000 -010

54, 260

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

0000 000x

54, 261

RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0

0-00 0000

54, 141

RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

0000 0000

54, 142

RTCVALH RTCC Value High Register Window based on RTCPTR<1:0>

xxxx xxxx

54, 144

RTCVALL RTCC Value Low Register Window based on RTCPTR<1:0>

xxxx xxxx

54, 144

ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0

0000 0000

54, 143

ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0

0000 0000

54, 144

ALRMVALH Alarm Value High Register Window based on ALRMPTR<1:0>

xxxx xxxx

54, 147

ALRMVALL Alarm Value Low Register Window based on ALRMPTR<1:0>

xxxx xxxx

54, 147

CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG

0-00 0000

54, 315

CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT

0000 0000

54, 316

CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0

0000 0000

54, 317

PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 —

---- -00-

54, 142

TABLE 6-3: PIC18F87J72 FAMILY REGISTER FILE SUMMARY (CONTINUED)

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Details on

page

Legend:

= unknown,

= unchanged,

= unimplemented,

= value depends on condition,

= reserved, do not modify

Note 1:

Bit 21 of the PC is only available in Test mode and Serial Programming modes.

Alternate names and definitions for these bits when the MSSP module is operating in I

C™ Slave mode. See

Section 18.4.3.2 “Address

Masking”

for details.

The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘

’. See

Section 3.4.3 “PLL

Frequency Multiplier”

for details.

RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal oscillator is selected as the default

clock source (FOSC2 Configuration bit =

); otherwise, they are disabled and these bits read as ‘

’.

PIC18F87J72 FAMILY

DS39979A-page 70 Preliminary  2010 Microchip Technology Inc.

6.3.5 STATUS REGISTER

The STATUS register, shown in Register 6-2, contains

the arithmetic status of the ALU. The STATUS register

can be the operand for any instruction, as with any

other register. If the STATUS register is the destination

for an instruction that affects the Z, DC, C, OV or N bits,

then the write to these five bits is disabled.

These bits are set or cleared according to the device

logic. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended. For example, CLRF STATUS will set the Z bit

but leave the other bits unchanged. The STATUS

mended, therefore, that only BCF, BSF, SWAPF,

MOVFF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C, DC, OV or N bits in the STATUS

For other instructions not affecting any Status bits, see

the instruction set summaries in Table 27-2 and

Table 27-3.

Note: The C and DC bits operate as a borrow and

digit borrow bit respectively, in subtraction.

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — —NOVZDC

(1) C(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 N: Negative bit

This bit is used for signed arithmetic (2’s complement). It indicates whether the result was

negative (ALU MSB = 1).

1 = Result was negative

0 = Result was positive

bit 3 OV: Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the

7-bit magnitude which causes the sign bit (bit 7) to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Borrow bit(1)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(2)

For ADDWF, ADDLW, SUBLW and SUBWF instructions:

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register.

2: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second

operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the

source register.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 71

PIC18F87J72 FAMILY

6.4 Data Addressing Modes

While the program memory can be addressed in only

one way – through the program counter – information

in the data memory space can be addressed in several

ways. For most instructions, the addressing mode is

fixed. Other instructions may use up to three modes,

depending on which operands are used and whether or

not the extended instruction set is enabled.

The addressing modes are:

• Inherent

• Literal

•Direct

•Indirect

An additional addressing mode, Indexed Literal Offset,

is available when the extended instruction set is

enabled (XINST Configuration bit = 1). Its operation is

discussed in greater detail in Section 6.6.1 “Indexed

Addressing with Literal Offset”.

6.4.1 INHERENT AND LITERAL

ADDRESSING

Many PIC18 control instructions do not need any

argument at all; they either perform an operation that

globally affects the device, or they operate implicitly on

one register. This addressing mode is known as Inherent

Addressing. Examples include SLEEP, RESET and DAW.

Other instructions work in a similar way, but require an

additional explicit argument in the opcode. This is

known as Literal Addressing mode, because they

require some literal value as an argument. Examples

include ADDLW and MOVLW, which respectively, add or

move a literal value to the W register. Other examples

include CALL and GOTO, which include a 20-bit

program memory address.

6.4.2 DIRECT ADDRESSING

Direct Addressing specifies all or part of the source

and/or destination address of the operation within the

opcode itself. The options are specified by the

arguments accompanying the instruction.

In the core PIC18 instruction set, bit-oriented and

byte-oriented instructions use some version of Direct

Addressing by default. All of these instructions include

some 8-bit literal address as their Least Significant

Byte. This address specifies either a register address in

one of the banks of data RAM (Section 6.3.3 “General

Purpose Register File”) or a location in the Access

Bank (Section 6.3.2 “Access Bank”) as the data

source for the instruction.

The Access RAM bit, ‘a’, determines how the address

is interpreted. When ‘a’ is ‘1’, the contents of the BSR

(Section 6.3.1 “Bank Select Register”) are used with

the address to determine the complete 12-bit address

of the register. When ‘a’ is ‘0’, the address is interpreted

as being a register in the Access Bank. Addressing that

uses the Access RAM is sometimes also known as

Direct Forced Addressing mode.

A few instructions, such as MOVFF, include the entire

12-bit address (either source or destination) in their

opcodes. In these cases, the BSR is ignored entirely.

The destination of the operation’s results is determined

by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are

stored back in the source register, overwriting its origi-

nal contents. When ‘d’ is ‘0’, the results are stored in

the W register. Instructions without the ‘d’ argument

have a destination that is implicit in the instruction; their

destination is either the target register being operated

on or the W register.

6.4.3 INDIRECT ADDRESSING

Indirect Addressing allows the user to access a location

in data memory without giving a fixed address in the

instruction. This is done by using File Select Registers

(FSRs) as pointers to the locations to be read or written

to. Since the FSRs are themselves located in RAM as

Special Function Registers, they can also be directly

manipulated under program control. This makes FSRs

very useful in implementing data structures such as

tables and arrays in data memory.

The registers for Indirect Addressing are also

implemented with Indirect File Operands (INDFs) that

permit automatic manipulation of the pointer value with

auto-incrementing, auto-decrementing or offsetting

with another value. This allows for efficient code using

loops, such as the example of clearing an entire RAM

bank in Example 6-5. It also enables users to perform

Indexed Addressing and other Stack Pointer

operations for program memory in data memory.

EXAMPLE 6-5: HOW TO CLEAR RAM

(BANK 1) USING INDIRECT

ADDRESSING

Note: The execution of some instructions in the

core PIC18 instruction set are changed

when the PIC18 extended instruction set is

enabled. See Section 6.6 “Data Memory

and the Extended Instruction Set” for

more information.

LFSR FSR0, 100h ;

NEXT CLRF POSTINC0 ; Clear INDF

; register then

; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank1?

BRA NEXT ; NO, clear next

CONTINUE ; YES, continue

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DS39979A-page 72 Preliminary  2010 Microchip Technology Inc.

6.4.3.1 FSR Registers and the

INDF Operand

At the core of Indirect Addressing are three sets of

registers: FSR0, FSR1 and FSR2. Each represents a

pair of 8-bit registers, FSRnH and FSRnL. The four

upper bits of the FSRnH register are not used, so each

FSR pair holds a 12-bit value. This represents a value

that can address the entire range of the data memory

in a linear fashion. The FSR register pairs, then, serve

as pointers to data memory locations.

Indirect Addressing is accomplished with a set of Indi-

rect File Operands, INDF0 through INDF2. These can

be thought of as “virtual” registers: they are mapped in

the SFR space but are not physically implemented.

Reading or writing to a particular INDF register actually

accesses its corresponding FSR register pair. A read

from INDF1, for example, reads the data at the address

indicated by FSR1H:FSR1L. Instructions that use the

INDF registers as operands actually use the contents

of their corresponding FSR as a pointer to the instruc-

tion’s target. The INDF operand is just a convenient

way of using the pointer.

Because Indirect Addressing uses a full 12-bit address,

data RAM banking is not necessary. Thus, the current

contents of the BSR and the Access RAM bit have no

effect on determining the target address.

FIGURE 6-8: INDIRECT ADDRESSING

FSR1H:FSR1L

Data Memory

000h

100h

200h

300h

F00h

E00h

FFFh

Bank 0

Bank 1

Bank 2

Bank 14

Bank 15

Bank 3

through

Bank 13

ADDWF, INDF1, 1

Using an instruction with one of the

Indirect Addressing registers as the

operand....

...uses the 12-bit address stored in

the FSR pair associated with that

...to determine the data memory

location to be used in that operation.

In this case, the FSR1 pair contains

FCCh. This means the contents of

location, FCCh, will be added to that

of the W register and stored back in

FCCh.

xxxx1111 11001100

 2010 Microchip Technology Inc. Preliminary DS39979A-page 73

PIC18F87J72 FAMILY

6.4.3.2 FSR Registers and POSTINC,

POSTDEC, PREINC and PLUSW

In addition to the INDF operand, each FSR register pair

also has four additional indirect operands. Like INDF,

these are “virtual” registers that cannot be indirectly

read or written to. Accessing these registers actually

accesses the associated FSR register pair, but also

performs a specific action on its stored value. They are:

• POSTDEC: accesses the FSR value, then

automatically decrements it by ‘1’ afterwards

• POSTINC: accesses the FSR value, then

automatically increments it by ‘1’ afterwards

• PREINC: increments the FSR value by ‘1’, then

uses it in the operation

• PLUSW: adds the signed value of the W register

(range of -127 to 128) to that of the FSR and uses

the new value in the operation

In this context, accessing an INDF register uses the

value in the FSR registers without changing them.

Similarly, accessing a PLUSW register gives the FSR

value offset by the value in the W register; neither value

is actually changed in the operation. Accessing the

other virtual registers changes the value of the FSR

registers.

Operations on the FSRs with POSTDEC, POSTINC

and PREINC affect the entire register pair; that is, roll-

overs of the FSRnL register from FFh to 00h carry over

to the FSRnH register. On the other hand, results of

these operations do not change the value of any flags

in the STATUS register (e.g., Z, N, OV, etc.).

The PLUSW register can be used to implement a form

of Indexed Addressing in the data memory space. By

manipulating the value in the W register, users can

reach addresses that are fixed offsets from pointer

addresses. In some applications, this can be used to

implement some powerful program control structure,

such as software stacks, inside of data memory.

6.4.3.3 Operations by FSRs on FSRs

Indirect Addressing operations that target other FSRs

or virtual registers represent special cases. For

example, using an FSR to point to one of the virtual

registers will not result in successful operations. As a

specific case, assume that the FSR0H:FSR0L regis-

ters contain FE7h, the address of INDF1. Attempts to

read the value of the INDF1, using INDF0 as an

operand, will return 00h. Attempts to write to INDF1,

using INDF0 as the operand, will result in a NOP.

On the other hand, using the virtual registers to write to

an FSR pair may not occur as planned. In these cases,

the value will be written to the FSR pair but without any

incrementing or decrementing. Thus, writing to INDF2

or POSTDEC2 will write the same value to the

FSR2H:FSR2L.

Since the FSRs are physical registers mapped in the

SFR space, they can be manipulated through all direct

operations. Users should proceed cautiously when

working on these registers, particularly if their code

uses Indirect Addressing.

Similarly, operations by Indirect Addressing are gener-

ally permitted on all other SFRs. Users should exercise

the appropriate caution that they do not inadvertently

change settings that might affect the operation of the

device.

6.5 Program Memory and the

Extended Instruction Set

The operation of program memory is unaffected by the

use of the extended instruction set.

Enabling the extended instruction set adds five

additional two-word commands to the existing PIC18

instruction set: ADDFSR, CALLW, MOVSF, MOVSS and

SUBFSR. These instructions are executed as described

in Section 6.2.4 “Two-Word Instructions”.

PIC18F87J72 FAMILY

DS39979A-page 74 Preliminary  2010 Microchip Technology Inc.

6.6 Data Memory and the Extended

Instruction Set

Enabling the PIC18 extended instruction set (XINST

Configuration bit = 1) significantly changes certain

aspects of data memory and its addressing. Specifically,

the use of the Access Bank for many of the core PIC18

instructions is different. This is due to the introduction of

a new addressing mode for the data memory space.

This mode also alters the behavior of Indirect

Addressing using FSR2 and its associated operands.

What does not change is just as important. The size of

the data memory space is unchanged, as well as its

linear addressing. The SFR map remains the same.

Core PIC18 instructions can still operate in both Direct

and Indirect Addressing mode; inherent and literal

instructions do not change at all. Indirect Addressing

with FSR0 and FSR1 also remains unchanged.

6.6.1 INDEXED ADDRESSING WITH

LITERAL OFFSET

Enabling the PIC18 extended instruction set changes

the behavior of Indirect Addressing using the FSR2

proper conditions, instructions that use the Access

Bank – that is, most bit-oriented and byte-oriented

instructions – can invoke a form of Indexed Addressing

using an offset specified in the instruction. This special

addressing mode is known as Indexed Addressing with

Literal Offset, or Indexed Literal Offset mode.

When using the extended instruction set, this

addressing mode requires the following:

• The use of the Access Bank is forced (‘a’ = 0);

and

• The file address argument is less than or equal to

5Fh.

Under these conditions, the file address of the

instruction is not interpreted as the lower byte of an

address (used with the BSR in Direct Addressing) or as

an 8-bit address in the Access Bank. Instead, the value

is interpreted as an offset value to an Address Pointer

specified by FSR2. The offset and the contents of FSR2

are added to obtain the target address of the operation.

6.6.2 INSTRUCTIONS AFFECTED BY

INDEXED LITERAL OFFSET MODE

Any of the core PIC18 instructions that can use Direct

Addressing are potentially affected by the Indexed

Literal Offset Addressing mode. This includes all

byte-oriented and bit-oriented instructions, or almost

one-half of the standard PIC18 instruction set. Instruc-

tions that only use Inherent or Literal Addressing

modes are unaffected.

Additionally, byte-oriented and bit-oriented instructions

are not affected if they use the Access Bank (Access

RAM bit is ‘1’) or include a file address of 60h or above.

Instructions meeting these criteria will continue to

execute as before. A comparison of the different

possible addressing modes when the extended

instruction set is enabled is shown in Figure 6-9.

Those who desire to use byte-oriented or bit-oriented

instructions in the Indexed Literal Offset mode should

note the changes to assembler syntax for this mode.

This is described in more detail in Section 27.2.1

“Extended Instruction Syntax”.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 75

PIC18F87J72 FAMILY

FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED

INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)

EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)

When a = 0 and f  60h:

The instruction executes in

Direct Forced mode. ‘f’ is

interpreted as a location in the

Access RAM between 060h

and FFFh. This is the same as

locations, F60h to FFFh

(Bank 15), of data memory.

Locations below 060h are not

available in this addressing

mode.

When a = 0 and f5Fh:

The instruction executes in

Indexed Literal Offset mode. ‘f’

is interpreted as an offset to the

address value in FSR2. The

two are added together to

obtain the address of the target

address can be anywhere in

the data memory space.

Note that in this mode, the

correct syntax is now:

ADDWF [k], d

where ‘k’ is the same as ‘f’.

When a = 1 (all values of f):

The instruction executes in

Direct mode (also known as

Direct Long mode). ‘f’ is

interpreted as a location in

one of the 16 banks of the data

memory space. The bank is

designated by the Bank Select

can be in any implemented

bank in the data memory

space.

000h

060h

100h

F00h

F40h

FFFh

Vali d range

00h

60h

FFh

Data Memory

Access RAM

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

000h

060h

100h

F00h

F40h

FFFh

Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

FSR2H FSR2L

ffffffff001001da

000h

060h

100h

F00h

F40h

FFFh

Data Memory

Bank 0

Bank 1

through

Bank 14

Bank 15

SFRs

for ‘f’

BSR

00000000

PIC18F87J72 FAMILY

DS39979A-page 76 Preliminary  2010 Microchip Technology Inc.

6.6.3 MAPPING THE ACCESS BANK IN

INDEXED LITERAL OFFSET MODE

The use of Indexed Literal Offset Addressing mode

effectively changes how the lower part of Access RAM

(00h to 5Fh) is mapped. Rather than containing just the

contents of the bottom part of Bank 0, this mode maps

the contents from Bank 0 and a user-defined “window”

that can be located anywhere in the data memory

space. The value of FSR2 establishes the lower bound-

ary of the addresses mapped into the window, while the

upper boundary is defined by FSR2 plus 95 (5Fh).

Addresses in the Access RAM above 5Fh are mapped

as previously described (see Section 6.3.2 “Access

Bank”). An example of Access Bank remapping in this

addressing mode is shown in Figure 6-10.

Remapping of the Access Bank applies only to opera-

tions using the Indexed Literal Offset mode. Operations

that use the BSR (Access RAM bit is ‘1’) will continue

to use Direct Addressing as before. Any Indirect or

Indexed Addressing operation that explicitly uses any

of the indirect file operands (including FSR2) will con-

tinue to operate as standard Indirect Addressing. Any

instruction that uses the Access Bank, but includes a

Addressing and the normal Access Bank map.

6.6.4 BSR IN INDEXED LITERAL

OFFSET MODE

Although the Access Bank is remapped when the

extended instruction set is enabled, the operation of the

BSR remains unchanged. Direct Addressing, using the

BSR to select the data memory bank, operates in the

same manner as previously described.

FIGURE 6-10: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL

OFFSET ADDRESSING

Data Memory

000h

100h

200h

F60h

F00h

FFFh

Bank 1

Bank 15

Bank 2

through

Bank 14

SFRs

05Fh

ADDWF f, d, a

FSR2H:FSR2L = 120h

Locations in the region

from the FSR2 Pointer

(120h) to the pointer plus

05Fh (17Fh) are mapped

to the bottom of the

Access RAM (000h-05Fh).

Special Function Registers

at F60h through FFFh are

mapped to 60h through

FFh, as usual.

Bank 0 addresses below

5Fh are not available in

this mode. They can still

be addressed by using the

BSR.

Access Bank

00h

FFh

Bank 0

SFRs

Bank 1 “Window”

Not Accessible

Window

Example Situation:

120h

17Fh

5Fh

60h

 2010 Microchip Technology Inc. Preliminary DS39979A-page 77

PIC18F87J72 FAMILY

7.0 FLASH PROGRAM MEMORY

The Flash program memory is readable, writable and

erasable during normal operation over the entire VDD

range.

A read from program memory is executed on one byte

at a time. A write to program memory is executed on

blocks of 64 bytes at a time or two bytes at a time. Pro-

gram memory is erased in blocks of 1,024 bytes at a

time. A bulk erase operation may not be issued from

user code.

Writing or erasing program memory will cease

instruction fetches until the operation is complete. The

program memory cannot be accessed during the write

or erase, therefore, code cannot execute. An internal

programming timer terminates program memory writes

and erases.

A value written to program memory does not need to be

a valid instruction. Executing a program memory

location that forms an invalid instruction results in a

NOP.

7.1 Table Reads and Table Writes

In order to read and write program memory, there are

two operations that allow the processor to move bytes

between the program memory space and the data RAM:

• Table Read (TBLRD)

• Table Write (TBLWT)

The program memory space is 16 bits wide, while the

data RAM space is 8 bits wide. Table reads and table

writes move data between these two memory spaces

through an 8-bit register (TABLAT).

Table read operations retrieve data from program

memory and place it into the data RAM space.

Figure 7-1 shows the operation of a table read with

program memory and data RAM.

Table write operations store data from the data memory

space into holding registers in program memory. The

procedure to write the contents of the holding registers

into program memory is detailed in Section 7.5 “Writing

to Flash Program Memory”. Figure 7-2 shows the

operation of a table write with program memory and data

RAM.

Table operations work with byte entities. A table block

containing data, rather than program instructions, is not

required to be word-aligned. Therefore, a table block can

start and end at any byte address. If a table write is being

used to write executable code into program memory,

program instructions will need to be word-aligned.

FIGURE 7-1: TABLE READ OPERATION

Table Pointer(1)

Table Latch (8-bit)

Program Memory

TBLPTRH TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer register points to a byte in program memory.

Program Memory

(TBLPTR)

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DS39979A-page 78 Preliminary  2010 Microchip Technology Inc.

FIGURE 7-2: TABLE WRITE OPERATION

7.2 Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. These include the:

• EECON1 register

• EECON2 register

• TABLAT register

• TBLPTR registers

7.2.1 EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 7-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The WPROG bit, when set, allows the user to program

a single word (two bytes) upon the execution of the WR

command. If this bit is cleared, the WR command

programs a block of 64 bytes.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WR bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software. It is cleared in

hardware at the completion of the write operation.

Table Pointer(1) Table Latch (8-bit)

TBLPTRH TBLPTRL TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by

TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in

Section 7.5 “Writing to Flash Program Memory”.

Holding Registers

Program Memory

Note: During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 79

PIC18F87J72 FAMILY

U-0 U-0 R/W-0 R/W-0 R/W-x R/W-0 R/S-0 U-0

—— WPROG FREE WRERR(1) WREN WR —

bit 7 bit 0

Legend: S = Settable bit (cannot be cleared in software)

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5 WPROG: One Word-Wide Program bit

1 = Program 2 bytes on the next WR command

0 = Program 64 bytes on the next WR command

bit 4 FREE: Flash Erase Enable bit

1 = Performs an erase operation on the next WR command (cleared by completion of erase operation)

0 = Perform write only

bit 3 WRERR: Flash Program Error Flag bit(1)

1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal

operation or an improper write attempt)

0 = The write operation completed

bit 2 WREN: Flash Program Write Enable bit

1 = Allows write cycles to Flash program memory

0 = Inhibits write cycles to Flash program memory

bit 1 WR: Write Control bit

1 = Initiates a program memory erase cycle or write cycle

(The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.)

0 = Write cycle is complete

bit 0 Unimplemented: Read as ‘0’

Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error

condition.

PIC18F87J72 FAMILY

DS39979A-page 80 Preliminary  2010 Microchip Technology Inc.

7.2.2 TABLE LATCH REGISTER (TABLAT)

The Table Latch (TABLAT) is an 8-bit register mapped

into the SFR space. The Table Latch register is used to

hold 8-bit data during data transfers between program

memory and data RAM.

7.2.3 TABLE POINTER REGISTER

(TBLPTR)

The Table Pointer (TBLPTR) register addresses a byte

within the program memory. The TBLPTR is comprised

of three SFR registers: Table Pointer Upper Byte, Table

Pointer High Byte and Table Pointer Low Byte

(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-

ters join to form a 22-bit wide pointer. The low-order

21 bits allow the device to address up to 2 Mbytes of

program memory space. The 22nd bit allows access to

the device ID, the user ID and the Configuration bits.

The Table Pointer register, TBLPTR, is used by the

TBLRD and TBLWT instructions. These instructions can

update the TBLPTR in one of four ways based on the

table operation. These operations are shown in

Table 7-1. These operations on the TBLPTR only affect

the low-order 21 bits.

7.2.4 TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes and erases of the

Flash program memory.

When a TBLRD is executed, all 22 bits of the TBLPTR

determine which byte is read from program memory

into TABLAT.

When a TBLWT is executed, the seven LSbs of the

Table Pointer register (TBLPTR<6:0>) determine which

of the 64 program memory holding registers is written

to. When the timed write to program memory begins

(via the WR bit), the 12 MSbs of the TBLPTR

(TBLPTR<21:10>) determine which program memory

block of 1,024 bytes is written to. For more detail, see

Section 7.5 “Writing to Flash Program Memory”.

When an erase of program memory is executed, the

12 MSbs of the Table Pointer register point to the

1,024-byte block that will be erased. The Least

Significant bits are ignored.

Figure 7-3 describes the relevant boundaries of

TBLPTR based on Flash program memory operations.

TABLE 7-1: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 7-3: TABLE POINTER BOUNDARIES BASED ON OPERATION

Example Operation on Table Pointer

TBLRD*

TBLWT* TBLPTR is not modified

TBLRD*+

TBLWT*+ TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*- TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+* TBLPTR is incremented before the read/write

21 16 15 87 0

ERASE: TBLPTR<20:10>

TABLE WRITE: TBLPTR<20:6>

TABLE READ: TBLPTR<21:0>

TBLPTRLTBLPTRH

TBLPTRU

 2010 Microchip Technology Inc. Preliminary DS39979A-page 81

PIC18F87J72 FAMILY

7.3 Reading the Flash Program

Memory

The TBLRD instruction is used to retrieve data from

program memory and places it into data RAM. Table

reads from program memory are performed one byte at

a time.

TBLPTR points to a byte address in program space.

Executing TBLRD places the byte pointed to into

TABLAT. In addition, TBLPTR can be modified

automatically for the next table read operation.

The internal program memory is typically organized by

words. The Least Significant bit of the address selects

between the high and low bytes of the word. Figure 7-4

shows the interface between the internal program

memory and the TABLAT.

FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY

EXAMPLE 7-1: READING A FLASH PROGRAM MEMORY WORD

(Even Byte Address)

Program Memory

(Odd Byte Address)

TBLRD TABLAT

TBLPTR = xxxxx1

FETCH

Instruction Register

(IR) Read Register

TBLPTR = xxxxx0

MOVLWCODE_ADDR_UPPER ; Load TBLPTR with the base

MOVWFTBLPTRU ; address of the word

MOVLWCODE_ADDR_HIGH

MOVWFTBLPTRH

MOVLWCODE_ADDR_LOW

MOVWFTBLPTRL

READ_WORD

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWFWORD_EVEN

TBLRD*+ ; read into TABLAT and increment

MOVF TABLAT, W ; get data

MOVWFWORD_ODD

PIC18F87J72 FAMILY

DS39979A-page 82 Preliminary  2010 Microchip Technology Inc.

7.4 Erasing Flash Program Memory

The minimum erase block is 512 words or 1,024 bytes.

Only through the use of an external programmer, or

through ICSP control, can larger blocks of program

memory be bulk erased. Word erase in the Flash array

is not supported.

When initiating an erase sequence from the micro-

controller itself, a block of 1,024 bytes of program

memory is erased. The Most Significant 12 bits of the

TBLPTR<21:10> point to the block being erased.

TBLPTR<9:0> are ignored.

The EECON1 register commands the erase operation.

The WREN bit must be set to enable write operations.

The FREE bit is set to select an erase operation. For

protection, the write initiate sequence for EECON2

must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

7.4.1 FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

1. Load Table Pointer register with the address

being erased.

2. Set the WREN and FREE bits (EECON1<2,4>)

to enable the erase operation.

3. Disable interrupts.

4. Write 55h to EECON2.

5. Write 0AAh to EECON2.

6. Set the WR bit. This will begin the erase cycle.

7. The CPU will stall for duration of the erase for

TIE (see parameter D133B).

8. Re-enable interrupts.

EXAMPLE 7-2: ERASING FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; load TBLPTR with the base

MOVWF TBLPTRU ; address of the memory block

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE

BSF EECON1, WREN

BSF EECON1, FREE ; enable Erase operation

BCF INTCON, GIE ; disable interrupts

Required MOVLW 55h

Sequence MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

 2010 Microchip Technology Inc. Preliminary DS39979A-page 83

PIC18F87J72 FAMILY

7.5 Writing to Flash Program Memory

The programming block is 32 words or 64 bytes.

Programming one word or two bytes at a time is also

supported.

Table writes are used internally to load the holding

registers needed to program the Flash memory. There

are 64 holding registers used by the table writes for

programming.

Since the Table Latch (TABLAT) is only a single byte, the

TBLWT instruction may need to be executed 64 times for

each programming operation (if WPROG = 0). All of the

table write operations will essentially be short writes

because only the holding registers are written. At the

end of updating the 64 holding registers, the EECON1

programming operation with a long write.

The long write is necessary for programming the inter-

nal Flash. Instruction execution is halted while in a long

write cycle. The long write will be terminated by the

internal programming timer.

The on-chip timer controls the write time. The

write/erase voltages are generated by an on-chip

charge pump, rated to operate over the voltage range

of the device.

FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY

7.5.1 FLASH PROGRAM MEMORY WRITE

SEQUENCE

The sequence of events for programming an internal

program memory location should be:

1. Read 1,024 bytes into RAM.

2. Update data values in RAM as necessary.

3. Load Table Pointer register with the address

being erased.

4. Execute the erase procedure.

5. Load Table Pointer register with the address of

the first byte being written, minus 1.

6. Write the 64 bytes into the holding registers with

auto-increment.

7. Set the WREN bit (EECON1<2>) to enable byte

writes.

8. Disable interrupts.

9. Write 55h to EECON2.

10. Write 0AAh to EECON2.

11. Set the WR bit. This will begin the write cycle.

12. The CPU will stall for the duration of the write for

TIW (parameter D133A).

13. Re-enable interrupts.

14. Repeat steps 6 through 13 until all 1,024 bytes

are written to program memory.

15. Verify the memory (table read).

An example of the required code is shown in

Example 7-3 on the following page.

Note 1: Unlike previous PIC18 Flash devices,

members of the PIC18F87J72 family do

not reset the holding registers after a

write occurs. The holding registers must

be cleared or overwritten before a

programming sequence.

2: To maintain the endurance of the program

memory cells, each Flash byte should not

be programmed more than one time

between erase operations. Before

attempting to modify the contents of the

target cell a second time, an erase of the

target, or a bulk erase of the entire

memory, must be performed.

TBLPTR = xxxx3FTBLPTR = xxxxx1TBLPTR = xxxxx0 TBLPTR = xxxxx2

Program Memory

Holding Register Holding Register Holding Register Holding Register

88 8 8

TABLAT

Write Register

Note: Before setting the WR bit, the Table

Pointer address needs to be within the

intended address range of the 64 bytes in

the holding register.

PIC18F87J72 FAMILY

DS39979A-page 84 Preliminary  2010 Microchip Technology Inc.

EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address

MOVWF TBLPTRU ; of the memory block, minus 1

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

ERASE_BLOCK

BSF EECON1, WREN ; enable write to memory

BSF EECON1, FREE ; enable Erase operation

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

MOVWF EECON2 ; write 55h

MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start erase (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

MOVLW D'16'

MOVWF WRITE_COUNTER ; Need to write 16 blocks of 64 to write

; one erase block of 1024

RESTART_BUFFER

MOVLW D'64'

MOVWF COUNTER

MOVLW BUFFER_ADDR_HIGH ; point to buffer

MOVWF FSR0H

MOVLW BUFFER_ADDR_LOW

MOVWF FSR0L

FILL_BUFFER

... ; read the new data from I2C, SPI,

; PSP, USART, etc.

WRITE_BUFFER

MOVLW D’64 ; number of bytes in holding register

MOVWF COUNTER

WRITE_BYTE_TO_HREGS

MOVFF POSTINC0, WREG ; get low byte of buffer data

MOVWF TABLAT ; present data to table latch

TBLWT+* ; write data, perform a short write

; to internal TBLWT holding register.

DECFSZ COUNTER ; loop until buffers are full

BRA WRITE_BYTE_TO_HREGS

PROGRAM_MEMORY

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WREN ; disable write to memory

DECFSZ WRITE_COUNTER ; done with one write cycle

BRA RESTART_BUFFER ; if not done replacing the erase block

 2010 Microchip Technology Inc. Preliminary DS39979A-page 85

PIC18F87J72 FAMILY

7.5.2 FLASH PROGRAM MEMORY WRITE

SEQUENCE (WORD

PROGRAMMING).

The PIC18F87J72 family of devices has a feature that

allows programming a single word (two bytes). This

feature is enabled when the WPROG bit is set. If the

memory location is already erased, the following

sequence is required to enable this feature:

1. Load the Table Pointer register with the address

of the data to be written

2. Write the 2 bytes into the holding registers and

perform a table write

3. Set WPROG to enable single-word write.

4. Set WREN to enable write to memory.

5. Disable interrupts.

6. Write 55h to EECON2.

7. Write 0AAh to EECON2.

8. Set the WR bit. This will begin the write cycle.

9. The CPU will stall for duration of the write for TIW

(see parameter D133A).

10. Re-enable interrupts.

EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY

MOVLW CODE_ADDR_UPPER ; Load TBLPTR with the base address

MOVWF TBLPTRU

MOVLW CODE_ADDR_HIGH

MOVWF TBLPTRH

MOVLW CODE_ADDR_LOW

MOVWF TBLPTRL

MOVLW DATA0

MOVWF TABLAT

TBLWT*+

MOVLW DATA1

MOVWF TABLAT

TBLWT*

PROGRAM_MEMORY

BSF EECON1, WPROG ; enable single word write

BSF EECON1, WREN ; enable write to memory

BCF INTCON, GIE ; disable interrupts

MOVLW 55h

Required MOVWF EECON2 ; write 55h

Sequence MOVLW 0AAh

MOVWF EECON2 ; write 0AAh

BSF EECON1, WR ; start program (CPU stall)

BSF INTCON, GIE ; re-enable interrupts

BCF EECON1, WPROG ; disable single word write

BCF EECON1, WREN ; disable write to memory

PIC18F87J72 FAMILY

DS39979A-page 86 Preliminary  2010 Microchip Technology Inc.

7.5.3 WRITE VERIFY

Depending on the application, good programming

practice may dictate that the value written to the

memory should be verified against the original value.

This should be used in applications where excessive

writes can stress bits near the specification limit.

7.5.4 UNEXPECTED TERMINATION OF

WRITE OPERATION

If a write is terminated by an unplanned event, such as

loss of power or an unexpected Reset, the memory

location just programmed should be verified and repro-

grammed if needed. If the write operation is interrupted

by a MCLR Reset or a WDT time-out Reset during

normal operation, the user can check the WRERR bit

and rewrite the location(s) as needed.

7.6 Flash Program Operation During

Code Protection

See Section 26.6 “Program Verification and Code

Protection” for details on code protection of Flash

program memory.

TABLE 7-2: REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values on

Page:

TBLPTRU —— bit 21 Program Memory Table Pointer Upper Byte

(TBLPTR<20:16>)

TBPLTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>) 49

TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>) 49

TABLAT Program Memory Table Latch 49

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

EECON2 EEPROM Control Register 2 (not a physical register) 51

EECON1 —— WPROG FREE WRERR WREN WR —51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 87

PIC18F87J72 FAMILY

8.0 8 x 8 HARDWARE MULTIPLIER

8.1 Introduction

All PIC18 devices include an 8 x 8 hardware multiplier

as part of the ALU. The multiplier performs an unsigned

operation and yields a 16-bit result that is stored in the

product register pair, PRODH:PRODL. The multiplier’s

operation does not affect any flags in the STATUS

Making multiplication a hardware operation allows it to

be completed in a single instruction cycle. This has the

advantages of higher computational throughput and

reduced code size for multiplication algorithms and

allows the PIC18 devices to be used in many applica-

tions previously reserved for digital signal processors.

A comparison of various hardware and software

multiply operations, along with the savings in memory

and execution time, is shown in Table 8-1.

8.2 Operation

Example 8-1 shows the instruction sequence for an 8 x 8

unsigned multiplication. Only one instruction is required

when one of the arguments is already loaded in the

WREG register.

Example 8-2 shows the sequence to do an 8 x 8 signed

multiplication. To account for the sign bits of the argu-

ments, each argument’s Most Significant bit (MSb) is

tested and the appropriate subtractions are done.

EXAMPLE 8-1: 8 x 8 UNSIGNED MULTIPLY

ROUTINE

EXAMPLE 8-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

TABLE 8-1: PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine Multiply Method

Program

Memory

(Words)

Cycles

(Max)

Time

@ 48 MHz @ 10 MHz @ 4 MHz

8 x 8 unsigned Without hardware multiply 13 69 5.7 s27.6 s69 s

Hardware multiply 1 1 83.3 ns 400 ns 1 s

8 x 8 signed Without hardware multiply 33 91 7.5 s36.4 s91 s

Hardware multiply 6 6 500 ns 2.4 s6 s

16 x 16 unsigned Without hardware multiply 21 242 20.1 s96.8 s242 s

Hardware multiply 28 28 2.3 s 11.2 s28 s

16 x 16 signed Without hardware multiply 52 254 21.6 s 102.6 s254 s

Hardware multiply 35 40 3.3 s16.0 s40 s

PIC18F87J72 FAMILY

DS39979A-page 88 Preliminary  2010 Microchip Technology Inc.

Example 8-3 shows the sequence to do a 16 x 16

unsigned multiplication. Equation 8-1 shows the

algorithm that is used. The 32-bit result is stored in four

registers (RES3:RES0).

EQUATION 8-1: 16 x 16 UNSIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16

signed multiply. Equation 8-2 shows the algorithm

used. The 32-bit result is stored in four registers

(RES3:RES0). To account for the sign bits of the

arguments, the MSb for each argument pair is tested

and the appropriate subtractions are done.

EQUATION 8-2: 16 x 16 SIGNED

MULTIPLICATION

ALGORITHM

EXAMPLE 8-4: 16 x 16 SIGNED MULTIPLY

ROUTINE

RES3:RES0 = ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L)

MOVF ARG1L, W

MULWF ARG2L ; ARG1L * ARG2L->

; PRODH:PRODL

MOVFF PRODH, RES1 ;

MOVFF PRODL, RES0 ;

;

MOVF ARG1H, W

MULWF ARG2H ; ARG1H * ARG2H->

; PRODH:PRODL

MOVFF PRODH, RES3 ;

MOVFF PRODL, RES2 ;

;

MOVF ARG1L, W

MULWF ARG2H ; ARG1L * ARG2H->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

;

MOVF ARG1H, W ;

MULWF ARG2L ; ARG1H * ARG2L->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWF RES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFC RES3, F ;

RES3:RES0= ARG1H:ARG1L  ARG2H:ARG2L

= (ARG1H  ARG2H  216) +

(ARG1H  ARG2L  28) +

(ARG1L  ARG2H  28) +

(ARG1L  ARG2L) +

(-1  ARG2H<7>  ARG1H:ARG1L  216) +

(-1  ARG1H<7>  ARG2H:ARG2L  216)

MOVF ARG1L, W

MULWFARG2L ; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFFPRODH, RES1;

MOVFFPRODL, RES0;

;

MOVF ARG1H, W

MULWFARG2H ; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFFPRODH, RES3;

MOVFFPRODL, RES2;

;

MOVF ARG1L, W

MULWFARG2H ; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWFRES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFCRES2, F ;

CLRF WREG ;

ADDWFCRES3, F ;

;

MOVF ARG1H, W ;

MULWFARG2L ; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF PRODL, W ;

ADDWFRES1, F ; Add cross

MOVF PRODH, W ; products

ADDWFC RES2, F ;

CLRF WREG ;

ADDWFCRES3, F ;

;

BTFSSARG2H, 7 ; ARG2H:ARG2L neg?

BRA SIGN_ARG1 ; no, check ARG1

MOVF ARG1L, W ;

SUBWFRES2 ;

MOVF ARG1H, W ;

SUBWFBRES3

;

SIGN_ARG1

BTFSSARG1H, 7 ; ARG1H:ARG1L neg?

BRA CONT_CODE ; no, done

MOVF ARG2L, W ;

SUBWFRES2 ;

MOVF ARG2H, W ;

SUBWFBRES3

;

CONT_CODE

 2010 Microchip Technology Inc. Preliminary DS39979A-page 89

PIC18F87J72 FAMILY

9.0 INTERRUPTS

Members of the PIC18F87J72 family of devices have

multiple interrupt sources and an interrupt priority

feature that allows most interrupt sources to be

assigned a high-priority level or a low-priority level. The

high-priority interrupt vector is at 0008h and the

low-priority interrupt vector is at 0018h. High-priority

interrupt events will interrupt any low-priority interrupts

that may be in progress.

There are thirteen registers which are used to control

interrupt operation. These registers are:

• RCON

•INTCON

• INTCON2

• INTCON3

• PIR1, PIR2, PIR3

• PIE1, PIE2, PIE3

• IPR1, IPR2, IPR3

It is recommended that the Microchip header files

supplied with MPLAB® IDE be used for the symbolic bit

names in these registers. This allows the

assembler/compiler to automatically take care of the

placement of these bits within the specified register.

In general, interrupt sources have three bits to control

their operation. They are:

•Flag bit to indicate that an interrupt event

occurred

•Enable bit that allows program execution to

branch to the interrupt vector address when the

flag bit is set

•Priority bit to select high priority or low priority

The interrupt priority feature is enabled by setting the

IPEN bit (RCON<7>). When interrupt priority is

enabled, there are two bits which enable interrupts

globally. Setting the GIEH bit (INTCON<7>) enables all

interrupts that have the priority bit set (high priority).

Setting the GIEL bit (INTCON<6>) enables all

interrupts that have the priority bit cleared (low priority).

When the interrupt flag, enable bit and appropriate

global interrupt enable bit are set, the interrupt will

vector immediately to address 0008h or 0018h,

depending on the priority bit setting. Individual

interrupts can be disabled through their corresponding

enable bits.

When the IPEN bit is cleared (default state), the

interrupt priority feature is disabled and interrupts are

compatible with PIC® mid-range devices. In

Compatibility mode, the interrupt priority bits for each

source have no effect. INTCON<6> is the PEIE bit

which enables/disables all peripheral interrupt sources.

INTCON<7> is the GIE bit which enables/disables all

interrupt sources. All interrupts branch to address

0008h in Compatibility mode.

When an interrupt is responded to, the global interrupt

enable bit is cleared to disable further interrupts. If the

IPEN bit is cleared, this is the GIE bit. If interrupt priority

levels are used, this will be either the GIEH or GIEL bit.

High-priority interrupt sources can interrupt a

low-priority interrupt. Low-priority interrupts are not

processed while high-priority interrupts are in progress.

The return address is pushed onto the stack and the

PC is loaded with the interrupt vector address (0008h

or 0018h). Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bits must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine and sets the GIE bit (GIEH or GIEL

if priority levels are used) which re-enables interrupts.

For external interrupt events, such as the INTx pins or

the PORTB input change interrupt, the interrupt latency

will be three to four instruction cycles. The exact

latency is the same for one or two-cycle instructions.

Individual interrupt flag bits are set regardless of the

status of their corresponding enable bit or the GIE bit.

Note: Do not use the MOVFF instruction to modify

any of the Interrupt Control registers while

any interrupt is enabled. Doing so may

cause erratic microcontroller behavior.

PIC18F87J72 FAMILY

DS39979A-page 90 Preliminary  2010 Microchip Technology Inc.

FIGURE 9-1: PIC18F87J72 FAMILY INTERRUPT LOGIC

TMR0IE

GIE/GIEH

PEIE/GIEL

Wake-up if in

Interrupt to CPU

Vector to Location

0008h

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP

IPEN

TMR0IF

TMR0IP

INT1IF

INT1IE

INT1IP

INT2IF

INT2IE

INT2IP

RBIF

RBIE

RBIP

INT0IF

INT0IE

PEIE/GIEL

Interrupt to CPU

Vector to Location

IPEN

0018h

PIR1<6:3,1:0>

PIE1<6:3,1:0>

IPR1<6:3,1:0>

High-Priority Interrupt Generation

Low-Priority Interrupt Generation

Idle or Sleep modes

GIE/GIEH

INT3IF

INT3IE

INT3IP

INT3IF

INT3IE

INT3IP

PIR2<7:6,3:1>

PIE2<7:6 3:1>

IPR2<7:6,3:1>

PIR3<6:0>

PIE3<6:0>

IPR3<6:0>

PIR1<6:3,1:0>

PIE1<6:3,1:0>

IPR1<6:3,1:0>

PIR2<7:6,3:1>

PIE2<7:6,3:1>

IPR2<7:6,3:1>

PIR3<6:0>

PIE3<6:0>

IPR3<6:0>

IPEN

 2010 Microchip Technology Inc. Preliminary DS39979A-page 91

PIC18F87J72 FAMILY

9.1 INTCON Registers

The INTCON registers are readable and writable

registers which contain various enable, priority and flag

bits.

Note: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

interrupt enable bit. User software should

ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt.

This feature allows for software polling.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN = 1:

1 = Enables all high-priority interrupts

0 = Disables all interrupts

bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit

When IPEN = 0:

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

When IPEN = 1:

1 = Enables all low-priority peripheral interrupts

0 = Disables all low-priority peripheral interrupts

bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 overflow interrupt

0 = Disables the TMR0 overflow interrupt

bit 4 INT0IE: INT0 External Interrupt Enable bit

1 = Enables the INT0 external interrupt

0 = Disables the INT0 external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 TMR0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

bit 1 INT0IF: INT0 External Interrupt Flag bit

1 = The INT0 external interrupt occurred (must be cleared in software)

0 = The INT0 external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit(1)

1 = At least one of the RB<7:4> pins changed state (must be cleared in software)

0 = None of the RB<7:4> pins have changed state

Note 1: A mismatch condition will continue to set this bit. Reading PORTB, then waiting one instruction cycle, will

end the mismatch condition and allow the bit to be cleared.

PIC18F87J72 FAMILY

DS39979A-page 92 Preliminary  2010 Microchip Technology Inc.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = All PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG0: External Interrupt 0 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 5 INTEDG1: External Interrupt 1 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 4 INTEDG2: External Interrupt 2 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 3 INTEDG3: External Interrupt 3 Edge Select bit

1 = Interrupt on rising edge

0 = Interrupt on falling edge

bit 2 TMR0IP: TMR0 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

bit 1 INT3IP: INT3 External Interrupt Priority bit

1 =High priority

0 = Low priority

bit 0 RBIP: RB Port Change Interrupt Priority bit

1 =High priority

0 = Low priority

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 93

PIC18F87J72 FAMILY

R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 INT2IP: INT2 External Interrupt Priority bit

1 =High priority

0 = Low priority

bit 6 INT1IP: INT1 External Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5 INT3IE: INT3 External Interrupt Enable bit

1 = Enables the INT3 external interrupt

0 = Disables the INT3 external interrupt

bit 4 INT2IE: INT2 External Interrupt Enable bit

1 = Enables the INT2 external interrupt

0 = Disables the INT2 external interrupt

bit 3 INT1IE: INT1 External Interrupt Enable bit

1 = Enables the INT1 external interrupt

0 = Disables the INT1 external interrupt

bit 2 INT3IF: INT3 External Interrupt Flag bit

1 = The INT3 external interrupt occurred (must be cleared in software)

0 = The INT3 external interrupt did not occur

bit 1 INT2IF: INT2 External Interrupt Flag bit

1 = The INT2 external interrupt occurred (must be cleared in software)

0 = The INT2 external interrupt did not occur

bit 0 INT1IF: INT1 External Interrupt Flag bit

1 = The INT1 external interrupt occurred (must be cleared in software)

0 = The INT1 external interrupt did not occur

Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding

enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits

are clear prior to enabling an interrupt. This feature allows for software polling.

PIC18F87J72 FAMILY

DS39979A-page 94 Preliminary  2010 Microchip Technology Inc.

9.2 PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Request (Flag) registers (PIR1, PIR2, PIR3).

Note 1: Interrupt flag bits are set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE (INTCON<7>).

2: User software should ensure the

appropriate interrupt flag bits are cleared

prior to enabling an interrupt and after

servicing that interrupt.

U-0 R/W-0 R-0 R-0 R/W-0 U-0 R/W-0 R/W-0

— ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

bit 5 RC1IF: EUSART Receive Interrupt Flag bit

1 = The EUSART receive buffer, RCREG1, is full (cleared when RCREG1 is read)

0 = The EUSART receive buffer is empty

bit 4 TX1IF: EUSART Transmit Interrupt Flag bit

1 = The EUSART transmit buffer, TXREG1, is empty (cleared when TXREG1 is written)

0 = The EUSART transmit buffer is full

bit 3 SSPIF: Master Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

bit 2 Unimplemented: Read as ‘0’

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

 2010 Microchip Technology Inc. Preliminary DS39979A-page 95

PIC18F87J72 FAMILY

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

OSCFIF CMIF ——BCLIFLVDIFTMR3IF—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit

1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0 = Device clock operating

bit 6 CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed (must be cleared in software)

0 = Comparator input has not changed

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision occurred (must be cleared in software)

0 = No bus collision occurred

bit 2 LVDIF: Low-Voltage Detect Interrupt Flag bit

1 = A low-voltage condition occurred (must be cleared in software)

0 = The device voltage is above the regulator’s low-voltage trip point

bit 1 TMR3IF: TMR3 Overflow Interrupt Flag bit

1 = TMR3 register overflowed (must be cleared in software)

0 = TMR3 register did not overflow

bit 0 Unimplemented: Read as ‘0’

PIC18F87J72 FAMILY

DS39979A-page 96 Preliminary  2010 Microchip Technology Inc.

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 LCDIF: LCD Interrupt Flag bit (valid when Type-B waveform with Non-Static mode is selected)

1 = LCD data of all COMs is output (must be cleared in software)

0 = LCD data of all COMs is not yet output

bit 5 RC2IF: AUSART Receive Interrupt Flag bit

1 = The AUSART receive buffer, RCREG2, is full (cleared when RCREG2 is read)

0 = The AUSART receive buffer is empty

bit 4 TX2IF: AUSART Transmit Interrupt Flag bit

1 = The AUSART transmit buffer, TXREG2, is empty (cleared when TXREG2 is written)

0 = The AUSART transmit buffer is full

bit 3 CTMUIF: CTMU Interrupt Flag bit

1 = CTMU interrupt occured (must be cleared in software)

0 = No CTMU interrupt occured

bit 2 CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1/TMR3 register capture occurred (must be cleared in software)

0 = No TMR1/TMR3 register capture occurred

Compare mode:

1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)

0 = No TMR1/TMR3 register compare match occurred

PWM mode:

Unused in this mode.

bit 1 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR1/TMR3 register capture occurred (must be cleared in software)

0 = No TMR1/TMR3 register capture occurred

Compare mode:

1 = A TMR1/TMR3 register compare match occurred (must be cleared in software)

0 = No TMR1/TMR3 register compare match occurred

PWM mode:

Unused in this mode.

bit 0 RTCCIF: RTCC Interrupt Flag bit

1 = RTCC interrupt occured (must be cleared in software)

0 = No RTCC interrupt occured

 2010 Microchip Technology Inc. Preliminary DS39979A-page 97

PIC18F87J72 FAMILY

9.3 PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Enable registers (PIE1, PIE2, PIE3). When

IPEN = 0, the PEIE bit must be set to enable any of

these peripheral interrupts.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

— ADIE RC1IE TX1IE SSPIE — TMR2IE TMR1IE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5 RC1IE: EUSART Receive Interrupt Enable bit

1 = Enables the EUSART receive interrupt

0 = Disables the EUSART receive interrupt

bit 4 TX1IE: EUSART Transmit Interrupt Enable bit

1 = Enables the EUSART transmit interrupt

0 = Disables the EUSART transmit interrupt

bit 3 SSPIE: Master Synchronous Serial Port Interrupt Enable bit

1 = Enables the MSSP interrupt

0 = Disables the MSSP interrupt

bit 2 Unimplemented: Read as ‘0’

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

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DS39979A-page 98 Preliminary  2010 Microchip Technology Inc.

R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0

OSCFIE CMIE —— BCLIE LVDIE TMR3IE —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 6 CMIE: Comparator Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCLIE: Bus Collision Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 2 LVDIE: Low-Voltage Detect Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 0 Unimplemented: Read as ‘0’

 2010 Microchip Technology Inc. Preliminary DS39979A-page 99

PIC18F87J72 FAMILY

U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

— LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 LCDIE: LCD Interrupt Enable bit (valid when Type-B waveform with Non-Static mode is selected)

1 = Enabled

0 = Disabled

bit 5 RC2IE: AUSART Receive Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 4 TX2IE: AUSART Transmit Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 3 CTMUIE: CTMU Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 2 CCP2IE: CCP2 Interrupt Enable bit

1 = Enabled

0 = Disabled

bit 1 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 0 RTCCIE: RTCC Interrupt Enable bit

1 = Enabled

0 = Disabled

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DS39979A-page 100 Preliminary  2010 Microchip Technology Inc.

9.4 IPR Registers

The IPR registers contain the individual priority bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are three Peripheral

Interrupt Priority registers (IPR1, IPR2, IPR3). Using

the priority bits requires that the Interrupt Priority

Enable (IPEN) bit be set.

U-0 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 R/W-1

— ADIP RC1IP TX1IP SSPIP — TMR2IP TMR1IP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 ADIP: A/D Converter Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5 RC1IP: EUSART Receive Interrupt Priority bit

1 =High priority

0 = Low priority

bit 4 TX1IP: EUSART Transmit Interrupt Priority bit

1 =High priority

0 = Low priority

bit 3 SSPIP: Master Synchronous Serial Port Interrupt Priority bit

1 =High priority

0 = Low priority

bit 2 Unimplemented: Read as ‘0’

bit 1 TMR2IP: TMR2 to PR2 Match Interrupt Priority bit

1 =High priority

0 = Low priority

bit 0 TMR1IP: TMR1 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

 2010 Microchip Technology Inc. Preliminary DS39979A-page 101

PIC18F87J72 FAMILY

R/W-1 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 U-0

OSCFIP CMIP —— BCLIP LVDIP TMR3IP —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit

1 =High priority

0 = Low priority

bit 6 CMIP: Comparator Interrupt Priority bit

1 =High priority

0 = Low priority

bit 5-4 Unimplemented: Read as ‘0’

bit 3 BCLIP: Bus Collision Interrupt Priority bit

1 =High priority

0 = Low priority

bit 2 LVDIP: Low-Voltage Detect Interrupt Priority bit

1 =High priority

0 = Low priority

bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit

1 =High priority

0 = Low priority

bit 0 Unimplemented: Read as ‘0’

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DS39979A-page 102 Preliminary  2010 Microchip Technology Inc.

U-0 R/W-1 R-1 R-1 R/W-1 R/W-1 R/W-1 R/W-1

— LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 LCDIP: LCD Interrupt Priority bit (valid when Type-B waveform with Non-Static mode is selected)

1 =High priority

0 = Low priority

bit 5 RC2IP: AUSART Receive Priority Flag bit

1 =High priority

0 = Low priority

bit 4 TX2IP: AUSART Transmit Interrupt Priority bit

1 =High priority

0 = Low priority

bit 3 CTMUIP: CTMU Interrupt Priority bit

1 =High priority

0 = Low priority

bit CCP2IP: CCP2 Interrupt Priority bit

1 =High priority

0 = Low priority

bit CCP1IP: CCP1 Interrupt Priority bit

1 =High priority

0 = Low priority

bit 0 RTCCIP: RTCC Interrupt Priority bit

1 =High priority

0 = Low priority

 2010 Microchip Technology Inc. Preliminary DS39979A-page 103

PIC18F87J72 FAMILY

9.5 RCON Register

The RCON register contains bits used to determine the

cause of the last Reset or wake-up from Idle or Sleep

modes. RCON also contains the bit that enables

interrupt priorities (IPEN).

R/W-0 U-0 R/W-1 R/W-1 R-1 R-1 R/W-0 R/W-0

IPEN —CMRI TO PD POR BOR

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IPEN: Interrupt Priority Enable bit

1 = Enable priority levels on interrupts

0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6 Unimplemented: Read as ‘0’

bit 5 CM: Configuration Mismatch Flag bit

1 = A Configuration Mismatch Reset has not occurred

0 = A Configuration Mismatch Reset has occurred (Must be subsequently set in software.)

bit 4 RI: RESET Instruction Flag bit

For details of bit operation, see Register 5-1.

bit 3 TO: Watchdog Timer Time-out Flag bit

For details of bit operation, see Register 5-1.

bit 2 PD: Power-Down Detection Flag bit

For details of bit operation, see Register 5-1.

bit 1 POR: Power-on Reset Status bit

For details of bit operation, see Register 5-1.

bit 0 BOR: Brown-out Reset Status bit

For details of bit operation, see Register 5-1.

PIC18F87J72 FAMILY

DS39979A-page 104 Preliminary  2010 Microchip Technology Inc.

9.6 INTx Pin Interrupts

External interrupts on the RB0/INT0, RB1/INT1,

RB2/INT2 and RB3/INT3 pins are edge-triggered. If the

corresponding INTEDGx bit in the INTCON2 register is

set (= 1), the interrupt is triggered by a rising edge; if

the bit is clear, the trigger is on the falling edge. When

a valid edge appears on the RBx/INTx pin, the

corresponding flag bit, INTxIF, is set. This interrupt can

be disabled by clearing the corresponding enable bit,

INTxIE. Flag bit, INTxIF, must be cleared in software in

the Interrupt Service Routine (ISR) before re-enabling

the interrupt.

All external interrupts (INT0, INT1, INT2 and INT3) can

wake-up the processor from the power-managed

modes if bit INTxIE was set prior to going into the

power-managed modes. If the Global Interrupt Enable

bit, GIE, is set, the processor will branch to the interrupt

vector following wake-up.

Interrupt priority for INT1, INT2 and INT3 is determined

by the value contained in the interrupt priority bits,

INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and

INT3IP (INTCON2<1>). There is no priority bit

associated with INT0. It is always a high-priority

interrupt source.

9.7 TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh 00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L register

pair (FFFFh 0000h) will set TMR0IF. The interrupt can

be enabled/disabled by setting/clearing enable bit,

TMR0IE (INTCON<5>). Interrupt priority for Timer0 is

determined by the value contained in the interrupt priority

bit, TMR0IP (INTCON2<2>). See Section 11.0 “Timer0

Module” for further details on the Timer0 module.

9.8 PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

9.9 Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the Fast Return Stack. If a fast

return from interrupt is not used (see Section 6.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 9-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 9-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF W_TEMP ; W_TEMP is in virtual bank

MOVFF STATUS, STATUS_TEMP ; STATUS_TEMP located anywhere

MOVFF BSR, BSR_TEMP ; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF BSR_TEMP, BSR ; Restore BSR

MOVF W_TEMP, W ; Restore WREG

MOVFF STATUS_TEMP, STATUS ; Restore STATUS

 2010 Microchip Technology Inc. Preliminary DS39979A-page 105

PIC18F87J72 FAMILY

10.0 I/O PORTS

Depending on the features enabled, there are up to

seven ports available. Some pins of the I/O ports are

multiplexed with an alternate function from the

peripheral features on the device. In general, when a

peripheral is enabled, that pin may not be used as a

general purpose I/O pin.

Each port has three memory mapped registers for its

operation:

• TRIS register (Data Direction register)

• PORT register (reads the levels on the pins of the

device)

• LAT register (Output Latch register)

Reading the PORT register reads the current status of

the pins, whereas writing to the PORT register, writes

to the Output Latch (LAT) register.

Setting a TRIS bit (= 1) makes the corresponding

PORT pin an input (i.e., put the corresponding output

driver in a high-impedance mode). Clearing a TRIS bit

(= 0) makes the corresponding PORT pin an output

(i.e., put the contents of the corresponding LAT bit on

the selected pin).

The Output Latch (LAT register) is useful for

read-modify-write operations on the value that the I/O

pins are driving. Read-modify-write operations on the

LAT register read and write the latched output value for

the PORT register.

A simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 10-1.

FIGURE 10-1: GENERIC I/O PORT

OPERATION

10.1 I/O Port Pin Capabilities

When developing an application, the capabilities of the

port pins must be considered. Outputs on some pins

have higher output drive strength than others. Similarly,

some pins can tolerate higher than VDD input levels.

10.1.1 INPUT PINS AND VOLTAGE

CONSIDERATIONS

The voltage tolerance of pins used as device inputs is

dependent on the pin’s input function. Most of the pins

that are used as digital only inputs are able to handle DC

voltages up to 5.5V, a level typical for digital logic circuits.

In contrast, pins that also have analog input functions of

any kind can only tolerate voltages up to VDD. Table 10-1

summarizes the input voltage capabilities of the I/O pins.

Refer to Section 29.0 “Electrical Characteristics” for

more details. Voltage excursions beyond VDD on these

pins should be avoided.

TABLE 10-1: INPUT VOLTAGE TOLERANCE

10.1.2 PIN OUTPUT DRIVE

When used as digital I/O, the output pin drive strengths

vary for groups of pins intended to meet the needs for

a variety of applications. In general, there are three

classes of output pins in terms of drive capability.

PORTB and PORTC, as well as PORTA<7:6>, are

designed to drive higher current loads, such as LEDs.

PORTD, PORTE and PORTJ can also drive LEDs but

only those with smaller current requirements. PORTF,

PORTG and PORTH, along with PORTA<5:0>, have

the lowest drive level but are capable of driving normal

digital circuit loads with a high input impedance.

Regardless of which port it is located on, all output pins

in LCD Segment or common-mode have sufficient

output to directly drive a display.

Table 10-2 summarizes the output capabilities of the

ports. Refer to the “Absolute Maximum Ratings” in

Section 29.0 “Electrical Characteristics” for more

details.

Data

Bus

WR LAT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Input

Buffer

I/O Pin

CKx

RD LAT

or PORT

PORT or Pin Tolerated

Input Description

PORTA<7:0>

VDD

Only VDD input levels

tolerated.

PORTC<1:0>

PORTF<1,0>

PORTF<7:1>

PORTG<3:2, 0>

PORTB<7:0>

5.5V

Tolerates input

levels above VDD,

useful for most

standard logic.

PORTC<7:2>

PORTD<7:0>

PORTE<7:2>

PORTG<4,1>

PIC18F87J72 FAMILY

DS39979A-page 106 Preliminary  2010 Microchip Technology Inc.

TABLE 10-2: OUTPUT DRIVE LEVELS FOR

VARIOUS PORTS

10.1.3 PULL-UP CONFIGURATION

Four of the I/O ports (PORTB, PORTD, PORTE and

PORTJ) implement configurable weak pull-ups on all

pins. These are internal pull-ups that allow floating

digital input signals to be pulled to a consistent level

without the use of external resistors.

The pull-ups are enabled with a single bit for each of the

ports: RBPU (INTCON2<7>) for PORTB, and RDPU,

REPU and PJPU (PORTG<7:5>) for the other ports.

10.1.4 OPEN-DRAIN OUTPUTS

The output pins for several peripherals are also

equipped with a configurable, open-drain output option.

This allows the peripherals to communicate with

external digital logic, operating at a higher voltage

level, without the use of level translators.

The open-drain option is implemented on port pins

specifically associated with the data and clock outputs

of the USARTs, the MSSP module (in SPI mode) and

the CCP modules. This option is selectively enabled by

setting the open-drain control bit for the corresponding

module in TRISG and LATG. Their configuration is dis-

cussed in more detail in Section 10.4 “PORTC, TRISC

and LATC Registers”, Section 10.6 “PORTE, TRISE

and LATE Registers” and Section 10.8 “PORTG,

TRISG and LATG Registers”.

When the open-drain option is required, the output pin

must also be tied through an external pull-up resistor

provided by the user to a higher voltage level, up to 5V

(Figure 10-2). When a digital logic high signal is output,

it is pulled up to the higher voltage level.

FIGURE 10-2: USING THE OPEN-DRAIN

OUTPUT (USART SHOWN

AS EXAMPLE)

10.2 PORTA, TRISA and

LATA Registers

PORTA is an 8-bit wide, bidirectional port. The corre-

sponding Data Direction and Output Latch registers are

TRISA and LATA.

RA4/T0CKI is a Schmitt Trigger input. All other PORTA

pins have TTL input levels and full CMOS output

drivers.

The RA4 pin is multiplexed with the Timer0 clock input

and one of the LCD segment drives. RA5 and RA<3:0>

are multiplexed with analog inputs for the A/D

Converter.

The operation of the analog inputs as A/D Converter

inputs is selected by clearing or setting the PCFG<3:0>

control bits in the ADCON1 register. The corresponding

TRISA bits control the direction of these pins, even

when they are being used as analog inputs. The user

must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

OSC2/CLKO/RA6 and OSC1/CLKI/RA7 normally

serve as the external circuit connections for the exter-

nal (primary) oscillator circuit (HS Oscillator modes) or

the external clock input and output (EC Oscillator

modes). In these cases, RA6 and RA7 are not available

as digital I/O and their corresponding TRIS and LAT

bits are read as ‘0’. When the device is configured to

use INTOSC or INTRC as the default oscillator mode

(FOSC2 Configuration bit is ‘0’), RA6 and RA7 are

automatically configured as digital I/O. The oscillator

and clock in/clock out functions are disabled.

RA1, RA4 and RA5 are multiplexed with LCD segment

drives, controlled by bits in the LCDSE1 and LCDSE2

registers. I/O port functionality is only available when

the LCD segments are disabled.

EXAMPLE 10-1: INITIALIZING PORTA

Low Medium High

PORTA<5:0> PORTD PORTA<7:6>

PORTF PORTE PORTB

PORTG PORTC

TXX

+5V

3.3V

(at logic ‘1’)

3.3V

VDD 5V

PIC18F87J72

Note: RA5 and RA<3:0> are configured as

analog inputs on any Reset and are read

as ‘0’. RA4 is configured as a digital input.

CLRF PORTA ; Initialize PORTA by

; clearing output latches

CLRF LATA ; Alternate method to

; clear output data latches

MOVLW 07h ; Configure A/D

MOVWF ADCON1 ; for digital inputs

MOVLW 0BFh ; Value used to initialize

; data direction

MOVWF TRISA ; Set RA<7, 5:0> as inputs,

; RA<6> as output

 2010 Microchip Technology Inc. Preliminary DS39979A-page 107

PIC18F87J72 FAMILY

TABLE 10-3: PORTA FUNCTIONS

TABLE 10-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Pin Name Function TRIS

Setting I/O I/O

Type Description

RA0/AN0 RA0 0O DIG LATA<0> data output; not affected by analog input.

1I TTL PORTA<0> data input; disabled when analog input is enabled.

AN0 1I ANA A/D Input Channel 0. Default input configuration on POR; does not

affect digital output.

RA1/AN1/SEG18 RA1 0O DIG LATA<1> data output; not affected by analog input.

1I TTL PORTA<1> data input; disabled when analog input is enabled.

AN1 1I ANA A/D Input Channel 1. Default input configuration on POR; does not

affect digital output.

SEG18 xO ANA LCD Segment 18 output; disables all other pin functions.

RA2/AN2/VREF-RA20O DIG LATA<2> data output; not affected by analog input.

1I TTL PORTA<2> data input; disabled when analog functions are enabled.

AN2 1I ANA A/D Input Channel 2. Default input configuration on POR.

VREF-1I ANA A/D and comparator low reference voltage input.

RA3/AN3/VREF+RA3 0O DIG LATA<3> data output; not affected by analog input.

1I TTL PORTA<3> data input; disabled when analog input is enabled.

AN3 1I ANA A/D Input Channel 3. Default input configuration on POR.

VREF+1I ANA A/D and comparator high reference voltage input.

RA4/T0CKI/

SEG14

RA4 0O DIG LATA<4> data output.

1I ST PORTA<4> data input. Default configuration on POR.

T0CKI xI ST Timer0 clock input.

SEG14 xO ANA LCD Segment 14 output; disables all other pin functions.

RA5/AN4/SEG15 RA5 0O DIG LATA<5> data output; not affected by analog input.

1I TTL PORTA<5> data input; disabled when analog input is enabled.

AN4 1I ANA A/D Input Channel 4. Default configuration on POR.

SEG15 xO ANA LCD Segment 15 output; disables all other pin functions.

OSC2/CLKO/RA6 OSC2 xO ANA Main oscillator feedback output connection (HS and HSPLL modes).

CLKO xO DIG System cycle clock output (FOSC/4) (EC and ECPLL modes).

RA6 0O DIG LATA<6> data output; disabled when FOSC2 Configuration bit is set.

1I TTL PORTA<6> data input; disabled when FOSC2 Configuration bit is set.

OSC1/CLKI/RA7 OSC1 xI ANA Main oscillator input connection (HS and HSPLL modes).

CLKI xI ANA Main external clock source input (EC and ECPLL modes).

RA7 0O DIG LATA<7> data output; disabled when FOSC2 Configuration bit is set.

1I TTL PORTA<7> data input; disabled when FOSC2 Configuration bit is set.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values

on page

PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52

LATA LATA7(1) LATA6(1) LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 52

TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 52

ADCON1 TRIGSEL —VCFG1 VCFG0PCFG3PCFG2PCFG1PCFG0 51

LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 51

LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA.

Note 1: These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are

disabled and read as ‘x’.

PIC18F87J72 FAMILY

DS39979A-page 108 Preliminary  2010 Microchip Technology Inc.

10.3 PORTB, TRISB and

LATB Registers

PORTB is an 8-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISB and LATB. All pins on PORTB are digital only

and tolerate voltages up to 5.5V.

EXAMPLE 10-2: INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB<7:4>) have an

interrupt-on-change feature. Only pins configured as

inputs can cause this interrupt to occur (i.e., any

RB<7:4> pin configured as an output is excluded from

the interrupt-on-change comparison). The input pins (of

RB<7:4>) are compared with the old value latched on

the last read of PORTB. The “mismatch” outputs of

RB<7:4> are ORed together to generate the RB Port

Change Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from

power-managed modes. The user, in the Interrupt

Service Routine, can clear the interrupt in the following

manner:

a) Any read or write of PORTB (except with the

MOVFF (ANY), PORTB instruction). This will end

the mismatch condition.

b) Wait one instruction cycle.

c) Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared after a delay of one

CY.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

RB<3:2> are multiplexed as CTMU edge inputs.

RB<5:0> are also multiplexed with LCD segment

drives, controlled by bits in the LCDSE1 and LCDSE3

registers. I/O port functionality is only available when

the LCD segments are disabled.

CLRF PORTB ; Initialize PORTB by

; clearing output

; data latches

CLRF LATB ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISB ; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

 2010 Microchip Technology Inc. Preliminary DS39979A-page 109

PIC18F87J72 FAMILY

TABLE 10-5: PORTB FUNCTIONS

Pin Name Function TRIS

Setting I/O I/O

Type Description

RB0/INT0/SEG30 RB0 0O DIG LATB<0> data output.

1I TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.

INT0 1I ST External Interrupt 0 input.

SEG30 xO ANA LCD Segment 30 output; disables all other pin functions.

RB1/INT1/SEG8 RB1 0O DIG LATB<1> data output.

1I TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.

INT1 1I ST External Interrupt 1 input.

SEG8 xO ANA LCD Segment 8 output; disables all other pin functions.

RB2/INT2/SEG9/

CTED1

RB2 0O DIG LATB<2> data output.

1I TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.

INT2 1I ST External Interrupt 2 input.

SEG9 xO ANA LCD Segment 9 output; disables all other pin functions.

CTED1 xI ST CTMU Edge 1 input.

RB3/INT3/SEG10/

CTED2

RB3 0O DIG LATB<3> data output.

1I TTL PORTB<3> data input; weak pull-up when RBPU bit is cleared.

INT3 1I ST External Interrupt 3 input.

SEG10 xO ANA LCD Segment 10 output; disables all other pin functions.

CTED2 xI ST CTMU Edge 2 input.

RB4/KBI0/SEG11 RB4 0O DIG LATB<4> data output.

1I TTL PORTB<4> data input; weak pull-up when RBPU bit is cleared.

KBI0 1I TTL Interrupt-on-pin change.

SEG11 xO ANA LCD Segment 11 output; disables all other pin functions.

RB5/KBI1/SEG29 RB5 0O DIG LATB<5> data output.

1I TTL PORTB<5> data input; weak pull-up when RBPU bit is cleared.

KBI1 1I TTL Interrupt-on-pin change.

SEG29 xO ANA LCD Segment 29 output; disables all other pin functions.

RB6/KBI2/PGC RB6 0O DIG LATB<6> data output.

1I TTL PORTB<6> data input; weak pull-up when RBPU bit is cleared.

KBI2 1I TTL Interrupt-on-pin change.

PGC xI ST Serial execution (ICSP™) clock input for ICSP and ICD operation.

RB7/KBI3/PGD RB7 0O DIG LATB<7> data output.

1I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared.

KBI3 1I TTL Interrupt-on-pin change.

PGD xO DIG Serial execution data output for ICSP™ and ICD operation.

xI ST Serial execution data input for ICSP and ICD operation.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F87J72 FAMILY

DS39979A-page 110 Preliminary  2010 Microchip Technology Inc.

TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Reset

Values on

page

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 52

LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 52

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 52

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP 49

INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF 49

LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 51

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

Legend: Shaded cells are not used by PORTB.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 111

PIC18F87J72 FAMILY

10.4 PORTC, TRISC and

LATC Registers

PORTC is an 8-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISC and LATC. Only PORTC pins, RC2 through

RC7, are digital only pins and can tolerate input voltages

up to 5.5V.

PORTC is multiplexed with CCP, MSSP and EUSART

peripheral functions (Table 10-7). The pins have

Schmitt Trigger input buffers. The pins for CCP, SPI

and EUSART are also configurable for open-drain out-

put whenever these functions are active. Open-drain

configuration is selected by setting the SPIOD,

CCPxOD, and U1OD control bits (TRISG<7:5> and

LATG<6>, respectively).

RC1 is normally configured as the default peripheral

pin for the CCP2 module. Assignment of CCP2 is

controlled by Configuration bit, CCP2MX (default state,

CCP2MX = 1).

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an output,

while other peripherals override the TRIS bit to make a

pin an input. The user should refer to the corresponding

peripheral section for the correct TRIS bit settings.

The contents of the TRISC register are affected by

peripheral overrides. Reading TRISC always returns

the current contents, even though a peripheral device

may be overriding one or more of the pins.

RC<7:1> pins are multiplexed with LCD segment

drives, controlled by bits in the LCDSE1, LCDSE2,

LCDSE3 and LCDSE4 registers. I/O port functionality

is only available when the LCD segments are disabled.

EXAMPLE 10-3: INITIALIZING PORTC

Note: These pins are configured as digital inputs

on any device Reset.

CLRF PORTC ; Initialize PORTC by

; clearing output

; data latches

CLRF LATC ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISC ; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

PIC18F87J72 FAMILY

DS39979A-page 112 Preliminary  2010 Microchip Technology Inc.

TABLE 10-7: PORTC FUNCTIONS

Pin Name Function TRIS

Setting I/O I/O

Type Description

RC0/T1OSO/

T13CKI

RC0 0O DIG LATC<0> data output.

1I ST PORTC<0> data input.

T1OSO xO ANA Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables

digital I/O and LCD segment driver.

T13CKI 1I ST Timer1/Timer3 counter input.

RC1/T1OSI/

CCP2/SEG32

RC1 0O DIG LATC<1> data output.

1I ST PORTC<1> data input.

T1OSI xI ANA Timer1 oscillator input.

CCP2(1) 0O DIG CCP2 Compare/PWM output.

1I ST CCP2 Capture input.

SEG32 xO ANA LCD Segment 32 output; disables all other pin functions.

RC2/CCP1/

SEG13

RC2 0O DIG LATC<2> data output.

1I ST PORTC<2> data input.

CCP1 0O DIG CCP1 Compare/PWM output; takes priority over port data.

1I ST CCP1 Capture input.

SEG13 xO ANA LCD Segment 13 output; disables all other pin functions.

RC3/SCK/SCL/

SEG17

RC3 0O DIG LATC<3> data output.

1I ST PORTC<3> data input.

SCK 0O DIG SPI clock output (MSSP module); takes priority over port data.

1I ST SPI clock input (MSSP module).

SCL 0ODIGI

2C™ clock output (MSSP module); takes priority over port data.

1II2CI

2C clock input (MSSP module); input type depends on module setting.

SEG17 xO ANA LCD Segment 17 output; disables all other pin functions.

RC4/SDI/SDA/

SEG16

RC4 0O DIG LATC<4> data output.

1I ST PORTC<4> data input.

SDI I ST SPI data input (MSSP module).

SDA 1ODIGI

2C data output (MSSP module); takes priority over port data.

1II2CI

2C data input (MSSP module); input type depends on module setting.

SEG16 xO ANA LCD Segment 16 output; disables all other pin functions.

RC5/SDO/

SEG12

RC5 0O DIG LATC<5> data output.

1I ST PORTC<5> data input.

SDO 0O DIG SPI data output (MSSP module).

SEG12 xO ANA LCD Segment 12 output; disables all other pin functions.

RC6/TX1/CK1/

SEG27

RC6 0O DIG LATC<6> data output.

1I ST PORTC<6> data input.

TX1 1O DIG Synchronous serial data output (EUSART module); takes priority over port data.

CK1 1O DIG Synchronous serial data input (EUSART module); user must configure as an input.

1I ST Synchronous serial clock input (EUSART module).

SEG27 xO ANA LCD Segment 27 output; disables all other pin functions.

RC7/RX1/DT1/

SEG28

RC7 0O DIG LATC<7> data output.

1I ST PORTC<7> data input.

RX1 1I ST Asynchronous serial receive data input (EUSART module).

DT1 1O DIG Synchronous serial data output (EUSART module); takes priority over port data.

1I ST Synchronous serial data input (EUSART module); user must configure as an input.

SEG28 xO ANA LCD Segment 28 output; disables all other pin functions.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,

I2C = I2C/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Default assignment for CCP2 when CCP2MX Configuration bit is set.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 113

PIC18F87J72 FAMILY

TABLE 10-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 52

LATC LATC7 LATBC6 LATC5 LATCB4 LATC3 LATC2 LATC1 LATC0 52

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 51

LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 51

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

LCDSE4 ——————— SE32 51

Legend: Shaded cells are not used by PORTC.

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DS39979A-page 114 Preliminary  2010 Microchip Technology Inc.

10.5 PORTD, TRISD and

LATD Registers

PORTD is an 8-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISD and LATD. All pins on PORTD are digital only

and tolerate voltages up to 5.5V.

All pins on PORTD are implemented with Schmitt

Trigger input buffers. Each pin is individually

configurable as an input or output.

Each of the PORTD pins has a weak internal pull-up. A

single control bit can turn off all the pull-ups. This is

performed by clearing bit, RDPU (PORTG<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on all device Resets.

All of the PORTD pins are multiplexed with LCD

segment drives, controlled by bits in the LCDSE0

Generator output.

I/O port functionality is only available when the LCD

segments are disabled.

EXAMPLE 10-4: INITIALIZING PORTD

Note: These pins are configured as digital inputs

on any device Reset.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD ; Alternate method

; to clear output

; data latches

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISD ; Set RD<3:0> as inputs

; RD<5:4> as outputs

; RD<7:6> as inputs

 2010 Microchip Technology Inc. Preliminary DS39979A-page 115

PIC18F87J72 FAMILY

TABLE 10-9: PORTD FUNCTIONS

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Pin Name Function TRIS

Setting I/O I/O

Type Description

RD0/SEG0/

CTPLS

RD0 0O DIG LATD<0> data output.

1I ST PORTD<0> data input.

SEG0 xO ANA LCD Segment 0 output; disables all other pin functions.

CTPLS xO DIG CTMU Pulse Generator output

RD1/SEG1 RD1 0O DIG LATD<1> data output.

1I ST PORTD<1> data input.

SEG1 xO ANA LCD Segment 1 output; disables all other pin functions.

RD2/SEG2 RD2 0O DIG LATD<2> data output.

1I ST PORTD<2> data input.

SEG2 xO ANA LCD Segment 2 output; disables all other pin functions.

RD3/SEG3 RD3 0O DIG LATD<3> data output.

1I ST PORTD<3> data input.

SEG3 xO ANA LCD Segment 3 output; disables all other pin functions.

RD4/SEG4 RD4 0O DIG LATD<4> data output.

1I ST PORTD<4> data input.

SEG4 xO ANA LCD Segment 4 output; disables all other pin functions.

RD5/SEG5 RD5 0O DIG LATD<5> data output.

1I ST PORTD<5> data input.

SEG5 xO ANA LCD Segment 5 output; disables all other pin functions.

RD6/SEG6 RD6 0O DIG LATD<6> data output.

1I ST PORTD<6> data input.

SEG6 xO ANA LCD Segment 6 output; disables all other pin functions.

RD7/SEG7 RD7 0O DIG LATD<7> data output.

1I ST PORTD<7> data input.

SEG7 xI ANA LCD Segment 7 output; disables all other pin functions.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 52

LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 52

TRISD TRISD7 TRISD6 TRISD5 TRISD4TRISD3TRISD2TRISD1TRISD0 52

PORTG RDPU REPU RJPU RG4 RG3 RG2 RG1 RG0 52

LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 51

Legend: Shaded cells are not used by PORTD.

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DS39979A-page 116 Preliminary  2010 Microchip Technology Inc.

10.6 PORTE, TRISE and

LATE Registers

PORTE is a 7-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISE and LATE. All pins on PORTE are digital only

and tolerate voltages up to 5.5V.

All pins on PORTE are implemented with Schmitt

Trigger input buffers. Each pin is individually

configurable as an input or output. The RE7 pin is also

configurable for open-drain output when CCP2 is active

on this pin. Open-drain configuration is selected by

setting the CCP2OD control bit (TRISG<6>)

Each of the PORTE pins has a weak internal pull-up. A

single control bit can turn off all the pull-ups. This is

performed by clearing bit, REPU (PORTG<6>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on any device Reset.

Pins, RE<6:3>, are multiplexed with the LCD common

drives. I/O port functions are only available on those

PORTE pins depending on which commons are active.

The configuration is determined by the LMUX<1:0>

control bits (LCDCON<1:0>). The availability is

summarized in Table 10-11.

TABLE 10-11: PORTE PINS AVAILABLE IN

DIFFERENT LCD DRIVE

CONFIGURATIONS

Pins, RE1 and RE0, are multiplexed with the functions

of LCDBIAS2 and LCDBIAS1. When LCD bias genera-

tion is required (i.e., any application where the device

is connected to an external LCD), these pins cannot be

used as digital I/O.

RE7 is multiplexed with the LCD segment drive

(SEG31) controlled by the LCDSE3<7> bit. I/O port

function is only available when the segment is disabled.

RE7 can also be configured as the alternate peripheral

pin for the CCP2 module. This is done by clearing the

CCP2MX Configuration bit.

EXAMPLE 10-5: INITIALIZING PORTE

Note: These pins are configured as digital inputs

on any device Reset.

LCDCON

<1:0>

Active LCD

Commons

PORTE Available

for I/O

00 COM0 RE6, RE5, RE4

01 COM0, COM1 RE6, RE5

10 COM0, COM1

and COM2

RE6

11 All (COM0

through COM3)

None

Note: The pin corresponding to RE2 of other

PIC18F parts has the function of

LCDBIAS3 in this device. It cannot be used

as digital I/O.

CLRF PORTE ; Initialize PORTE by

; clearing output

; data latches

CLRF LATE ; Alternate method

; to clear output

; data latches

MOVLW 03h ; Value used to

; initialize data

; direction

MOVWF TRISE ; Set RE<1:0> as inputs

; RE<7:2> as outputs

 2010 Microchip Technology Inc. Preliminary DS39979A-page 117

PIC18F87J72 FAMILY

TABLE 10-12: PORTE FUNCTIONS

TABLE 10-13: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Pin Name Function TRIS

Setting I/O I/O

Type Description

RE0/LCDBIAS1 RE0 0O DIG LATE<0> data output.

1I ST PORTE<0> data input.

LCDBIAS1 — I ANA LCD module bias voltage input.

RE1/LCDBIAS2 RE1 0O DIG LATE<1> data output.

1I ST PORTE<1> data input.

LCDBIAS2 — I ANA LCD module bias voltage input.

RE3/COM0 RE3 0O DIG LATE<3> data output.

1I ST PORTE<3> data input.

COM0 xO ANA LCD Common 0 output; disables all other outputs.

RE4/COM1 RE4 0O DIG LATE<4> data output.

1I ST PORTE<4> data input.

COM1 xO ANA LCD Common 1 output; disables all other outputs.

RE5/COM2 RE5 0O DIG LATE<5> data output.

1I ST PORTE<5> data input.

COM2 xO ANA LCD Common 2 output; disables all other outputs.

RE6/COM3 RE6 0O DIG LATE<6> data output.

1I ST PORTE<6> data input.

COM3 xO ANA LCD Common 3 output; disables all other outputs.

RE7/CCP2/

SEG31

RE7 0O DIG LATE<7> data output.

1I ST PORTE<7> data input.

CCP2(1) 0O DIG CCP2 Compare/PWM output; takes priority over port data.

1I ST CCP2 Capture input.

SEG31 xO ANA Segment 31 analog output for LCD; disables digital output.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Note 1: Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

PORTE RE7 RE6 RE5 RE4 RE3 —RE1RE052

LATE LATE7 LATE6 LATE5 LATE4 LATE3 —LATE1LATE052

TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 — TRISE1 TRISE0 52

PORTG RDPU REPU RJPU RG4 RG3 RG2 RG1 RG0 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

LCDCON LCDEN SLPEN WERR —CS1 CS0 LMUX1 LMUX0 51

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

Legend: Shaded cells are not used by PORTE.

PIC18F87J72 FAMILY

DS39979A-page 118 Preliminary  2010 Microchip Technology Inc.

10.7 PORTF, LATF and TRISF Registers

PORTF is a 7-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISF and LATF. All pins on PORTF are

implemented with Schmitt Trigger input buffers. Each pin

is individually configurable as an input or output.

PORTF is multiplexed with analog peripheral functions,

as well as LCD segments. Pins, RF1 through RF6, may

be used as comparator inputs or outputs by setting the

appropriate bits in the CMCON register. To use

RF<6:3> as digital inputs, it is also necessary to turn off

the comparators.

PORTF is also multiplexed with LCD segment drives

controlled by bits in the LCDSE2 and LCDSE3

registers. I/O port functions are only available when the

segments are disabled.

EXAMPLE 10-6: INITIALIZING PORTF

Note 1: On device Resets, pins, RF<6:1>, are

configured as analog inputs and are read

as ‘0’.

2: To configure PORTF as digital I/O, turn off

comparators and set ADCON1 value.

CLRF PORTF ; Initialize PORTF by

; clearing output

; data latches

CLRF LATF ; Alternate method

; to clear output

; data latches

MOVLW 07h ;

MOVWF CMCON ; Turn off comparators

MOVLW 0Fh ;

MOVWF ADCON1 ; Set PORTF as digital I/O

MOVLW 0CEh ; Value used to

; initialize data

; direction

MOVWF TRISF ; Set RF3:RF1 as inputs

; RF5:RF4 as outputs

; RF7:RF6 as inputs

 2010 Microchip Technology Inc. Preliminary DS39979A-page 119

PIC18F87J72 FAMILY

TABLE 10-14: PORTF FUNCTIONS

Pin Name Function TRIS

Setting I/O I/O

Type Description

RF1/AN6/C2OUT/

SEG19

RF1 0O DIG LATF<1> data output; not affected by analog input.

1I ST PORTF<1> data input; disabled when analog input is enabled.

AN6 1I ANA A/D Input Channel 6. Default configuration on POR.

C2OUT 0O DIG Comparator 2 output; takes priority over port data.

SEG19 xO ANA LCD Segment 19 output; disables all other pin functions.

RF2/AN7/C1OUT/

SEG20

RF2 0O DIG LATF<2> data output; not affected by analog input.

1I ST PORTF<2> data input; disabled when analog input is enabled.

AN7 1I ANA A/D Input Channel 7. Default configuration on POR.

C1OUT 0O DIG Comparator 1 output; takes priority over port data.

SEG20 xO ANA LCD Segment 20 output; disables all other pin functions.

RF3/AN8/SEG21/

C2INB

RF3 0O DIG LATF<3> data output; not affected by analog input.

1I ST PORTF<3> data input; disabled when analog input is enabled.

AN8 1I ANA A/D Input Channel 8 and Comparator C2+ input. Default input

configuration on POR; not affected by analog output.

SEG21 xO ANA LCD Segment 21 output; disables all other pin functions.

C2INB 1I ANA Comparator 2 Input B.

RF4/AN9/SEG22/

C2INA

RF4 0O DIG LATF<4> data output; not affected by analog input.

1I ST PORTF<4> data input; disabled when analog input is enabled.

AN9 1I ANA A/D Input Channel 9 and Comparator C2- input. Default input

configuration on POR; does not affect digital output.

SEG22 xO ANA LCD Segment 22 output; disables all other pin functions.

C2INA 1I ANA Comparator 2 Input A.

RF5/AN10/CVREF/

SEG23/C1INB

RF5 0O DIG LATF<5> data output; not affected by analog input. Disabled when

CVREF output is enabled.

1I ST PORTF<5> data input; disabled when analog input is enabled.

Disabled when CVREF output is enabled.

AN10 1I ANA A/D Input Channel 10 and Comparator C1+ input. Default input

configuration on POR.

CVREF xO ANA Comparator voltage reference output. Enabling this feature disables

digital I/O.

SEG23 xO ANA LCD Segment 23 output; disables all other pin functions.

C1INB 1I ANA Comparator 1 Input B.

RF6/AN11/SEG24/

C1INA

RF6 0O DIG LATF<6> data output; not affected by analog input.

1I ST PORTF<6> data input; disabled when analog input is enabled.

AN11 1I ANA A/D Input Channel 11 and Comparator C1- input. Default input

configuration on POR; does not affect digital output.

SEG24 xO ANA LCD Segment 24 output; disables all other pin functions.

C1INA 1I ANA Comparator 1 Input A.

RF7/AN5/SS/

SEG25

RF7 0O DIG LATF<7> data output; not affected by analog input.

1I ST PORTF<7> data input; disabled when analog input is enabled.

AN5 1I ANA A/D Input Channel 5. Default configuration on POR.

SS 1I TTL Slave select input for MSSP module.

SEG25 xO ANA LCD Segment 25 output; disables all other pin functions.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

PIC18F87J72 FAMILY

DS39979A-page 120 Preliminary  2010 Microchip Technology Inc.

TABLE 10-15: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —52

LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —52

TRISF TRISF7TRISF6TRISF5TRISF4TRISF3TRISF2TRISF1 —52

ADCON1 TRIGSEL —VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 51

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 121

PIC18F87J72 FAMILY

10.8 PORTG, TRISG and

LATG Registers

PORTG is a 5-bit wide, bidirectional port. The

corresponding Data Direction and Output Latch registers

are TRISG and LATG. All pins on PORTG are digital only

and tolerate voltages up to 5.5V.

PORTG is multiplexed with both AUSART and LCD

functions (Table 10-16). When operating as I/O, all

PORTG pins have Schmitt Trigger input buffers. The

RG1 pin is also configurable for open-drain output

when the AUSART is active. Open-drain configuration

is selected by setting the U2OD control bit (LATG<7>).

RG4 is multiplexed with LCD segment drives controlled

by bits in the LCDSE2 register and as the RTCC pin.

The I/O port function is only available when the

segments are disabled.

RG3 and RG2 are multiplexed with VLCAP pins for the

LCD charge pump and RG0 is multiplexed with the

LCDBIAS0 bias voltage input. When these pins are

used for LCD bias generation, the I/O and other

functions are unavailable.

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTG pin. Some

peripherals override the TRIS bit to make a pin an

output, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the

corresponding peripheral section for the correct TRIS bit

settings. The pin override value is not loaded into the

TRIS register. This allows read-modify-write of the TRIS

Although the port itself is only five bits wide, the

PORTG<7:5> bits are still implemented to control the

weak pull-ups on the I/O ports associated with PORTD,

PORTE and PORTJ. Clearing these bits enables the

respective port pull-ups. By default, all pull-ups are

disabled on device Resets.

Most of the corresponding TRISG and LATG bits are

implemented as open-drain control bits for CCP1,

CCP2 and SPI (TRISG<7:5>), and the USARTs

(LATG<7:6>). Setting these bits configures the output

pin for the corresponding peripheral for open-drain

operation. LATG<5> is not implemented.

EXAMPLE 10-7: INITIALIZING PORTG

CLRF PORTG ; Initialize PORTG by

; clearing output

; data latches

CLRF LATG ; Alternate method

; to clear output

; data latches

MOVLW 04h ; Value used to

; initialize data

; direction

MOVWF TRISG ; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as inputs

PIC18F87J72 FAMILY

DS39979A-page 122 Preliminary  2010 Microchip Technology Inc.

TABLE 10-16: PORTG FUNCTIONS

TABLE 10-17: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG

Pin Name Function TRIS

Setting I/O I/O

Type Description

RG0/LCDBIAS0 RG0 0O DIG LATG<0> data output.

1I ST PORTG<0> data input.

LCDBIAS0 xI ANA LCD module bias voltage input.

RG1/TX2/CK2 RG1 0O DIG LATG<1> data output.

1I ST PORTG<1> data input.

TX2 1O DIG Synchronous serial data output (AUSART module); takes priority over

port data.

CK2 1O DIG Synchronous serial data input (AUSART module); user must configure

as an input.

1I ST Synchronous serial clock input (AUSART module).

RG2/RX2/DT2/

VLCAP1

RG2 0O DIG LATG<2> data output.

1I ST PORTG<2> data input.

RX2 1I ST Asynchronous serial receive data input (AUSART module).

DT2 1O DIG Synchronous serial data output (AUSART module); takes priority over

port data.

1I ST Synchronous serial data input (AUSART module); user must configure

as an input.

VLCAP1xI ANA LCD charge pump capacitor input.

RG3/VLCAP2RG30O DIG LATG<3> data output.

1I ST PORTG<3> data input.

VLCAP2xI ANA LCD charge pump capacitor input.

RG4/SEG26/

RTCC

RG4 0O DIG LATG<4> data output.

1I ST PORTG<4> data input.

SEG26 xO ANA LCD Segment 26 output; disables all other pin functions.

RTCC xO DIG RTCC output.

Legend: O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,

x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values on

page

PORTG RDPU REPU RJPU RG4 RG3 RG2 RG1 RG0 52

LATG U2OD U1OD — LATG4 LATG3 LATG2 LATG1 LATG0 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 123

PIC18F87J72 FAMILY

11.0 TIMER0 MODULE

The Timer0 module incorporates the following features:

• Software selectable operation as a timer or

counter in both 8-bit or 16-bit modes

• Readable and writable registers

• Dedicated 8-bit, software programmable

prescaler

• Selectable clock source (internal or external)

• Edge select for external clock

• Interrupt-on-overflow

The T0CON register (Register 11-1) controls all

aspects of the module’s operation, including the

prescale selection; it is both readable and writable.

A simplified block diagram of the Timer0 module in 8-bit

mode is shown in Figure 11-1. Figure 11-2 shows a

simplified block diagram of the Timer0 module in 16-bit

mode.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TMR0ON: Timer0 On/Off Control bit

1 = Enables Timer0

0 = Stops Timer0

bit 6 T08BIT: Timer0 8-Bit/16-Bit Control bit

1 = Timer0 is configured as an 8-bit timer/counter

0 = Timer0 is configured as a 16-bit timer/counter

bit 5 T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin input edge

0 = Internal clock (2/4)

bit 4 T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Timer0 Prescaler Assignment bit

1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler.

0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits

111 = 1:256 Prescale value

110 = 1:128 Prescale value

101 = 1:64 Prescale value

100 = 1:32 Prescale value

011 = 1:16 Prescale value

010 = 1:8 Prescale value

001 = 1:4 Prescale value

000 = 1:2 Prescale value

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DS39979A-page 124 Preliminary  2010 Microchip Technology Inc.

11.1 Timer0 Operation

Timer0 can operate as either a timer or a counter. The

mode is selected with the T0CS bit (T0CON<5>). In

Timer mode (T0CS = 0), the module increments on

every clock by default unless a different prescaler value

is selected (see Section 11.3 “Prescaler”). If the

TMR0 register is written to, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

The Counter mode is selected by setting the T0CS bit

(= 1). In this mode, Timer0 increments either on every

rising or falling edge of pin, RA4/T0CKI. The increment-

ing edge is determined by the Timer0 Source Edge

Select bit, T0SE (T0CON<4>); clearing this bit selects

the rising edge. Restrictions on the external clock input

are discussed below.

An external clock source can be used to drive Timer0,

however, it must meet certain requirements to ensure

that the external clock can be synchronized with the

internal phase clock (T

OSC). There is a delay between

synchronization and the onset of incrementing the

timer/counter.

11.2 Timer0 Reads and Writes in

16-Bit Mode

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0, which is not directly readable nor writ-

able (refer to Figure 11-2). TMR0H is updated with the

contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte were valid, due to a rollover between

successive reads of the high and low byte.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

FIGURE 11-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)

Note: Upon Reset, Timer0 is enabled in 8-bit mode with the clock input from T0CKI max. prescale.

T0CKI Pin

T0SE

T0CS

FOSC/4

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

Programmable

Prescaler

Note: Upon Reset, Timer0 is enabled in 8-bit mode with the clock input from T0CKI max. prescale.

T0CKI Pin

T0SE

T0CS

FOSC/4

Sync with

Internal

Clocks

TMR0L

(2 TCY Delay)

Internal Data Bus

PSA

T0PS<2:0>

Set

TMR0IF

on Overflow

TMR0

TMR0H

High Byte

Read TMR0L

Write TMR0L

Programmable

Prescaler

 2010 Microchip Technology Inc. Preliminary DS39979A-page 125

PIC18F87J72 FAMILY

11.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0

module. The prescaler is not directly readable or writable.

Its value is set by the PSA and T0PS<2:0> bits

(T0CON<3:0>) which determine the prescaler

assignment and prescale ratio.

Clearing the PSA bit assigns the prescaler to the

Timer0 module. When it is assigned, prescale values

from 1:2 through 1:256, in power-of-2 increments, are

selectable.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF TMR0, MOVWF

TMR0, BSF TMR0, etc.) clear the prescaler count.

11.3.1 SWITCHING PRESCALER

ASSIGNMENT

The prescaler assignment is fully under software

control and can be changed “on-the-fly” during program

execution.

11.4 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0

from FFFFh to 0000h in 16-bit mode. This overflow sets

the TMR0IF flag bit. The interrupt can be masked by

clearing the TMR0IE bit (INTCON<5>). Before

re-enabling the interrupt, the TMR0IF bit must be

cleared in software by the Interrupt Service Routine.

Since Timer0 is shut down in Sleep mode, the TMR0

interrupt cannot awaken the processor from Sleep.

TABLE 11-1: REGISTERS ASSOCIATED WITH TIMER0

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count but will not change the prescaler

assignment.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

TMR0L Timer0 Register Low Byte 50

TMR0H Timer0 Register High Byte 50

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 50

TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0.

Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal

oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are

disabled and these bits read as ‘0’.

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DS39979A-page 126 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 127

PIC18F87J72 FAMILY

12.0 TIMER1 MODULE

The Timer1 timer/counter module incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR1H

and TMR1L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Reset on CCP Special Event Trigger

• Device clock status flag (T1RUN)

A simplified block diagram of the Timer1 module is

shown in Figure 12-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 12-2.

The module incorporates its own low-power oscillator

to provide an additional clocking option. The Timer1

oscillator can also be used as a low-power clock source

for the microcontroller in power-managed operation.

Timer1 can also be used to provide Real-Time Clock

(RTC) functionality to applications with only a minimal

addition of external components and code overhead.

Timer1 is controlled through the T1CON Control

Oscillator Enable bit (T1OSCEN). Timer1 can be

enabled or disabled by setting or clearing control bit,

TMR1ON (T1CON<0>).

R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T1RUN T1CKPS1 T1CKPS0

T1OSCEN

T1SYNC TMR1CS TMR1ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of TImer1 in one 16-bit operation

0 = Enables register read/write of Timer1 in two 8-bit operations

bit 6 T1RUN: Timer1 System Clock Status bit

1 = Device clock is derived from Timer1 oscillator

0 = Device clock is derived from another source

bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable bit

1 = Timer1 oscillator is enabled

0 = Timer1 oscillator is shut off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin, RC0/T1OSO/T13CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1

0 =Stops Timer1

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DS39979A-page 128 Preliminary  2010 Microchip Technology Inc.

12.1 Timer1 Operation

Timer1 can operate in one of these modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). When TMR1CS is cleared

(= 0), Timer1 increments on every internal instruction

cycle (FOSC/4). When the bit is set, Timer1 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

When Timer1 is enabled, the RC1/T1OSI/SEG32 and

RC0/T1OSO/T13CKI pins become inputs. This means

the values of TRISC<1:0> are ignored and the pins are

read as ‘0’.

FIGURE 12-1: TIMER1 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 12-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

On/Off

T1OSO/T13CKI

T1OSI

TMR1ON

TMR1L

Set

TMR1IF

on Overflow

TMR1

High Byte

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer1

Timer1 Clock Input

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1SYNC

TMR1CS

T1CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

T1OSO/T13CKI

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR1L

Internal Data Bus

Set

TMR1IF

on Overflow

TMR1

TMR1H

High Byte

Read TMR1L

Write TMR1L

TMR1ON

Clear TMR1

(CCP Special Event Trigger)

Timer1 Oscillator

On/Off

Timer1

Timer1 Clock Input

Prescaler

1, 2, 4, 8

Synchronize

Detect

 2010 Microchip Technology Inc. Preliminary DS39979A-page 129

PIC18F87J72 FAMILY

12.2 Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes

(see Figure 12-2). When the RD16 control bit

(T1CON<7>) is set, the address for TMR1H is mapped

to a buffer register for the high byte of Timer1. A read

from TMR1L will load the contents of the high byte of

Timer1 into the Timer1 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether

a read of the high byte, followed by a read of the low

byte, has become invalid due to a rollover between

reads.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all

16 bits to both the high and low bytes of Timer1 at once.

The high byte of Timer1 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer1 High Byte Buffer register.

Writes to TMR1H do not clear the Timer1 prescaler.

The prescaler is only cleared on writes to TMR1L.

12.3 Timer1 Oscillator

An on-chip crystal oscillator circuit is incorporated

between pins, T1OSI (input) and T1OSO (amplifier

output). It is enabled by setting the Timer1 Oscillator

Enable bit, T1OSCEN (T1CON<3>). The oscillator is a

low-power circuit rated for 32 kHz crystals. It will

continue to run during all power-managed modes. The

circuit for a typical LP oscillator is shown in Figure 12-3.

Table 12-1 shows the capacitor selection for the Timer1

oscillator.

The user must provide a software time delay to ensure

proper start-up of the Timer1 oscillator.

FIGURE 12-3: EXTERNAL COMPONENTS

FOR THE TIMER1 LP

OSCILLATOR

TABLE 12-1: CAPACITOR SELECTION FOR

THE TIMER1

OSCILLATOR(2,3,4)

12.3.1 USING TIMER1 AS A

CLOCK SOURCE

The Timer1 oscillator is also available as a clock source

in power-managed modes. By setting the System

Clock Select bits, SCS<1:0> (OSCCON<1:0>), to ‘01’,

the device switches to SEC_RUN mode. Both the CPU

and peripherals are clocked from the Timer1 oscillator.

If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP

instruction is executed, the device enters SEC_IDLE

mode. Additional details are available in Section 4.0

“Power-Managed Modes”.

Whenever the Timer1 oscillator is providing the clock

source, the Timer1 system clock status flag, T1RUN

(T1CON<6>), is set. This can be used to determine the

controller’s current clocking mode. It can also indicate

the clock source being currently used by the Fail-Safe

Clock Monitor. If the Clock Monitor is enabled and the

Timer1 oscillator fails while providing the clock, polling

the T1RUN bit will indicate whether the clock is being

provided by the Timer1 oscillator or another source.

Note: See the Notes with Table 12-1 for additional

information about capacitor selection.

XTAL

T1OSI

T1OSO

32.768 kHz

27 pF

PIC18F87J72

Oscillator

Type Freq. C1 C2

LP 32.768 kHz 27 pF(1) 27 pF(1)

Note 1: Microchip suggests these values as a

starting point in validating the oscillator

circuit.

2: Higher capacitance increases the stability

of the oscillator but also increases the

start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external

components.

4: Capacitor values are for design guidance

only.

PIC18F87J72 FAMILY

DS39979A-page 130 Preliminary  2010 Microchip Technology Inc.

12.3.2 TIMER1 OSCILLATOR LAYOUT

CONSIDERATIONS

The Timer1 oscillator circuit draws very little power

during operation. Due to the low-power nature of the

oscillator, it may also be sensitive to rapidly changing

signals in close proximity.

The oscillator circuit, shown in Figure 12-3, should be

located as close as possible to the microcontroller.

There should be no circuits passing within the oscillator

circuit boundaries other than VSS or VDD.

If a high-speed circuit must be located near the oscilla-

tor (such as the CCP1 pin in Output Compare or PWM

mode, or the primary oscillator using the OSC2 pin), a

grounded guard ring around the oscillator circuit, as

shown in Figure 12-4, may be helpful when used on a

single-sided PCB or in addition to a ground plane.

FIGURE 12-4: OSCILLATOR CIRCUIT

WITH GROUNDED

GUARD RING

12.4 Timer1 Interrupt

The TMR1 register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

Timer1 interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit, TMR1IF

(PIR1<0>). This interrupt can be enabled or disabled

by setting or clearing the Timer1 Interrupt Enable bit,

TMR1IE (PIE1<0>).

12.5 Resetting Timer1 Using the CCP

Special Event Trigger

If CCP1 or CCP2 is configured to use Timer1 and to

generate a Special Event Trigger in Compare mode

(CCPxM<3:0> = 1011), this signal will reset Timer3.

The trigger from CCP2 will also start an A/D conversion

if the A/D module is enabled (see Section 16.3.4

“Special Event Trigger” for more information).

The module must be configured as either a timer or a

synchronous counter to take advantage of this feature.

When used this way, the CCPRxH:CCPRxL register

pair effectively becomes a period register for Timer1.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

Special Event Trigger, the write operation will take

precedence.

12.6 Using Timer1 as a Real-Time Clock

Adding an external LP oscillator to Timer1 (such as the

one described in Section 12.3 “Timer1 Oscillator”

above) gives users the option to include RTC function-

ality to their applications. This is accomplished with an

inexpensive watch crystal to provide an accurate time

base and several lines of application code to calculate

the time. When operating in Sleep mode and using a

battery or supercapacitor as a power source, it can

completely eliminate the need for a separate RTC

device and battery backup.

The application code routine, RTCisr, shown in

Example 12-1, demonstrates a simple method to

increment a counter at one-second intervals using an

Interrupt Service Routine. Incrementing the TMR1

the routine which increments the seconds counter by

one. Additional counters for minutes and hours are

incremented as the previous counter overflows.

Since the register pair is 16 bits wide, counting up to

overflow the register directly from a 32.768 kHz clock

would take 2 seconds. To force the overflow at the

required one-second intervals, it is necessary to pre-

load it. The simplest method is to set the MSb of

TMR1H with a BSF instruction. Note that the TMR1L

introduce cumulative error over many cycles.

For this method to be accurate, Timer1 must operate in

Asynchronous mode and the Timer1 overflow interrupt

must be enabled (PIE1<0> = 1) as shown in the

routine, RTCinit. The Timer1 oscillator must also be

enabled and running at all times.

VDD

OSC1

VSS

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

Note: The Special Event Triggers from the CCPx

module will not set the TMR1IF interrupt

flag bit (PIR1<0>).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 131

PIC18F87J72 FAMILY

EXAMPLE 12-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

TMR1L Timer1 Register Low Byte 50

TMR1H Timer1 Register High Byte 50

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50

Legend: Shaded cells are not used by the Timer1 module.

RTCinit

MOVLW 80h ; Preload TMR1 register pair

MOVWF TMR1H ; for 1 second overflow

CLRF TMR1L

MOVLW b’00001111’ ; Configure for external clock,

MOVWF T1CON ; Asynchronous operation, external oscillator

CLRF secs ; Initialize timekeeping registers

CLRF mins ;

MOVLW .12

MOVWF hours

BSF PIE1, TMR1IE ; Enable Timer1 interrupt

RETURN

RTCisr

BSF TMR1H, 7 ; Preload for 1 sec overflow

BCF PIR1, TMR1IF ; Clear interrupt flag

INCF secs, F ; Increment seconds

MOVLW .59 ; 60 seconds elapsed?

CPFSGT secs

RETURN ; No, done

CLRF secs ; Clear seconds

INCF mins, F ; Increment minutes

MOVLW .59 ; 60 minutes elapsed?

CPFSGT mins

RETURN ; No, done

CLRF mins ; clear minutes

INCF hours, F ; Increment hours

MOVLW .23 ; 24 hours elapsed?

CPFSGT hours

RETURN ; No, done

CLRF hours ; Reset hours

RETURN ; Done

PIC18F87J72 FAMILY

DS39979A-page 132 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 133

PIC18F87J72 FAMILY

13.0 TIMER2 MODULE

The Timer2 module incorporates the following features:

• 8-bit Timer and Period registers (TMR2 and PR2,

respectively)

• Readable and writable (both registers)

• Software programmable prescaler

(1:1, 1:4 and 1:16)

• Software programmable postscaler

(1:1 through 1:16)

• Interrupt on TMR2 to PR2 match

• Optional use as the shift clock for the

MSSP module

The module is controlled through the T2CON register

(Register 13-1), which enables or disables the timer

and configures the prescaler and postscaler. Timer2

can be shut off by clearing control bit, TMR2ON

(T2CON<2>), to minimize power consumption.

A simplified block diagram of the module is shown in

Figure 13-1.

13.1 Timer2 Operation

In normal operation, TMR2 is incremented from 00h on

each clock (FOSC/4). A 4-bit counter/prescaler on the

clock input gives direct input, divide-by-4 and

divide-by-16 prescale options. These are selected by

the prescaler control bits, T2CKPS<1:0>

(T2CON<1:0>). The value of TMR2 is compared to that

of the Period register, PR2, on each clock cycle. When

the two values match, the comparator generates a

match signal as the timer output. This signal also resets

the value of TMR2 to 00h on the next cycle and drives

the output counter/postscaler (see Section 13.2

“Timer2 Interrupt”).

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared on any

device Reset, while the PR2 register initializes at FFh.

Both the prescaler and postscaler counters are cleared

on the following events:

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00 = Prescaler is 1

01 = Prescaler is 4

1x = Prescaler is 16

PIC18F87J72 FAMILY

DS39979A-page 134 Preliminary  2010 Microchip Technology Inc.

13.2 Timer2 Interrupt

Timer2 can also generate an optional device interrupt.

The Timer2 output signal (TMR2 to PR2 match) pro-

vides the input for the 4-bit output counter/postscaler.

This counter generates the TMR2 match interrupt flag

which is latched in TMR2IF (PIR1<1>). The interrupt is

enabled by setting the TMR2 Match Interrupt Enable

bit, TMR2IE (PIE1<1>).

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS<3:0> (T2CON<6:3>).

13.3 Timer2 Output

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 18.0

“Master Synchronous Serial Port (MSSP) Module”.

FIGURE 13-1: TIMER2 BLOCK DIAGRAM

TABLE 13-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IETMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IPTMR1IP 52

TMR2 Timer2 Register 50

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50

PR2 Timer2 Period Register 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Comparator

TMR2 Output

TMR2

Postscaler

Prescaler PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

T2OUTPS<3:0>

T2CKPS<1:0>

Set TMR2IF

Internal Data Bus

Reset

TMR2/PR2

(to PWM or MSSP)

Match

 2010 Microchip Technology Inc. Preliminary DS39979A-page 135

PIC18F87J72 FAMILY

14.0 TIMER3 MODULE

The Timer3 timer/counter module incorporates these

features:

• Software selectable operation as a 16-bit timer or

counter

• Readable and writable 8-bit registers (TMR3H

and TMR3L)

• Selectable clock source (internal or external) with

device clock or Timer1 oscillator internal options

• Interrupt-on-overflow

• Module Reset on CCP Special Event Trigger

A simplified block diagram of the Timer3 module is

shown in Figure 14-1. A block diagram of the module’s

operation in Read/Write mode is shown in Figure 14-2.

The Timer3 module is controlled through the T3CON

options for the CCP modules. See Section 16.2.2

“Timer1/Timer3 Mode Selection” for more

information.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RD16: 16-Bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation

0 = Enables register read/write of Timer3 in two 8-bit operations

bit 6,3 T3CCP<2:1>: Timer3 and Timer1 to CCPx Enable bits

1x = Timer3 is the capture/compare clock source for the CCP modules

01 = Timer3 is the capture/compare clock source for CCP2;

Timer1 is the capture/compare clock source for CCP1

00 = Timer1 is the capture/compare clock source for the CCP modules

bit 5-4 T3CKPS<1:0>: Timer3 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 2 T3SYNC: Timer3 External Clock Input Synchronization Control bit

(Not usable if the device clock comes from Timer1/Timer3.)

When TMR3CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR3CS = 0:

This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1 TMR3CS: Timer3 Clock Source Select bit

1 = External clock input from Timer1 oscillator or T13CKI (on the rising edge after the first

falling edge)

0 = Internal clock (FOSC/4)

bit 0 TMR3ON: Timer3 On bit

1 = Enables Timer3

0 = Stops Timer3

PIC18F87J72 FAMILY

DS39979A-page 136 Preliminary  2010 Microchip Technology Inc.

14.1 Timer3 Operation

Timer3 can operate in one of three modes:

•Timer

• Synchronous Counter

• Asynchronous Counter

The operating mode is determined by the clock select

bit, TMR3CS (T3CON<1>). When TMR3CS is cleared

(= 0), Timer3 increments on every internal instruction

cycle (FOSC/4). When the bit is set, Timer3 increments

on every rising edge of the Timer1 external clock input

or the Timer1 oscillator, if enabled.

As with Timer1, the RC1/T1OSI/SEG32 and

RC0/T1OSO/T13CKI pins become inputs when the

Timer1 oscillator is enabled. This means the values of

TRISC<1:0> are ignored and the pins are read as ‘0’.

FIGURE 14-1: TIMER3 BLOCK DIAGRAM (8-BIT MODE)

FIGURE 14-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

T3SYNC

TMR3CS

T3CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T1OSO/T13CKI

T1OSI

TMR3ON

TMR3L Set

TMR3IF

on Overflow

TMR3

High Byte

Timer1 Oscillator

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

On/Off

Timer3

CCPx Special Event Trigger

CCPx Select from T3CON<6,3>

Clear TMR3

Timer1 Clock Input

T3SYNC

TMR3CS

T3CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T13CKI/T1OSO

T1OSI

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR3L

Internal Data Bus

Set

TMR3IF

on Overflow

TMR3

TMR3H

High Byte

Read TMR3L

Write TMR3L

TMR3ON

CCPx Special Event Trigger

Timer1 Oscillator

On/Off

Timer3

Timer1 Clock Input

CCPx Select from T3CON<6,3>

Clear TMR3

 2010 Microchip Technology Inc. Preliminary DS39979A-page 137

PIC18F87J72 FAMILY

14.2 Timer3 16-Bit Read/Write Mode

Timer3 can be configured for 16-bit reads and writes

(see Figure 14-2). When the RD16 control bit

(T3CON<7>) is set, the address for TMR3H is mapped

to a buffer register for the high byte of Timer3. A read

from TMR3L will load the contents of the high byte of

Timer3 into the Timer3 High Byte Buffer register. This

provides the user with the ability to accurately read all

16 bits of Timer1 without having to determine whether

a read of the high byte, followed by a read of the low

byte, has become invalid due to a rollover between

reads.

A write to the high byte of Timer3 must also take place

through the TMR3H Buffer register. The Timer3 high

byte is updated with the contents of TMR3H when a

write occurs to TMR3L. This allows a user to write all

16 bits to both the high and low bytes of Timer3 at once.

The high byte of Timer3 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer3 High Byte Buffer register.

Writes to TMR3H do not clear the Timer3 prescaler.

The prescaler is only cleared on writes to TMR3L.

14.3 Using the Timer1 Oscillator as the

Timer3 Clock Source

The Timer1 internal oscillator may be used as the clock

source for Timer3. The Timer1 oscillator is enabled by

setting the T1OSCEN (T1CON<3>) bit. To use it as the

Timer3 clock source, the TMR3CS bit must also be set.

As previously noted, this also configures Timer3 to

increment on every rising edge of the oscillator source.

The Timer1 oscillator is described in Section 12.0

“Timer1 Module”.

14.4 Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in interrupt flag bit, TMR3IF (PIR2<1>).

This interrupt can be enabled or disabled by setting or

clearing the Timer3 Interrupt Enable bit, TMR3IE

(PIE2<1>).

14.5 Resetting Timer3 Using the CCP

Special Event Trigger

If CCP1 or CCP2 is configured to use Timer3 and to

generate a Special Event Trigger in Compare mode

(CCPxM<3:0> = 1011), this signal will reset Timer3.

The trigger from CCP2 will also start an A/D conversion

if the A/D module is enabled (see Section 16.3.4

“Special Event Trigger” for more information).

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPRxH:CCPRxL register

pair effectively becomes a period register for Timer3.

If Timer3 is running in Asynchronous Counter mode,

the Reset operation may not work.

In the event that a write to Timer3 coincides with a

Special Event Trigger from a CCP module, the write will

take precedence.

TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note: The Special Event Triggers from the CCPx

module will not set the TMR3IF interrupt

flag bit (PIR2<1>).

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —52

PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —52

IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —52

TMR3L Timer3 Register Low Byte 51

TMR3H Timer3 Register High Byte 51

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.

PIC18F87J72 FAMILY

DS39979A-page 138 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 139

PIC18F87J72 FAMILY

15.0 REAL-TIME CLOCK AND

CALENDAR (RTCC)

The key features of the Real-Time Clock and Calendar

(RTCC) module are:

• Time: hours, minutes and seconds

• 24-hour format (military time)

• Calendar: weekday, date, month and year

• Alarm configurable

• Year range: 2000 to 2099

• Leap year correction

• BCD format for compact firmware

• Optimized for low-power operation

• User calibration with auto-adjust

• Calibration range: 2.64 seconds error per month

• Requirements: external 32.768 kHz clock crystal

• Alarm pulse or seconds clock output on RTCC pin

The RTCC module is intended for applications, where

accurate time must be maintained for an extended

period with minimum to no intervention from the CPU.

The module is optimized for low-power usage in order

to provide extended battery life while keeping track of

time.

The module is a 100-year clock and calendar with auto-

matic leap year detection. The range of the clock is

from 00:00:00 (midnight) on January 1, 2000 to

23:59:59 on December 31, 2099. Hours are measured

in 24-hour (military time) format. The clock provides a

granularity of one second with half-second visibility to

the user.

FIGURE 15-1: RTCC BLOCK DIAGRAM

RTCC Prescalers

RTCC Timer

Comparator

Compare Registers

Repeat Counter

YEAR

MTHDY

WKDYHR

MINSEC

ALMTHDY

ALWDHR

ALMINSEC

with Masks

RTCC Interrupt Logic

RTCCFG

ALRMRPT

Alarm

Event

0.5s

RTCC Clock Domain

Alarm Pulse

RTCC Interrupt

CPU Clock Domain

RTCVALx

ALRMVALx

RTCC Pin

RTCOE

32.768 kHz Input

from Timer1 Oscillator

Internal RC

PIC18F87J72 FAMILY

DS39979A-page 140 Preliminary  2010 Microchip Technology Inc.

15.1 RTCC MODULE REGISTERS

The RTCC module registers are divided into following

categories:

RTCC Control Registers

• RTCCFG

• RTCCAL

• PADCFG1

•ALRMCFG

•ALRMRPT

RTCC Value Registers

• RTCVALH and RTCVALL – Can access the fol-

lowing registers

- YEAR

-MONTH

-DAY

- WEEKDAY

-HOUR

- MINUTE

- SECOND

Alarm Value Registers

• ALRMVALH and ALRMVALL – Can access the

following registers:

- ALRMMNTH

-ALRMDAY

-ALRMWD

-ALRMHR

- ALRMMIN

- ALRMSEC

Note: The RTCVALH and RTCVALL registers

can be accessed through RTCRPT<1:0>.

ALRMVALH and ALRMVALL can be

accessed through ALRMPTR<1:0>.

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15.1.1 RTCC CONTROL REGISTERS

R/W-0 U-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0

RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RTCEN: RTCC Enable bit(2)

1 = RTCC module is enabled

0 = RTCC module is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 RTCWREN: RTCC Value Registers Write Enable bit

1 = RTCVALH and RTCVALL registers can be written to by the user

0 = RTCVALH and RTCVALL registers are locked out from being written to by the user

bit 4 RTCSYNC: RTCC Value Registers Read Synchronization bit

1 = RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple

resulting in an invalid data read. If the register is read twice and results in the same data, the data

can be assumed to be valid.

0 = RTCVALH, RTCVALL and ALCFGRPT registers can be read without concern over a rollover

ripple

bit 3 HALFSEC: Half-Second Status bit(3)

1 = Second half period of a second

0 = First half period of a second

bit 2 RTCOE: RTCC Output Enable bit

1 = RTCC clock output is enabled

0 = RTCC clock output is disabled

bit 1-0 RTCPTR<1:0>: RTCC Value Register Window Pointer bits

Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers.

The RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches ‘00’.

RTCVALH:

00 = Minutes

01 = Weekday

10 = Month

11 = Reserved

RTCVALL:

00 = Seconds

01 = Hours

10 = Day

11 = Year

Note 1: The RTCCFG register is only affected by a POR. For Resets other than POR, RTCC will continue to run

even if the device is in Reset.

2: A write to the RTCEN bit is only allowed when RTCWREN = 1.

3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 CAL<7:0>: RTC Drift Calibration bits

01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute

00000001 = Minimum positive adjustment; adds four RTC clock pulses every minute

00000000 = No adjustment

11111111 = Minimum negative adjustment; subtracts four RTC clock pulses every minute

10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every minute

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0

— — — — — RTSECSEL1(1) RTSECSEL0(1) —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-1 RTSECSEL<1:0>: RTCC Seconds Clock Output Select bits(1)

11 = Reserved; do not use

10 = RTCC source clock is selected for the RTCC pin (pin can be INTOSC or Timer1 oscillator,

depending on the RTCOSC (CONFIG3L<1>) bit setting)(2)

01 = RTCC seconds clock is selected for the RTCC pin

00 = RTCC alarm pulse is selected for the RTCC pin

bit 0 Unimplemented: Read as ‘0’

Note 1: To enable the actual RTCC output, the RTCOE (RTCCFG<2>) bit must be set.

2: If the Timer1 oscillator is the clock source for RTCC, T1OSCEN bit should be set (T1CON<3> = 1).

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ALRMEN: Alarm Enable bit

1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00

and CHIME = 0)

0 = Alarm is disabled

bit 6 CHIME: Chime Enable bit

1 = Chime is enabled; ALRMPTR<1:0> bits are allowed to roll over from 00h to FFh

0 = Chime is disabled; ALRMPTR<1:0> bits stop once they reach 00h

bit 5-2 AMASK<3:0>: Alarm Mask Configuration bits

0000 = Every half second

0001 = Every second

0010 = Every 10 seconds

0011 = Every minute

0100 = Every 10 minutes

0101 = Every hour

0110 = Once a day

0111 = Once a week

1000 = Once a month

1001 = Once a year (except when configured for February 29th, once every four years)

101x = Reserved – do not use

11xx = Reserved – do not use

bit 1-0 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits

Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL

registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches

‘00’.

ALRMVALH:

00 = ALRMMIN

01 =ALRMWD

10 =ALRMMNTH

11 = Unimplemented

ALRMVALL:

00 = ALRMSEC

01 =ALRMHR

10 =ALRMDAY

11 = Unimplemented

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15.1.2 RTCVALH AND RTCVALL

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits

11111111 = Alarm will repeat 255 more times

00000000 = Alarm will not repeat

The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to

FFh unless CHIME = 1.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 Unimplemented: Read as ‘0’

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits

Contains a value from 0 to 9.

bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.

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U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bits

Contains a value of 0 or 1.

bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal value of Day’s Tens Digit bits

Contains a value from 0 to 3.

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY2 WDAY1 WDAY0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits

Contains a value from 0 to 6.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits

Contains a value from 0 to 2.

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits

Contains a value from 0 to 9.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

Contains a value from 0 to 9.

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15.1.3 ALRMVALH AND ALRMVALL

U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x

— — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bits

Contains a value of 0 or 1.

bit 3-0 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits

Contains a value from 0 to 3.

bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x

— — — — — WDAY2 WDAY1 WDAY0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-3 Unimplemented: Read as ‘0’

bit 2-0 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits

Contains a value from 0 to 6.

Note 1: A write to this register is only allowed when RTCWREN = 1.

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U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

—— HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits

Contains a value from 0 to 2.

bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits

Contains a value from 0 to 9.

Note 1: A write to this register is only allowed when RTCWREN = 1.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits

Contains a value from 0 to 9.

U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x

— SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits

Contains a value from 0 to 5.

bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits

Contains a value from 0 to 9.

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15.1.4 RTCEN BIT WRITE

An attempt to write to the RTCEN bit while

RTCWREN = 0 will be ignored. RTCWREN must be

set before a write to RTCEN can take place.

Like the RTCEN bit, the RTCVALH and RTCVALL

registers can only be written to when RTCWREN = 1.

A write to these registers, while RTCWREN = 0, will be

ignored.

15.2 Operation

15.2.1 REGISTER INTERFACE

The register interface for the RTCC and alarm values is

implemented using the Binary Coded Decimal (BCD)

format. This simplifies the firmware when using the

module, as each of the digits is contained within its own

4-bit value (see Figure 15-2 and Figure 15-3).

FIGURE 15-2: TIMER DIGIT FORMAT

FIGURE 15-3: ALARM DIGIT FORMAT

0-60-9 0-9 0-3 0-9

0-9 0-9 0-90-2 0-5 0-5 0/1

Day of WeekYear Day

Hours

(24-hour format) Minutes Seconds

1/2 Second Bit

0-1 0-9

Month

(binary format)

0-60-3 0-9

0-9 0-9 0-90-2 0-5 0-5

Day of WeekDay

Hours

(24-hour format) Minutes Seconds

0-1 0-9

Month

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15.2.2 CLOCK SOURCE

As mentioned earlier, the RTCC module is intended to

be clocked by an external Real-Time Clock crystal

oscillating at 32.768 kHz, but can also be an internal

oscillator. The RTCC clock selection is decided by the

RTCOSC bit (CONFIG3L<1>).

Calibration of the crystal can be done through this mod-

ule to yield an error of 3 seconds or less per month.

(For further details, see Section 15.2.9 “Calibration”.)

FIGURE 15-4: CLOCK SOURCE MULTIPLEXING

15.2.2.1 Real-Time Clock Enable

The RTCC module can be clocked by an external,

32.768 kHz crystal (Timer1 oscillator) or the internal RC

oscillator, which can be selected in CONFIG3L<1>.

If the external clock is used, the Timer1 oscillator

should be enabled by setting the T1OSCEN bit

(T1CON<3> = 1). If INTRC is providing the clock, the

INTRC clock can be brought out to the RTCC pin by the

RTSECSEL<1:0> bits in the PADCFG register.

15.2.3 DIGIT CARRY RULES

This section explains which timer values are affected

when there is a rollover.

• Time of Day: from 23:59:59 to 00:00:00 with a

carry to the Day field

• Month: from 12/31 to 01/01 with a carry to the

Year field

• Day of Week: from 6 to 0 with no carry (see

Table 15-1)

• Year Carry: from 99 to 00; this also surpasses the

use of the RTCC

For the day to month rollover schedule, see Table 15-2.

Considering that the following values are in BCD for-

mat, the carry to the upper BCD digit will occur at a

count of 10 and not at 16 (SECONDS, MINUTES,

HOURS, WEEKDAY, DAYS and MONTHS).

TABLE 15-1: DAY OF WEEK SCHEDULE

TABLE 15-2: DAY TO MONTH ROLLOVER

SCHEDULE

Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second

synchronization; clock prescaler is held in Reset when RTCEN = 0.

32.768 kHz XTAL

1:16384

Half Second(1)

Half-Second

Clock One-Second Clock

Year

Month

Day

Day of Week

Second Hour:Minute

Clock Prescaler(1)

from SOSC

Internal RC

CONFIG 3L<1>

Day of Week

Sunday 0

Monday 1

Tuesday 2

Wednesday 3

Thursday 4

Friday 5

Saturday 6

Month Maximum Day Field

01 (January) 31

02 (February) 28 or 29(1)

03 (March) 31

04 (April) 30

05 (May) 31

06 (June) 30

07 (July) 31

08 (August) 31

09 (September) 30

10 (October) 31

11 (November) 30

12 (December) 31

Note 1: See Section 15.2.4 “Leap Year”.

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15.2.4 LEAP YEAR

Since the year range on the RTCC module is 2000 to

2099, the leap year calculation is determined by any year

divisible by 4 in the above range. Only February is

effected in a leap year.

February will have 29 days in a leap year and 28 days in

any other year.

15.2.5 GENERAL FUNCTIONALITY

All Timer registers containing a time value of seconds or

greater are writable. The user configures the time by

writing the required year, month, day, hour, minutes and

seconds to the Timer registers via register pointers (see

Section 15.2.8 “Register Mapping”).

The timer uses the newly written values and proceeds

with the count from the required starting point.

The RTCC is enabled by setting the RTCEN bit

(RTCCFG<7>). If enabled while adjusting these regis-

ters, the timer still continues to increment. However, any

time the MINSEC register is written to, both of the timer

prescalers are reset to ‘0’. This allows fraction of a

second synchronization.

The Timer registers are updated in the same cycle as

the write instruction’s execution by the CPU. The user

must ensure that when RTCEN = 1, the updated regis-

ters will not be incremented at the same time. This can

be accomplished in several ways:

• By checking the RTCSYNC bit (RTCCFG<4>)

• By checking the preceding digits from which a

carry can occur

• By updating the registers immediately following

the seconds pulse (or alarm interrupt)

The user has visibility to the half-second field of the

counter. This value is read-only and can be reset only

by writing to the lower half of the SECONDS register.

15.2.6 SAFETY WINDOW FOR REGISTER

READS AND WRITES

The RTCSYNC bit indicates a time window during

which the RTCC clock domain registers can be safely

read and written without concern about a rollover.

When RTCSYNC = 0, the registers can be safely

accessed by the CPU.

Whether RTCSYNC = 1 or 0, the user should employ a

firmware solution to ensure that the data read did not

fall on a rollover boundary, resulting in an invalid or

partial read. This firmware solution would consist of

reading each register twice and then comparing the two

values. If the two values matched, then a rollover did

not occur.

15.2.7 WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RTCCFG<5>) must be set.

To avoid accidental writes to the RTCC Timer register,

it is recommended that the RTCWREN bit

(RTCCFG<5>) be kept clear at any time other than

while writing to it. For the RTCWREN bit to be set, there

is only one instruction cycle time window allowed

between the 55h/AA sequence and the setting of

RTCWREN. For that reason, it is recommended that

users follow the code example in Example 15-1.

EXAMPLE 15-1: SETTING THE RTCWREN

BIT

15.2.8 REGISTER MAPPING

To limit the register interface, the RTCC Timer and

Alarm Timer registers are accessed through

corresponding register pointers. The RTCC Value

RTCPTR bits (RTCCFG<1:0>) to select the required

Timer register pair.

By reading or writing to the RTCVALH register, the

RTCC Pointer value (RTCPTR<1:0>) decrements by ‘1’

until it reaches ‘00’. Once it reaches ‘00’, the MINUTES

and SECONDS value will be accessible through

RTCVALH and RTCVALL until the pointer value is

manually changed.

TABLE 15-3: RTCVALH AND RTCVALL

The Alarm Value register window (ALRMVALH and

ALRMVALL) uses the ALRMPTR bits (ALRMCFG<1:0>)

to select the desired Alarm register pair.

By reading or writing to the ALRMVALH register, the

Alarm Pointer value, ALRMPTR<1:0>, decrements by ‘1’

until it reaches ‘00’. Once it reaches ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

movlw 0x55

movwf EECON2

movlw 0xAA

movwf EECON2

bsf RTCCFG,RTCWREN

RTCPTR<1:0>

RTCC Value Register Window

RTCVALH RTCVALL

00 MINUTES SECONDS

01 WEEKDAY HOURS

10 MONTH DAY

11 — YEAR

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DS39979A-page 152 Preliminary  2010 Microchip Technology Inc.

TABLE 15-4: ALRMVAL REGISTER

MAPPING

15.2.9 CALIBRATION

The real-time crystal input can be calibrated using the

periodic auto-adjust feature. When properly calibrated,

the RTCC can provide an error of less than three

seconds per month.

To perform this calibration, find the number of error

clock pulses and store the value into the lower half of

the RTCCAL register. The 8-bit, signed value, loaded

into RTCCAL, is multiplied by 4 and will either be added

or subtracted from the RTCC timer, once every minute.

To calibrate the RTCC module:

1. Use another timer resource on the device to find

the error of the 32.768 kHz crystal.

2. Convert the number of error clock pulses per

minute (see Equation 15-1).

• If the oscillator is faster than ideal (negative

result from step 2), the RCFGCALL register

value needs to be negative. This causes the

specified number of clock pulses to be

subtracted from the timer counter once every

minute.

• If the oscillator is slower than ideal (positive

result from step 2), the RCFGCALL register

value needs to be positive. This causes the

specified number of clock pulses to be added to

the timer counter once every minute.

3. Load the RTCCAL register with the correct

value.

Writes to the RTCCAL register should occur only when

the timer is turned off, or immediately after the rising

edge of the seconds pulse.

15.3 Alarm

The Alarm features and characteristics are:

• Configurable from half a second to one year

• Enabled using the ALRMEN bit (ALRMCFG<7>,

• Offers one-time and repeat alarm options

15.3.1 CONFIGURING THE ALARM

The alarm feature is enabled using the ALRMEN bit.

This bit is cleared when an alarm is issued. The bit will

not be cleared if the CHIME bit = 1 or if ALRMRPT  0.

The interval selection of the alarm is configured

through the ALRMCFG bits (AMASK<3:0>). (See

Figure 15-5.) These bits determine which and how

many digits of the alarm must match the clock value for

the alarm to occur.

The alarm can also be configured to repeat based on a

preconfigured interval. The number of times this

occurs, after the alarm is enabled, is stored in the

ALRMRPT register.

ALRMPTR<1:0>

Alarm Value Register Window

ALRMVALH ALRMVALL

00 ALRMMIN ALRMSEC

01 ALRMWD ALRMHR

10 ALRMMNTH ALRMDAY

11 ——

EQUATION 15-1: CONVERTING ERROR

CLOCK PULSES

(Ideal Frequency (32,758) – Measured Frequency) * 60 =

Error Clocks per Minute

Note: In determining the crystal’s error value, it

is the user’s responsibility to include the

crystal’s initial error from drift due to

temperature or crystal aging.

Note: While the alarm is enabled (ALRMEN = 1),

changing any of the registers, other than

the RTCCAL, ALRMCFG and ALRMRPT

registers, and the CHIME bit, can result in

a false alarm event leading to a false

alarm interrupt. To avoid this, only change

the timer and alarm values while the alarm

is disabled (ALRMEN = 0). It is recom-

mended that the ALRMCFG and

ALRMRPT registers and CHIME bit be

changed when RTCSYNC = 0.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 153

PIC18F87J72 FAMILY

FIGURE 15-5: ALARM MASK SETTINGS

When ALRMCFG = 00 and the CHIME bit = 0

(ALRMCFG<6>), the repeat function is disabled and

only a single alarm will occur. The alarm can be

repeated up to 255 times by loading the ALRMRPT

After each alarm is issued, the ALRMRPT register is

decremented by one. Once the register has reached

‘00’, the alarm will be issued one last time.

After the alarm is issued a last time, the ALRMEN bit is

cleared automatically and the alarm turned off. Indefinite

repetition of the alarm can occur if the CHIME bit = 1.

When CHIME = 1, the alarm is not disabled when the

ALRMRPT register reaches ‘00’, but it rolls over to FF

and continues counting indefinitely.

Note 1: Annually, except when configured for February 29.

mss

mm s s

hh mm ss

dhhmmss

dd hh mm ss

mm d d h h mm s s

Day of the

Week Month Day Hours Minutes Seconds

Alarm Mask Setting

AMASK<3:0>

0000 – Every half second

0001 – Every second

0010 – Every 10 seconds

0011 – Every minute

0100 – Every 10 minutes

0101 – Every hour

0110 – Every day

0111 – Every week

1000 – Every month

1001 – Every year(1)

PIC18F87J72 FAMILY

DS39979A-page 154 Preliminary  2010 Microchip Technology Inc.

15.3.2 ALARM INTERRUPT

At every alarm event, an interrupt is generated. Addi-

tionally, an alarm pulse output is provided that operates

at half the frequency of the alarm.

The alarm pulse output is completely synchronous with

the RTCC clock and can be used as a trigger clock to

other peripherals. This output is available on the RTCC

pin. The output pulse is a clock with a 50% duty cycle

and a frequency half that of the alarm event (see

Figure 15-6).

The RTCC pin can also output the seconds clock. The

user can select between the alarm pulse, generated by

the RTCC module, or the seconds clock output.

The RTSECSEL<1:0> (PADCFG1<2:1>) bits select

between these two outputs:

• Alarm Pulse – RTSECSEL<1:0> = 00

• Seconds Clock – RTSECSEL<1:0> = 01

FIGURE 15-6: TIMER PULSE GENERATION

15.4 Sleep Mode

The timer and alarm continue to operate while in Sleep

mode. The operation of the alarm is not affected by

Sleep as an alarm event can always wake-up the CPU.

The Idle mode does not affect the operation of the timer

or alarm.

15.5 Reset

15.5.1 DEVICE RESET

When a device Reset occurs, the ALCFGRPT register

is forced to its Reset state, causing the alarm to be

disabled (if enabled prior to the Reset). If the RTCC

was enabled, it will continue to operate when a basic

device Reset occurs.

15.5.2 POWER-ON RESET (POR)

The RTCCFG and ALRMRPT registers are reset only

on a POR. Once the device exits the POR state, the

clock registers should be reloaded with the desired

values.

The timer prescaler values can be reset only by writing

to the SECONDS register. No device Reset can affect

the prescalers.

RTCEN bit

ALRMEN bit

RTCC Alarm Event

RTCC Pin

 2010 Microchip Technology Inc. Preliminary DS39979A-page 155

PIC18F87J72 FAMILY

15.6 Register Maps

Table 15-5, Table 15-6 and Table 15-7 summarize the

registers associated with the RTCC module.

TABLE 15-5: RTCC CONTROL REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

on Page

RTCCFG RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 54

RTCCAL CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 54

PADCFG1 — — — — — RTSECSEL1 RTSECSEL0 —54

ALRMCFG ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 54

ALRMRPT ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 54

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.

TABLE 15-6: RTCC VALUE REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

on Page

RTCVALH RTCC Value High Register Window Based on RTCPTR<1:0> 54

RTCVALL RTCC Value Low Register Window Based on RTCPTR<1:0> 54

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.

TABLE 15-7: ALARM VALUE REGISTERS

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets

on Page

ALRMVALH Alarm Value High Register Window Based on ALRMPTR<1:0> 54

ALRMVALL Alarm Value Low Register Window Based on ALRMPTR<1:0> 54

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 80-pin devices.

PIC18F87J72 FAMILY

DS39979A-page 156 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 157

PIC18F87J72 FAMILY

16.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

PIC18F87J72 family devices have two CCP

(Capture/Compare/PWM) modules, designated CCP1

and CCP2. Both modules implement standard capture,

compare and Pulse-Width Modulation (PWM) modes.

Each CCP module contains two 8-bit registers that can

operate as two 8-bit Capture registers, two 8-bit

Compare registers or two PWM Master/Slave Duty

Cycle registers. For the sake of clarity, all CCP module

operation in the following sections is described with

respect to CCP2, but is equally applicable to CCP1.

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 DCxB<1:0>: PWM Duty Cycle bit 1 and bit 0 for CCPx Module

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two Least Significant bits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight

Most Significant bits (DCx<9:2>) of the duty cycle are found in CCPRxL.

bit 3-0 CCPxM<3:0>: CCPx Module Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module)

0001 = Reserved

0010 = Compare mode, toggle output on match (CCPxIF bit is set)

0011 = Reserved

0100 = Capture mode, every falling edge

0101 = Capture mode, every rising edge

0110 = Capture mode, every 4th rising edge

0111 = Capture mode, every 16th rising edge

1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit

is set)

1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit

is set)

1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin

reflects I/O state)

1011 = Compare mode: Special Event Trigger; reset timer; start A/D conversion on CCPx match

(CCPxIF bit is set)(1)

11xx =PWM mode

Note 1: CCPxM<3:0> = 1011 will only reset the timer and not start an A/D conversion on a CCP1 match.

PIC18F87J72 FAMILY

DS39979A-page 158 Preliminary  2010 Microchip Technology Inc.

16.1 CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

16.1.1 CCP MODULES AND TIMER

RESOURCES

The CCP modules utilize timers, 1, 2 or 3, depending

on the mode selected. Timer1 and Timer3 are available

to modules in Capture or Compare modes, while

Timer2 is available for modules in PWM mode.

TABLE 16-1: CCP MODE – TIMER

RESOURCE

The assignment of a particular timer to a module is

determined by the Timer to CCP enable bits in the

T3CON register (Register 14-1). Both modules may be

active at any given time and may share the same timer

resource if they are configured to operate in the same

mode (Capture/Compare or PWM) at the same time.

The interactions between the two modules are

summarized in Table 16-2.

Depending on the configuration selected, up to four

timers may be active at once, with modules in the same

configuration (Capture/Compare or PWM) sharing

timer resources. The possible configurations are

shown in Figure 16-1.

16.1.2 OPEN-DRAIN OUTPUT OPTION

When operating in Output mode (i.e., in Compare or

PWM modes), the drivers for the CCPx pins can be

optionally configured as open-drain outputs. This

feature allows the voltage level on the pin to be pulled

to a higher level through an external pull-up resistor

and allows the output to communicate with external

circuits without the need for additional level shifters.

The open-drain output option is controlled by the

CCP2OD and CCP1OD bits (TRISG<6:5>). Setting the

appropriate bit configures the pin for the corresponding

module for open-drain operation.

16.1.3 CCP2 PIN ASSIGNMENT

The pin assignment for CCP2 (capture input, compare

and PWM output) can change, based on device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assigned to RC1 (CCP2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RE7.

Changing the pin assignment of CCP2 does not

automatically change any requirements for configuring

the port pin. Users must always verify that the appropri-

ate TRIS register is configured correctly for CCP2

operation, regardless of where it is located.

FIGURE 16-1: CCP AND TIMER INTERCONNECT CONFIGURATIONS

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

TMR1

TMR2

TMR3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP2

CCP1

TMR1 TMR3

TMR2

CCP2

CCP1

T3CCP<2:1> = 00 T3CCP<2:1> = 01 T3CCP<2:1> = 1x

Timer1 is used for all capture

and compare operations for

all CCP modules. Timer2 is

used for PWM operations for

all CCP modules. Modules

may share either timer

resource as a common time

base.

Timer1 is used for capture

and compare operations for

CCP1 and Timer 3 is used for

CCP2.

Both the modules use Timer2

as a common time base if they

are in PWM modes.

Timer3 is used for all capture

and compare operations for

all CCP modules. Timer2 is

used for PWM operations for

all CCP modules. Modules

may share either timer

resource as a common time

base.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 159

PIC18F87J72 FAMILY

TABLE 16-2: INTERACTIONS BETWEEN CCP1 AND CCP2 FOR TIMER RESOURCES

CCP1 Mode CCP2 Mode Interaction

Capture Capture Each module can use TMR1 or TMR3 as the time base. The time base can be different

for each CCP.

Capture Compare CCP2 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Automatic A/D conversions on trigger event

can also be done. Operation of CCP1 could be affected if it is using the same timer as a

time base.

Compare Capture CCP1 can be configured for the Special Event Trigger to reset TMR1 or TMR3

(depending upon which time base is used). Operation of CCP2 could be affected if it is

using the same timer as a time base.

Compare Compare Either module can be configured for the Special Event Trigger to reset the time base.

Automatic A/D conversions on CCP2 trigger event can be done. Conflicts may occur if

both modules are using the same time base.

Capture PWM None

Compare PWM None

PWM Capture None

PWM Compare None

PWM PWM Both PWMs will have the same frequency and update rate (TMR2 interrupt).

PIC18F87J72 FAMILY

DS39979A-page 160 Preliminary  2010 Microchip Technology Inc.

16.2 Capture Mode

In Capture mode, the CCPR2H:CCPR2L register pair

captures the 16-bit value of the TMR1 or TMR3 register

when an event occurs on the CCP2 pin (RC1 or RE7,

depending on device configuration). An event is

defined as one of the following:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

The event is selected by the mode select bits,

CCP2M<3:0> (CCP2CON<3:0>). When a capture is

made, the interrupt request flag bit, CCP2IF (PIR3<2>), is

set; it must be cleared in software. If another capture

occurs before the value in register, CCPR2, is read, the

old captured value is overwritten by the new captured

value.

16.2.1 CCP PIN CONFIGURATION

In Capture mode, the appropriate CCPx pin should be

configured as an input by setting the corresponding

TRIS direction bit.

16.2.2 TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature

(Timer1 and/or Timer3) must be running in Timer mode or

Synchronized Counter mode. In Asynchronous Counter

mode, the capture operation may not work. The timer to

be used with each CCP module is selected in the T3CON

Resources”).

16.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP2IE bit (PIE3<2>) clear to avoid false interrupts

and should clear the flag bit, CCP2IF, following any

such change in operating mode.

16.2.4 CCP PRESCALER

There are four prescaler settings in Capture mode.

They are specified as part of the operating mode

selected by the mode select bits (CCP2M<3:0>).

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. This means that any Reset will clear the

prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared; therefore, the first capture may be from

a non-zero prescaler. Example 16-1 shows the

recommended method for switching between capture

prescalers. This example also clears the prescaler

counter and will not generate the “false” interrupt.

EXAMPLE 16-1: CHANGING BETWEEN

CAPTURE PRESCALERS

FIGURE 16-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

Note: If RC1/CCP2 or RE7/CCP2 is configured

as an output, a write to the port can cause

a capture condition.

CLRF CCP2CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP2CON ; Load CCP2CON with

; this value

CCPR1H CCPR1L

TMR1H TMR1L

Set CCP1IF

TMR3

Enable

Q1:Q4

CCP1CON<3:0>

CCP1 Pin

Prescaler

 1, 4, 16

and

Edge Detect

TMR1

Enable

T3CCP2

CCPR2H CCPR2L

TMR1H TMR1L

Set CCP2IF

TMR3

Enable

CCP2CON<3:0>

CCP2 Pin

Prescaler

 1, 4, 16

TMR3H TMR3L

TMR1

Enable

T3CCP2

T3CCP1

T3CCP2

T3CCP1

TMR3H TMR3L

and

Edge Detect

 2010 Microchip Technology Inc. Preliminary DS39979A-page 161

PIC18F87J72 FAMILY

16.3 Compare Mode

In Compare mode, the 16-bit CCPR2 register value is

constantly compared against either the TMR1 or TMR3

pin can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (CCP2M<3:0>). At the same time, the

interrupt flag bit, CCP2IF, is set.

16.3.1 CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRIS bit.

16.3.2 TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

16.3.3 SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCP2M<3:0> = 1010), the CCP2 pin is not affected.

Only a CCP interrupt is generated, if enabled, and the

CCP2IE bit is set.

16.3.4 SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare Special Event Trigger mode

(CCP2M<3:0> = 1011).

For either CCP module, the Special Event Trigger resets

the Timer register pair for whichever timer resource is

currently assigned as the module’s time base. This

allows the CCPRx registers to serve as a programmable

period register for either timer.

The Special Event Trigger for CCP2 can also start an

A/D conversion. In order to do this, the A/D Converter

must already be enabled.

FIGURE 16-3: COMPARE MODE OPERATION BLOCK DIAGRAM

Note: Clearing the CCP2CON register will force

the RC1 or RE7 compare output latch

(depending on device configuration) to the

default low level. This is not the PORTC or

PORTE I/O data latch.

Note: The Special Event Trigger of CCP1 only

resets Timer1/Timer3 and cannot start an

A/D conversion even when the A/D

Converter is enabled.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator Q

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 Pin

TRIS

CCP1CON<3:0>

Output Enable

TMR3H TMR3L

CCPR2H CCPR2L

Comparator

T3CCP2

T3CCP1

Set CCP2IF

Compare

(Timer1 Reset)

Output

Logic

Special Event Trigger

CCP2 Pin

TRIS

CCP2CON<3:0>

Output Enable

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match

PIC18F87J72 FAMILY

DS39979A-page 162 Preliminary  2010 Microchip Technology Inc.

TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

RCON IPEN —CM RI TO PD POR BOR 50

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —52

PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —52

IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —52

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52

TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 —TRISE1 TRISE0 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

TMR1L Timer1 Register Low Byte 50

TMR1H Timer1 Register High Byte 50

T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 50

TMR3H Timer3 Register High Byte 51

TMR3L Timer3 Register Low Byte 51

T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 51

CCPR1L Capture/Compare/PWM Register 1 Low Byte 53

CCPR1H Capture/Compare/PWM Register 1 High Byte 53

CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53

CCPR2L Capture/Compare/PWM Register 2 Low Byte 53

CCPR2H Capture/Compare/PWM Register 2 High Byte 53

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare, Timer1 or Timer3.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 163

PIC18F87J72 FAMILY

16.4 PWM Mode

In Pulse-Width Modulation (PWM) mode, the CCP2 pin

produces up to a 10-bit resolution PWM output. Since

the CCP2 pin is multiplexed with a PORTC or PORTE

data latch, the appropriate TRIS bit must be cleared to

make the CCP2 pin an output.

Figure 16-4 shows a simplified block diagram of the

CCP1 module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 16.4.3

“Setup for PWM Operation”.

FIGURE 16-4: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 16-5) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 16-5: PWM OUTPUT

16.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

EQUATION 16-1:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

•TMR2 is cleared

• The CCP2 pin is set (exception: if PWM duty

cycle = 0%, the CCP2 pin will not be set)

• The PWM duty cycle is latched from CCPR2L into

CCPR2H

Note: Clearing the CCP2CON register will force

the RC1 or RE7 output latch (depending

on device configuration) to the default low

level. This is not the PORTC or PORTE

I/O data latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create

the 10-bit time base.

Note: The Timer2 postscalers (see Section 13.0

“Timer2 Module”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

PWM Period = (PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

PIC18F87J72 FAMILY

DS39979A-page 164 Preliminary  2010 Microchip Technology Inc.

16.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR2L register and to the CCP2CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR2L contains

the eight MSbs and the CCP2CON<5:4> bits contain

the two LSbs. This 10-bit value is represented by

CCPR2L:CCP2CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 16-2:

CCPR2L and CCP2CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR2H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR2H is a read-only register.

The CCPR2H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPR2H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP2 pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation:

EQUATION 16-3:

TABLE 16-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •

TOSC • (TMR2 Prescale Value)

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP2 pin will not be

cleared.

FOSC

FPWM

---------------





log

2log

----------------------------- b i t s=

PWM Resolution (max)

PWM Frequency 2.44 kHz 9.77 kHz 39.06 kHz 156.25 kHz 312.50 kHz 416.67 kHz

Timer Prescaler (1, 4, 16)1641111

PR2 Value FFh FFh FFh 3Fh 1Fh 17h

Maximum Resolution (bits) 14 12 10 8 7 6.58

 2010 Microchip Technology Inc. Preliminary DS39979A-page 165

PIC18F87J72 FAMILY

16.4.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR2L register and CCP2CON<5:4> bits.

3. Make the CCP2 pin an output by clearing the

appropriate TRIS bit.

4. Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

5. Configure the CCP2 module for PWM operation.

TABLE 16-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

RCON IPEN —CM RI TO PD POR BOR 50

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IFTMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IETMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IPTMR1IP 52

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52

TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 —TRISE1 TRISE0 52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

TMR2 Timer2 Register 50

PR2 Timer2 Period Register 50

T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 50

CCPR1L Capture/Compare/PWM Register 1 Low Byte 53

CCPR1H Capture/Compare/PWM Register 1 High Byte 53

CCP1CON —— DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53

CCPR2L Capture/Compare/PWM Register 2 Low Byte 53

CCPR2H Capture/Compare/PWM Register 2 High Byte 53

CCP2CON —— DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2.

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NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 167

PIC18F87J72 FAMILY

17.0 LIQUID CRYSTAL DISPLAY

(LCD) DRIVER MODULE

The Liquid Crystal Display (LCD) driver module

generates the timing control to drive a static or

multiplexed LCD panel. It also provides control of the

LCD pixel data. The module can drive panels of up to

132 pixels (33 segments by 4 commons).

The LCD driver module supports these features:

• Direct driving of LCD panel

• On-chip bias generator with dedicated charge

pump to support a range of fixed and variable bias

options

• Up to four commons, with four Multiplexing modes

• Up to 33 segments

• Three LCD clock sources with selectable prescaler,

with a fourth source available for use with the LCD

charge pump

A simplified block diagram of the module is shown in

Figure 17-1.

FIGURE 17-1: LCD DRIVER MODULE BLOCK DIAGRAM

COM<3:0>

Timing Control

Data Bus

INTRC Oscillator

FOSC/4

T13CKI

132

MUX SEG<32:0>

To I/O Pins

20 x 8 (= 4 x 40)

LCD DATA

LCDCON

LCDPS

LCDSEx

LCDDATA0

LCDDATA1

LCDDATA21

LCDDATA22

LCD Bias Generation

LCD Clock

Source Select

LCD

Charge Pump

Bias

Voltage

INTOSC Oscillator

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17.1 LCD Registers

The LCD driver module has 33 registers:

• LCD Control Register (LCDCON)

• LCD Phase Register (LCDPS)

• LCDREG Register (LCD Regulator Control)

• Five LCD Segment Enable Registers

(LCDSE4:LCDSE0)

• 20 LCD Data Registers (LCDDATAx, for x from 0 to

22, with 5, 11 and 17 not implemented)

17.1.1 LCD CONTROL REGISTERS

The LCDCON register, shown in Register 17-1,

controls the overall operation of the module. Once the

module is configured, the LCDEN (LCDCON<7>) bit is

used to enable or disable the LCD module. The LCD

panel can also operate during Sleep by clearing the

SLPEN (LCDCON<6>) bit.

The LCDPS register, shown in Register 17-2,

configures the LCD clock source prescaler and the type

of waveform: Type-A or Type-B. Details on these

features are provided in Section 17.2 “LCD Clock

Source”, Section 17.3 “LCD Bias Generation” and

Section 17.8 “LCD Waveform Generation”.

The LCDREG register is described in Section 17.3

“LCD Bias Generation”.

The LCD Segment Enable registers (LCDSEx)

configure the functions of the port pins. Setting the

segment enable bit for a particular segment configures

that pin as an LCD driver. The prototype LCDSE

LCDSE registers (LCDSE4:LCDSE0), listed in

Table 17-1.

R/W-0 R/W-0 R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0

bit 7 bit 0

Legend: C = Clearable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 LCDEN: LCD Driver Enable bit

1 = LCD driver module is enabled

0 = LCD driver module is disabled

bit 6 SLPEN: LCD Driver Enable in Sleep mode bit

1 = LCD driver module is disabled in Sleep mode

0 = LCD driver module is enabled in Sleep mode

bit 5 WERR: LCD Write Failed Error bit

1 = LCDDATAx register written while LCDPS<4> = 0 (must be cleared in software)

0 = No LCD write error

bit 4 Unimplemented: Read as ‘0’

bit 3-2 CS<1:0>: Clock Source Select bits

1x = INTRC (31 kHz)

01 = T13CKI (Timer1)

00 = System clock (FOSC/4)

bit 1-0 LMUX<1:0>: Commons Select bits

LMUX<1:0> Multiplex Type Maximum Number

of Pixels Bias Type

00 Static (COM0) 33 Static

01 1/2 (COM1:COM0) 66 1/2 or 1/3

10 1/3 (COM2:COM0) 99 1/2 or 1/3

11 1/4 (COM3:COM0) 132 1/3

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R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

WFT BIASMD LCDA WA LP3 LP2 LP1 LP0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WFT: Waveform Type Select bit

1 = Type-B waveform (phase changes on each frame boundary)

0 = Type-A waveform (phase changes within each common type)

bit 6 BIASMD: Bias Mode Select bit

When LMUX<1:0> = 00:

0 = Static Bias mode (do not set this bit to ‘1’)

When LMUX<1:0> = 01 or 10:

1 = 1/2 Bias mode

0 = 1/3 Bias mode

When LMUX<1:0> = 11:

0 = 1/3 Bias mode (do not set this bit to ‘1’)

bit 5 LCDA: LCD Active Status bit

1 = LCD driver module is active

0 = LCD driver module is inactive

bit 4 WA: LCD Write Allow Status bit

1 = Write into the LCDDATAx registers is allowed

0 = Write into the LCDDATAx registers is not allowed

bit 3-0 LP<3:0>: LCD Prescaler Select bits

1111 = 1:16

1110 = 1:15

1101 = 1:14

1100 = 1:13

1011 = 1:12

1010 = 1:11

1001 = 1:10

1000 = 1:9

0111 = 1:8

0110 = 1:7

0101 = 1:6

0100 = 1:5

0011 = 1:4

0010 = 1:3

0001 = 1:2

0000 = 1:1

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TABLE 17-1: LCDSE REGISTERS AND ASSOCIATED SEGMENTS

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

SE(n + 7) SE(n + 6) SE(n + 5) SE(n + 4) SE(n + 3) SE(n + 2) SE(n + 1) SE(n)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 SEG(n + 7):SEG(n): Segment Enable bits

For LCDSE0: n = 0

For LCDSE1: n = 8

For LCDSE2: n = 16

For LCDSE3: n = 24

For LCDSE4: n = 32

1 = Segment function of the pin is enabled; digital I/O disabled

0 = I/O function of the pin is enabled

LCDSE0 7:0

LCDSE1 15:8

LCDSE2 23:16

LCDSE3 31:24

LCDSE4(1) 32

Note 1: Only LCDSE4<0> (SEG32) is implemented.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 171

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17.1.2 LCD DATA REGISTERS

Once the module is initialized for the LCD panel, the

individual bits of the LCDDATA registers are cleared or

set to represent a clear or dark pixel, respectively.

Specific sets of LCDDATA registers are used with

specific segments and common signals. Each bit

represents a unique combination of a specific segment

connected to a specific common.

Individual LCDDATA bits are named by the convention

“SxxCy”, with “xx” as the segment number and “y” as

the common number. The relationship is summarized

in Table 17-2. The prototype LCDDATA register is

shown in Register 17-4.

TABLE 17-2: LCDDATA REGISTERS AND BITS FOR SEGMENT AND COM COMBINATIONS

Note:

LCDDATA5, LCDDATA11 and LCDDATA17

are not implemented.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

S(n + 7)Cy S(n + 6)Cy S(n + 5)Cy S(n + 4)Cy S(n + 3)Cy S(n + 2)Cy S(n + 1)Cy S(n)Cy

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 S(n + 7)Cy:S(n)Cy: Pixel On bits

For LCDDATA0 through LCDDATA5: n = (8x), y = 0(1)

For LCDDATA6 through LCDDATA10: n = (8(x – 6)), y = 1

For LCDDATA12 through LCDDATA16: n = (8(x – 12)), y = 2(1)

For LCDDATA18 through LCDDATA22: n = (8(x – 18)), y = 3(1)

1 = Pixel on (dark)

0 = Pixel off (clear)

Note 1: LCDDATA5, LCDDATA11 and LCDDATA17 are not implemented.

Segments

COM Lines

0123

0 through 7 LCDDATA0 LCDDATA6 LCDDATA12 LCDDATA18

S00C0:S07C0 S00C1:S07C1 S00C2:S07C2 S00C3:S07C3

8 through 15 LCDDATA1 LCDDATA7 LCDDATA13 LCDDATA19

S08C0:S15C0 S08C1:S15C1 S08C2:S15C2 S08C0:S15C3

16 through 23 LCDDATA2 LCDDATA8 LCDDATA14 LCDDATA20

S16C0:S23C0 S16C1:S23C1 S16C2:S23C2 S16C3:S23C3

24 through 31 LCDDATA3 LCDDATA9 LCDDATA15 LCDDATA21

S24C0:S31C0 S24C1:S31C1 S24C2:S31C2 S24C3:S31C3

32 LCDDATA4(1) LCDDATA10(1) LCDDATA16(1) LCDDATA22(1)

S32C0 S32C1 S32C2 S32C3

Note 1: Only bit<0> of these registers is implemented.

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DS39979A-page 172 Preliminary  2010 Microchip Technology Inc.

17.2 LCD Clock Source

The LCD driver module generates its internal clock

from 3 possible sources:

• System clock (FOSC/4)

• Timer1 oscillator

• INTRC source

The LCD clock generator uses a configurable

divide-by-32/divide-by-8192 postscaler to produce a

baseline frequency of about 1 kHz nominal, regardless

of the source selected. The clock source selection and

the postscaler configuration are determined by the

Clock Source Select bits, CS<1:0> (LCDCON<3:2>).

An additional programmable prescaler is used to derive

the LCD frame frequency from the 1 kHz baseline. The

prescaler is configured using the LP<3:0> bits

(LCDPS<3:0>) for any one of 16 options, ranging from

1:1 to 1:16.

Proper timing for waveform generation is set by the

LMUX<1:0> bits (LCDCON<1:0>). These bits

determine which Commons Multiplexing mode is to be

used, and divide down the LCD clock source as

required. They also determine the configuration of the

ring counter that is used to switch the LCD commons

on or off.

17.2.1 LCD VOLTAGE REGULATOR

CLOCK SOURCE

In addition to the clock source for LCD timing, a

separate 31 kHz nominal clock is required for the LCD

charge pump. This is provided from a distinct branch of

the LCD clock source.

The charge pump clock can use either the Timer1

oscillator or the INTRC source, as well as the 8 MHz

INTOSC source (after being divided by 256 by a

prescaler). The charge pump clock source is configured

using the CKSEL<1:0> bits (LCDREG<1:0>).

17.2.2 CLOCK SOURCE

CONSIDERATIONS

When using the system clock as the LCD clock source,

it is assumed that the system clock frequency is a nom-

inal 32 MHz (for a FOSC/4 frequency of 8 MHz).

Because the prescaler option for the FOSC/4 clock

selection is fixed at divide-by-8192, system clock

speeds that differ from 32 MHz will produce frame

frequencies and refresh rates different than discussed

in this chapter. The user will need to keep this in mind

when designing the display application.

The Timer1 and INTRC sources can be used as LCD

clock sources when the device is in Sleep mode. To

use the Timer1 oscillator, it is necessary to set the

T1OSCEN bit (T1CON<3>). Selecting either Timer1 or

INTRC as the LCD clock source will not automatically

activate these sources.

Similarly, selecting the INTOSC as the charge pump

clock source will not turn the oscillator on. To use

INTOSC, it must be selected as the system clock

source by using the FOSC2 Configuration bit.

If Timer1 is used as a clock source for the device, either

as an LCD clock source or for any other purpose, LCD

Segment 32 becomes unavailable.

FIGURE 17-2: LCD CLOCK GENERATION

LCDCON<3:2>

Timer1 Oscillator

Internal 31 kHz Source

÷4

Programmable

÷1, 2, 3, 4

Ring Counter

COM0

COM1

COM2

COM3

÷2 ÷32

LCDCON<1:0>

LCDPS<3:0>

System Clock (FOSC/4)

INTOSC 8 MHz Source

1:1 to 1:16

Prescaler

31 kHz Clock

LCDREG<1:0>

to LCD Charge Pump

÷8192

÷256

 2010 Microchip Technology Inc. Preliminary DS39979A-page 173

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17.3 LCD Bias Generation

The LCD driver module is capable of generating the

required bias voltages for LCD operation with a mini-

mum of external components. This includes the ability

to generate the different voltage levels required by the

different bias types required by the LCD. The driver

module can also provide bias voltages both above and

below microcontroller VDD through the use of an

on-chip LCD voltage regulator.

17.3.1 LCD BIAS TYPES

PIC18F87J72 family devices support three bias types

based on the waveforms generated to control

segments and commons:

• Static (two discrete levels)

• 1/2 Bias (three discrete levels

• 1/3 Bias (four discrete levels)

The use of different waveforms in driving the LCD is dis-

cussed in more detail in Section 17.8 “LCD Waveform

Generation”.

17.3.2 LCD VOLTAGE REGULATOR

The purpose of the LCD regulator is to provide proper

bias voltage and good contrast for the LCD, regardless

of VDD levels. This module contains a charge pump and

internal voltage reference. The regulator can be config-

ured by using external components to boost bias

voltage above VDD. It can also operate a display at a

constant voltage below VDD. The regulator can also be

selectively disabled to allow bias voltages to be

generated by an external resistor network.

The LCD regulator is controlled through the LCDREG

the CKSEL<1:0> bits, while the charge pump can be

selectively enabled using the CPEN bit. When the reg-

ulator is enabled, the MODE13 bit is used to select the

bias type. The peak LCD bias voltage, measured as a

difference between the potentials of LCDBIAS3 and

LCDBIAS0, is configured with the BIAS bits.

U-0 RW-0RW-1RW-1RW-1RW-1RW-0RW-0

— CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6 CPEN: LCD Charge Pump Enable bit

1 = Charge pump enabled; highest LCD bias voltage is 3.6V

0 = Charge pump disabled; highest LCD bias voltage is AVDD

bit 5-3 BIAS<2:0>: Regulator Voltage Output Control bits

111 = 3.60V peak (offset on LCDBIAS0 of 0V)

110 = 3.47V peak (offset on LCDBIAS0 of 0.13V)

101 = 3.34V peak (offset on LCDBIAS0 of 0.26V)

100 = 3.21V peak (offset on LCDBIAS0 of 0.39V)

011 = 3.08V peak (offset on LCDBIAS0 of 0.52V)

010 = 2.95V peak (offset on LCDBIAS0 of 0.65V)

001 = 2.82V peak (offset on LCDBIAS0 of 0.78V)

000 = 2.69V peak (offset on LCDBIAS0 of 0.91V)

bit 2 MODE13: 1/3 LCD Bias Enable bit

1 = Regulator output supports 1/3 LCD Bias mode

0 = Regulator output supports Static LCD Bias mode

bit 1-0 CKSEL<1:0>: Regulator Clock Source Select bits

11 = INTRC

10 = INTOSC 8 MHz source

01 = Timer1 oscillator

00 = LCD regulator disabled

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DS39979A-page 174 Preliminary  2010 Microchip Technology Inc.

17.3.3 BIAS CONFIGURATIONS

PIC18F87J72 family devices have four distinct circuit

configurations for LCD bias generation:

• M0: Regulator with Boost

• M1: Regulator without Boost

• M2: Resistor Ladder with Software Contrast

• M3: Resistor Ladder with Hardware Contrast

17.3.3.1 M0 (Regulator with Boost)

In M0 operation, the LCD charge pump feature is

enabled. This allows the regulator to generate voltages

up to +3.6V to the LCD (as measured at LCDBIAS3).

M0 uses a flyback capacitor connected between

VLCAP1 and VLCAP2, as well as filter capacitors on

LCDBIAS0 through LCDBIAS3, to obtain the required

voltage boost (Figure 17-3). The output voltage (VBIAS)

is the difference of potential between LCDBIAS3 and

LCDBIAS0. It is set by the BIAS<2:0> bits which adjust

the offset between LCDBIAS0 and VSS. The flyback

capacitor (CFLY) acts as a charge storage element for

large LCD loads. This mode is useful in those cases

where the voltage requirements of the LCD are higher

than the microcontroller’s VDD. It also permits software

control of the display’s contrast by adjustment of bias

voltage by changing the value of the BIAS bits.

M0 supports Static and 1/3 Bias types. Generation of

the voltage levels for 1/3 Bias is handled automatically,

but must be configured in software.

M0 is enabled by selecting a valid regulator clock

source (CKSEL<1:0> set to any value except ‘00’) and

setting the CPEN bit. If Static Bias type is required, the

MODE13 bit must be cleared.

17.3.3.2 M1 (Regulator without Boost)

M1 operation is similar to M0, but does not use the LCD

charge pump. It can provide VBIAS up to the voltage

level supplied directly to LCDBIAS3. It can be used in

cases where VDD for the application is expected to

never drop below a level that can provide adequate

contrast for the LCD. The connection of external com-

ponents is very similar to M0, except that LCDBIAS3

must be tied directly to VDD (Figure 17-3).

The BIAS<2:0> bits can still be used to adjust contrast

in software by changing VBIAS. As with M0, changing

these bits changes the offset between LCDBIAS0 and

VSS. In M1, this is reflected in the change between the

LCDBIAS0 and the voltage tied to LCDBIAS3. Thus, if

VDD should change, VBIAS will also change; where in

M0, the level of VBIAS is constant.

Like M0, M1 supports Static and 1/3 Bias types.

Generation of the voltage levels for 1/3 Bias is handled

automatically but must be configured in software.

M1 is enabled by selecting a valid regulator clock

source (CKSEL<1:0> set to any value except ‘00’) and

clearing the CPEN bit. If 1/3 Bias type is required, the

MODE13 bit should also be set.

FIGURE 17-3: LCD REGULATOR CONNECTIONS FOR M0 AND M1 CONFIGURATIONS

Note: When the device enters Sleep mode while

operating in Bias modes, M0 or M1, be

sure that the bias capacitors are fully dis-

charged in order to get the lowest Sleep

current.

LCDBIAS3

LCDBIAS2

LCDBIAS1

LCDBIAS0

AVDD

VDD

VLCAP1

VLCAP2

CFLY

VDD

(VBIAS up to 3.6V)

Mode 0

(VBIAS  VDD)

Mode 1

CFLY

Note 1: These values are provided for design guidance only. They should be optimized for the application by the designer based on the

actual LCD specifications.

0.47 µF(1)

PIC18F87J72

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17.3.3.3 M2 (Resistor Ladder with

Software Contrast)

M2 operation also uses the LCD regulator but disables

the charge pump. The regulator’s internal voltage refer-

ence remains active as a way to regulate contrast. It is

used in cases where the current requirements of the

LCD exceed the capacity of the regulator’s charge

pump.

In this configuration, the LCD bias voltage levels are

created by an external resistor voltage divider

connected across LCDBIAS0 through LCDBIAS3, with

the top of the divider tied to VDD (Figure 17-4). The

potential at the bottom of the ladder is determined by

the LCD regulator’s voltage reference, tied internally to

LCDBIAS0. The bias type is determined by the volt-

ages on the LCDBIAS pins, which are controlled by the

configuration of the resistor ladder. Most applications

using M2 will use a 1/3 or 1/2 Bias type. While Static

Bias can also be used, it offers extremely limited

contrast range and additional current consumption

over other bias generation modes.

Like M1, the LCDBIAS bits can be used to control con-

trast, limited by the level of VDD supplied to the device.

Also, since there is no capacitor required across

VLCAP1 and VLCAP2, these pins are available as digital

I/O ports, RG2 and RG3.

M2 is selected by clearing the CKSEL<1:0> bits and

setting the CPEN bit.

FIGURE 17-4: RESISTOR LADDER CONNECTIONS FOR M2 CONFIGURATION

LCDBIAS3

Note 1: These values are provided for design guidance only; they should be optimized for the application by the designer

based on the actual LCD specifications.

Bias Level at Pin

Bias Type

1/2 Bias 1/3 Bias

LCDBIAS0 (Internal low reference voltage) (Internal low reference voltage)

LCDBIAS1 1/2 VBIAS 1/3 VBIAS

LCDBIAS2 1/2 VBIAS 2/3 VBIAS

LCDBIAS3 VBIAS (up to AVDD)VBIAS (up to AVDD)

10 k(1)

1/2 Bias 1/3 Bias

LCDBIAS2

LCDBIAS1

LCDBIAS0

AVDD

10 k(1)

VDD

PIC18F87J72

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DS39979A-page 176 Preliminary  2010 Microchip Technology Inc.

17.3.3.4 M3 (Hardware Contrast)

In M3, the LCD regulator is completely disabled. Like

M2, LCD bias levels are tied to AVDD, and are generated

using an external divider. The difference is that the inter-

nal voltage reference is also disabled and the bottom of

the ladder is tied to ground (VSS); see Figure 17-5. The

value of the resistors, and the difference between VSS

and VDD, determine the contrast range; no software

adjustment is possible. This configuration is also used

where the LCD’s current requirements exceed the

capacity of the charge pump and software contrast

control is not needed.

Depending on the bias type required, resistors are

connected between some or all of the pins. A potentio-

meter can also be connected between LCDBIAS3 and

VDD to allow for hardware controlled contrast

adjustment.

M3 is selected by clearing the CKSEL<1:0> and CPEN

bits.

FIGURE 17-5: RESISTOR LADDER CONNECTIONS FOR M3 CONFIGURATION

LCDBIAS3

Note 1: These values are provided for design guidance only; they should be optimized for the application by the

designer based on the actual LCD specifications.

2: Potentiometer for manual contrast adjustment is optional; it may be omitted entirely.

Bias Level at Pin

Bias Type

Static 1/2 Bias 1/3 Bias

LCDBIAS0 AVSS AVSS AVSS

LCDBIAS1 AVSS 1/2 AVDD 1/3 AVDD

LCDBIAS2 AVDD 1/2 AVDD 2/3 AVDD

LCDBIAS3 AVDD AVDD AVDD

10 k(1)

Static Bias 1/2 Bias 1/3 Bias

LCDBIAS2

LCDBIAS1

LCDBIAS0

AVDD

10 k(1)

VDD

(2)

PIC18F87J72

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17.3.4 DESIGN CONSIDERATIONS FOR

THE LCD CHARGE PUMP

When designing applications that use the LCD regula-

tor with the charge pump enabled, users must always

consider both the dynamic current and RMS (static)

current requirements of the display, and what the

charge pump can deliver. Both dynamic and static

current can be determined by Equation 17-1:

EQUATION 17-1:

For dynamic current, C is the value of the capacitors

attached to LCDBIAS3 and LCDBIAS2. The variable,

dV, is the voltage drop allowed on C2 and C3 during a

voltage switch on the LCD display, and dT is the dura-

tion of the transient current after a clock pulse occurs.

For practical design purposes, these will be assumed

to be 0.047 F for C, 0.1V for dV and 1 s for dT. This

yields a dynamic current of 4.7 mA for 1 s.

RMS current is determined by the value of CFLY for C,

the voltage across VLCAP1 and VLCAP2 for dV and the

regulator clock period (TPER) for dT. Assuming CFLY of

0.047 F, a value of 1.02V across CFLY and TPER of

30 s, the maximum theoretical static current will be

1.8 mA. Since the charge pump must charge five

capacitors, the maximum current becomes 360 A. For

a real-world assumption of 50% efficiency, this yields a

practical current of 180 A.

Users should compare the calculated current capacity

against the requirements of the LCD. While dV and dT

are relatively fixed by device design, the values of CFLY

and the capacitors on the LCDBIAS pins can be

changed to increase or decrease current. As always,

any changes should be evaluated in the actual circuit

for its impact on the application.

17.4 LCD Multiplex Types

The LCD driver module can be configured into four

multiplex types:

• Static (only COM0 used)

• 1/2 Multiplex (COM0 and COM1 are used)

• 1/3 Multiplex (COM0, COM1 and COM2 are used)

• 1/4 Multiplex (all COM0, COM1, COM2 and COM3

are used)

The number of active commons used is configured by

the LMUX<1:0> bits (LCDCON<1:0>), which deter-

mines the function of the PORTE<6:4> pins (see

Table 17-3 for details). If the pin is configured as a COM

drive, the port I/O function is disabled and the TRIS

setting of that pin is overridden.

TABLE 17-3: PORTE<6:4> FUNCTION

17.5 Segment Enables

The LCDSEx registers are used to select the pin

function for each segment pin. Setting a bit configures

the corresponding pin to function as a segment driver.

LCDSEx registers do not override the TRIS bit settings,

so the TRIS bits must be configured as input for that

pin.

17.6 Pixel Control

The LCDDATAx registers contain bits which define the

state of each pixel. Each bit defines one unique pixel.

Table 17-2 shows the correlation of each bit in the

LCDDATAx registers to the respective common and

segment signals. Any LCD pixel location not being

used for display can be used as general purpose RAM.

I = C x dV

Note: On a Power-on Reset, the LMUX<1:0>

bits are ‘00’.

LMUX<1:0> PORTE<6> PORTE<5> PORTE<4>

00 Digital I/O Digital I/O Digital I/O

01 Digital I/O Digital I/O COM1 Driver

10 Digital I/O COM2 Driver COM1 Driver

11 COM3 Driver COM2 Driver COM1 Driver

Note: On a Power-on Reset, these pins are

configured as digital I/O.

PIC18F87J72 FAMILY

DS39979A-page 178 Preliminary  2010 Microchip Technology Inc.

17.7 LCD Frame Frequency

The rate at which the COM and SEG outputs change is

called the LCD frame frequency. Frame frequency is

set by the LP<3:0> bits (LCDPS<3:0>) and is also

affected by the Multiplex mode being used. The rela-

tionship between the Multiplex mode, LP bits setting

and frame rate is shown in Table 17-4 and Table 17-5.

TABLE 17-4: FRAME FREQUENCY

FORMULAS

TABLE 17-5: APPROXIMATE FRAME

FREQUENCY (IN Hz) FOR LP

PRESCALER SETTINGS

17.8 LCD Waveform Generation

LCD waveform generation is based on the principle

that the net AC voltage across the dark pixel should be

maximized and the net AC voltage across the clear

pixel should be minimized. The net DC voltage across

any pixel should be zero.

The COM signal represents the time slice for each

common, while the SEG contains the pixel data. The

pixel signal (COM-SEG) will have no DC component

and it can take only one of the two rms values. The

higher rms value will create a dark pixel and a lower

rms value will create a clear pixel.

As the number of commons increases, the delta

between the two rms values decreases. The delta

represents the maximum contrast that the display can

have.

The LCDs can be driven by two types of waveform:

Type-A and Type-B. In the Type-A waveform, the

phase changes within each common type, whereas in

the Type-B waveform, the phase changes on each

frame boundary. Thus, the Type-A waveform maintains

0 VDC over a single frame, whereas the Type-B

waveform takes two frames.

Figure 17-6 through Figure 17-16 provide waveforms

for static, half multiplex, one-third multiplex and quarter

multiplex drives for Type-A and Type-B waveforms.

Multiplex

Mode Frame Frequency (Hz)

Static Clock source/(4 x 1 x (LP<3:0> + 1))

1/2 Clock source/(2 x 2 x (LP<3:0> + 1))

1/3 Clock source/(1 x 3 x (LP<3:0> + 1))

1/4 Clock source/(1 x 4 x (LP<3:0> + 1))

LP<3:0>

Multiplex Mode

Static 1/2 1/3 1/4

1 125 125 167 125

2 83 83 111 83

3 62628362

4 50506750

5 42425642

6 36364836

7 31314231

Note 1: If the power-managed Sleep mode is

invoked while the LCD Sleep bit is set

(LCDCON<6> is ‘1’), take care to execute

Sleep only when the VDC on all the pixels

is ‘0’.

2: When the LCD clock source is the system

clock, the LCD module will go to Sleep if

the microcontroller goes into Sleep mode,

regardless of the setting of the SPLEN bit.

Thus, always take care to see that the VDC

on all pixels is ‘0’ whenever Sleep mode is

invoked.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 179

PIC18F87J72 FAMILY

FIGURE 17-6: TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE

COM0

SEG0

COM0-SEG0

COM0-SEG1

SEG1

-V1

1 Frame

COM0

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

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DS39979A-page 180 Preliminary  2010 Microchip Technology Inc.

FIGURE 17-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

-V2

-V1

-V2

-V1

COM0

COM1

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM1

COM0

SEG0

SEG1

SEG2

SEG3

 2010 Microchip Technology Inc. Preliminary DS39979A-page 181

PIC18F87J72 FAMILY

FIGURE 17-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

-V2

-V1

-V2

-V1

COM0

COM1

SEG0

SEG1

COM0-SEG0

COM0-SEG1

COM1

COM0

SEG0

SEG1

SEG2

SEG3

2 Frames

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DS39979A-page 182 Preliminary  2010 Microchip Technology Inc.

FIGURE 17-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM1

COM0

SEG0

SEG1

SEG2

SEG3

 2010 Microchip Technology Inc. Preliminary DS39979A-page 183

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FIGURE 17-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

SEG0

SEG1

COM0-SEG0

COM0-SEG1

COM1

COM0

SEG0

SEG1

SEG2

SEG3

2 Frames

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DS39979A-page 184 Preliminary  2010 Microchip Technology Inc.

FIGURE 17-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

-V2

-V1

-V2

-V1

COM0

COM1

COM2

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM2

COM1

COM0

SEG0

SEG1

SEG2

 2010 Microchip Technology Inc. Preliminary DS39979A-page 185

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FIGURE 17-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

-V2

-V1

-V2

-V1

COM0

COM1

COM2

SEG0

SEG1

COM0-SEG0

COM0-SEG1

2 Frames

COM2

COM1

COM0

SEG0

SEG1

SEG2

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DS39979A-page 186 Preliminary  2010 Microchip Technology Inc.

FIGURE 17-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

COM2

SEG0

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

COM2

COM1

COM0

SEG0

SEG1

SEG2

 2010 Microchip Technology Inc. Preliminary DS39979A-page 187

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FIGURE 17-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

COM2

SEG0

SEG1

COM0-SEG0

COM0-SEG1

2 Frames

COM2

COM1

COM0

SEG0

SEG1

SEG2

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DS39979A-page 188 Preliminary  2010 Microchip Technology Inc.

FIGURE 17-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

COM2

COM3

SEG0

SEG1

COM0-SEG0

COM0-SEG1

COM3

COM2

COM1

COM0

1 Frame

SEG0

SEG1

 2010 Microchip Technology Inc. Preliminary DS39979A-page 189

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FIGURE 17-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

-V3

-V2

-V1

-V3

-V2

-V1

COM0

COM1

COM2

COM3

SEG0

SEG1

COM0-SEG0

COM0-SEG1

COM3

COM2

COM1

COM0

2 Frames

SEG0

SEG1

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DS39979A-page 190 Preliminary  2010 Microchip Technology Inc.

17.9 LCD Interrupts

The LCD timing generation provides an interrupt that

defines the LCD frame timing. This interrupt can be

used to coordinate the writing of the pixel data with the

start of a new frame. Writing pixel data at the frame

boundary allows a visually crisp transition of the image.

This interrupt can also be used to synchronize external

events to the LCD. For example, the interface to an

external segment driver can be synchronized for

segment data update to the LCD frame.

A new frame is defined to begin at the leading edge of

the COM0 common signal. The interrupt will be set

immediately after the LCD controller completes

accessing all pixel data required for a frame. This will

occur at a fixed interval before the frame boundary

(TFINT), as shown in Figure 17-17. The LCD controller

will begin to access data for the next frame within the

interval from the interrupt to when the controller begins

to access data after the interrupt (TFWR). New data

must be written within TFWR, as this is when the LCD

controller will begin to access the data for the next

frame.

When the LCD driver is running with Type-B wave-

forms, and the LMUX<1:0> bits are not equal to ‘00’,

there are some additional issues that must be

addressed. Since the DC voltage on the pixel takes two

frames to maintain zero volts, the pixel data must not

change between subsequent frames. If the pixel data

were allowed to change, the waveform for the odd

frames would not necessarily be the complement of the

waveform generated in the even frames and a DC

component would be introduced into the panel. There-

fore, when using Type-B waveforms, the user must

synchronize the LCD pixel updates to occur within a

subframe after the frame interrupt.

To correctly sequence writing while in Type-B, the

interrupt will only occur on complete phase intervals. If

the user attempts to write when the write is disabled,

the WERR (LCDCON<5>) bit is set.

FIGURE 17-17: EXAMPLE WAVEFORMS AND INTERRUPT TIMING

IN QUARTER DUTY CYCLE DRIVE

Note: The interrupt is not generated when the

Type-A waveform is selected and when the

Type-B with no multiplex (static) is

selected.

Frame

Boundary

Frame

Boundary

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

TFINT

TFWR

TFWR =TFRAME/2 * (LMUX<1:0> + 1) + TCY/2

TFINT =(TFWR/2 – (2 TCY + 40 ns)) Minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)

(TFWR/2 – (1 TCY + 40 ns)) Maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)

Frame

Boundary

COM0

COM1

COM2

COM3

2 Frames

 2010 Microchip Technology Inc. Preliminary DS39979A-page 191

PIC18F87J72 FAMILY

17.10 Operation During Sleep

The LCD module can operate during Sleep. The selec-

tion is controlled by the SLPEN bit (LCDCON<6>).

Setting the SLPEN bit allows the LCD module to go to

Sleep. Clearing the SLPEN bit allows the module to

continue to operate during Sleep.

If a SLEEP instruction is executed and SLPEN = 1, the

LCD module will cease all functions and go into a very

low-current consumption mode. The module will stop

operation immediately and drive the minimum LCD

voltage on both segment and common lines.

Figure 17-18 shows this operation.

To ensure that no DC component is introduced on the

panel, the SLEEP instruction should be executed imme-

diately after a LCD frame boundary. The LCD interrupt

can be used to determine the frame boundary. See

Section 17.9 “LCD Interrupts” for the formulas to

calculate the delay.

If a SLEEP instruction is executed and SLPEN = 0, the

module will continue to display the current contents of

the LCDDATA registers. To allow the module to

continue operation while in Sleep, the clock source

must be either the Timer1 oscillator or one of the

internal oscillators (either INTRC or INTOSC as the

default system clock). While in Sleep, the LCD data

cannot be changed. The LCD module current

consumption will not decrease in this mode; however,

the overall consumption of the device will be lower due

to shutdown of the core and other peripheral functions.

If the system clock is selected and the module is not

configured for Sleep operation, the module will ignore

the SLPEN bit and stop operation immediately. The

minimum LCD voltage will then be driven onto the

segments and commons

17.10.1 USING THE LCD REGULATOR

DURING SLEEP

Applications that use the LCD regulator for bias

generation may not achieve the same degree of power

reductions in Sleep mode when compared to applica-

tions using Mode 3 (resistor ladder) biasing. This is

particularly true with Mode 0 operation, where the

charge pump is active.

If Modes 0, 1 or 2 are used for bias generation,

software contrast control will not be available.

FIGURE 17-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00

SLEEP Instruction Execution Wake-up

2 Frames

COM0

COM1

COM2

SEG0

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DS39979A-page 192 Preliminary  2010 Microchip Technology Inc.

17.11 Configuring the LCD Module

The following is the sequence of steps to configure the

LCD module.

1. Select the frame clock prescale using bits,

LP<3:0> (LCDPS<3:0>).

2. Configure the appropriate pins to function as

segment drivers using the LCDSEx registers.

3. Configure the appropriate pins as inputs using

the TRISx registers.

4. Configure the LCD module for the following

using the LCDCON register:

• Multiplex and Bias mode (LMUX<1:0>)

• Timing source (CS<1:0>)

• Sleep mode (SLPEN)

5. Write initial values to pixel data registers,

LCDDATA0 through LCDDATA23.

6. Configure the LCD regulator:

a) If M2 or M3 bias configuration is to be used,

turn off the regulator by setting

CKSEL<1:0> (LCDREG<1:0>) to ‘00’. Set

or clear the CPEN bit (LCDREG<6>) to

select Mode 2 or Mode 3, as appropriate.

b) If M0 or M1 bias generation is to be used:

•Set the V

BIAS level using the BIAS<2:0>

bits (LCDREG<5:3>).

• Set or clear the CPEN bit to enable or

disable the charge pump.

• Set or clear the MODE13 bit

(LCDREG<2>) to select the Bias mode.

• Select a regulator clock source using the

CKSEL<1:0> bits.

7. Clear LCD Interrupt Flag, LCDIF (PIR3<6>),

and if desired, enable the interrupt by setting the

LCDIE bit (PIE3<6>).

8. Enable the LCD module by setting the LCDEN

bit (LCDCON<7>).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 193

PIC18F87J72 FAMILY

TABLE 17-6: REGISTERS ASSOCIATED WITH LCD OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIFRC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 — LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 — LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCON IPEN —CM RI TO PD POR BOR 50

LCDDATA22 — — — — — — — S32C3 53

LCDDATA21 S31C3 S30C3 S29C3 S28C3 S27C3 S26C3 S25C3 S24C3 53

LCDDATA20 S23C3 S22C3 S21C3 S20C3 S19C3 S18C3 S17C3 S16C3 53

LCDDATA19 S15C3 S14C3 S13C3 S12C3 S11C3 S10C3 S09C3 S08C3 53

LCDDATA18 S07C3 S06C3 S05C3 S04C3 S03C3 S02C3 S01C3 S00C3 53

LCDDATA16 — — — — — — — S32C2 53

LCDDATA15 S31C2 S30C2 S29C2 S28C2 S27C2 S26C2 S25C2 S24C2 53

LCDDATA14 S23C2 S22C2 S21C2 S20C2 S19C2 S18C2 S17C2 S16C2 53

LCDDATA13 S15C2 S14C2 S13C2 S12C2 S11C2 S10C2 S09C2 S08C2 53

LCDDATA12 S07C2 S06C2 S05C2 S04C2 S03C2 S02C2 S01C2 S00C2 53

LCDDATA10 — — — — — — — S32C1 53

LCDDATA9 S31C1 S30C1 S29C1 S28C1 S27C1 S26C1 S25C1 S24C1 53

LCDDATA8 S23C1 S22C1 S21C1 S20C1 S19C1 S18C1 S17C1 S16C1 53

LCDDATA7 S15C1 S14C1 S13C1 S12C1 S11C1 S10C1 S09C1 S08C1 53

LCDDATA6 S07C1 S06C1 S05C1 S04C1 S03C1 S02C1 S01C1 S00C1 53

LCDDATA4 — — — — — — — S32C0 51

LCDDATA3 S31C0 S30C0 S29C0 S28C0 S27C0 S26C0 S25C0 S24C0 51

LCDDATA2 S23C0 S22C0 S21C0 S20C0 S19C0 S18C0 S17C0 S16C0 51

LCDDATA1 S15C0 S14C0 S13C0 S12C0 S11C0 S10C0 S09C0 S08C0 51

LCDDATA0 S07C0 S06C0 S05C0 S04C0 S03C0 S02C0 S01C0 S00C0 51

LCDSE4 — — — — — — — SE32 51

LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 51

LCDSE2 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 51

LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE09 SE08 51

LCDSE0 SE07 SE06 SE05 SE04 SE03 SE02 SE01 SE00 51

LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX1 LMUX0 51

LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 51

LCDREG — CPEN BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL0 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for LCD operation.

Note 1: These registers or individual bits are unimplemented on PIC18F86J72 devices.

Note: When the device enters Sleep mode while operating in Bias modes, M0 or M1, be sure that the bias

capacitors are fully discharged in order to get the lowest Sleep current.

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NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 195

PIC18F87J72 FAMILY

18.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

18.1 Master SSP (MSSP) Module

Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface, useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D Converters, etc. The MSSP

module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I2C™)

- Full Master mode

- Slave mode (with general address call)

The I2C interface supports the following modes in

hardware:

•Master mode

• Multi-Master mode

• Slave mode

18.2 Control Registers

Each MSSP module has three associated control

registers. These include a status register (SSPSTAT)

and two control registers (SSPCON1 and SSPCON2).

The use of these registers and their individual bits differ

significantly depending on whether the MSSP module

is operated in SPI or I2C mode.

Additional details are provided under the individual

sections.

18.3 SPI Mode

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. All four

modes of SPI are supported. To accomplish

communication, typically three pins are used:

• Serial Data Out (SDO) – RC5/SDO/SEG12

• Serial Data In (SDI) – RC4/SDI/SDA/SEG16

• Serial Clock (SCK) – RC3/SCK/SCL/SEG17

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) – RF7/AN5/SS/SEG25

Figure 18-1 shows the block diagram of the MSSP

module when operating in SPI mode.

FIGURE 18-1: MSSP BLOCK DIAGRAM

(SPI MODE)

( )

Read Write

Internal

Data Bus

SSPSR reg

SSPM<3:0>

bit 0 Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TXx/RXx in SSPSR

TRIS bit

SMP:CKE

SDO

SSPBUF reg

SDI

SCK

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DS39979A-page 196 Preliminary  2010 Microchip Technology Inc.

18.3.1 REGISTERS

Each MSSP module has four registers for SPI mode

operation. These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register (SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1

the SSPSTAT are read-only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together,

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R0 R-0

SMP CKE(1) D/A PSR/WUA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Sample bit

SPI Master mode:

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode.

bit 6 CKE: SPI Clock Select bit(1)

1 = Transmit occurs on transition from active to Idle clock state

0 = Transmit occurs on transition from Idle to active clock state

bit 5 D/A: Data/Address bit

Used in I2C™ mode only.

bit 4 P: Stop bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.

bit 3 S: Start bit

Used in I2C mode only.

bit 2 R/W: Read/Write Information bit

Used in I2C mode only.

bit 1 UA: Update Address bit

Used in I2C mode only.

bit 0 BF: Buffer Full Status bit (Receive mode only)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Note 1: Polarity of clock state is set by the CKP bit (SSPCON1<4>).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 197

PIC18F87J72 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV(1) SSPEN(2) CKP SSPM3(3) SSPM2(3) SSPM1(3) SSPM0(3)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit (Transmit mode only)

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit(1)

SPI Slave mode:

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-

flow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the

SSPBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software).

0 = No overflow

bit 5 SSPEN: Master Synchronous Serial Port Enable bit(2)

1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: Clock Polarity Select bit

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

bit 3-0 SSPM<3:0>: Master Synchronous Serial Port Mode Select bits(3)

0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as an I/O pin

0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled

0011 = SPI Master mode, clock = TMR2 output/2

0010 = SPI Master mode, clock = FOSC/64

0001 = SPI Master mode, clock = FOSC/16

0000 = SPI Master mode, clock = FOSC/4

Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by

writing to the SSPBUF register.

2: When enabled, these pins must be properly configured as input or output.

3: Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only.

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18.3.2 OPERATION

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON1<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

Each MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the Write Collision detect bit, WCOL

(SSPCON1<7>), will be set. User software must clear

the WCOL bit so that it can be determined if the follow-

ing write(s) to the SSPBUF register completed

successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

Buffer Full bit, BF (SSPSTAT<0>), indicates when

SSPBUF has been loaded with the received data (trans-

mission is complete). When the SSPBUF is read, the BF

bit is cleared. This data may be irrelevant if the SPI is

only a transmitter. Generally, the MSSP interrupt is used

to determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 18-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSPSTAT register indicates the

various status conditions.

EXAMPLE 18-1: LOADING THE SSPBUF (SSPSR) REGISTER

Note: To prevent lost data in Master mode, read

SSPBUF after each transmission to clear

the BF bit.

LOOP BTFSS SSPSTAT, BF ;Has data been received (transmit complete)?

BRA LOOP ;No

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

 2010 Microchip Technology Inc. Preliminary DS39979A-page 199

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18.3.3 ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON1<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, reinitialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed as follows:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

•SS

must have TRISF<7> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

18.3.4 OPEN-DRAIN OUTPUT OPTION

The drivers for the SDO output and SCK clock pins can

be optionally configured as open-drain outputs. This

feature allows the voltage level on the pin to be pulled

to a higher level through an external pull-up resistor,

and allows the output to communicate with external

circuits without the need for additional level shifters.

The open-drain output option is controlled by the

SPIOD bit (TRISG<7>). Setting the bit configures both

pins for open-drain operation.

18.3.5 TYPICAL CONNECTION

Figure 18-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge and latched on the opposite edge

of the clock. Both processors should be programmed to

the same Clock Polarity (CKP), then both controllers

would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data–Slave sends dummy data

• Master sends data–Slave sends data

• Master sends dummy data–Slave sends data

FIGURE 18-2: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM<3:0> = 00xx

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM<3:0> = 010x

Serial Clock

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18.3.6 MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 18-2) will

broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be dis-

abled (programmed as an input). The SSPSR register

will continue to shift in the signal present on the SDI pin

at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

The clock polarity is selected by appropriately

programming the CKP bit (SSPCON1<4>). This, then,

would give waveforms for SPI communication as

shown in Figure 18-3, Figure 18-5 and Figure 18-6,

where the MSB is transmitted first. In Master mode, the

SPI clock rate (bit rate) is user-programmable to be one

of the following:

•F

OSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum data rate (at 40 MHz) of

10.00 Mbps.

Figure 18-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

FIGURE 18-3: SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

bit 7

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

(CKE = 0)

(CKE = 1)

Next Q4 Cycle

after Q2

bit 0

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18.3.7 SLAVE MODE

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Before enabling the module in SPI Slave mode, the

clock line must match the proper Idle state. The clock

line can be observed by reading the SCK pin. The Idle

state is determined by the CKP bit (SSPCON1<4>).

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

18.3.8 SLAVE SELECT

SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The SPI

must be in Slave mode with SS pin control enabled

(SSPCON1<3:0> = 04h). When the SS pin is low, trans-

mission and reception are enabled and the SDO pin is

driven. When the SS pin goes high, the SDO pin is no

longer driven, even if in the middle of a transmitted byte

and becomes a floating output. External

pull-up/pull-down resistors may be desirable depending

on the application.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

FIGURE 18-4: SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON1<3:0> = 0100),

the SPI module will reset if the SS pin is set

to VDD.

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be

enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit 0

bit 7

bit 0

Next Q4 Cycle

after Q2



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FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Optional

Next Q4 Cycle

after Q2

bit 0

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit 7 bit 0

SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

SSPIF

Interrupt

(SMP = 0)

CKE = 1)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

Not Optional

Next Q4 Cycle

after Q2

 2010 Microchip Technology Inc. Preliminary DS39979A-page 203

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18.3.9 OPERATION IN POWER-MANAGED

MODES

In SPI Master mode, module clocks may be operating

at a different speed than when in Full-Power mode; in

the case of Sleep mode, all clocks are halted.

In Idle modes, a clock is provided to the peripherals.

That clock should be from the primary clock source, the

secondary clock (Timer1 oscillator at 32.768 kHz) or

the INTRC source. See Section 3.3 “Clock Sources

and Oscillator Switching” for additional information.

In most cases, the speed that the master clocks SPI

data is not important; however, this should be

evaluated for each system.

If MSSP interrupts are enabled, they can wake the con-

troller from Sleep mode, or one of the Idle modes, when

the master completes sending data. If an exit from

Sleep or Idle mode is not desired, MSSP interrupts

should be disabled.

If the Sleep mode is selected, all module clocks are

halted and the transmission/reception will remain in

that state until the devices wakes. After the device

returns to Run mode, the module will resume

transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

allows the device to be placed in any power-managed

mode and data to be shifted into the SPI

Transmit/Receive Shift register. When all 8 bits have

been received, the MSSP interrupt flag bit will be set,

and if enabled, will wake the device.

18.3.10 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

18.3.11 BUS MODE COMPATIBILITY

Table 18-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

There is also an SMP bit which controls when the data

is sampled.

TABLE 18-1: SPI BUS MODES

TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode

Terminology

Control Bits State

CKP CKE

0, 0(1) 01

0, 1 0 0

1, 0 1 1

1, 1(1) 10

Note 1: Use one of these modes when using the

SPI to communicate with the AFE. See

Section 22.5 “Using the AFE” for more

information.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52

TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52

TRISG SPIOD CCP2OD CCP1OD TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 52

SSPBUF MSSP Receive Buffer/Transmit Register 50

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50

SSPSTAT SMP CKE D/A P S R/W UA BF 50

Legend: Shaded cells are not used by the MSSP module in SPI mode.

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18.4 I2C Mode

The MSSP module in I2C mode fully implements all

master and slave functions (including general call

support) and provides interrupts on Start and Stop bits

in hardware to determine a free bus (multi-master

function). The MSSP module implements the standard

mode specifications as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer:

• Serial clock (SCL) – RC3/SCK/SCL/SEG17

• Serial data (SDA) – RC4/SDI/SDA/SEG16

The user must configure these pins as inputs by setting

the TRISC<4:3> bits.

FIGURE 18-7: MSSP BLOCK DIAGRAM

(I2C™ MODE)

18.4.1 REGISTERS

The MSSP module has six registers for I2C operation.

These are:

• MSSP Control Register 1 (SSPCON1)

• MSSP Control Register 2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer Register

(SSPBUF)

• MSSP Shift Register (SSPSR) – Not directly

accessible

• MSSP Address Register (SSPADD)

SSPCON1, SSPCON2 and SSPSTAT are the control

and status registers in I2C mode operation. The

SSPCON1 and SSPCON2 registers are readable and

writable. The lower 6 bits of the SSPSTAT are

read-only. The upper two bits of the SSPSTAT are

read/write.

Many of the bits in SSPCON2 assume different

functions, depending on whether the module is operat-

ing in Master or Slave mode; bits<5:2> also assume

different names in Slave mode. The different aspects of

SSPCON2 are shown in Register 18-5 (for Master

mode) and Register 18-6 (Slave mode).

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

SSPADD register holds the slave device address when

the MSSP is configured in I2C Slave mode. When the

MSSP is configured in Master mode, the lower seven

bits of SSPADD act as the Baud Rate Generator reload

value.

In receive operations, SSPSR and SSPBUF together,

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During transmission, the SSPBUF is not double-

buffered. A write to SSPBUF will write to both SSPBUF

and SSPSR.

Read Write

SSPSR reg

Match Detect

SSPADD reg

Start and

Stop bit Detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

Shift

Clock

MSb LSb

SCL

SDA

Address Mask

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R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A P(1) S(1) R/W UA BF

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SMP: Slew Rate Control bit

In Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

bit 6 CKE: SMBus Select bit

In Master or Slave mode:

1 = Enable SMBus specific inputs

0 = Disable SMBus specific inputs

bit 5 D/A: Data/Address bit

In Master mode:

Reserved.

In Slave mode:

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

bit 4 P: Stop bit(1)

1 = Indicates that a Stop bit has been detected last

0 = Stop bit was not detected last

bit 3 S: Start bit(1)

1 = Indicates that a Start bit has been detected last

0 = Start bit was not detected last

bit 2 R/W: Read/Write Information bit (I2C™ mode only)

In Slave mode:(2)

1 = Read

0 = Write

In Master mode:(3)

1 = Transmit is in progress

0 = Transmit is not in progress

bit 1 UA: Update Address bit (10-Bit Slave mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

bit 0 BF: Buffer Full Status bit

In Transmit mode:

1 = SSPBUF is full

0 = SSPBUF is empty

In Receive mode:

1 = SSPBUF is full (does not include the ACK and Stop bits)

0 = SSPBUF is empty (does not include the ACK and Stop bits)

Note 1: This bit is cleared on Reset and when SSPEN is cleared.

2: This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next Start bit, Stop bit or not ACK bit.

3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN(1) CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 WCOL: Write Collision Detect bit

In Master Transmit mode:

1 = A write to the SSPBUF register is attempted while the I2C™ conditions are not valid for a

transmission to be started (must be cleared in software)

0 = No collision

In Slave Transmit mode:

1 = The SSPBUF register is written while it was still transmitting the previous word (must be cleared in

software)

0 = No collision

In Receive mode (Master or Slave modes):

This is a “don’t care” bit.

bit 6 SSPOV: Receive Overflow Indicator bit

In Receive mode:

1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in

software)

0 = No overflow

In Transmit mode:

This is a “don’t care” bit in Transmit mode.

bit 5 SSPEN: Master Synchronous Serial Port Enable bit(1)

1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4 CKP: SCK Release Control bit

In Slave mode:

1 = Releases clock

0 = Holds clock low (clock stretch); used to ensure data setup time

In Master mode:

Unused in this mode.

bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits

1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1011 = I2C Firmware Controlled Master mode (slave Idle)

1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD + 1))

0111 = I2C Slave mode, 10-bit address

0110 = I2C Slave mode, 7-bit address

Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.

Note 1: When enabled, the SDA and SCL pins must be configured as inputs.

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ACKDT(1) ACKEN(2) RCEN(2) PEN(2) RSEN(2) SEN(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit

Unused in Master mode.

bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

1 = Acknowledge was not received from slave

0 = Acknowledge was received from slave

bit 5 ACKDT: Acknowledge Data bit (Master Receive mode only)(1)

1 = Not Acknowledge

0 = Acknowledge

bit 4 ACKEN: Acknowledge Sequence Enable bit(2)

1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically

cleared by hardware.

0 = Acknowledge sequence Idle

bit 3 RCEN: Receive Enable bit (Master Receive mode only)(2)

1 = Enables Receive mode for I2C™

0 = Receive Idle

bit 2 PEN: Stop Condition Enable bit(2)

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1 RSEN: Repeated Start Condition Enable bit(2)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0 SEN: Start Condition Enable bit(2)

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

2: If the I2C module is active, these bits may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

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R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

GCEN ACKSTAT ADMSK5 ADMSK4 ADMSK3 ADMSK2 ADMSK1 SEN(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GCEN: General Call Enable bit

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR

0 = General call address disabled

bit 6 ACKSTAT: Acknowledge Status bit

Unused in Slave mode.

bit 5-2 ADMSK<5:2>: Slave Address Mask Select bits

1 = Masking of corresponding bits of SSPADD is enabled

0 = Masking of corresponding bits of SSPADD is disabled

bit 1 ADMSK1: Slave Address Least Significant bit(s) Mask Select bit

In 7-Bit Addressing mode:

1 = Masking of SSPADD<1> only is enabled

0 = Masking of SSPADD<1> only is disabled

In 10-Bit Addressing mode:

1 = Masking of SSPADD<1:0> is enabled

0 = Masking of SSPADD<1:0> is disabled

bit 0 SEN: Stretch Enable bit(1)

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1: If the I2C™ module is active, this bit may not be set (no spooling) and the SSPBUF may not be written (or

writes to the SSPBUF are disabled).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 209

PIC18F87J72 FAMILY

18.4.2 OPERATION

The MSSP module functions are enabled by setting the

MSSP Enable bit, SSPEN (SSPCON1<5>).

The SSPCON1 register allows control of the I2C

operation. Four mode selection bits (SSPCON1<3:0>)

allow one of the following I2C modes to be selected:

•I

2C Master mode,

clock = (FOSC/4) x (SSPADD + 1)

•I

2C Slave mode (7-bit address)

•I

2C Slave mode (10-bit address)

•I

2C Slave mode (7-bit address) with Start and

Stop bit interrupts enabled

•I

2C Slave mode (10-bit address) with Start and

Stop bit interrupts enabled

•I

2C Firmware Controlled Master mode,

slave is Idle

Selection of any I2C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain,

provided these pins are programmed to inputs by

setting the appropriate TRISC or TRISD bits. To ensure

proper operation of the module, pull-up resistors must

be provided externally to the SCL and SDA pins.

18.4.3 SLAVE MODE

In Slave mode, the SCL and SDA pins must be

configured as inputs (TRISC<4:3> set). The MSSP

module will override the input state with the output data

when required (slave-transmitter).

The I2C Slave mode hardware will always generate an

interrupt on an exact address match. In addition,

address masking will also allow the hardware to gener-

ate an interrupt for more than one address (up to 31 in

7-bit addressing and up to 63 in 10-bit addressing).

Through the mode select bits, the user can also choose

to interrupt on Start and Stop bits.

When an address is matched, or the data transfer after

an address match is received, the hardware auto-

matically will generate the Acknowledge (ACK) pulse

and load the SSPBUF register with the received value

currently in the SSPSR register.

Any combination of the following conditions will cause

the MSSP module not to give this ACK pulse:

• The Buffer Full bit, BF (SSPSTAT<0>), was set

before the transfer was received.

• The overflow bit, SSPOV (SSPCON1<6>), was

set before the transfer was received.

In this case, the SSPSR register value is not loaded

into the SSPBUF, but bit, SSPIF, is set. The BF bit is

cleared by reading the SSPBUF register, while bit,

SSPOV, is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the

MSSP module, are shown in timing Parameter 100 and

Parameter 101.

18.4.3.1 Addressing

Once the MSSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition, the

8 bits are shifted into the SSPSR register. All incoming

bits are sampled with the rising edge of the clock (SCL)

line. The value of register, SSPSR<7:1>, is compared to

the value of the SSPADD register. The address is com-

pared on the falling edge of the eighth clock (SCL) pulse.

If the addresses match and the BF and SSPOV bits are

clear, the following events occur:

1. The SSPSR register value is loaded into the

SSPBUF register.

2. The Buffer Full bit, BF, is set.

3. An ACK pulse is generated.

4. The MSSP Interrupt Flag bit, SSPIF, is set (and

interrupt is generated, if enabled) on the falling

edge of the ninth SCL pulse.

In 10-Bit Addressing mode, two address bytes need to

be received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit, R/W (SSPSTAT<2>), must specify a write

so the slave device will receive the second address

byte. For a 10-bit address, the first byte would equal

‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the two

MSbs of the address. The sequence of events for 10-bit

addressing is as follows, with steps 7 through 9 for the

slave-transmitter:

1. Receive first (high) byte of address (SSPIF, BF

and UA bits (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears UA bit and releases the

SCL line).

3. Read the SSPBUF register (clears BF bit) and

clear flag bit, SSPIF.

4. Receive second (low) byte of address (SSPIF,

BF and UA bits are set).

5. Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear UA bit.

6. Read the SSPBUF register (clears BF bit) and

clear flag bit, SSPIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of address (SSPIF and

BF bits are set).

9. Read the SSPBUF register (clears BF bit) and

clear flag bit, SSPIF.

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18.4.3.2 Address Masking

Masking an address bit causes that bit to become a

“don’t care”. When one address bit is masked, two

addresses will be Acknowledged and cause an

interrupt. It is possible to mask more than one address

bit at a time, which makes it possible to Acknowledge

up to 31 addresses in 7-bit mode and up to

63 addresses in 10-bit mode (see Example 18-2).

The I2C Slave behaves the same way whether address

masking is used or not. However, when address

masking is used, the I2C slave can Acknowledge

multiple addresses and cause interrupts. When this

occurs, it is necessary to determine which address

caused the interrupt by checking SSPBUF.

In 7-Bit Addressing mode, Address Mask bits,

ADMSK<5:1> (SSPCON<5:1>), mask the correspond-

ing address bits in the SSPADD register. For any ADMSK

bits that are set (ADMSK<x> = 1), the corresponding

address bit is ignored (SSPADD<x> = x). For the module

to issue an address Acknowledge, it is sufficient to match

only on addresses that do not have an active address

mask.

In 10-Bit Addressing mode, ADMSK<5:2> bits mask

the corresponding address bits in the SSPADD regis-

ter. In addition, ADMSK1 simultaneously masks the two

LSbs of the address (SSPADD<1:0>). For any ADMSK

bits that are active (ADMSK<x> = 1), the correspond-

ing address bit is ignored (SSPADD<x> = x). Also note,

that although in 10-Bit Addressing mode, the upper

address bits reuse part of the SSPADD register bits; the

address mask bits do not interact with those bits. They

only affect the lower address bits.

EXAMPLE 18-2: ADDRESS MASKING EXAMPLES

Note 1: ADMSK1 masks the two Least Significant

bits of the address.

2: The two Most Significant bits of the

address are not affected by address

masking.

7-Bit Addressing:

SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)

ADMSK<5:1> = 00111

Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh

10-Bit Addressing:

SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are

not affected by masking)

ADMSK<5:1> = 00111

Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh

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18.4.3.3 Reception

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

the SSPBUF register and the SDA line is held low

(ACK).

When the address byte overflow condition exists, then

the no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit, BF (SSPSTAT<0>), is

set or bit, SSPOV (SSPCON1<6>), is set.

An MSSP interrupt is generated for each data transfer

byte. The interrupt flag bit, SSPIF, must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

If SEN is enabled (SSPCON2<0> = 1), SCK/SCL will

be held low (clock stretch) following each data

transfer. The clock must be released by setting bit,

CKP (SSPCON1<4>). See Section 18.4.4 “Clock

Stretching” for more details.

18.4.3.4 Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit and pin, RC3, is held low,

regardless of SEN (see Section 18.4.4 “Clock

Stretching” for more details). By stretching the clock,

the master will be unable to assert another clock pulse

until the slave is done preparing the transmit data. The

transmit data must be loaded into the SSPBUF register

which also loads the SSPSR register. Then, the RC3

pin should be enabled by setting bit, CKP

(SSPCON1<4>). The eight data bits are shifted out on

the falling edge of the SCL input. This ensures that the

SDA signal is valid during the SCL high time

(Figure 18-10).

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. If the SDA

line is high (not ACK), then the data transfer is

complete. In this case, when the ACK is latched by the

slave, the slave logic is reset and the slave monitors for

another occurrence of the Start bit. If the SDA line was

low (ACK), the next transmit data must be loaded into

the SSPBUF register. Again, pin, RC3, must be

enabled by setting bit, CKP.

An MSSP interrupt is generated for each data transfer

byte. The SSPIF bit must be cleared in software and

the SSPSTAT register is used to determine the status

of the byte. The SSPIF bit is set on the falling edge of

the ninth clock pulse.

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FIGURE 18-8: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S1234567891234567891 2345 789 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP

(CKP does not reset to ‘0’ when SEN = 0)

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FIGURE 18-9: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01011

(RECEPTION, 7-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S1 234567 89 12 34567 891 2345 7 89 P

A7 A6 A5 X A3 X X D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP

(CKP does not reset to ‘0’ when SEN = 0)

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A7.A6.A5.X.A3.X.X will be Acknowledged and cause an interrupt.

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FIGURE 18-10: I2C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESSING)

SDA

SCL

BF (SSPxSTAT<0>)

A6 A5 A4 A3 A2 A1 D6 D5 D4 D3 D2 D1 D0

1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9

SSPBUF is written in software

Cleared in software

Data in

sampled

ACK

Transmitting Data

R/W = 1

ACK

Receiving Address

A7 D7

9 1

D6 D5 D4 D3 D2 D1 D0

2 3 4 5 6 7 8 9

SSPBUF is written in software

Cleared in software

From SSPIF ISR

Transmitting Data

CKP

(SSPxCON1<4>)

ACK

CKP is set in software CKP is set in software

SCL held low

while CPU

responds to SSPIF

SSPIF (PIR1<3> or PIR3<7>)

From SSPIF ISR

Clear by reading

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FIGURE 18-11: I2C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7 D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR

Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

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FIGURE 18-12: I2C™ SLAVE MODE TIMING WITH SEN = 0 AND ADMSK<5:1> = 01001

(RECEPTION, 10-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9 A8 A7 A6 A5 X A3 A2 X X D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware

when SSPADD is updated

with low byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address

SSPBUF is written with

contents of SSPSR

Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

(CKP does not reset to ‘0’ when SEN = 0)

Clock is held low until

update of SSPADD has

taken place

Note 1: x = Don’t care (i.e., address bit can be either a ‘1’ or a ‘0’).

2: In this example, an address equal to A9.A8.A7.A6.A5.X.A3.A2.X.X will be Acknowledged and cause an interrupt.

3: Note that the Most Significant bits of the address are not affected by the bit masking.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 217

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FIGURE 18-13: I2C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S12345 6789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 11110 A8

R/W = 1

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Bus master

terminates

transfer

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address.

SSPBUF is written with

contents of SSPSR

Dummy read of SSPBUF

to clear BF flag

Receive First Byte of Address

12345 789

D7 D6 D5 D4 D3 D1

ACK

Transmitting Data Byte

Dummy read of SSPBUF

to clear BF flag

Cleared in software

Write of SSPBUF

initiates transmit

Cleared in software

Completion of

clears BF flag

CKP (SSPCON1<4>)

CKP is set in software

CKP is automatically cleared in hardware, holding SCL low

Clock is held low until

update of SSPADD has

taken place

data transmission

Clock is held low until

CKP is set to ‘1’

third address sequence

BF flag is clear

at the end of the

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18.4.4 CLOCK STRETCHING

Both 7-Bit and 10-Bit Slave modes implement

automatic clock stretching during a transmit sequence.

The SEN bit (SSPCON2<0>) allows clock stretching to

be enabled during receives. Setting SEN will cause

the SCL pin to be held low at the end of each data

receive sequence.

18.4.4.1 Clock Stretching for 7-Bit Slave

Receive Mode (SEN = 1)

In 7-Bit Slave Receive mode, on the falling edge of the

ninth clock at the end of the ACK sequence, if the BF

bit is set, the CKP bit in the SSPCON1 register is

automatically cleared, forcing the SCL output to be

held low. The CKP being cleared to ‘0’ will assert the

SCL line low. The CKP bit must be set in the user’s

ISR before reception is allowed to continue. By holding

the SCL line low, the user has time to service the ISR

and read the contents of the SSPBUF before the

master device can initiate another receive sequence.

This will prevent buffer overruns from occurring (see

Figure 18-15).

18.4.4.2 Clock Stretching for 10-Bit Slave

Receive Mode (SEN = 1)

In 10-Bit Slave Receive mode, during the address

sequence, clock stretching automatically takes place

but CKP is not cleared. During this time, if the UA bit is

set after the ninth clock, clock stretching is initiated.

The UA bit is set after receiving the upper byte of the

10-bit address and following the receive of the second

byte of the 10-bit address with the R/W bit cleared to

‘0’. The release of the clock line occurs upon updating

SSPADD. Clock stretching will occur on each data

receive sequence as described in 7-bit mode.

18.4.4.3 Clock Stretching for 7-Bit Slave

Transmit Mode

The 7-Bit Slave Transmit mode implements clock

stretching by clearing the CKP bit after the falling edge

of the ninth clock if the BF bit is clear. This occurs

regardless of the state of the SEN bit.

The user’s ISR must set the CKP bit before transmis-

sion is allowed to continue. By holding the SCL line

low, the user has time to service the ISR and load the

contents of the SSPBUF before the master device can

initiate another transmit sequence (see Figure 18-10).

18.4.4.4 Clock Stretching for 10-Bit Slave

Transmit Mode

In 10-Bit Slave Transmit mode, clock stretching is con-

trolled during the first two address sequences by the

state of the UA bit, just as it is in 10-Bit Slave Receive

mode. The first two addresses are followed by a third

address sequence which contains the high-order bits

of the 10-bit address and the R/W bit set to ‘1’. After

the third address sequence is performed, the UA bit is

not set, the module is now configured in Transmit

mode and clock stretching is controlled by the BF flag

as in 7-Bit Slave Transmit mode (see Figure 18-13).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the

ninth clock, thus clearing the BF bit, the

CKP bit will not be cleared and clock

stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit. The

user should be careful to clear the BF bit

in the ISR before the next receive

sequence in order to prevent an overflow

condition.

Note: If the user polls the UA bit and clears it by

updating the SSPADD register before the

falling edge of the ninth clock occurs and if

the user hasn’t cleared the BF bit by read-

ing the SSPBUF register before that time,

then the CKP bit will still NOT be asserted

low. Clock stretching on the basis of the

state of the BF bit only occurs during a

data sequence, not an address sequence.

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of

the ninth clock, the CKP bit will not be

cleared and clock stretching will not occur.

2: The CKP bit can be set in software

regardless of the state of the BF bit.

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18.4.4.5 Clock Synchronization and

the CKP bit

When the CKP bit is cleared, the SCL output is forced

to ‘0’. However, clearing the CKP bit will not assert the

SCL output low until the SCL output is already

sampled low. Therefore, the CKP bit will not assert the

SCL line until an external I2C master device has

already asserted the SCL line. The SCL output will

remain low until the CKP bit is set and all other

devices on the I2C bus have deasserted SCL. This

ensures that a write to the CKP bit will not violate the

minimum high time requirement for SCL (see

Figure 18-14).

FIGURE 18-14: CLOCK SYNCHRONIZATION TIMING

SDA

SCL

DX – 1DX

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SSPCON

CKP

Master device

deasserts clock

Master device

asserts clock

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FIGURE 18-15: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

S1 234 567 89 1 2345 67 89 1 23 45 7 89 P

A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D1 D0

ACK

Receiving Data

ACK

Receiving Data

R/W = 0

ACK

Receiving Address

Cleared in software

SSPBUF is read

Bus master

terminates

transfer

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

CKP

written

to ‘1’ in

If BF is cleared

prior to the falling

edge of the 9th clock,

CKP will not be reset

to ‘0’ and no clock

stretching will occur

software

Clock is held low until

CKP is set to ‘1’

Clock is not held low

because buffer full bit is

clear prior to falling edge

of 9th clock

Clock is not held low

because ACK =

BF is set after falling

edge of the 9th clock,

CKP is reset to ‘0’ and

clock stretching occurs

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FIGURE 18-16: I2C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESSING)

SDA

SCL

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

S123456789 123456789 12345 789 P

1 1 1 1 0 A9A8 A7 A6A5A4A3A2A1A0 D7D6D5D4D3 D1D0

Receive Data Byte

ACK

R/W = 0

ACK

Receive First Byte of Address

Cleared in software

Receive Second Byte of Address

Cleared by hardware when

SSPADD is updated with low

byte of address after falling edge

UA (SSPSTAT<1>)

Clock is held low until

update of SSPADD has

taken place

UA is set indicating that

the SSPADD needs to be

updated

UA is set indicating that

SSPADD needs to be

updated

Cleared by hardware when

SSPADD is updated with high

byte of address after falling edge

SSPBUF is written with

contents of SSPSR

Dummy read of SSPBUF

to clear BF flag

ACK

CKP

12345 789

D7 D6 D5 D4 D3 D1 D0

Receive Data Byte

Bus master

terminates

transfer

ACK

Cleared in software Cleared in software

SSPOV (SSPCON1<6>)

CKP written to

‘

’

Note: An update of the SSPADD register before the

falling edge of the ninth clock will have no effect

on UA and UA will remain set.

Note: An update of the SSPADD

edge of the ninth clock will

have no effect on UA and

UA will remain set.

in software

Clock is held low until

update of SSPADD has

taken place

of ninth clock

SSPOV is set

because SSPBUF is

still full. ACK is not sent.

Dummy read of SSPBUF

to clear BF flag

Clock is held low until

CKP is set to

‘

’

Clock is not held low

because ACK =

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18.4.5 GENERAL CALL ADDRESS

SUPPORT

The addressing procedure for the I2C bus is such that

the first byte after the Start condition usually

determines which device will be the slave addressed by

the master. The exception is the general call address

which can address all devices. When this address is

used, all devices should, in theory, respond with an

Acknowledge.

The general call address is one of eight addresses

reserved for specific purposes by the I2C protocol. It

consists of all ‘0’s with R/W = 0.

The general call address is recognized when the

General Call Enable bit, GCEN, is enabled

(SSPCON2<7> set). Following a Start bit detect, 8 bits

are shifted into the SSPSR and the address is

compared against the SSPADD. It is also compared to

the general call address and fixed in hardware.

If the general call address matches, the SSPSR is

transferred to the SSPBUF, the BF flag bit is set (eighth

bit), and on the falling edge of the ninth bit (ACK bit),

the SSPIF interrupt flag bit is set.

When the interrupt is serviced, the source for the

interrupt can be checked by reading the contents of the

SSPBUF. The value can be used to determine if the

address was device-specific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when the GCEN bit is set, while the slave is

configured in 10-Bit Addressing mode, then the second

half of the address is not necessary, the UA bit will not

be set and the slave will begin receiving data after the

Acknowledge (Figure 18-17).

FIGURE 18-17: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

(7 OR 10-BIT ADDRESSING MODE)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data ACK

123456789123456789

D7 D6 D5 D4 D3 D2 D1 D0

after ACK, set interrupt

‘0’

‘1’

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18.4.6 MASTER MODE

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. In Master mode, the SCL and SDA lines

are manipulated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop con-

ditions. The Stop (P) and Start (S) bits are cleared from

a Reset or when the MSSP module is disabled. Control

of the I2C bus may be taken when the P bit is set, or the

bus is Idle, with both the S and P bits clear.

In Firmware Controlled Master mode, user code

conducts all I2C bus operations based on Start and

Stop bit conditions.

Once Master mode is enabled, the user has six

options.

1. Assert a Start condition on SDA and SCL.

2. Assert a Repeated Start condition on SDA and

SCL.

3. Write to the SSPBUF register initiating

transmission of data/address.

4. Configure the I2C port to receive data.

5. Generate an Acknowledge condition at the end

of a received byte of data.

6. Generate a Stop condition on SDA and SCL.

The following events will cause the MSSP Interrupt

Flag bit, SSPIF, to be set (and MSSP interrupt, if

enabled):

• Start condition

• Stop condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 18-18: MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)

Note: The MSSP module, when configured in

I2C Master mode, does not allow queueing

of events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPBUF register to

initiate transmission before the Start con-

dition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Read Write

SSPSR

Start bit, Stop bit,

SSPBUF

Internal

Data Bus

Set/Reset S, P, WCOL (SSPSTAT, SSPCON1)

Shift

Clock

MSb LSb

SDA

Acknowledge

Generate

Stop bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

End of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Clock Cntl

Clock Arbitrate/WCOL Detect

(hold off clock source)

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM<3:0>

Start bit Detect

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DS39979A-page 224 Preliminary  2010 Microchip Technology Inc.

18.4.6.1 I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I2C bus will

not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted, 8 bits at a time. After each byte is transmit-

ted, an Acknowledge bit is received. Start and Stop

conditions are output to indicate the beginning and the

end of a serial transfer.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received 8 bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. Start and Stop conditions indicate the beginning

and end of transmission.

The Baud Rate Generator, used for the SPI mode

operation, is used to set the SCL clock frequency for

either 100 kHz, 400 kHz or 1 MHz I2C operation. See

Section 18.4.7 “Baud Rate” for more detail.

A typical transmit sequence would go as follows:

1. The user generates a Start condition by setting

the Start Enable bit, SEN (SSPCON2<0>).

2. SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

3. The user loads the SSPBUF with the slave

address to transmit.

4. Address is shifted out the SDA pin until all 8 bits

are transmitted.

5. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

6. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

7. The user loads the SSPBUF with eight bits of

data.

8. Data is shifted out the SDA pin until all 8 bits are

transmitted.

9. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

11. The user generates a Stop condition by setting

the Stop Enable bit, PEN (SSPCON2<2>).

12. Interrupt is generated once the Stop condition is

complete.

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18.4.7 BAUD RATE

In I2C Master mode, the Baud Rate Generator (BRG)

reload value is placed in the lower 7 bits of the

SSPADD register (Figure 18-19). When a write occurs

to SSPBUF, the Baud Rate Generator will automatically

begin counting. The BRG counts down to 0 and stops

until another reload has taken place. The BRG count is

decremented twice per instruction cycle (T

CY) on the

Q2 and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically.

Once the given operation is complete (i.e., transmis-

sion of the last data bit is followed by ACK), the internal

clock will automatically stop counting and the SCL pin

will remain in its last state.

Table 18-3 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPADD.

18.4.7.1 Baud Rate Generation in

Power-Managed Modes

When the device is operating in one of the

power-managed modes, the clock source to the BRG

may change frequency or even stop, depending on the

mode and clock source selected. Switching to a Run or

Idle mode from either the secondary clock or internal

oscillator is likely to change the clock rate to the BRG.

In Sleep mode, the BRG will not be clocked at all.

FIGURE 18-19: BAUD RATE GENERATOR BLOCK DIAGRAM

TABLE 18-3: I2C™ CLOCK RATE w/BRG

Note: A BRG value of 00h is not supported.

FCY FCY * 2 BRG Value FSCL

(2 Rollovers of BRG)

16 MHz 32 MHz 03h 1 MHz(1)

10 MHz 20 MHz 18h 400 kHz(2)

10 MHz 20 MHz 1Fh 312.5 kHz

10 MHz 20 MHz 63h 100 kHz

4 MHz 8 MHz 09h 400 kHz(2)

4 MHz 8 MHz 0Ch 308 kHz

4 MHz 8 MHz 27h 100 kHz

1 MHz 2 MHz 02h 333 kHz(2)

1 MHz 2 MHz 09h 100 kHz

Note 1: FOSC must be at least 16 MHz for I2C bus operation at this speed.

2: The I2C™ interface does not conform to the 400 kHz I2C specification (which applies to rates greater than

100 kHz) in all details, but may be used with care where higher rates are required by the application.

SSPM<3:0>

BRG Down Counter

CLKO FOSC/4

SSPADD<6:0>

SSPM<3:0>

SCL

Reload

Control

Reload

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18.4.7.2 Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 18-20).

FIGURE 18-20: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

SCL

SCL deasserted but slave holds

DX – 1DX

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h 02h 01h 00h (hold off) 03h 02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

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18.4.8 I2C MASTER MODE START

CONDITION TIMING

To initiate a Start condition, the user sets the Start

Enable bit, SEN (SSPCON2<0>). If the SDA and SCL

pins are sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and starts

its count. If SCL and SDA are both sampled high when

the Baud Rate Generator times out (TBRG), the SDA

pin is driven low. The action of the SDA being driven

low while SCL is high is the Start condition and causes

the S bit (SSPSTAT<3>) to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPADD<6:0> and resumes its count. When the Baud

Rate Generator times out (TBRG), the SEN bit

(SSPCON2<0>) will automatically be cleared by

hardware. The Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

18.4.8.1 WCOL Status Flag

If the user writes the SSPBUF when a Start sequence

is in progress, the WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 18-21: FIRST START BIT TIMING

Note: If, at the beginning of the Start condition,

the SDA and SCL pins are already

sampled low, or if during the Start condi-

tion, the SCL line is sampled low before

the SDA line is driven low, a bus collision

occurs. The Bus Collision Interrupt Flag,

BCLIF, is set, the Start condition is aborted

and the I2C module is reset into its Idle

state.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the Start

condition is complete.

SDA

SCL

TBRG

1st bit 2nd bit

TBRG

SDA = 1, At completion of Start bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

hardware clears SEN bit

TBRG

Write to SEN bit occurs here Set S bit (SSPSTAT<3>)

and sets SSPIF bit

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DS39979A-page 228 Preliminary  2010 Microchip Technology Inc.

18.4.9 I2C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I2C logic

module is in the Idle state. When the RSEN bit is set,

the SCL pin is asserted low. When the SCL pin is

sampled low, the Baud Rate Generator is loaded with

the contents of SSPADD<6:0> and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be deasserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPADD<6:0> and begins

counting. SDA and SCL must be sampled high for one

TBRG. This action is then followed by assertion of the

SDA pin (SDA = 0) for one TBRG while SCL is high.

Following this, the RSEN bit (SSPCON2<1>) will be

automatically cleared and the Baud Rate Generator will

not be reloaded, leaving the SDA pin held low. As soon

as a Start condition is detected on the SDA and SCL

pins, the S bit (SSPSTAT<3>) will be set. The SSPIF bit

will not be set until the Baud Rate Generator has timed

out.

Immediately following the SSPIF bit getting set, the user

may write the SSPBUF with the 7-bit address in 7-bit

mode or the default first address in 10-bit mode. After the

first eight bits are transmitted and an ACK is received,

the user may then transmit an additional eight bits of

address (10-bit mode) or eight bits of data (7-bit mode).

18.4.9.1 WCOL Status Flag

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, the WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 18-22: REPEATED START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low-to-high.

• SCL goes low before SDA is

asserted low. This may indicate that

another master is attempting to

transmit a data ‘1’.

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

SDA

SCL

Sr = Repeated Start

Write to SSPCON2

Write to SSPBUF occurs here

on falling edge of ninth clock,

end of XMIT

At completion of Start bit,

hardware clears RSEN bit

1st bit

S bit set by hardware

TBRG

SDA = 1,

SCL (no change)

SCL = 1

occurs here:

TBRG TBRG

and sets SSPIF

RSEN bit set by hardware

TBRG

 2010 Microchip Technology Inc. Preliminary DS39979A-page 229

PIC18F87J72 FAMILY

18.4.10 I2C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address, is accomplished by

simply writing a value to the SSPBUF register. This

action will set the Buffer Full bit, BF, and allow the Baud

Rate Generator to begin counting and start the next

transmission. Each bit of address/data will be shifted

out onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification

Parameter 106). SCL is held low for one Baud Rate

Generator rollover count (TBRG). Data should be valid

before SCL is released high (see data setup time

specification Parameter 107). When the SCL pin is

released high, it is held that way for TBRG. The data on

the SDA pin must remain stable for that duration and

some hold time after the next falling edge of SCL. After

the eighth bit is shifted out (the falling edge of the eighth

clock), the BF flag is cleared and the master releases

SDA. This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKDT bit on

the falling edge of the ninth clock. If the master receives

an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared; if not, the bit is set. After the ninth

clock, the SSPIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 18-23).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

deassert the SDA pin, allowing the slave to respond

with an Acknowledge. On the falling edge of the ninth

clock, the master will sample the SDA pin to see if the

address was recognized by a slave. The status of the

ACK bit is loaded into the ACKSTAT status bit

(SSPCON2<6>). Following the falling edge of the ninth

clock transmission of the address, the SSPIF is set, the

BF flag is cleared and the Baud Rate Generator is

turned off until another write to the SSPBUF takes

place, holding SCL low and allowing SDA to float.

18.4.10.1 BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set

when the CPU writes to SSPBUF and is cleared when

all 8 bits are shifted out.

18.4.10.2 WCOL Status Flag

If the user writes to the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur) after 2 TCY

after the SSPBUF write. If SSPBUF is rewritten within

2 TCY, the WCOL bit is set and SSPBUF is updated.

This may result in a corrupted transfer.

The user should verify that the WCOL is clear after

each write to SSPBUF to ensure the transfer is correct.

In all cases, WCOL must be cleared in software.

18.4.10.3 ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an Acknowledge

(ACK =0) and is set when the slave does not Acknowl-

edge (ACK = 1). A slave sends an Acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

18.4.11 I2C MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (SSPCON2<3>).

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes

(high-to-low/low-to-high) and data is shifted into the

SSPSR. After the falling edge of the eighth clock, the

receive enable flag is automatically cleared, the con-

tents of the SSPSR are loaded into the SSPBUF, the

BF flag bit is set, the SSPIF flag bit is set and the Baud

Rate Generator is suspended from counting, holding

SCL low. The MSSP is now in Idle state awaiting the

next command. When the buffer is read by the CPU,

the BF flag bit is automatically cleared. The user can

then send an Acknowledge bit at the end of reception

by setting the Acknowledge Sequence Enable bit,

ACKEN (SSPCON2<4>).

18.4.11.1 BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

18.4.11.2 SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits

are received into the SSPSR and the BF flag bit is

already set from a previous reception.

18.4.11.3 WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

Note: The MSSP module must be in an Idle state

before the RCEN bit is set or the RCEN bit

will be disregarded.

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DS39979A-page 230 Preliminary  2010 Microchip Technology Inc.

FIGURE 18-23: I2C™ MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESSING)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SEN

A7 A6 A5 A4 A3 A2 A1 ACK = 0D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting Data or Second Half

R/W = 0Transmit Address to Slave

123456789 123456789 P

Cleared in software service routine

SSPBUF is written in software

from MSSP interrupt

After Start condition, SEN cleared by hardware

SSPBUF written with 7-bit address and R/W

start transmit

SCL held low

while CPU

responds to SSPIF

SEN = 0

of 10-bit Address

Write SSPCON2<0> (SEN = 1),

Start condition begins From slave, clear ACKSTAT bit (SSPCON2<6>)

ACKSTAT in

SSPCON2 = 1

Cleared in software

SSPBUF written

PEN

R/W

Cleared in software

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FIGURE 18-24: I2C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESSING)

98765

D0D1D2D3D4D5D6D7

A7 A6 A5 A4 A3 A2 A1

SDA

SCL 1 23456 789 12345678 9 12 3 4

Bus master

terminates

transfer

ACK

Receiving Data from Slave

D0D1D2D3D4D5D6D7

ACK

R/W = 1

Transmit Address to Slave

SSPIF

ACK is not sent

Write to SSPCON2<0> (SEN = 1),

Write to SSPBUF occurs here, ACK from Slave

Master configured as a receiver

by programming SSPCON2<3> (RCEN = 1)

PEN bit = 1

written here

Data shifted in on falling edge of CLK

Cleared in software

start XMIT

SEN = 0

SSPOV

SDA = 0, SCL = 1

while CPU

(SSPSTAT<0>)

ACK

Cleared in software

Set SSPIF interrupt

at end of receive

Set P bit

(SSPSTAT<4>)

and SSPIF

ACK from Master,

Set SSPIF at end

Set SSPIF interrupt

at end of Acknowledge

sequence

Set SSPIF interrupt

at end of Acknowledge

sequence

of receive

Set ACKEN, start Acknowledge sequence,

SDA = ACKDT = 1

RCEN cleared

automatically

RCEN = 1, start

next receive

Write to SSPCON2<4>

to start Acknowledge sequence,

SDA = ACKDT (SSPCON2<5>) = 0

RCEN cleared

automatically

ACKEN

begin Start condition

Cleared in software

SDA = ACKDT = 0

Last bit is shifted into SSPSR and

contents are unloaded into SSPBUF

Cleared in

software

SSPOV is set because

SSPBUF is still full

responds to SSPIF

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18.4.12 ACKNOWLEDGE SEQUENCE

TIMING

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to gen-

erate an Acknowledge, then the ACKDT bit should be

cleared. If not, the user should set the ACKDT bit before

starting an Acknowledge sequence. The Baud Rate

Generator then counts for one rollover period (TBRG)

and the SCL pin is deasserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the Baud

Rate Generator counts for TBRG. The SCL pin is then

pulled low. Following this, the ACKEN bit is automatically

cleared, the Baud Rate Generator is turned off and the

MSSP module then goes into Idle mode (Figure 18-25).

18.4.12.1 WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

18.4.13 STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN (SSPCON2<2>). At the end of a

receive/transmit, the SCL line is held low after the fall-

ing edge of the ninth clock. When the PEN bit is set, the

master will assert the SDA line low. When the SDA line

is sampled low, the Baud Rate Generator is reloaded

and counts down to 0. When the Baud Rate Generator

times out, the SCL pin will be brought high and one

TBRG (Baud Rate Generator rollover count) later, the

SDA pin will be deasserted. When the SDA pin is

sampled high while SCL is high, the P bit

(SSPSTAT<4>) is set. A TBRG later, the PEN bit is

cleared and the SSPIF bit is set (Figure 18-26).

18.4.13.1 WCOL Status Flag

If the user writes the SSPBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 18-25: ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 18-26: STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: TBRG = one Baud Rate Generator period.

SDA

SCL

SSPIF set at

Acknowledge sequence starts here,

write to SSPCON2, ACKEN automatically cleared

Cleared in

TBRG TBRG

the end of receive

ACKEN = 1, ACKDT = 0

SSPIF

software SSPIF set at the end

of Acknowledge sequence

Cleared in

software

ACK

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2,

set PEN

Falling edge of

SCL = 1 for TBRG, followed by SDA = 1 for TBRG

9th clock

SCL brought high after TBRG

Note: TBRG = one Baud Rate Generator period.

TBRG TBRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

TBRG

to setup Stop condition

ACK

TBRG

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

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18.4.14 SLEEP OPERATION

While in Sleep mode, the I2C module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

18.4.15 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

18.4.16 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I2C bus may

be taken when the P bit (SSPSTAT<4>) is set, or the

bus is Idle, with both the S and P bits clear. When the

bus is busy, enabling the MSSP interrupt will generate

the interrupt when the Stop condition occurs.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed in

hardware with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

18.4.17 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA by letting SDA float high, and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCLIF, and reset the

I2C port to its Idle state (Figure 18-27).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPBUF can be written to. When the user services the

bus collision Interrupt Service Routine, and if the I2C bus

is free, the user can resume communication by asserting

a Start condition.

If a Start, Repeated Start, Stop or Acknowledge condition

was in progress when the bus collision occurred, the

condition is aborted, the SDA and SCL lines are

deasserted, and the respective control bits in the

SSPCON2 register, are cleared. When the user services

the bus collision Interrupt Service Routine and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the deter-

mination of when the bus is free. Control of the I2C bus

can be taken when the P bit is set in the SSPSTAT

cleared.

FIGURE 18-27: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,

data doesn’t match what is driven

Bus collision has occurred.

Set bus collision

interrupt (BCLIF)

by the master.

by master

Data changes

while SCL = 0

PIC18F87J72 FAMILY

DS39979A-page 234 Preliminary  2010 Microchip Technology Inc.

18.4.17.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 18-28).

b) SCL is sampled low before SDA is asserted low

(Figure 18-29).

During a Start condition, both the SDA and the SCL

pins are monitored.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted;

• the BCLIF flag is set; and

• the MSSP module is reset to its Idle state

(Figure 18-28).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

while SDA is high, a bus collision occurs, because it is

assumed that another master is attempting to drive a

data ‘1’ during the Start condition.

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 18-30). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to 0. If the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

FIGURE 18-28: BUS COLLISION DURING START CONDITION (SDA ONLY)

Note: The reason that bus collision is not a factor

during a Start condition is that no two bus

masters can assert a Start condition at the

exact same time. Therefore, one master

will always assert SDA before the other.

This condition does not cause a bus colli-

sion because the two masters must be

allowed to arbitrate the first address

following the Start condition. If the address

is the same, arbitration must be allowed to

continue into the data portion, Repeated

Start or Stop conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

MSSP module reset into Idle state.

SEN cleared automatically because of bus collision.

S bit and SSPIF set because

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLIF

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF are

cleared in software

SSPIF and BCLIF are

cleared in software

Set BCLIF,

Start condition. Set BCLIF.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 235

PIC18F87J72 FAMILY

FIGURE 18-29: BUS COLLISION DURING START CONDITION (SCL = 0)

FIGURE 18-30: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA

SCL

SEN bus collision occurs. Set BCLIF.

SCL = 0 before SDA = 0,

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupt cleared

in software

bus collision occurs. Set BCLIF.

SCL = 0 before BRG time-out,

‘0’‘0’

SDA

SCL

SEN

Set S

Less than TBRG TBRG

SDA = 0, SCL = 1

BCLIF

SSPIF

Interrupts cleared

in software

set SSPIF

SDA = 0, SCL = 1,

SCL pulled low after BRG

time-out

Set SSPIF

‘0’

SDA pulled low by other master.

Reset BRG and assert SDA.

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

PIC18F87J72 FAMILY

DS39979A-page 236 Preliminary  2010 Microchip Technology Inc.

18.4.17.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’.

When the user deasserts SDA and the pin is allowed to

float high, the BRG is loaded with SSPADD<6:0> and

counts down to ‘0’. The SCL pin is then deasserted and

when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, see

Figure 18-31). If SDA is sampled high, the BRG is

reloaded and begins counting. If SDA goes from

high-to-low before the BRG times out, no bus collision

occurs because no two masters can assert SDA at

exactly the same time.

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition

(see Figure 18-32).

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is complete.

FIGURE 18-31: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 18-32: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

SSPIF

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL.

Cleared in software

‘0’

SDA

SCL

BCLIF

RSEN

SSPIF

Interrupt cleared

in software

SCL goes low before SDA,

set BCLIF. Release SDA and SCL.

TBRG TBRG

‘0’

 2010 Microchip Technology Inc. Preliminary DS39979A-page 237

PIC18F87J72 FAMILY

18.4.17.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high.

The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPADD<6:0>

and counts down to 0. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 18-33). If the SCL pin is

sampled low before SDA is allowed to float high, a bus

collision occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 18-34).

FIGURE 18-33: BUS COLLISION DURING A STOP CONDITION (CASE 1)

FIGURE 18-34: BUS COLLISION DURING A STOP CONDITION (CASE 2)

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

SDA asserted low

SDA sampled

low after TBRG,

set BCLIF

‘0’

SDA

SCL

BCLIF

PEN

SSPIF

TBRG TBRG TBRG

Assert SDA SCL goes low before SDA goes high,

set BCLIF

‘0’

PIC18F87J72 FAMILY

DS39979A-page 238 Preliminary  2010 Microchip Technology Inc.

TABLE 18-4: REGISTERS ASSOCIATED WITH I2C™ OPERATION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

PIR2 OSCFIF CMIF ——BCLIFLVDIF TMR3IF —52

PIE2 OSCFIE CMIE ——BCLIELVDIE TMR3IE —52

IPR2 OSCFIP CMIP ——BCLIPLVDIP TMR3IP —52

TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 52

SSPBUF MSSP Receive Buffer/Transmit Register 50

SSPADD MSSP Address Register (I2C™ Slave mode),

MSSP Baud Rate Reload Register (I2C Master mode)

SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 50

SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 50

GCEN ACKSTAT ADMSK5(1) ADMSK4(1) ADMSK3(1) ADMSK2(1) ADMSK1(1) SEN

SSPSTAT SMP CKE D/A PSR/WUA BF 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.

Note 1: Alternate bit definitions for use in I2C Slave mode operations only.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 239

PIC18F87J72 FAMILY

19.0 ENHANCED UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

PIC18F87J72 family devices have three serial I/O

modules: the MSSP module, discussed in the previous

chapter and two Universal Synchronous Asynchronous

Receiver Transmitter (USART) modules. (Generically,

the USART is also known as a Serial Communications

Interface or SCI.) The USART can be configured as a

full-duplex asynchronous system that can communi-

cate with peripheral devices, such as CRT terminals

and personal computers. It can also be configured as a

half-duplex synchronous system that can communicate

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs, etc.

There are two distinct implementations of the USART

module in these devices: the Enhanced USART

(EUSART) discussed here and the Addressable

USART discussed in the next chapter. For this device

family, USART1 always refers to the EUSART, while

USART2 is always the AUSART.

The EUSART and AUSART modules implement the

same core features for serial communications; their

basic operation is essentially the same. The EUSART

module provides additional features, including Auto-

matic Baud Rate Detection and calibration, automatic

wake-up on Sync Break reception and 12-bit Break

character transmit. These features make it ideally

suited for use in Local Interconnect Network bus

(LIN/J2602 bus) systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full-duplex) with:

- Auto-wake-up on character reception

- Auto-baud calibration

- 12-bit Break character transmission

• Synchronous – Master (half-duplex) with

selectable clock polarity

• Synchronous – Slave (half-duplex) with selectable

clock polarity

The pins of the EUSART are multiplexed with the

functions of PORTC (RC6/TX1/CK1/SEG27 and

RC7/RX1/DT1/SEG28). In order to configure these

pins as an EUSART:

• SPEN bit (RCSTA1<7>) must be set (= 1)

• TRISC<7> bit must be set (= 1)

• TRISC<6> bit must be set (= 1)

The driver for the TX1 output pin can also be optionally

configured as an open-drain output. This feature allows

the voltage level on the pin to be pulled to a higher level

through an external pull-up resistor, and allows the out-

put to communicate with external circuits without the

need for additional level shifters.

The open-drain output option is controlled by the U1OD

bit (LATG<6>). Setting this bit configures the pin for

open-drain operation.

19.1 Control Registers

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control Register 1 (TXSTA1)

• Receive Status and Control Register 1 (RCSTA1)

• Baud Rate Control Register 1 (BAUDCON1)

The registers are described in Register 19-1,

Note: The EUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F87J72 FAMILY

DS39979A-page 240 Preliminary  2010 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-Bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit is enabled

0 = Transmit is disabled

bit 4 SYNC: EUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 SENDB: Send Break Character bit

Asynchronous mode:

1 = Send Sync Break on next transmission (cleared by hardware upon completion)

0 = Sync Break transmission completed

Synchronous mode:

Don’t care.

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode.

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR is empty

0 = TSR is full

bit 0 TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 241

PIC18F87J72 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port is enabled

0 = Serial port is disabled (held in Reset)

bit 6 RX9: 9-Bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2 FERR: Framing Error bit

1 = Framing error (can be cleared by reading the RCREG1 register and receiving the next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit, CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

PIC18F87J72 FAMILY

DS39979A-page 242 Preliminary  2010 Microchip Technology Inc.

R/W-0 R-1 R/W - 0 R/W-0 R/W-0 U-0 R/W-0 R/W-0

ABDOVF RCMT RXDTP TXCKP BRG16 — WUE ABDEN

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ABDOVF: Auto-Baud Acquisition Rollover Status bit

1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software)

0 = No BRG rollover has occurred

bit 6 RCMT: Receive Operation Idle Status bit

1 = Receive operation is Idle

0 = Receive operation is active

bit 5 RXDTP: Received Data Polarity Select bit (Asynchronous mode only)

1 = RXx data is inverted

0 = RXx data is not inverted

bit 4 TXCKP: Clock and Data Polarity Select bit

Asynchronous mode:

1 = Transmit idle state is low

0 = Transmit idle state is high

Synchronous mode:

1 = CKx clock idle state is high

0 = CKx clock idle state is low

bit 3 BRG16: 16-Bit Baud Rate Register Enable bit

1 = 16-bit Baud Rate Generator – SPBRGH1 and SPBRG1

0 = 8-bit Baud Rate Generator – SPBRG1 only (Compatible mode), SPBRGH1 value is ignored

bit 2 Unimplemented: Read as ‘0’

bit 1 WUE: Wake-up Enable bit

Asynchronous mode:

1 = EUSART will continue to sample the RX1 pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge

0 = RX1 pin is not monitored or a rising edge detected

Synchronous mode:

Unused in this mode.

bit 0 ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);

cleared in hardware upon completion.

0 = Baud rate measurement is disabled or completed

Synchronous mode:

Unused in this mode.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 243

PIC18F87J72 FAMILY

19.2 EUSART Baud Rate Generator

(BRG)

The BRG is a dedicated, 8-bit or 16-bit generator that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode; setting the BRG16 bit (BAUDCON1<3>)

selects 16-bit mode.

The SPBRGH1:SPBRG1 register pair controls the

period of a free-running timer. In Asynchronous mode,

BRGH (TXSTA1<2>) and BRG16 (BAUDCON1<3>) bits

also control the baud rate. In Synchronous mode, BRGH

is ignored. Table 19-1 shows the formula for computa-

tion of the baud rate for different EUSART modes that

only apply in Master mode (internally generated clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH1:SPBRG1 registers can

be calculated using the formulas in Table 19-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 19-1. Typical baud rates

and error values for the various Asynchronous modes

are shown in Table 19-2. It may be advantageous to use

the high baud rate (BRGH = 1) or the 16-bit BRG to

reduce the baud rate error, or achieve a slow baud rate

for a fast oscillator frequency.

Writing a new value to the SPBRGH1:SPBRG1 regis-

ters causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

SPBRGH1:SPBRG1 values of 0000h and 0001h are

not supported in Synchronous mode.

19.2.1 OPERATION IN POWER-MANAGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

different frequency. This may require an adjustment to

the value in the SPBRG1 register pair.

19.2.2 SAMPLING

The data on the RX1 pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present at the RX1 pin.

TABLE 19-1: BAUD RATE FORMULAS

EXAMPLE 19-1: CALCULATING BAUD RATE ERROR

TABLE 19-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Configuration Bits BRG/EUSART Mode Baud Rate Formula

SYNC BRG16 BRGH

000 8-bit/Asynchronous FOSC/[64 (n + 1)]

001 8-bit/Asynchronous FOSC/[16 (n + 1)]

010 16-bit/Asynchronous

011 16-bit/Asynchronous

FOSC/[4 (n + 1)]10x 8-bit/Synchronous

11x 16-bit/Synchronous

Legend: x = Don’t care, n = Value of SPBRGH1:SPBRG1 register pair

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values

on Page

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Desired Baud Rate = FOSC/(64 ([SPBRGH1:SPBRG1] + 1))

Solving for SPBRGH1:SPBRG1:

X = ((FOSC/Desired Baud Rate)/64) – 1

= ((16000000/9600)/64) – 1

= [25.042] = 25

Calculated Baud Rate=16000000/(64 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

= (9615 – 9600)/9600 = 0.16%

PIC18F87J72 FAMILY

DS39979A-page 244 Preliminary  2010 Microchip Technology Inc.

TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103

2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51

9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12

19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —

57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51

1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12

2.4 2.404 0.16 25 2.403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2————————————

2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207

9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 — — — — — — 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

 2010 Microchip Technology Inc. Preliminary DS39979A-page 245

PIC18F87J72 FAMILY

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 8332 0.300 0.02 4165 0.300 0.02 2082 0.300 -0.04 1665

1.2 1.200 0.02 2082 1.200 -0.03 1041 1.200 -0.03 520 1.201 -0.16 415

2.4 2.402 0.06 1040 2.399 -0.03 520 2.404 0.16 259 2.403 -0.16 207

9.6 9.615 0.16 259 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.04 832 0.300 -0.16 415 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.00 33332 0.300 0.00 16665 0.300 0.00 8332 0.300 -0.01 6665

1.2 1.200 0.00 8332 1.200 0.02 4165 1.200 0.02 2082 1.200 -0.04 1665

2.4 2.400 0.02 4165 2.400 0.02 2082 2.402 0.06 1040 2.400 -0.04 832

9.6 9.606 0.06 1040 9.596 -0.03 520 9.615 0.16 259 9.615 -0.16 207

19.2 19.193 -0.03 520 19.231 0.16 259 19.231 0.16 129 19.230 -0.16 103

57.6 57.803 0.35 172 57.471 -0.22 86 58.140 0.94 42 57.142 0.79 34

115.2 114.943 -0.22 86 116.279 0.94 42 113.636 -1.36 21 117.647 -2.12 16

BAUD

RATE

(K)

SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.01 3332 0.300 -0.04 1665 0.300 -0.04 832

1.2 1.200 0.04 832 1.201 -0.16 415 1.201 -0.16 207

2.4 2.404 0.16 415 2.403 -0.16 207 2.403 -0.16 103

9.6 9.615 0.16 103 9.615 -0.16 51 9.615 -0.16 25

19.2 19.231 0.16 51 19.230 -0.16 25 19.230 -0.16 12

57.6 58.824 2.12 16 55.555 3.55 8 — — —

115.2 111.111 -3.55 8 — — — — — —

TABLE 19-3: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)

PIC18F87J72 FAMILY

DS39979A-page 246 Preliminary  2010 Microchip Technology Inc.

19.2.3 AUTO-BAUD RATE DETECT

The Enhanced USART module supports the automatic

detection and calibration of baud rate. This feature is

active only in Asynchronous mode and while the WUE

bit is clear.

The automatic baud rate measurement sequence

(Figure 19-1) begins whenever a Start bit is received

and the ABDEN bit is set. The calculation is

self-averaging.

In the Auto-Baud Rate Detect (ABD) mode, the clock to

the BRG is reversed. Rather than the BRG clocking the

incoming RX1 signal, the RX1 signal is timing the BRG.

In ABD mode, the internal Baud Rate Generator is

used as a counter to time the bit period of the incoming

serial byte stream.

Once the ABDEN bit is set, the state machine will clear

the BRG and look for a Start bit. The Auto-Baud Rate

Detect must receive a byte with the value, 55h (ASCII

“U”, which is also the LIN/J2602 bus Sync character),

in order to calculate the proper bit rate. The measure-

ment is taken over both a low and a high bit time in

order to minimize any effects caused by asymmetry of

the incoming signal. After a Start bit, the SPBRG1

begins counting up, using the preselected clock source

on the first rising edge of RX1. After eight bits on the

RX1 pin or the fifth rising edge, an accumulated value

totalling the proper BRG period is left in the

SPBRGH1:SPBRG1 register pair. Once the 5th edge is

seen (this should correspond to the Stop bit), the

ABDEN bit is automatically cleared.

If a rollover of the BRG occurs (an overflow from FFFFh

to 0000h), the event is trapped by the ABDOVF status bit

(BAUDCON1<7>). It is set in hardware by BRG rollovers

and can be set or cleared by the user in software. ABD

mode remains active after rollover events and the

ABDEN bit remains set (Figure 19-2).

While calibrating the baud rate period, the BRG

registers are clocked at 1/8th the preconfigured clock

rate. Note that the BRG clock is configured by the

BRG16 and BRGH bits. The BRG16 bit

(BAUDCON1<3>) must be set to use the SPBRG1 and

SPBRGH1 registers as a 16-bit counter. This allows the

user to verify that no carry occurred for 8-bit modes by

checking for 00h in the SPBRGH1 register. Refer to

Table 19-4 for counter clock rates to the BRG.

While the ABD sequence takes place, the EUSART

state machine is held in Idle. The RC1IF interrupt is set

once the fifth rising edge on RX1 is detected. The value

in the RCREG1 needs to be read to clear the RC1IF

interrupt. The contents of RCREG1 should be

discarded.

TABLE 19-4: BRG COUNTER CLOCK

RATES

19.2.3.1 ABD and EUSART Transmission

Since the BRG clock is reversed during ABD acquisi-

tion, the EUSART transmitter cannot be used during

ABD. This means that whenever the ABDEN bit is set,

TXREG1 cannot be written to. Users should also

ensure that ABDEN does not become set during a

transmit sequence. Failing to do this may result in

unpredictable EUSART operation.

Note 1: If the WUE bit is set with the ABDEN bit,

Auto-Baud Rate Detection will occur on

the byte following the Break character.

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible

due to bit error rates. Overall system

timing and communication baud rates

must be taken into consideration when

using the Auto-Baud Rate Detection

feature.

BRG16 BRGH BRG Counter Clock

00 FOSC/512

01 FOSC/128

10 FOSC/128

11 FOSC/32

Note: During the ABD sequence, SPBRG1 and

SPBRGH1 are both used as a 16-bit

counter, independent of the BRG16 setting.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 247

PIC18F87J72 FAMILY

FIGURE 19-1: AUTOMATIC BAUD RATE CALCULATION

FIGURE 19-2: BRG OVERFLOW SEQUENCE

BRG Value

RX1 Pin

ABDEN bit

RC1IF bit

bit 0 bit 1

(Interrupt)

Read

RCREG1

BRG Clock

Start

Auto-Cleared

Set by User

XXXXh 0000h

Edge #1

bit 2 bit 3

Edge #2

bit 4 bit 5

Edge #3

bit 6 bit 7

Edge #4

Stop bit

Edge #5

001Ch

Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.

SPBRG1 XXXXh 1Ch

SPBRGH1 XXXXh 00h

Start bit 0

XXXXh 0000h 0000h

FFFFh

BRG Clock

ABDEN bit

RX1 Pin

ABDOVF bit

BRG Value

PIC18F87J72 FAMILY

DS39979A-page 248 Preliminary  2010 Microchip Technology Inc.

19.3 EUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA1<4>). In this mode, the

EUSART uses standard Non-Return-to-Zero (NRZ) for-

mat (one Start bit, eight or nine data bits and one Stop

bit). The most common data format is 8 bits. An on-chip

dedicated 8-bit/16-bit Baud Rate Generator can be

used to derive standard baud rate frequencies from the

oscillator.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but use the same data format and baud

rate. The Baud Rate Generator produces a clock, either

x16 or x64 of the bit shift rate, depending on the BRGH

and BRG16 bits (TXSTA1<2> and BAUDCON1<3>).

Parity is not supported by the hardware but can be

implemented in software and stored as the 9th data bit.

When operating in Asynchronous mode, the EUSART

module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

• Auto-Wake-up on Sync Break Character

• 12-Bit Break Character Transmit

• Auto-Baud Rate Detection

19.3.1 EUSART ASYNCHRONOUS

TRANSMITTER

The EUSART transmitter block diagram is shown in

Figure 19-3. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG1. The TXREG1 register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG1 register (if available).

Once the TXREG1 register transfers the data to the

TSR register (occurs in one T

CY), the TXREG1 register

is empty and the TX1IF flag bit (PIR1<4>) is set. This

interrupt can be enabled or disabled by setting or clear-

ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF

will be set regardless of the state of TX1IE; it cannot be

cleared in software. TX1IF is also not cleared immedi-

ately upon loading TXREG1, but becomes valid in the

second instruction cycle following the load instruction.

Polling TX1IF immediately following a load of TXREG1

will return invalid results.

While TX1IF indicates the status of the TXREG1

status of the TSR register. TRMT is a read-only bit

which is set when the TSR register is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

To set up an Asynchronous Transmission:

1. Initialize the SPBRGH1:SPBRG1 registers for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, TX1IE.

4. If 9-bit transmission is desired, set transmit bit,

TX9; can be used as address/data bit.

5. Enable the transmission by setting bit, TXEN,

which will also set bit, TX1IF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Load data to the TXREG1 register (starts

transmission).

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 19-3: EUSART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit, TX1IF, is set when enable bit,

TXEN, is set.

TX1IF

TX1IE

Interrupt

TXEN Baud Rate CLK

SPBRG1

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG1 Register

TSR Register

(8) 0

TX9

TRMT SPEN

TX1 Pin

Pin Buffer

and Control



SPBRGH1

BRG16

 2010 Microchip Technology Inc. Preliminary DS39979A-page 249

PIC18F87J72 FAMILY

FIGURE 19-4: ASYNCHRONOUS TRANSMISSION

FIGURE 19-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

TABLE 19-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

TXREG1 EUSART Transmit Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG1

BRG Output

(Shift Clock)

TX1 (pin)

TX1IF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

Word 1

Stop bit

Transmit Shift Reg.

Write to TXREG1

BRG Output

(Shift Clock)

TX1 (pin)

TX1IF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

Start bit

PIC18F87J72 FAMILY

DS39979A-page 250 Preliminary  2010 Microchip Technology Inc.

19.3.2 EUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 19-6.

The data is received on the RX1 pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter operating at x16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

To set up an Asynchronous Reception:

1. Initialize the SPBRGH1:SPBRG1 registers for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, RC1IE.

4. If 9-bit reception is desired, set bit, RX9.

5. Enable the reception by setting bit, CREN.

6. Flag bit, RC1IF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RC1IE, was set.

7. Read the RCSTA1 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG1 register.

9. If any error occurred, clear the error by clearing

enable bit, CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

19.3.3 SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRGH1:SPBRG1 registers for

the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RC1IP

bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

7. The RC1IF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RC1IE and GIE bits are set.

8. Read the RCSTA1 register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

9. Read RCREG1 to determine if the device is

being addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 19-6: EUSART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

Baud Rate Generator

RX1

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG1 Register

FIFO

Interrupt RC1IF

RC1IE

Data Bus

 64

 16

Stop Start

(8) 7 1 0

RX9



SPBRG1SPBRGH1

BRG16

 4

 2010 Microchip Technology Inc. Preliminary DS39979A-page 251

PIC18F87J72 FAMILY

FIGURE 19-7: ASYNCHRONOUS RECEPTION

TABLE 19-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

RCREG1 EUSART Receive Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 — WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 51

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX1 (pin)

Rcv Buffer Reg

Rcv Shift Reg

Read Rcv

Buffer Reg

RCREG1

RC1IF

(Interrupt Flag)

OERR bit

CREN bit

Word 1

RCREG1

Word 2

RCREG1

Stop

bit

Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word

causing the OERR (Overrun) bit to be set.

PIC18F87J72 FAMILY

DS39979A-page 252 Preliminary  2010 Microchip Technology Inc.

19.3.4 AUTO-WAKE-UP ON SYNC BREAK

CHARACTER

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper byte reception cannot be per-

formed. The auto-wake-up feature allows the controller

to wake-up, due to activity on the RX1/DT1 line, while

the EUSART is operating in Asynchronous mode.

The auto-wake-up feature is enabled by setting the

WUE bit (BAUDCON<1>). Once set, the typical receive

sequence on RX1/DT1 is disabled and the EUSART

remains in an Idle state, monitoring for a wake-up event

independent of the CPU mode. A wake-up event

consists of a high-to-low transition on the RX1/DT1

line. (This coincides with the start of a Sync Break or a

Wake-up Signal character for the LIN/J2602 protocol.)

Following a wake-up event, the module generates an

RC1IF interrupt. The interrupt is generated synchro-

nously to the Q clocks in normal operating modes

(Figure 19-8) and asynchronously, if the device is in

Sleep mode (Figure 19-9). The interrupt condition is

cleared by reading the RCREG1 register.

The WUE bit is automatically cleared once a low-to-high

transition is observed on the RX1 line following the

wake-up event. At this point, the EUSART module is in

Idle mode and returns to normal operation. This signals

to the user that the Sync Break event is over.

19.3.4.1 Special Considerations Using

Auto-Wake-up

Since auto-wake-up functions by sensing rising edge

transitions on RX1/DT1, information with any state

changes before the Stop bit may signal a false

End-of-Character (EOC and cause data or framing

errors. Therefore, to work properly, the initial character

in the transmission must be all ‘0’s. This can be 00h

(8 bits) for standard RS-232 devices, or 000h (12 bits)

for LIN/J2602 bus.

Oscillator start-up time must also be considered,

especially in applications using oscillators with longer

start-up intervals (i.e., XT or HS mode). The Sync

Break (or Wake-up Signal) character must be of

sufficient length and be followed by a sufficient interval

to allow enough time for the selected oscillator to start

and provide proper initialization of the EUSART.

19.3.4.2 Special Considerations Using

the WUE Bit

The timing of WUE and RC1IF events may cause some

confusion when it comes to determining the validity of

received data. As noted, setting the WUE bit places the

EUSART in an Idle mode. The wake-up event causes

a receive interrupt by setting the RC1IF bit. The WUE

bit is cleared after this when a rising edge is seen on

RX1/DT1. The interrupt condition is then cleared by

reading the RCREG1 register. Ordinarily, the data in

RCREG1 will be dummy data and should be discarded.

The fact that the WUE bit has been cleared (or is still

set) and the RC1IF flag is set should not be used as an

indicator of the integrity of the data in RCREG1. Users

should consider implementing a parallel method in

firmware to verify received data integrity.

To assure that no actual data is lost, check the RCMT

bit to verify that a receive operation is not in process. If

a receive operation is not occurring, the WUE bit may

then be set just prior to entering the Sleep mode.

FIGURE 19-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION

FIGURE 19-9: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(1)

RX1/DT1 Line

RC1IF

Cleared due to user read of RCREG1

Note 1: The EUSART remains in Idle while the WUE bit is set.

Bit set by user Auto-Cleared

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

WUE bit(2)

RX1/DT1 Line

RC1IF

Cleared due to user read of RCREG1

SLEEP Command Executed

Note 1: If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur while the stposc signal is still active.

This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

Sleep Ends

Auto-Cleared

Note 1

Bit set by user

 2010 Microchip Technology Inc. Preliminary DS39979A-page 253

PIC18F87J72 FAMILY

19.3.5 BREAK CHARACTER SEQUENCE

The Enhanced USART module has the capability of

sending the special Break character sequences that are

required by the LIN/J2602 bus standard. The Break

character transmit consists of a Start bit, followed by

twelve ‘0’ bits and a Stop bit. The Frame Break character

is sent whenever the SENDB and TXEN bits

(TXSTA<3> and TXSTA<5>) are set while the Transmit

Shift register is loaded with data. Note that the value of

data written to TXREG1 will be ignored and all ‘0’s will be

transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN/J2602 specification).

Note that the data value written to the TXREG1 for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 19-10 for the timing of the Break

character sequence.

19.3.5.1 Break and Sync Transmit Sequence

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte. This sequence is typical of a LIN/J2602 bus

master.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to set up the

Break character.

3. Load the TXREG1 with a dummy character to

initiate transmission (the value is ignored).

4. Write ‘55h’ to TXREG1 to load the Sync

character into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode.

When the TXREG1 becomes empty, as indicated by the

TX1IF, the next data byte can be written to TXREG1.

19.3.6 RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a frequency of 9/13 the typical speed. This allows for

the Stop bit transition to be at the correct sampling

location (13 bits for Break versus Start bit and 8 data

bits for typical data).

The second method uses the auto-wake-up feature

described in Section 19.3.4 “Auto-Wake-up On Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on

RX1/DT1, cause an RC1IF interrupt and receive the

next data byte followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

once the TX1IF interrupt is observed.

FIGURE 19-10: SEND BREAK CHARACTER SEQUENCE

Write to TXREG1

BRG Output

(Shift Clock)

Start bit bit 0 bit 1 bit 11 Stop bit

Break

TX1IF bit

(Transmit Buffer

Reg. Empty Flag)

TX1 (pin)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(Transmit Shift

Reg. Empty Flag)

SENDB sampled here Auto-Cleared

Dummy Write

PIC18F87J72 FAMILY

DS39979A-page 254 Preliminary  2010 Microchip Technology Inc.

19.4 EUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit,

SYNC (TXSTA<4>). In addition, enable bit, SPEN

(RCSTA1<7>), is set in order to configure the TX1 and

RX1 pins to CK1 (clock) and DT1 (data) lines,

respectively.

The Master mode indicates that the processor trans-

mits the master clock on the CK1 line. Clock polarity is

selected with the TXCKP bit (BAUDCON<4>). Setting

TXCKP sets the Idle state on CK1 as high, while clear-

ing the bit sets the Idle state as low. This option is

provided to support Microwire devices with this module.

19.4.1 EUSART SYNCHRONOUS MASTER

TRANSMISSION

The EUSART transmitter block diagram is shown in

Figure 19-3. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG1. The TXREG1 register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG1 (if available).

Once the TXREG1 register transfers the data to the

TSR register (occurs in one TCYCLE), the TXREG1 is

empty and the TX1IF flag bit (PIR1<4>) is set. The

interrupt can be enabled or disabled by setting or clear-

ing the interrupt enable bit, TX1IE (PIE1<4>). TX1IF is

set regardless of the state of enable bit, TX1IE; it can-

not be cleared in software. It will reset only when new

data is loaded into the TXREG1 register.

While flag bit, TX1IF, indicates the status of the TXREG1

status of the TSR register. TRMT is a read-only bit which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user.

To set up a Synchronous Master Transmission:

1. Initialize the SPBRGH1:SPBRG1 registers for

the appropriate baud rate. Set or clear the

BRG16 bit, as required, to achieve the desired

baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit, TX1IE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting bit, TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the

TXREG1 register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 19-11: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX1/DT1/SEG28

Write to

TXREG1 Reg

TX1IF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG1 = 0; continuous transmission of two 8-bit words.

RC6/TX1/CK1/SEG27 pin

(TXCKP = 0)

(TXCKP = 1)

RC6/TX1/CK1/SEG27 pin

 2010 Microchip Technology Inc. Preliminary DS39979A-page 255

PIC18F87J72 FAMILY

FIGURE 19-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 19-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

TXREG1 EUSART Transmit Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

RC7/RX1/DT1/SEG28 Pin

RC6/TX1/CK1/SEG27 Pin

Write to

TXREG1 Reg

TX1IF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

PIC18F87J72 FAMILY

DS39979A-page 256 Preliminary  2010 Microchip Technology Inc.

19.4.2 EUSART SYNCHRONOUS

MASTER RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA1<5>), or the Continuous Receive

Enable bit, CREN (RCSTA1<4>). Data is sampled on

the RX1 pin on the falling edge of the clock.

If enable bit, SREN, is set, only a single word is

received. If enable bit, CREN, is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

To set up a Synchronous Master Reception:

1. Initialize the SPBRGH1:SPBRG1 registers for the

appropriate baud rate. Set or clear the BRG16 bit,

as required, to achieve the desired baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. Ensure bits, CREN and SREN, are clear.

4. If interrupts are desired, set enable bit, RC1IE.

5. If 9-bit reception is desired, set bit, RX9.

6. If a single reception is required, set bit, SREN.

For continuous reception, set bit, CREN.

7. Interrupt flag bit, RC1IF, will be set when recep-

tion is complete and an interrupt will be generated

if the enable bit, RC1IE, was set.

8. Read the RCSTA1 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG1 register.

10. If any error occurred, clear the error by clearing

bit, CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 19-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 19-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

RCREG1 EUSART Receive Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

CREN bit

RC7/RX1/DT1/

RC6/TX1/CK1/SEG27

Write to

SREN bit

RC1IF bit

(Interrupt)

Read

RCREG1

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘

’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘

’

Q1 Q2 Q3 Q4

Note: Timing diagram demonstrates Sync Master mode with bit, SREN = 1, and bit, BRGH = 0.

RC6/TX1/CK1/SEG27

SEG28 pin

pin (TXCKP = 0)

pin (TXCKP = 1)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 257

PIC18F87J72 FAMILY

19.5 EUSART Synchronous Slave Mode

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA<7>). This mode differs from the

Synchronous Master mode in that the shift clock is

supplied externally at the CK1 pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in any

low-power mode.

19.5.1 EUSART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical except in the case of Sleep mode.

If two words are written to the TXREG1 and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in the TXREG1

c) Flag bit, TX1IF, will not be set.

d) When the first word has been shifted out of TSR,

the TXREG1 register will transfer the second

word to the TSR and flag bit, TX1IF, will now be

set.

e) If enable bit, TX1IE, is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. Clear bits, CREN and SREN.

3. If interrupts are desired, set enable bit, TX1IE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting enable bit,

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the

TXREG1 register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 19-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

TXREG1 EUSART Transmit Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F87J72 FAMILY

DS39979A-page 258 Preliminary  2010 Microchip Technology Inc.

19.5.2 EUSART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical except in the case of Sleep or any

Idle mode, and bit, SREN, which is a “don’t care” in

Slave mode.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG1 register; if the RC1IE enable bit is set, the

interrupt generated will wake the chip from the

low-power mode. If the global interrupt is enabled, the

program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. If interrupts are desired, set enable bit, RC1IE.

3. If 9-bit reception is desired, set bit, RX9.

4. To enable reception, set enable bit, CREN.

5. Flag bit, RC1IF, will be set when reception is

complete. An interrupt will be generated if

enable bit, RC1IE, was set.

6. Read the RCSTA1 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG1 register.

8. If any error occurred, clear the error by clearing

bit, CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 19-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIF RC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIE RC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIP RC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 51

RCREG1 EUSART Receive Register 51

TXSTA1 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 51

BAUDCON1 ABDOVF RCMT RXDTP TXCKP BRG16 —WUE ABDEN 53

SPBRGH1 EUSART Baud Rate Generator Register High Byte 53

SPBRG1 EUSART Baud Rate Generator Register Low Byte 51

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 259

PIC18F87J72 FAMILY

20.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (AUSART)

The Addressable Universal Synchronous Asynchro-

nous Receiver Transmitter (AUSART) module is very

similar in function to the Enhanced USART module,

discussed in the previous chapter. It is provided as an

additional channel for serial communication with

external devices, for those situations that do not require

auto-baud detection or LIN/J2602 bus support.

The AUSART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous – Master (half-duplex)

• Synchronous – Slave (half-duplex)

The pins of the AUSART module are multiplexed with

the functions of PORTG (RG1/TX2/CK2 and

RG2/RX2/DT2/VLCAP1, respectively). In order to

configure these pins as an AUSART:

• PEN bit (RCSTA2<7>) must be set (= 1)

• TXEN bit (TXSTA2<5>) must also be set (= 1) to

configure TX2/CK2 to transmit

• TRISG<2> bit must be set (= 1)

• TRISG<1> bit must be cleared (= 0) for

Asynchronous and Synchronous Master modes

• TRISG<1> bit must be set (= 1) for Synchronous

Slave mode

The driver for the TX2 output pin can also be optionally

configured as an open-drain output. This feature allows

the voltage level on the pin to be pulled to a higher level

through an external pull-up resistor and allows the

output to communicate with external circuits without the

need for additional level shifters.

The open-drain output option is controlled by the U2OD

bit (LATG<7>). Setting the bit configures the pin for

open-drain operation.

20.1 Control Registers

The operation of the Addressable USART module is

controlled through two registers: TXSTA2 and

RXSTA2. These are detailed in Register 20-1 and

Note: The AUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F87J72 FAMILY

DS39979A-page 260 Preliminary  2010 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care.

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-Bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit(1)

1 = Transmit enabled

0 = Transmit disabled

bit 4 SYNC: AUSART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 Unimplemented: Read as ‘0’

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode.

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 261

PIC18F87J72 FAMILY

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RX2/DT2 and TX2/CK2 pins as serial port pins; TXEN must also

be set to configure TX2/CK2 to transmit)

0 = Serial port disabled (held in Reset)

bit 6 RX9: 9-Bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care.

Synchronous mode – Master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave:

Don’t care.

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables receiver

0 = Disables receiver

Synchronous mode:

1 = Enables continuous receive until enable bit, CREN, is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 9-bit (RX9 = 0):

Don’t care.

bit 2 FERR: Framing Error bit

1 = Framing error (can be cleared by reading RCREG2 register and receiving next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

This can be an address/data bit or a parity bit and must be calculated by user firmware.

PIC18F87J72 FAMILY

DS39979A-page 262 Preliminary  2010 Microchip Technology Inc.

20.2 AUSART Baud Rate Generator

(BRG)

The BRG is a dedicated, 8-bit generator that supports

both the Asynchronous and Synchronous modes of the

AUSART.

The SPBRG2 register controls the period of a

free-running timer. In Asynchronous mode, the BRGH

(TXSTA<2>) bit also controls the baud rate. In

Synchronous mode, BRGH is ignored. Table 20-1

shows the formula for computation of the baud rate for

different AUSART modes, which only apply in Master

mode (internally generated clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG2 register can be calculated

using the formulas in Table 20-1. From this, the error in

baud rate can be determined. An example calculation is

shown in Example 20-1. Typical baud rates and error

values for the various Asynchronous modes are shown

in Table 20-2. It may be advantageous to use the high

baud rate (BRGH = 1) to reduce the baud rate error, or

achieve a slow baud rate for a fast oscillator frequency.

Writing a new value to the SPBRG2 register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before outputting

the new baud rate.

20.2.1 OPERATION IN POWER-MANAGED

MODES

The device clock is used to generate the desired baud

rate. When one of the power-managed modes is

entered, the new clock source may be operating at a

different frequency. This may require an adjustment to

the value in the SPBRG2 register.

20.2.2 SAMPLING

The data on the RX2 pin is sampled three times by a

majority detect circuit to determine if a high or a low

level is present on the RX2 pin.

TABLE 20-1: BAUD RATE FORMULAS

EXAMPLE 20-1: CALCULATING BAUD RATE ERROR

TABLE 20-2: REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR

Configuration Bits

BRG/AUSART Mode Baud Rate Formula

SYNC BRGH

00 Asynchronous FOSC/[64 (n + 1)]

01 Asynchronous FOSC/[16 (n + 1)]

1x Synchronous FOSC/[4 (n + 1)]

Legend: x = Don’t care, n = Value of SPBRG2 register

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values on

Page

TXSTA2 CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 54

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

Legend: Shaded cells are not used by the BRG.

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, BRGH = 0:

Desired Baud Rate = FOSC/(64 ([SPBRG2] + 1))

Solving for SPBRG2:

X = ((FOSC/Desired Baud Rate)/64) – 1

= ((16000000/9600)/64) – 1

= [25.042] = 25

Calculated Baud Rate=16000000/(64 (25 + 1))

= 9615

Error = (Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

= (9615 – 9600)/9600 = 0.16%

 2010 Microchip Technology Inc. Preliminary DS39979A-page 263

PIC18F87J72 FAMILY

TABLE 20-3: BAUD RATES FOR ASYNCHRONOUS MODES

BRGH = 0

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

BAUD

RATE

(K)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2 — — — 1.221 1.73 255 1.202 0.16 129 1.201 -0.16 103

2.4 2.441 1.73 255 2.404 0.16 129 2.404 0.16 64 2.403 -0.16 51

9.6 9.615 0.16 64 9.766 1.73 31 9.766 1.73 15 9.615 -0.16 12

19.2 19.531 1.73 31 19.531 1.73 15 19.531 1.73 7 — — —

57.6 56.818 -1.36 10 62.500 8.51 4 52.083 -9.58 2 — — —

115.2 125.000 8.51 4 104.167 -9.58 2 78.125 -32.18 1 — — —

BRGH = 0

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

BAUD

RATE

(K)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 0.300 0.16 207 0.300 -0.16 103 0.300 -0.16 51

1.2 1.202 0.16 51 1.201 -0.16 25 1.201 -0.16 12

2.4 2.404 0.16 25 2.403 -0.16 12 — — —

9.6 8.929 -6.99 6 — — — — — —

19.2 20.833 8.51 2 — — — — — —

57.6 62.500 8.51 0 — — — — — —

115.2 62.500 -45.75 0 — — — — — —

BAUD

RATE

(K)

BRGH = 1

FOSC = 40.000 MHz FOSC = 20.000 MHz FOSC = 10.000 MHz FOSC = 8.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3————————————

1.2————————————

2.4 — — — — — — 2.441 1.73 255 2.403 -0.16 207

9.6 9.766 1.73 255 9.615 0.16 129 9.615 0.16 64 9.615 -0.16 51

19.2 19.231 0.16 129 19.231 0.16 64 19.531 1.73 31 19.230 -0.16 25

57.6 58.140 0.94 42 56.818 -1.36 21 56.818 -1.36 10 55.555 3.55 8

115.2 113.636 -1.36 21 113.636 -1.36 10 125.000 8.51 4 — — —

BAUD

RATE

(K)

BRGH = 1

FOSC = 4.000 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

Actual

Rate

(K)

Error

SPBRG

value

(decimal)

0.3 — — — — — — 0.300 -0.16 207

1.2 1.202 0.16 207 1.201 -0.16 103 1.201 -0.16 51

2.4 2.404 0.16 103 2.403 -0.16 51 2.403 -0.16 25

9.6 9.615 0.16 25 9.615 -0.16 12 — — —

19.2 19.231 0.16 12 — — — — — —

57.6 62.500 8.51 3 — — — — — —

115.2 125.000 8.51 1 — — — — — —

PIC18F87J72 FAMILY

DS39979A-page 264 Preliminary  2010 Microchip Technology Inc.

20.3 AUSART Asynchronous Mode

The Asynchronous mode of operation is selected by

clearing the SYNC bit (TXSTA2<4>). In this mode, the

AUSART uses standard Non-Return-to-Zero (NRZ)

format (one Start bit, eight or nine data bits and one

Stop bit). The most common data format is 8 bits. An

on-chip, dedicated, 8-bit Baud Rate Generator can be

used to derive standard baud rate frequencies from the

oscillator.

The AUSART transmits and receives the LSb first. The

AUSART’s transmitter and receiver are functionally

independent but use the same data format and baud

rate. The Baud Rate Generator produces a clock,

either x16 or x64 of the bit shift rate, depending on the

BRGH bit (TXSTA2<2>). Parity is not supported by the

hardware but can be implemented in software and

stored as the 9th data bit.

When operating in Asynchronous mode, the AUSART

module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

20.3.1 AUSART ASYNCHRONOUS

TRANSMITTER

The AUSART transmitter block diagram is shown in

Figure 20-1. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG2. The TXREG2 register is loaded with data in

software. The TSR register is not loaded until the Stop

bit has been transmitted from the previous load. As

soon as the Stop bit is transmitted, the TSR is loaded

with new data from the TXREG2 register (if available).

Once the TXREG2 register transfers the data to the

TSR register (occurs in one T

CY), the TXREG2 register

is empty and the TX2IF flag bit (PIR3<4>) is set. This

interrupt can be enabled or disabled by setting or

clearing the interrupt enable bit, TX2IE (PIE3<4>).

TX2IF will be set regardless of the state of TX2IE; it

cannot be cleared in software. TX2IF is also not

cleared immediately upon loading TXREG2, but

becomes valid in the second instruction cycle following

the load instruction. Polling TX2IF immediately

following a load of TXREG2 will return invalid results.

While TX2IF indicates the status of the TXREG2

status of the TSR register. TRMT is a read-only bit

which is set when the TSR register is empty. No inter-

rupt logic is tied to this bit so the user has to poll this bit

in order to determine if the TSR register is empty.

To set up an Asynchronous Transmission:

1. Initialize the SPBRG2 register for the appropriate

baud rate. Set or clear the BRGH bit, as required,

to achieve the desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, TX2IE.

4. If 9-bit transmission is desired, set transmit bit,

TX9. Can be used as address/data bit.

5. Enable the transmission by setting bit, TXEN,

which will also set bit, TX2IF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Load data to the TXREG2 register (starts

transmission).

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 20-1: AUSART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

2: Flag bit, TX2IF, is set when enable bit,

TXEN, is set.

TX2IF

TX2IE

Interrupt

TXEN Baud Rate CLK

SPBRG2

Baud Rate Generator

TX9D

MSb LSb

Data Bus

TXREG2 Register

TSR Register

(8) 0

TX9

TRMT SPEN

TX2 Pin

Pin Buffer

and Control



 2010 Microchip Technology Inc. Preliminary DS39979A-page 265

PIC18F87J72 FAMILY

FIGURE 20-2: ASYNCHRONOUS TRANSMISSION

FIGURE 20-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

TABLE 20-4: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

TXREG2 AUSART Transmit Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Word 1

Transmit Shift Reg

Start bit bit 0 bit 1 bit 7/8

Write to TXREG2

BRG Output

(Shift Clock)

TX2 (pin)

TX2IF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

Word 1

Stop bit

Transmit Shift Reg.

Write to TXREG2

BRG Output

(Shift Clock)

TX2 (pin)

TX2IF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

Stop bit Start bit

Transmit Shift Reg.

Word 1 Word 2

bit 0 bit 1 bit 7/8 bit 0

Note: This timing diagram shows two consecutive transmissions.

1 TCY

Start bit

PIC18F87J72 FAMILY

DS39979A-page 266 Preliminary  2010 Microchip Technology Inc.

20.3.2 AUSART ASYNCHRONOUS

RECEIVER

The receiver block diagram is shown in Figure 20-4.

The data is received on the RX2 pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter operating at x16 times the baud rate,

whereas the main receive serial shifter operates at the

bit rate or at FOSC. This mode would typically be used

in RS-232 systems.

To set up an Asynchronous Reception:

1. Initialize the SPBRG2 register for the appropriate

baud rate. Set or clear the BRGH bit, as required,

to achieve the desired baud rate.

2. Enable the asynchronous serial port by clearing

bit, SYNC, and setting bit, SPEN.

3. If interrupts are desired, set enable bit, RC2IE.

4. If 9-bit reception is desired, set bit, RX9.

5. Enable the reception by setting bit, CREN.

6. Flag bit, RC2IF, will be set when reception is

complete and an interrupt will be generated if

enable bit, RC2IE, was set.

7. Read the RCSTA2 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG2 register.

9. If any error occurred, clear the error by clearing

enable bit, CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

20.3.3 SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPBRG2 register for the appropriate

baud rate. Set or clear the BRGH and BRG16

bits, as required, to achieve the desired baud

rate.

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If interrupts are required, set the RCEN bit and

select the desired priority level with the RC2IP

bit.

4. Set the RX9 bit to enable 9-bit reception.

5. Set the ADDEN bit to enable address detect.

6. Enable reception by setting the CREN bit.

7. The RC2IF bit will be set when reception is

complete. The interrupt will be Acknowledged if

the RC2IE and GIE bits are set.

8. Read the RCSTA2 register to determine if any

error occurred during reception, as well as read

bit 9 of data (if applicable).

9. Read RCREG2 to determine if the device is

being addressed.

10. If any error occurred, clear the CREN bit.

11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and interrupt the CPU.

FIGURE 20-4: AUSART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

Baud Rate Generator

RX2 Pin

Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG2 Register

FIFO

Interrupt RC2IF

RC2IE

Data Bus

 64

 16

Stop Start

(8) 7 1 0

RX9



SPBRG2

 4

 2010 Microchip Technology Inc. Preliminary DS39979A-page 267

PIC18F87J72 FAMILY

FIGURE 20-5: ASYNCHRONOUS RECEPTION

TABLE 20-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

RCREG2 AUSART Receive Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Start

bit bit 7/8

bit 1bit 0 bit 7/8 bit 0Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RX2 (pin)

Rcv Buffer Reg

Rcv Shift Reg

Read Rcv

Buffer Reg

RCREG2

RC2IF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG2

Word 2

RCREG2

Stop

bit

Note: This timing diagram shows three words appearing on the RX2 input. The RCREG2 (Receive Buffer register) is read after the third word

causing the OERR (Overrun) bit to be set.

PIC18F87J72 FAMILY

DS39979A-page 268 Preliminary  2010 Microchip Technology Inc.

20.4 AUSART Synchronous

Master Mode

The Synchronous Master mode is entered by setting

the CSRC bit (TXSTA2<7>). In this mode, the data is

transmitted in a half-duplex manner (i.e., transmission

and reception do not occur at the same time). When

transmitting data, the reception is inhibited and vice

versa. Synchronous mode is entered by setting bit,

SYNC (TXSTA2<4>). In addition, enable bit, SPEN

(RCSTA2<7>), is set in order to configure the TX2 and

RX2 pins to CK2 (clock) and DT2 (data) lines,

respectively.

The Master mode indicates that the processor transmits

the master clock on the CK2 line.

20.4.1 AUSART SYNCHRONOUS MASTER

TRANSMISSION

The AUSART transmitter block diagram is shown in

Figure 20-1. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register:

TXREG2. The TXREG2 register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG2 (if available).

Once the TXREG2 register transfers the data to the

TSR register (occurs in one TCYCLE), the TXREG2 is

empty and the TX2IF flag bit (PIR3<4>) is set. The

interrupt can be enabled or disabled by setting or clear-

ing the interrupt enable bit, TX2IE (PIE3<4>). TX2IF is

set regardless of the state of enable bit, TX2IE; it

cannot be cleared in software. It will reset only when

new data is loaded into the TXREG2 register.

While flag bit, TX2IF, indicates the status of the TXREG2

status of the TSR register. TRMT is a read-only bit which

is set when the TSR is empty. No interrupt logic is tied to

this bit so the user has to poll this bit in order to deter-

mine if the TSR register is empty. The TSR is not

mapped in data memory so it is not available to the user.

To set up a Synchronous Master Transmission:

1. Initialize the SPBRG2 register for the appropriate

baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit, TX2IE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting bit, TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the

TXREG2 register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 20-6: SYNCHRONOUS TRANSMISSION

bit 0 bit 1 bit 7

Word 1

Q1 Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

bit 2 bit 0 bit 1 bit 7

RX2/DT2 pin

TX2/CK2 pin

Write to

TXREG2 Reg

TX2IF bit

(Interrupt Flag)

TXEN bit ‘1’ ‘1’

Word 2

TRMT bit

Write Word 1 Write Word 2

Note: Sync Master mode, SPBRG2 = 0; continuous transmission of two 8-bit words.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 269

PIC18F87J72 FAMILY

FIGURE 20-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

TABLE 20-6: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

TXREG2 AUSART Transmit Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

RX2/DT2 Pin

TX2/CK2 Pin

Write to

TXREG2 Reg

TX2IF bit

TRMT bit

bit 0 bit 1 bit 2 bit 6 bit 7

TXEN bit

PIC18F87J72 FAMILY

DS39979A-page 270 Preliminary  2010 Microchip Technology Inc.

20.4.2 AUSART SYNCHRONOUS

MASTER RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA2<5>), or the Continuous Receive

Enable bit, CREN (RCSTA2<4>). Data is sampled on

the RX2 pin on the falling edge of the clock.

If enable bit, SREN, is set, only a single word is

received. If enable bit, CREN, is set, the reception is

continuous until CREN is cleared. If both bits are set,

then CREN takes precedence.

To set up a Synchronous Master Reception:

1. Initialize the SPBRG2 register for the appropriate

baud rate.

2. Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

3. Ensure bits, CREN and SREN, are clear.

4. If interrupts are desired, set enable bit, RC2IE.

5. If 9-bit reception is desired, set bit, RX9.

6. If a single reception is required, set bit, SREN.

For continuous reception, set bit, CREN.

7. Interrupt flag bit, RC2IF, will be set when recep-

tion is complete and an interrupt will be generated

if the enable bit, RC2IE, was set.

8. Read the RCSTA2 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG2 register.

10. If any error occurred, clear the error by clearing

bit, CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 20-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

TABLE 20-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

RCREG2 AUSART Receive Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

CREN bit

RX2/DT2 pin

TX2/CK2 pin

Write to

bit SREN

SREN bit

RC2IF bit

(Interrupt)

Read

RCREG2

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q2 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘

’

bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7

‘

’

Q1 Q2 Q3 Q4

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 271

PIC18F87J72 FAMILY

20.5 AUSART Synchronous Slave Mode

Synchronous Slave mode is entered by clearing bit,

CSRC (TXSTA2<7>). This mode differs from the

Synchronous Master mode in that the shift clock is

supplied externally at the CK2 pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in any

low-power mode.

20.5.1 AUSART SYNCHRONOUS

SLAVE TRANSMIT

The operation of the Synchronous Master and Slave

modes are identical except in the case of the Sleep

mode.

If two words are written to the TXREG2 and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in the TXREG2

c) Flag bit, TX2IF, will not be set.

d) When the first word has been shifted out of TSR,

the TXREG2 register will transfer the second

word to the TSR and flag bit, TX2IF, will now be

set.

e) If enable bit, TX2IE, is set, the interrupt will wake

the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt

vector.

To set up a Synchronous Slave Transmission:

1. Enable the synchronous slave serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. Clear bits, CREN and SREN.

3. If interrupts are desired, set enable bit, TX2IE.

4. If 9-bit transmission is desired, set bit, TX9.

5. Enable the transmission by setting enable bit,

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit, TX9D.

7. Start transmission by loading data to the

TXREG2 register.

8. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 20-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

TXREG2 AUSART Transmit Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

LATG U2OD U1OD —LATG4 LATG3 LATG2 LATG1 LATG0 52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

PIC18F87J72 FAMILY

DS39979A-page 272 Preliminary  2010 Microchip Technology Inc.

20.5.2 AUSART SYNCHRONOUS

SLAVE RECEPTION

The operation of the Synchronous Master and Slave

modes is identical except in the case of Sleep or any

Idle mode, and bit SREN, which is a “don’t care” in

Slave mode.

If receive is enabled by setting the CREN bit prior to

entering Sleep, or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG2 register; if the RC2IE enable bit is set, the

interrupt generated will wake the chip from low-power

mode. If the global interrupt is enabled, the program will

branch to the interrupt vector.

To set up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits, SYNC and SPEN, and clearing bit,

CSRC.

2. If interrupts are desired, set enable bit, RC2IE.

3. If 9-bit reception is desired, set bit, RX9.

4. To enable reception, set enable bit, CREN.

5. Flag bit, RC2IF, will be set when reception is

complete. An interrupt will be generated if

enable bit, RC2IE, was set.

6. Read the RCSTA2 register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG2 register.

8. If any error occurred, clear the error by clearing

bit, CREN.

9. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 20-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 54

RCREG2 AUSART Receive Register 54

TXSTA2 CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 54

SPBRG2 AUSART Baud Rate Generator Register 54

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 273

PIC18F87J72 FAMILY

21.0 12-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital (A/D) Converter module has

12 inputs for all PIC18F87J72 family devices. This

module allows conversion of an analog input signal to

a corresponding 12-bit digital number.

The module has these registers:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

• A/D Control Register 2 (ADCON2)

The ADCON0 register, shown in Register 21-1,

controls the operation of the A/D module. The

ADCON1 register, shown in Register 21-2, configures

the functions of the port pins. The ADCON2 register,

shown in Register 21-3, configures the A/D clock

source, programmed acquisition time and justification.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADCAL: A/D Calibration bit

1 = Calibration is performed on the next A/D conversion

0 = Normal A/D Converter operation (no calibration is performed)

bit 6 Unimplemented: Read as ‘0’

bit 5-2 CHS<3:0>: Analog Channel Select bits

0000 = Channel 00 (AN0)

0001 = Channel 01 (AN1)

0010 = Channel 02 (AN2)

0011 = Channel 03 (AN3)

0100 = Channel 04 (AN4)

0101 = Channel 05 (AN5)

0110 = Channel 06 (AN6)

0111 = Channel 07 (AN7)

1000 = Channel 08 (AN8)

1001 = Channel 09 (AN9)

1010 = Channel 10 (AN10)

1011 = Channel 11 (AN11)

11xx = Unused

bit 1 GO/DONE: A/D Conversion Status bit

When ADON = 1:

1 = A/D conversion is in progress

0 = A/D is Idle

bit 0 ADON: A/D On bit

1 = A/D Converter module is enabled

0 = A/D Converter module is disabled

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DS39979A-page 274 Preliminary  2010 Microchip Technology Inc.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

TRIGSEL — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 TRIGSEL: Special Trigger Select bit

1 = Selects the special trigger from the CTMU

0 = Selects the special trigger from the CCP2

bit 6 Unimplemented: Read as ‘0’

bit 5 VCFG1: Voltage Reference Configuration bit (VREF- source)

1 =V

REF- (AN2)

0 =AV

bit 4 VCFG0: Voltage Reference Configuration bit (VREF+ source)

1 =VREF+ (AN3)

0 =AV

bit 3-0 PCFG<3:0>: A/D Port Configuration Control bits:

A = Analog input D = Digital I/O

PCFG<3:0> AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

0000 AAAAAAAAAAAA

0001 AAAAAAAAAAAA

0010 AAAAAAAAAAAA

0011 AAAAAAAAAAAA

0100 DAAAAAAAAAAA

0101 DDAAAAAAAAAA

0110 DDDAAAAAAAAA

0111 DDDDAAAAAAAA

1000 DDDDDAAAAAAA

1001 DDDDDDAAAAAA

1010 DDDDDDDAAAAA

1011 DDDDDDDDAAAA

1100 DDDDDDDDDAAA

1101 DDDDDDDDDDAA

1110 DDDDDDDDDDDA

1111 DDDDDDDDDDDD

 2010 Microchip Technology Inc. Preliminary DS39979A-page 275

PIC18F87J72 FAMILY

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified

0 = Left justified

bit 6 Unimplemented: Read as ‘0’

bit 5-3 ACQT<2:0>: A/D Acquisition Time Select bits

111 = 20 T

110 = 16 TAD

101 = 12 TAD

100 = 8 TAD

011 = 6 TAD

010 = 4 TAD

001 = 2 TAD

000 = 0 TAD(1)

bit 2-0 ADCS<2:0>: A/D Conversion Clock Select bits

111 = FRC (clock derived from A/D RC oscillator)(1)

110 = FOSC/64

101 = FOSC/16

100 = FOSC/4

011 = FRC (clock derived from A/D RC oscillator)(1)

010 = FOSC/32

001 = FOSC/8

000 = FOSC/2

Note 1: If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D

clock starts. This allows the SLEEP instruction to be executed before starting a conversion.

PIC18F87J72 FAMILY

DS39979A-page 276 Preliminary  2010 Microchip Technology Inc.

The analog reference voltage is software selectable to

either the device’s positive and negative supply voltage

(AVDD and AVSS) or the voltage level on the RA3/AN3/

VREF+ and RA2/AN2/VREF- pins.

The A/D Converter has a unique feature of being able

to operate while the device is in Sleep mode. To

operate in Sleep, the A/D conversion clock must be

derived from the A/D’s internal RC oscillator.

The output of the sample and hold is the input into the

converter, which generates the result via successive

approximation.

Each port pin associated with the A/D Converter can be

configured as an analog input or as a digital I/O. The

ADRESH and ADRESL registers contain the result of the

A/D conversion. When the A/D conversion is complete,

the result is loaded into the ADRESH:ADRESL register

pair, the GO/DONE bit (ADCON0<1>) is cleared and the

A/D Interrupt Flag bit, ADIF, is set.

A device Reset forces all registers to their Reset state.

This forces the A/D module to be turned off and any

conversion in progress is aborted. The value in the

ADRESH:ADRESL register pair is not modified for a

Power-on Reset. These registers will contain unknown

data after a Power-on Reset.

The block diagram of the A/D module is shown in

Figure 21-1.

FIGURE 21-1: A/D BLOCK DIAGRAM(1,2)

(Input Voltage)

VAIN

VREF+

Reference

Voltage

AVDD

VCFG<1:0>

CHS<3:0>

AN7

AN6

AN4

AN3

AN2

AN1

AN0

0111

0110

0100

0011

0010

0001

0000

12-Bit

A/D

VREF-

AVSS

Converter

AN11

AN10

AN9

AN8

1011

1010

1001

1000

Note 1: Channels, AN15 through AN12, are not available on PIC18F87J62 devices.

2: I/O pins have diode protection to VDD and VSS.

AN5

0101

 2010 Microchip Technology Inc. Preliminary DS39979A-page 277

PIC18F87J72 FAMILY

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

To determine acquisition time, see Section 21.1 “A/D

Acquisition Requirements”. After this acquisition

time has elapsed, the A/D conversion can be started.

An acquisition time can be programmed to occur

between setting the GO/DONE bit and the actual start

of the conversion.

The following steps should be followed to do an A/D

conversion:

1. Configure the A/D module:

• Configure analog pins, voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D acquisition time (ADCON2)

• Select A/D conversion clock (ADCON2)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time (if required).

4. Start conversion:

• Set GO/DONE bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH:ADRESL);

clear ADIF bit, if required.

7. For next conversion, go to step 1 or step 2, as

required. The A/D conversion time per bit is

defined as T

AD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 21-2: ANALOG INPUT MODEL

VAIN CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V ILEAKAGE

RIC 1k

Sampling

Switch

SS RSS

CHOLD = 25 pF

VSS

Sampling Switch

1234

(k)

VDD

±100 nA

Legend: CPIN

ILEAKAGE

RIC

CHOLD

= Input Capacitance

= Threshold Voltage

= Leakage Current at the pin due to

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

various junctions

= Sampling Switch ResistanceRSS

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DS39979A-page 278 Preliminary  2010 Microchip Technology Inc.

21.1 A/D Acquisition Requirements

For the A/D Converter to meet its specified accuracy,

the Charge Holding Capacitor (CHOLD) must be

allowed to fully charge to the input channel voltage

level. The analog input model is shown in Figure 21-2.

The source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor, CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The

maximum recommended impedance for analog

sources is 2.5 k. After the analog input channel is

selected (changed), the channel must be sampled for

at least the minimum acquisition time before starting a

conversion.

To calculate the minimum acquisition time,

Equation 21-1 may be used. This equation assumes

that 1/2 LSb error is used (1,024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

Equation 21-3 shows the calculation of the minimum

required acquisition time, T

ACQ. This calculation is

based on the following application system

assumptions:

EQUATION 21-1: ACQUISITION TIME

EQUATION 21-2: A/D MINIMUM CHARGING TIME

EQUATION 21-3: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note: When the conversion is started, the

holding capacitor is disconnected from the

input pin.

CHOLD =25 pF

Rs = 2.5 k

Conversion Error 1/2 LSb

VDD =3VRss = 2 k

Temperature = 85C (system max.)

TACQ = Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP + TC + TCOFF

VHOLD = (VREF – (VREF/2048)) • (1 – e(-TC/CHOLD(RIC + RSS + RS)))

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048)

TACQ =TAMP + TC + TCOFF

TAMP =0.2 s

TCOFF = (Temp – 25C)(0.02 s/C)

(85C – 25C)(0.02 s/C)

1.2 s

Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms.

TC = -(CHOLD)(RIC + RSS + RS) ln(1/2048) s

-(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) s

1.05 s

TACQ =0.2 s + 1 s + 1.2 s

2.4 s

 2010 Microchip Technology Inc. Preliminary DS39979A-page 279

PIC18F87J72 FAMILY

21.2 Selecting and Configuring

Automatic Acquisition Time

The ADCON2 register allows the user to select an

acquisition time that occurs each time the GO/DONE

bit is set.

When the GO/DONE bit is set, sampling is stopped and

a conversion begins. The user is responsible for ensur-

ing the required acquisition time has passed between

selecting the desired input channel and setting the

GO/DONE bit. This occurs when the ACQT<2:0> bits

(ADCON2<5:3>) remain in their Reset state (‘000’) and

is compatible with devices that do not offer

programmable acquisition times.

If desired, the ACQT bits can be set to select a

programmable acquisition time for the A/D module.

When the GO/DONE bit is set, the A/D module continues

to sample the input for the selected acquisition time, then

automatically begins a conversion. Since the acquisition

time is programmed, there may be no need to wait for an

acquisition time between selecting a channel and setting

the GO/DONE bit.

In either case, when the conversion is completed, the

GO/DONE bit is cleared, the ADIF flag is set and the

A/D begins sampling the currently selected channel

again. If an acquisition time is programmed, there is

nothing to indicate if the acquisition time has ended or

if the conversion has begun.

21.3 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 11 T

AD per 12-bit conversion.

The source of the A/D conversion clock is software

selectable.

There are seven possible options for TAD:

•2 T

OSC

•4 TOSC

•8 TOSC

•16 TOSC

•32 TOSC

•64 T

OSC

• Internal RC Oscillator

For correct A/D conversions, the A/D conversion clock

AD) must be as short as possible but greater than the

minimum TAD.

Table 21-1 shows the resultant T

AD times derived from

the device operating frequencies and the A/D clock

source selected.

TABLE 21-1: TAD vs. DEVICE OPERATING

FREQUENCIES

21.4 Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers

control the operation of the A/D port pins. The port pins

needed as analog inputs must have their correspond-

ing TRIS bits set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) will be

converted.

The A/D operation is independent of the state of the

CHS<3:0> bits and the TRIS bits.

AD Clock Source (TAD)Maximum

Device

Frequency

Operation ADCS<2:0>

2 T

OSC 000 2.86 MHz

4 T

OSC 100 5.71 MHz

8 TOSC 001 11.43 MHz

16 TOSC 101 22.86 MHz

32 TOSC 010 40.0 MHz

64 TOSC 110 40.0 MHz

RC(2) x11 1.00 MHz(1)

Note 1: The RC source has a typical TAD time of

4s.

2: For device frequencies above 1 MHz, the

device must be in Sleep mode for the entire

conversion or the A/D accuracy may be out

of specification.

Note 1: When reading the PORT register, all pins

configured as analog input channels will

read as cleared (a low level). Pins config-

ured as digital inputs will convert an

analog input. Analog levels on a digitally

configured input will be accurately

converted.

2: Analog levels on any pin defined as a

digital input may cause the digital input

buffer to consume current out of the

device’s specification limits.

PIC18F87J72 FAMILY

DS39979A-page 280 Preliminary  2010 Microchip Technology Inc.

21.5 A/D Conversions

Figure 21-1 shows the operation of the A/D Converter

after the GO/DONE bit has been set and the

ACQT<2:0> bits are cleared. A conversion is started

after the following instruction to allow entry into Sleep

mode before the conversion begins.

Figure 21-2 shows the operation of the A/D Converter

after the GO/DONE bit has been set. The ACQT<2:0>

bits are set to ‘010’ and a 4 T

AD acquisition time is

selected before the conversion starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

AD wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

21.6 Use of the CCP2 Trigger

An A/D conversion can be started by the “Special Event

Trigger” of the CCP2 module. This requires that the

CCP2M<3:0> bits (CCP2CON<3:0>) be programmed

as ‘1011’ and that the A/D module is enabled (ADON

bit is set). When the trigger occurs, the GO/DONE bit

will be set, starting the A/D acquisition and conversion,

and the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH:ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition period is either timed by

the user or an appropriate TACQ time is selected before

the Special Event Trigger sets the GO/DONE bit (starts

a conversion).

If the A/D module is not enabled (ADON is cleared), the

Special Event Trigger will be ignored by the A/D module,

but will still reset the Timer1 (or Timer3) counter.

FIGURE 21-1: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 21-2: A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10TCY – TAD

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input

Conversion starts

b11 b8 b7 b6 b5 b4 b3

b10 b9

On the following cycle:

Discharge

TAD13TAD12

b0b1

TAD1

(typically 200 ns)

123 4 567813

Set GO/DONE bit

(Holding capacitor is disconnected)

912

Conversion starts

1234

(Holding capacitor continues

acquiring input)

ACQT Cycles TAD Cycles

Automatic

Acquisition

Time

b0b11 b8 b7 b6 b5 b4 b1

b10 b9

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input

On the following cycle:

TAD1

Discharge

10 11

b3 b2

(typically

200 ns)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 281

PIC18F87J72 FAMILY

21.7 A/D Converter Calibration

The A/D Converter in the PIC18F87J72 family of

devices includes a self-calibration feature which

compensates for any offset generated within the

module. The calibration process is automated and is

initiated by setting the ADCAL bit (ADCON0<7>). The

next time the GO/DONE bit is set, the module will per-

form a “dummy” conversion (which means it is reading

none of the input channels) and store the resulting value

internally to compensate for the offset. Thus,

subsequent offsets will be compensated.

The calibration process assumes that the device is in a

relatively steady-state operating condition. If A/D

calibration is used, it should be performed after each

device Reset or if there are other major changes in

operating conditions.

21.8 Operation in Power-Managed

Modes

The selection of the automatic acquisition time and A/D

conversion clock is determined in part by the clock

source and frequency while in a power-managed mode.

If the A/D is expected to operate while the device is in

a power-managed mode, the ACQT<2:0> and

ADCS<2:0> bits in ADCON2 should be updated in

accordance with the power-managed mode clock that

will be used. After the power-managed mode is entered

(either of the power-managed Run modes), an A/D

acquisition or conversion may be started. Once an

acquisition or conversion is started, the device should

continue to be clocked by the same power-managed

mode clock source until the conversion has been

completed. If desired, the device may be placed into

the corresponding power-managed Idle mode during

the conversion.

If the power-managed mode clock frequency is less

than 1 MHz, the A/D RC clock source should be

selected.

Operation in Sleep mode requires the A/D RC clock to

be selected. If bits, ACQT<2:0>, are set to ‘000’ and a

conversion is started, the conversion will be delayed

one instruction cycle to allow execution of the SLEEP

instruction and entry to Sleep mode. The IDLEN and

SCSx bits in the OSCCON register must have already

been cleared prior to starting the conversion.

TABLE 21-2: SUMMARY OF A/D REGISTERS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on Page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR1 —ADIFRC1IF TX1IF SSPIF —TMR2IF TMR1IF 52

PIE1 —ADIERC1IE TX1IE SSPIE —TMR2IE TMR1IE 52

IPR1 —ADIPRC1IP TX1IP SSPIP —TMR2IP TMR1IP 52

PIR3 —LCDIF RC2IF TX2IF CTMUIF CCP2IF CCP1IF RTCCIF 52

PIE3 —LCDIE RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE 52

IPR3 —LCDIP RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP 52

ADRESH A/D Result Register High Byte 51

ADRESL A/D Result Register Low Byte 51

ADCON0 ADCAL — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 51

ADCON1 TRIGSEL — VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 51

ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 51

CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53

PORTA RA7(1) RA6(1) RA5 RA4 RA3 RA2 RA1 RA0 52

TRISA TRISA7(1) TRISA6(1) TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 52

PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —52

TRISF TRISF5 TRISF4 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.

Note 1: RA<7:6> and their associated latch and direction bits are configured as port pins only when the internal

oscillator is selected as the default clock source (FOSC2 Configuration bit = 0); otherwise, they are

disabled and these bits read as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 282 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 283

PIC18F87J72 FAMILY

22.0 DUAL-CHANNEL, 24-BIT

ANALOG FRONT END (AFE)

The dual-channel, 24-bit Analog Front End (AFE) is an

integrated, high-performance analog subsystem that

has been tailored for energy metering and power

measurement applications. The AFE contains two

synchronous sampling Delta-Sigma Analog-to-Digital

Converters ( ADC), two PGAs, a phase delay

compensation block, an internal voltage reference and

a dedicated, high-speed 20 MHz SPI compatible serial

interface. A functional block diagram of the AFE is

shown in Figure 22-1.

The A/D Converters contain a proprietary dithering

algorithm for reduced Idle tones and improved THD.

Each converter is preceded by a PGA, allowing for

weak signal amplification and true differential voltage

inputs to the converters. This allows the AFE to inter-

face with a large variety of voltage and current sensors

including shunts, current transformers, Rogowski coils

and Hall effect sensors.

AFE data and control functions are accessed through a

dedicated register map. The map contains 24-bit wide

data words for each ADC (readable as 8-bit registers),

as well as five writable control registers to program

amplifier gain, oversampling, phase, resolution, dither-

ing, shutdown, Reset and communication features.

Communication is largely simplified with various

continuous read modes that can be accessed through

the serial interface and with a separate data ready pin

that can directly be connected to a microcontroller’s

IRQ input.

Because of the complexity of and comprehensive

options available on the AFE, a detailed explanation of

all of its functional elements is not provided in this

chapter. These are described in Appendix B:

“Dual-Channel, 24-Bit AFE Reference”. This chapter

explains the important points of configuring and using

the AFE in a PIC18F8XJ72 based application. Direct

links to relevant information in the AFE reference are

provided throughout the chapter for the reader’s

convenience.

FIGURE 22-1: DUAL-CHANNEL ANALOG FRONT END FUNCTIONAL DIAGRAM

CH0+

CH0-

CH1+

CH1-

SDOA

SDIA

SCKA

DUAL-DS ADC

ANALOG DIGITAL

SINC3

PGA

MCLK CLKIA

ARESET

Digital SPI

Interface

Clock

Generation

SINC3

PGA Modulator

AMCLK

DMCLK/DRCLK

DMCLK

Phase

Shifter

PHASE <7:0>

OSR<1:0>

PRE<1:0>

DATA_CH0<23:0>

DATA_CH1<23:0>

SDN<1:0>, RESET<1:0>, GAIN<7:0>

CSA

REFIN+/OUT+

REFIN -

SAVDD

SAVSS SVSS

SVDD

POR

SVDD

Monitoring POR

Modulator

VREF+VREF-/

VREFEXT

Voltage

Reference

VREF

D-S

PIC18F87J72 FAMILY

DS39979A-page 284 Preliminary  2010 Microchip Technology Inc.

22.1 Functional Overview

While it is convenient to think of the dual-channel AFE

as a high-precision ADC, there are actually many more

components involved. The main components are

described below. The dual-channel AFE reference

provides more in-depth information on each.

22.1.1 DELTA-SIGMA ADC

ARCHITECTURE

Each Delta-Sigma ADC is an oversampling converter

that incorporates a built-in modulator which is digitizing

the quantity of charge integrated by the modulator loop.

The quantizer is the block that is performing the

analog-to-digital conversion. The quantizer is typically

1-bit, or a simple comparator, which helps to maintain

the linearity performance of the ADC (the DAC

structure is, in this case, inherently linear).

Multi-bit quantizers help to lower the quantization error

(the error fed back in the loop can be very large with

1-bit quantizers) without changing the order of the

modulator or the OSR which leads to better SNR

figures. However, typically, the linearity of such

architectures is more difficult to achieve since the DAC

is no more simple to realize and its linearity limits the

THD of such ADCs.

The 5-level quantizer is a Flash ADC composed of

4 comparators arranged with equally spaced thresholds

and a thermometer coding. The AFE also includes pro-

prietary 5-level DAC architecture that is inherently linear

for improved THD figures.

The resulting channel data is either a 16-bit or 24-bit

word, presented in 23-bit or 15-bit plus sign, two’s

complement format and is MSb (left) justified.

22.1.2 ANALOG INPUTS (CHn+/-)

The analog inputs can be connected directly to current

and voltage transducers. Each input pin is protected by

specialized ESD structures that are certified to pass

7 kV HBM and 400V MM contact charge. These

structures allow bipolar ±6V continuous voltage with

respect to SAVSS, to be present at their inputs without

the risk of permanent damage.

22.1.3 PROGRAMMABLE GAIN

AMPLIFIERS (PGA)

The two Programmable Gain Amplifiers (PGAs) reside

at the front-end of each Delta-Sigma ADC. They have

two functions: translate the common-mode of the input

from SAVss to an internal level between SAVSS and

SAVDD, and amplify the input differential signal. The

translation of the common-mode does not change the

differential signal, but recenters the common-mode so

that the input signal can be properly amplified.

The PGA block can be used to amplify very low signals,

but the differential input range of the Delta-Sigma

modulator must not be exceeded.

22.1.4 SINC3 FILTER

Both ADCs include a decimation filter that is a

third-order sinc (or notch) filter. This filter processes the

multi-bit stream into either 16-bit or 24-bit words,

depending on the configuration chosen. The settling

time of the filter is three DMCLK periods. The resolution

achievable at the output of the sinc filter (the output of

the ADC) is dependent on the oversampling ratio

selected.

22.1.4.1 Internal Voltage Reference

The AFE contains an internal voltage reference source

specially designed to minimize drift over temperature.

This internal VREF supplies reference voltage to both

channels. The typical value of this voltage reference is

2.37V ±2%. The internal reference has a very low typi-

cal temperature coefficient of ±12 ppm/°C, allowing the

output codes to have minimal variation with respect to

temperature since they are proportional to (1/VREF).

The output pin for the internal voltage reference is

REFIN+/OUT.

Optionally, the AFE can be configured to use an exter-

nal voltage reference supplied on the REFIN+ and

REFIN- pins.

22.1.5 PHASE DELAY BLOCK

The AFE incorporates a phase delay generator which

ensures that the two ADCs are converting the inputs

with a fixed delay between them. The two ADCs are

synchronously sampling but the averaging of

modulator outputs is delayed, so that the SINC filter

outputs (thus, the ADC outputs) show a fixed phase

delay, configured by the PHASE register.

22.1.6 INTERNAL AFE CLOCK

The AFE uses an external clock signal to operate its

internal digital logic. The AFE includes a clock genera-

tion chain of back-to-back dividers to produce a range

of sampling frequencies.

22.1.7 SERIAL INTERFACE

The AFE uses an SPI-compatible slave serial interface.

Its operation is discussed in Section 22.3 “Serial

Interface”.

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22.2 AFE Register Map

The dual-channel AFE uses its own internal registers

for data and control. This memory is not mapped to the

microcontroller’s SFR space, but is accessed through

the AFE’s serial interface. The memory space is

divided into eight registers:

• Two 24-bit registers, one for the data of each ADC

• Five 8-bit control registers

• One reserved 8-bit register address

Although the data registers are 24 bits wide, they may

be directly addressed as three different 8-bit registers.

The complete memory map is listed in Table 22-1.

All registers are fully described in Section B.6 “Internal

Registers” of the AFE reference.

Registers may be read singly in a single read opera-

tion; continuously, as part of a group of registers; or

continuously, by type (i.e., data registers vs. control

registers). The type of read operation is handled

through the AFE’s serial interface by selecting the type

of read operation. The grouping of registers is shown in

Table 22-2. A complete description of the different read

operations and how to implement them is described in

Section B.5.3 “Reading from the Device” of the AFE

reference.

TABLE 22-2: REGISTER MAP GROUPING FOR CONTINUOUS READ MODES

TABLE 22-1: AFE REGISTER MAP

Address Name Bits R/W Description

00h DATA_CH0 24 R Channel 0 ADC Data <23:0>, MSB First

03h DATA_CH1 24 R Channel 1 ADC Data <23:0>, MSB First

06h Reserved 8 — Reserved; ignore reads, do not write

07h PHASE 8 R/W Phase Delay Configuration Register

08h GAIN 8 R/W Gain Configuration Register

09h STATUS/COM 8 R/W Status/Communication Register

0Ah CONFIG1 8 R/W Configuration Register 1

0Bh CONFIG2 8 R/W Configuration Register 2

Function Address READ<1:0>

“01”“10”“11”

DATA_CH0

00h

Group

Type

Loop Entire

01h

02h

DATA_CH1

03h

Group04h

05h

PHASE 07h Group

Type

GAIN 08h

STATUS/COM 09h

GroupCONFIG1 0Ah

CONFIG2 0Bh

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22.3 Serial Interface

22.3.1 OVERVIEW

All communication with the dual-channel AFE is

handled through its serial interface; this includes the

exchange of data with the PIC18F8XJ72 device itself.

This arrangement allows the AFE to direct data with

other microcontrollers on an SPI bus in complex appli-

cations, and work cooperatively with other SPI enabled

analog devices.

The serial interface is an SPI-compatible slave inter-

face, compatible with SPI modes, 0,0 and 1,1. Data is

clocked out of the AFE on the falling edge of SCKA

and, clocked into the device on the rising edge of

SCKA. In these modes, SCKA can Idle either high or

low.

A complete discussion of the serial interface is pro-

vided in Section B.5 “Serial Interface Description” of

the AFE Reference.

22.3.2 CONTROL BYTE

The first byte transmitted to the AFE is always a control

byte. This byte is composed of three fields

(Figure 22-2):

• Two address bits (A<6:5>, the MSbs)

• Five register address bits (A<4:0>)

• One Read/Write bit (R/W, the LSbs)

The AFE interface is device-addressable (through

A<6:5>), so that multiple devices can be present on the

same SPI bus with no data bus contention. This

functionality allows external SPI Master devices on the

bus, such as another microcontroller, to read and share

data. It also enables three-phase power metering

systems containing two additional analog front end

devices, controlled by a single SPI bus (single CS,

SCK, SDI and SDO pins).

The SPI device address bits of the PIC18F87J72

interface are always ‘00’; they cannot be changed.

FIGURE 22-2: CONTROL BYTE

A read on undefined addresses gives an output of all

zeros on the first and all subsequent transmitted bytes.

Writing to an undefined address has no effect and does

not increment the address counter either.

22.3.3 READING FROM THE DEVICE

The first data byte read is the one defined by the

address given in the control byte. After this first byte is

transmitted, if the CSA pin is held low, the communica-

tion continues and the address of the next transmitted

byte is determined by the configuration of the interface,

set by the read bits in the STATUS/COM register.

22.3.4 WRITING TO THE DEVICE

The first data byte written is the one defined by the

address given in the control byte. The write

communication automatically increments the address

for subsequent bytes.

The address of the next transmitted byte within the

same communication (CSA stays low) is the next

address defined on the register map. At the end of the

effect.

The SDOA pin remains in a high-impedance state

during a write communication.

22.3.5 CONTINUOUS COMMUNICATION

AND LOOPING ON ADDRESS SETS

If the user wishes to read back one or both of the ADC

channels continuously, the internal address counter of

the AFE can be set to loop on specific register sets.

This method also makes it possible to continuously

read specific register groups, one of the register types

or all of the registers.

In each case, one control byte on SDIA starts the

communication. The part stays within the same loop

until CSA returns high.

Continuous communication is described in more detail

in Section B.5.7 “Continuous Communication,

Looping On Address Sets” of the AFE Reference.

22.3.6 DATA READY PIN (DR)

In addition to the standard SPI interface pins (SDIA,

SDOA, SCKA and CSA), the AFE provides an addi-

tional Data Ready (DR) signal. This signifies to an

external device when conversion data is available. The

DR signal, available on the pin of the same name, is an

active-low pulse at the end of a channel conversion,

with a period that is equal to the DRCLK clock period

and with a width equal to one DMCLK period.

The DR pin can be configured to operate in different

modes that are defined by the availability of conversion

data on the ADC channels. The various Data Ready

modes and configuration options for the DR pin are

described in Section B.5.9 “Data Ready Pin (DR)” of

the AFE Reference.

A6 A5 A4 A3 A2 A1 A0 R/W

Read

Write Bit

Device

Address Bits

Address

Bits

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22.4 AFE Connections

The dual-channel AFE has multiple data and power con-

nections that are independent of the digital side of the

microcontroller. These connections are required to use

the AFE, and are in addition to the connection and layout

connections provided in Section 2.0 “Guidelines for

Getting Started with PIC18FJ Microcontrollers”.

All of the connections required for proper operation of

the AFE are shown in Figure 22-3.

22.4.1 VOLTAGE AND GROUND

CONNECTIONS

The AFE has independent voltage supply requirements

that differ from the rest of the microcontroller. Digital cir-

cuits are supplied through the SVDD pin, which requires

a voltage of 2.7V to 5.5V. Typically, SVDD can be tied to

3.3V, the same as the VDD and AVDD pins. Analog cir-

cuits are separately supplied through the SAVDD pin,

which requires a voltage of 4.5V to 5.5V (5V ±10%).

Independent ground returns are provided through the

SVss and SAVss pins, respectively.

As with the microcontroller’s VDD/VSS and AVDD/AVSS

pins, bypass capacitors are required on the AFE power

and return pin pairs. Requirements for these capacitors

are identical to those for the VDD/VSS and AVDD/AVSS

pins.

It is recommended that designs using PIC18F87J72

family devices incorporate a separate ground return

path for analog circuits. SAVss, as well as other AFE

analog pins (e.g., REFIN-) that require grounding,

should be tied to this analog return. SVSS can be tied to

the digital ground, along with VSS and AVSS. The ana-

log and digital grounds may be tied to a single point at

the power source.

FIGURE 22-3: REQUIRED CONNECTIONS FOR AFE OPERATION

PIC18F8XJ72

SDIA

GPIO(1)

SDO

SDI

CH1-

SAVSS

REFIN+/OUT

REFIN-

SCKA

SDOA

Key (all values are recommendations):

C1 and C2: 0.1 F, 20V ceramic

C3 and C4: 100 nF, 20V ceramic.

Bold lines show SPI connections.

Note 1: Any available I/O pins may be used to control ARESET and CSA. The software examples discussed in this chapter

use RD0 and RD7, respectively.

2: The software examples discussed in this chapter use CCP1 to generate the AFE clock source. Other clock sources

may be used, as required.

GPIO(1)

ARESET

CSA

INT0

SCK

CCP1(2)

CLKIA

C3 C4

CH1+

CH0-

CH0+

Differential

Analog

Inputs

SVSS

SAVDD

SVDD

C1 C2

Analog GND

SVDD (3.3V)

SAVDD (5V)

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22.4.2 SERIAL INTERFACE

CONNECTIONS

The AFE uses its own dedicated Serial Peripheral

Interface (SPI) to both send output data from its A/D

Converters, and send and receive control information.

The interface allows the AFE to operate directly with

other microcontrollers and analog peripherals that use

SPI on a common serial bus.

To use the interface, the following connections are

required between the AFE and the MSSP module:

• from SDO (RC5) to SDIA

• from SDI (RC4) to SDOA

• from SCK (RC3) to SCKA

In addition, the AFE requires a chip select signal on the

CSA pin (active-low) to function properly. The chip

select signal can be supplied by any available I/O pin.

22.4.3 OTHER INTERFACE

CONNECTIONS

In addition to the SPI connections, the AFE requires

three other digital signals for proper control:

• the Data Ready (DR) output, asserted low to

signal that a conversion has been completed and

is ready to be transferred;

• a module Reset (ARESET), asserted low to inde-

pendently force the AFE into a POR event; and

• a clock for the AFE’s digital circuits, supplied on

the CLKIA pin.

To use the Data Ready, tie the DR pin to an external

interrupt pin, such as INT0. Asserting DR will cause an

interrupt, the ISR for which can be used to read the

AFE’s data through the SPI. Note that whatever inter-

rupt trigger is used, it must be properly configured to

trigger when the pin is asserted low.

For the Reset input, use an available I/O pin to drive

ARESET low when needed.

For the AFE clock signal, any suitable clock signal in

the proper frequency range (1 MHz to 5 MHz) can be

used. One convenient and low pin count method is to

use a CCP module in PWM mode to generate an

appropriate clock, then connect the module’s output pin

to CLKIA.

22.4.4 ANALOG INPUTS

The analog signals to be converted to digital values are

connected to the pins of CH0 and/or CH1. Each chan-

nel has inverting and non-inverting inputs (CHn- and

CHn+, respectively), and is fully differential. Limits and

absolute maximums for the inputs are described in

Section 29.0 “Electrical Characteristics”.

The REFIN+/OUT and REFIN- pins are used to supply

an external voltage reference to the AFE; the

REFIN+/OUT pin can also be configured to provide

voltage generated by the AFE’s internal voltage refer-

ence. If the internal voltage reference is enabled,

bypass capacitors to analog ground are recommended

for the REFIN+/OUT pin. The REFIN- pin should be

directly connected to analog ground (as shown in

Figure 22-3).

22.5 Using the AFE

To configure the AFE and read A/D conversion data,

follow this sequence:

1. Initialize the MSSP module:

a) Configure for SPI Master mode, in either

SPI mode 0,0 (CKP = 0, CKE = 1) or mode

1,1 (CKP = 1, CKE = 0).

b) Configure TRISC for SCK and SDO as out-

puts, and SDI as input.

2. Reset the AFE by pulling ARESET low.

3. Pull CSA high.

4. Disable the chip select signals of all the devices

connected to the same SPI bus.

5. Pull CSA low, then write the register address

with command (read or write selection) to the

AFE through the SPI.

As long as CSA

is enabled, the address will

increment automatically after each SPI transfer

is completed. After sending the address and

command, the registers of the AFE can be

written or read.

Disable CSA after read or write to a set of AFE

registers.

6. When the DR signal is asserted, signalling that

an A/D conversion is complete, use an interrupt

routine to read the data from one or both chan-

nels. The overall method is similar to that for

reading other AFE registers over the SPI,

described in step 5.

Note that SPI operations to read or write the AFE’s reg-

isters can be performed even without providing CLKIA

to the AFE. The CLKIA signal is required to perform

A/D conversions and make the Data Ready (DR) signal

available after conversions are done.

Note: The first byte sent to the AFE upon

initialization must always be a control byte.

See Appendix B.5 “Serial Interface

Description” for more information.

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Example 22-1 provides a general outline for imple-

menting a driver routine for the AFE. Example 22-2

through Example 22-5 show the details for each step.

The example shown here assumes the following

loopback connections:

• RC4 (SDI) to SDOA

• RC5 (SDO) to SDIA

• RC3 (SCK) to SCKA

• RD0 to ARESET

• RD7 to CSA

• RC2 (CCP1) to CLKIA

• RB0 (INT0) to DR

Aside from the SPI, which is determined by the

microcontroller’s single MSSP module, the other

connections may change based on the particular appli-

cation’s requirements. For example, the AFE clock on

CLKIA is generated from the PWM of CCP1 in this

demonstration; other clock sources may be available.

Users should modify the individual code segments

accordingly.

EXAMPLE 22-1: OVERALL STRUCTURE FOR USING THE AFE

///////////////////////////////////////////////////////////////////////////////////////////////

// Outline of a typical driver routine for the dual-channel AFE.

///////////////////////////////////////////////////////////////////////////////////////////////

#include "p18F87J72.h"

void main(void)

{

///////////////////////////////////////////////////////////////////////////////////

// STEP 1:Initialize MSSP (Example 22-2)

////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////

// STEP 2: Issue Reset to AFE (Example 22-2)

/////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////

// STEPS 3: Disable all Chip Selects on all SPI devices (Example 22-2)

////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////

// STEP 4: Write to AFE registers; read back (optionally) to confirm settings (Example 22-4)

////////////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////////////

// STEP 5: Configure CCP1 to serve as AFE clock source (Example 22-3)

/////////////////////////////////////////////////////////////////////////////////////////////

///STEP 6: Configure Interrupt INT0 for use with DR pin (Example 22-3)

/////////////////////////////////////////////////////////////////////////////////////////////

while(1);

}

/////////////////////////////////////////////////////////////////////////////////////////////

//STEP 7: ISR for reading AFE data (Example 22-5)

////////////////////////////////////////////////////////////////////////////////////////////

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EXAMPLE 22-2: INITIALIZING THE MSSP MODULE

EXAMPLE 22-3: AFE CLOCK SOURCE AND INTERRUPT CONFIGURATION

///////////////////////////////////////////////////////////////////////////////////

// STEP 1: Initialize the MSSP in SPI Master mode to access the AFE

// Connections: SCK--SCKA, SDI--SDOA, SDO--SDIA

////////////////////////////////////////////////////////////////////////////////////

SSPCON1bits.CKP = 1; // SPI mode 1,1: idle state for SCK is high,

SSPCON1bits.CKE = 0; // data transmitted on transition from idle to active state

// SSPCON1bits.CKP = 0; // If SPI mode 0,0 is used instead, SCK idle state is low,

// SSPCON1bits.CKE = 1; // data trasmitted on transition from active to idle state

SSPCON1bits.SSPEN = 1; // Enable SPI

TRISCbits.TRISC3 = 0; // define SCK pin as output

TRISCbits.TRISC4 = 1; // define SDI pin as input

TRISCbits.TRISC5 = 0; // define SDO pin as output

///////////////////////////////////////////////////////////////////////////////

// STEP 2: Issue Reset to AFE. ARESET pin is connected to RD0 in this example

/////////////////////////////////////////////////////////////////////////////////////

LATDbits.LATD0 = 0;

TRISDbits.TRISD0=0; // Put the Delta Sigma ADC module in reset

LATDbits.LATD0 = 1; // Release the Delta Sigma ADC module from reset

////////////////////////////////////////////////////////////////////////////////////

// STEP 3:

// Disable all chip selects for all devices connected to SPI, including chip select

// for the AFE. CSA is connected to RD7 in this example

////////////////////////////////////////////////////////////////////////////////////

TRISDbits.TRISD7=0;

LATDbits.LATD7=1;

///////////////////////////////////////////////////////////////////////////////////////////////

// STEP 5: Set up Clock to AFE.

// Connections: In this example CLKIA is connected to CCP1.

///////////////////////////////////////////////////////////////////////////////////////////////

CCP1CON |= 0b00001100; // ccpxm3:ccpxm0 11xx=pwm mode

CCPR1L=0x01; // 50% Duty Cycle Clock

TRISCbits.TRISC2 = 0; // Make RC2 Output; RC2 is connected to CLKIA of AFE

T2CONbits.TMR2ON = 0; // STOP TIMER2 registers to POR state

PR2 = 0x01; // Set period

T2CONbits.TMR2ON = 1; // Turn on PWM1

///////////////////////////////////////////////////////////////////////////////////////////////

// STEP 6: Interrupt Configuration

// DR output of AFE can be used as interrupt. It can be connected to any external interrupt,

// like INT0. It can be declared as low or high priority interrupt.

// This example configures INT0 (connected to DR)as a high-priority interrupt.

///////////////////////////////////////////////////////////////////////////////////////////////

RCONbits.IPEN=1; //Priority Interrupt

INTCON2bits.RBPU=0; //Enable INT0 pull-up; required

INTCON2bits.INTEDG0=0; //Falling edge select; DR is active low pulse

INTCONbits.GIEH = 1; //Enable high pririty interrupts

INTCONbits.INT0IE = 1; //Enable INT0 interrupt

 2010 Microchip Technology Inc. Preliminary DS39979A-page 291

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EXAMPLE 22-4: WRITING AND READING AFE REGISTERS THROUGH THE MSSP

///////////////////////////////////////////////////////////////////////////////////////////////

// STEP 4: Write to AFE registers

// Initialize the AFE by writing to PHASE, GAIN, STATUS, CONFIG1 and CONFIG2 registers.

// Below is an example. The registers can be programmed with values as required

// by the application.

///////////////////////////////////////////////////////////////////////////////////////////////

LATDbits.LATD7=0; //Chipselect enable for Delta Sigma ADC

if (SSPSTATbits.BF==1)

Dummy_Read=SSPBUF;

SSPBUF = 0x0E; //Address and Write command for Gain Register

// A6-A5--->00;A4-A0---->0x07;R/W---0 for write

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF; //Dummy read to clear Buffer Full Status bit

SSPBUF =0x00; //PHASE Register: No Delay

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF;

SSPBUF =0x04; //Address automatically incremented GAIN Register

//CH1 gain 16, CH0 gain 1, No Boost

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF;

SSPBUF = 0xA0; //Address automatically incremented STATUS Register

//Default values

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF;

SSPBUF = 0x10; //Address automatically incrementedData for CONFIG1 Register

//No Dither, Other values are default

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF;

SSPBUF = 0x01; //Address automatically incremented Data for CONFIG2 Register

//CLKEXT bit should be always programmed to 1

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF;

LATDbits.LATD7=1; //Disable chip select after read/write of each set of registers

///////////////////////////////////////////////////////////////////////////////////////////////

// Read from AFE registers to verify; this step is optional and does not affect AFE Operation.

// As an example, only GAIN, STATUS, CONFIG1 and CONFIG2 are read.

///////////////////////////////////////////////////////////////////////////////////////////////

LATDbits.LATD7=0; //Chip select enable for AFE

SSPBUF = 0x11; //Address and Read command for Gain Register

// A6-A5--->00;A4-A0---->0x08;R/W---1 for read

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF; //Dummy read to clear Buffer Full Status bit

SSPBUF =0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data1=SSPBUF; //Data from GAIN Register

SSPBUF =0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data2=SSPBUF; //Data from STATUS Register, Address automatically incremented

SSPBUF =0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data3=SSPBUF; //Data from CONFIG1 Register, Address automatically incremented

SSPBUF = 0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data4=SSPBUF; //Data from CONFIG2 Register, Address automatically incremented

LATDbits.LATD7=1; //Disable chip select after read/write of each set of registers

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EXAMPLE 22-5: READING DATA FROM AFE DURING INTERRUPT

/////////////////////////////////////////////////////////////////////////////////////////////

// STEP 7: Reading AFE results in Interrupt Routine.

// ADC is configured in 16-bit result mode, thus 16-bit result of each Channel can be read.

// In this example DR is connected to INT0; after each convesion, DR issues interrupt to INT0.

// INT0 is configured as high priority interrupt

////////////////////////////////////////////////////////////////////////////////////////////

#pragma interrupt High_isr_routine

void High_isr_routine(void)

{

char D_S_ADC_data1=0,D_S_ADC_data2=0,D_S_ADC_data3=0,D_S_ADC_data4=0,Dummy_Read=0;

if((INTCONbits.INT0IF)&&(INTCONbits.INT0IE))

{

// Disable all Chip selects of other devices connected to SPI

LATDbits.LATD7=0; //Chip select enable for Delta Sigma ADC

SSP1BUF = 0x01; //Address and Read command for Channel0 result MSB register

while(!SSPSTATbits.BF);

Dummy_Read=SSPBUF; //Dummy read to clear Buffer Full Status bit

SSPBUF =0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data1=SSPBUF; //Data from Channel0 MSB

SSPBUF = 0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data2=SSPBUF; //Data from Channel0 LSB, Address automatically incremented

SSPBUF = 0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data3=SSPBUF; //Data from Channel1 MSB, Address automatically incremented

SSPBUF = 0x00;

while(!SSPSTATbits.BF);

D_S_ADC_data4=SSPBUF; //Data from Channel1 LSB, Address automatically incremented

LATDbits.LATD7=1; //Disable chip select after read/write of registers

INTCONbits.INT0IF=0; //Clear INT0IF for next interrupt

}

#pragma code High_isr=0x08

void High_ISR(void)

{

_asm goto High_isr_routine _endasm

}

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23.0 COMPARATOR MODULE

The analog comparator module contains two

comparators that can be configured in a variety of

ways. The inputs can be selected from the analog

inputs multiplexed with pins, RF1 through RF6, as well

as the on-chip voltage reference (see Section 24.0

“Comparator Voltage Reference Module”). The digi-

tal outputs (normal or inverted) are available at the pin

level and can also be read through the control register.

The CMCON register (Register 23-1) selects the

comparator input and output configuration. Block

diagrams of the various comparator configurations are

shown in Figure 23-1.

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1

C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 C2OUT: Comparator 2 Output bit

When C2INV = 0:

1 = C2 VIN+ > C2 VIN-

0 = C2 VIN+ < C2 VIN-

When C2INV = 1:

1 = C2 VIN+ < C2 VIN-

0 = C2 VIN+ > C2 VIN-

bit 6 C1OUT: Comparator 1 Output bit

When C1INV = 0:

1 = C1 VIN+ > C1 VIN-

0 = C1 VIN+ < C1 VIN-

When C1INV = 1:

1 = C1 VIN+ < C1 VIN-

0 = C1 VIN+ > C1 VIN-

bit 5 C2INV: Comparator 2 Output Inversion bit

1 = C2 output is inverted

0 = C2 output is not inverted

bit 4 C1INV: Comparator 1 Output Inversion bit

1 = C1 output is inverted

0 = C1 output is not inverted

bit 3 CIS: Comparator Input Switch bit

When CM<2:0> = 110:

1 =C1 VIN- connects to RF5/AN10/CVREF/SEG23/C1INB

C2 VIN- connects to RF3/AN8/SEG21/C2INB

0 =C1 V

IN- connects to RF6/AN11/SEG24/C1INA

C2 VIN- connects to RF4/AN9/SEG22/C2INA

bit 2-0 CM<2:0>: Comparator Mode bits

Figure 23-1 shows the Comparator modes and the CM<2:0> bit settings.

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DS39979A-page 294 Preliminary  2010 Microchip Technology Inc.

23.1 Comparator Configuration

There are eight modes of operation for the compara-

tors, shown in Figure 23-1. The CM<2:0> bits of the

CMCON register are used to select these modes. The

TRISF register controls the data direction of the

comparator pins for each mode. If the Comparator

mode is changed, the comparator output level may not

be valid for the specified mode change delay shown in

Section 29.0 “Electrical Characteristics”.

FIGURE 23-1: COMPARATOR I/O OPERATING MODES

Note: Comparator interrupts should be disabled

during a Comparator mode change;

otherwise, a false interrupt may occur.

VIN-

VIN+Off (Read as ‘0’)

Comparator Outputs Disabled

CM<2:0> = 000

VIN-

VIN+Off (Read as ‘0’)

VIN-

VIN+C1OUT

Two Independent Comparators

CM<2:0> = 010

VIN-

VIN+C2OUT

VIN-

VIN+C1OUT

Two Common Reference Comparators

CM<2:0> = 100

VIN-

VIN+C2OUT

VIN-

VIN+Off (Read as ‘0’)

One Independent Comparator with Output

CM<2:0> = 001

VIN-

VIN+C1OUT

VIN-

VIN+Off (Read as ‘0’)

Comparators Off (POR Default Value)

CM<2:0> = 111

VIN-

VIN+Off (Read as ‘0’)

VIN-

VIN+C1OUT

Four Inputs Multiplexed to Two Comparators

CM<2:0> = 110

VIN-

VIN+C2OUT

From VREF module

CIS = 0

CIS = 1

CIS = 0

CIS = 1

VIN-

VIN+C1OUT

Two Common Reference Comparators with Outputs

CM<2:0> = 101

VIN-

VIN+C2OUT

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch

CVREF

VIN-

VIN+C1OUT

Two Independent Comparators with Outputs

CM<2:0> = 011

VIN-

VIN+C2OUT

RF1/AN6/C2OUT*/SEG19

RF2/AN7/C1OUT*/SEG20

* Setting the TRISF<2:1> bits will disable the comparator outputs by configuring the pins as inputs.

C1INA

C1INB

C2INA

C2INB

C1INB

C2INA

C2INB

C1INA

C1INB

C2INA

RF2/AN7/C1OUT*/SEG20

RF1/AN6/C2OUT*/SEG19

RF2/AN7/C1OUT*/

SEG20

C1INA

C1INB

C2INA

C2INB

C1INA

C1INB

C2INA

C2INB

C1INA

C1INB

C2INA

C2INB

C1INA

C1INB

C2INA

C2INB

C1INA

C1INB

C2INA

C2INB

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23.2 Comparator Operation

A single comparator is shown in Figure 23-2, along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 23-2 represent

the uncertainty due to input offsets and response time.

23.3 Comparator Reference

Depending on the comparator operating mode, either

an external or internal voltage reference may be used.

The analog signal present at VIN- is compared to the

signal at VIN+ and the digital output of the comparator

is adjusted accordingly (Figure 23-2).

FIGURE 23-2: SINGLE COMPARATOR

23.3.1 EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the

comparator module can be configured to have the com-

parators operate from the same or different reference

sources. However, threshold detector applications may

require the same reference. The reference signal must

be between VSS and VDD and can be applied to either

pin of the comparator(s).

23.3.2 INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an

internally generated voltage reference from the

comparator voltage reference module. This module is

described in more detail in Section 24.0 “Comparator

Voltage Reference Module”.

The internal reference is only available in the mode

where four inputs are multiplexed to two comparators

(CM<2:0> = 110). In this mode, the internal voltage

reference is applied to the VIN+ pin of both comparators.

23.4 Comparator Response Time

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output has a valid level. If the internal ref-

erence is changed, the maximum delay of the internal

voltage reference must be considered when using the

comparator outputs. Otherwise, the maximum delay of

the comparators should be used (see Section 29.0

“Electrical Characteristics”).

23.5 Comparator Outputs

The comparator outputs are read through the CMCON

outputs may also be directly output to the RF1 and RF2

I/O pins. When enabled, multiplexers in the output path

of the RF1 and RF2 pins will switch and the output of

each pin will be the unsynchronized output of the

comparator. The uncertainty of each of the

comparators is related to the input offset voltage and

the response time given in the specifications.

Figure 23-3 shows the comparator output block

diagram.

The TRISF bits will still function as an output enable/

disable for the RF1 and RF2 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C2INV and C1INV bits (CMCON<5:4>).

–

VIN+

VIN-

Output

VIN-

VIN+

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as

‘0’. Pins configured as digital inputs will

convert an analog input according to the

Schmitt Trigger input specification.

2: Analog levels on any pin defined as a

digital input may cause the input buffer to

consume more current than is specified.

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DS39979A-page 296 Preliminary  2010 Microchip Technology Inc.

FIGURE 23-3: COMPARATOR OUTPUT BLOCK DIAGRAM

23.6 Comparator Interrupts

The comparator interrupt flag is set whenever there is

a change in the output value of either comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON<7:6>, to

determine the actual change that occurred. The CMIF

bit (PIR2<6>) is the Comparator Interrupt Flag. The

CMIF bit must be reset by clearing it. Since it is also

possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

Both the CMIE bit (PIE2<6>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupt. In

addition, the GIE bit (INTCON<7>) must also be set. If

any of these bits are clear, the interrupt is not enabled,

though the CMIF bit will still be set if an interrupt

condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON will end the

mismatch condition.

b) Clear flag bit, CMIF.

A mismatch condition will continue to set flag bit, CMIF.

Reading CMCON will end the mismatch condition and

allow flag bit, CMIF, to be cleared.

23.7 Comparator Operation

During Sleep

When a comparator is active and the device is placed

in Sleep mode, the comparator remains active and the

interrupt is functional, if enabled. This interrupt will

wake-up the device from Sleep mode, when enabled.

Each operational comparator will consume additional

current, as shown in the comparator specifications. To

minimize power consumption while in Sleep mode, turn

off the comparators (CM<2:0> = 111) before entering

Sleep. If the device wakes up from Sleep, the contents

of the CMCON register are not affected.

23.8 Effects of a Reset

A device Reset forces the CMCON register to its Reset

state, causing the comparator modules to be turned off

(CM<2:0> = 111). However, the input pins (RF3

through RF6) are configured as analog inputs by

default on device Reset. The I/O configuration for these

pins is determined by the setting of the PCFG<3:0> bits

(ADCON1<3:0>). Therefore, device current is

minimized when analog inputs are present at Reset

time.

To RF1 or

RF2 Pin

Bus

Data

Set

MULTIPLEX

CMIF

bit

Port Pins

Read CMCON

Reset

From

Other

Comparator

CxINV

EN CL

Note: If a change in the CMCON register

(C1OUT or C2OUT) should occur when a

read operation is being executed (start of

the Q2 cycle), then the CMIF (PIR2<6>)

interrupt flag may not get set.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 297

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23.9 Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 23-4. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up condition may

occur. A maximum source impedance of 10 k is

recommended for the analog sources. Any external

component connected to an analog input pin, such as

a capacitor or a Zener diode, should have very little

leakage current.

FIGURE 23-4: COMPARATOR ANALOG INPUT MODEL

TABLE 23-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 49

PIR2 OSCFIF CMIF — — BCLIF LVDIF TMR3IF —52

PIE2 OSCFIE CMIE — — BCLIE LVDIE TMR3IE —52

IPR2 OSCFIP CMIP — — BCLIP LVDIP TMR3IP —52

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 —52

LATF LATF7 LATF6 LATF5 LATF4 LATF3 LATF2 LATF1 —52

TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the comparator module.

RS < 10k

AIN

CPIN

5 pF

VDD

VT = 0.6V

RIC

ILEAKAGE

±100 nA

VSS

Legend: CPIN = Input Capacitance

VT= Threshold Voltage

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS= Source Impedance

VA = Analog Voltage

Comparator

Input

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NOTES:

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24.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The comparator voltage reference is a 16-tap resistor

ladder network that provides a selectable reference

voltage. Although its primary purpose is to provide a

reference for the analog comparators, it may also be

used independently of them.

A block diagram of the module is shown in Figure 24-1.

The resistor ladder is segmented to provide two ranges

of CVREF values and has a power-down function to

conserve power when the reference is not being used.

The module’s supply reference can be provided from

either device VDD/VSS or an external voltage reference.

24.1 Configuring the Comparator

Voltage Reference

The comparator voltage reference module is controlled

through the CVRCON register (Register 24-1). The

comparator voltage reference provides two ranges of

output voltage, each with 16 distinct levels.

The range to be used is selected by the CVRR bit

(CVRCON<5>). The primary difference between the

ranges is the size of the steps selected by the CVREF

Selection bits (CVR<3:0>), with one range offering finer

resolution. The equations used to calculate the output

of the comparator voltage reference are as follows:

If CVRR = 1:

CVREF = ((CVR<3:0>)/24) x (CVRSRC)

If CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR<3:0>)/32) x (CVRSRC)

The comparator reference supply voltage can come

from either VDD and VSS, or the external VREF+ and

VREF- that are multiplexed with RA2 and RA3. The

voltage source is selected by the CVRSS bit

(CVRCON<4>).

The settling time of the comparator voltage reference

must be considered when changing the CVREF

output (see Table 29-3 in Section 29.0 “Electrical

Characteristics”).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CVREN CVROE(1) CVRR CVRSS CVR3 CVR2 CVR1 CVR0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CVREN: Comparator Voltage Reference Enable bit

1 =CV

REF circuit powered on

0 =CV

REF circuit powered down

bit 6 CVROE: Comparator VREF Output Enable bit(1)

1 =CVREF voltage level is also output on the RF5/AN10/CVREF/SEG23/C1INB pin

0 =CV

REF voltage is disconnected from the RF5/AN10/CVREF/SEG23/C1INB pin

bit 5 CVRR: Comparator VREF Range Selection bit

1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range)

0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range)

bit 4 CVRSS: Comparator VREF Source Selection bit

1 = Comparator reference source, CVRSRC = (VREF+) – (VREF-)

0 = Comparator reference source, CVRSRC = VDD – VSS

bit 3-0 CVR<3:0>: Comparator VREF Value Selection bits (0  (CVR<3:0>)  15)

When CVRR = 1:

CVREF = ((CVR<3:0>)/24)  (CVRSRC)

When CVRR = 0:

CVREF = (CVRSRC/4) + ((CVR<3:0>)/32)  (CVRSRC)

Note 1: CVROE overrides the TRISF<5> bit setting.

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DS39979A-page 300 Preliminary  2010 Microchip Technology Inc.

FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

24.2 Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized

due to the construction of the module. The transistors

on the top and bottom of the resistor ladder network

(Figure 24-1) keep CVREF from approaching the refer-

ence source rails. The voltage reference is derived

from the reference source; therefore, the CVREF output

changes with fluctuations in that source. The tested

absolute accuracy of the voltage reference can be

found in Section 29.0 “Electrical Characteristics”.

24.3 Operation During Sleep

When the device wakes up from Sleep through an

interrupt or a Watchdog Timer time-out, the contents of

the CVRCON register are not affected. To minimize

current consumption in Sleep mode, the voltage

reference should be disabled.

24.4 Effects of a Reset

A device Reset disables the voltage reference by

clearing bit, CVREN (CVRCON<7>). This Reset also

disconnects the reference from the RA2 pin by clearing

bit, CVROE (CVRCON<6>) and selects the high-voltage

range by clearing bit, CVRR (CVRCON<5>). The CVR

value select bits are also cleared.

24.5 Connection Considerations

The voltage reference module operates independently

of the comparator module. The output of the reference

generator may be connected to the RF5 pin if the

CVROE bit is set. Enabling the voltage reference out-

put onto RA2 when it is configured as a digital input will

increase current consumption. Connecting RF5 as a

digital output with CVRSS enabled will also increase

current consumption.

The RF5 pin can be used as a simple D/A output with

limited drive capability. Due to the limited current drive

capability, a buffer must be used on the voltage

reference output for external connections to VREF.

Figure 24-2 shows an example buffering technique.

16-to-1 MUX

CVR<3:0>

CVREN

CVRSS = 0

VDD

VREF+CVRSS = 1

CVRSS = 0

VREF-CVRSS = 1

16 Steps

CVRR

CVREF

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FIGURE 24-2: COMPARATOR VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

TABLE 24-1: REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page

CVRCON CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 51

CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 51

TRISF TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 —52

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used with the comparator voltage reference.

CVREF Output

–

CVREF

Module

Voltage

Reference

Output

Impedance

R(1)

RF5

Note 1: R is dependent upon the Comparator Voltage Reference bits, CVRCON<5> and CVRCON<3:0>.

PIC18F87J72

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NOTES:

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25.0 CHARGE TIME

MEASUREMENT UNIT (CTMU)

The Charge Time Measurement Unit (CTMU) is a

flexible analog module that provides accurate differen-

tial time measurement between pulse sources, as well

as asynchronous pulse generation. By working with

other on-chip analog modules, the CTMU can be used

to precisely measure time, measure capacitance,

measure relative changes in capacitance or generate

output pulses with a specific time delay. The CTMU is

ideal for interfacing with capacitive-based sensors.

The module includes the following key features:

• Up to 13 channels available for capacitive or time

measurement input

• On-chip precision current source

• Four-edge input trigger sources

• Polarity control for each edge source

• Control of edge sequence

• Control of response to edges

• Time measurement resolution of 1 nanosecond

• High-precision time measurement

• Time delay of external or internal signal

asynchronous to system clock

• Accurate current source suitable for capacitive

measurement

The CTMU works in conjunction with the A/D Converter

to provide up to 13 channels for time or charge

measurement, depending on the specific device and

the number of A/D channels available. When config-

ured for time delay, the CTMU is connected to one of

the analog comparators. The level-sensitive input edge

sources can be selected from four sources: two

external inputs or CCP1/CCP2 Special Event Triggers.

Figure 25-1 provides a block diagram of the CTMU.

FIGURE 25-1: CTMU BLOCK DIAGRAM

CTEDG1

CTEDG2

Current Source

Edge

Control

Logic

CTMUCON

Pulse

Generator

A/D Converter Comparator 2

Input

CCP2

CCP1

Current

Control

ITRIM<5:0>

IRNG<1:0>

CTMUICON

CTMU

Control

Logic

EDGEN

EDGSEQEN

EDG1SELx

EDG1POL

EDG2SELx

EDG2POL

EDG1STAT

EDG2STAT

TGEN

IDISSEN

CTTRIG

A/D Trigger

CTPLS

Comparator 2 Output

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DS39979A-page 304 Preliminary  2010 Microchip Technology Inc.

25.1 CTMU Operation

The CTMU works by using a fixed current source to

charge a circuit. The type of circuit depends on the type

of measurement being made. In the case of charge

measurement, the current is fixed, and the amount of

time the current is applied to the circuit is fixed. The

amount of voltage read by the A/D is then a measure-

ment of the capacitance of the circuit. In the case of

time measurement, the current, as well as the capaci-

tance of the circuit, is fixed. In this case, the voltage

read by the A/D is then representative of the amount of

time elapsed from the time the current source starts

and stops charging the circuit.

If the CTMU is being used as a time delay, both capaci-

tance and current source are fixed, as well as the voltage

supplied to the comparator circuit. The delay of a signal

is determined by the amount of time it takes the voltage

to charge to the comparator threshold voltage.

25.1.1 THEORY OF OPERATION

The operation of the CTMU is based on the equation

for charge:

More simply, the amount of charge measured in

coulombs in a circuit is defined as current in amperes

(I) multiplied by the amount of time in seconds that the

current flows (t). Charge is also defined as the capaci-

tance in farads (C) multiplied by the voltage of the

circuit (V). It follows that:

The CTMU module provides a constant, known current

source. The A/D Converter is used to measure (V) in

the equation, leaving two unknowns: capacitance (C)

and time (t). The above equation can be used to calcu-

late capacitance or time, by either the relationship

using the known fixed capacitance of the circuit:

or by:

using a fixed time that the current source is applied to

the circuit.

25.1.2 CURRENT SOURCE

At the heart of the CTMU is a precision current source,

designed to provide a constant reference for measure-

ments. The level of current is user-selectable across

three ranges or a total of two orders of magnitude, with

the ability to trim the output in ±2% increments

(nominal). The current range is selected by the

IRNG<1:0> bits (CTMUICON<1:0>), with a value of

‘00’ representing the lowest range.

Current trim is provided by the ITRIM<5:0> bits

(CTMUICON<7:2>). These six bits allow trimming of

the current source in steps of approximately 2% per

step. Note that half of the range adjusts the current

source positively and the other half reduces the current

source. A value of ‘000000’ is the neutral position (no

change). A value of ‘100000’ is the maximum negative

adjustment (approximately -62%) and ‘011111’ is the

maximum positive adjustment (approximately +62%).

25.1.3 EDGE SELECTION AND CONTROL

CTMU measurements are controlled by edge events

occurring on the module’s two input channels. Each

channel, referred to as Edge 1 and Edge 2, can be con-

figured to receive input pulses from one of the edge

input pins (CTEDG1 and CTEDG2) or CCPx Special

Event Triggers. The input channels are level-sensitive,

responding to the instantaneous level on the channel

rather than a transition between levels. The inputs are

selected using the EDG1SEL and EDG2SEL bit pairs

(CTMUCONL<3:2, 6:5>).

In addition to source, each channel can be configured for

event polarity using the EDGE2POL and EDGE1POL

bits (CTMUCONL<7,4>). The input channels can also

be filtered for an edge event sequence (Edge 1 occur-

ring before Edge 2) by setting the EDGSEQEN bit

(CTMUCONH<2>).

25.1.4 EDGE STATUS

The CTMUCON register also contains two status bits,

EDG2STAT and EDG1STAT (CTMUCONL<1:0>).

Their primary function is to show if an edge response

has occurred on the corresponding channel. The

CTMU automatically sets a particular bit when an edge

response is detected on its channel. The level-sensitive

nature of the input channels also means that the status

bits become set immediately if the channel’s configura-

tion is changed and is the same as the channel’s

current state.

The module uses the edge status bits to control the cur-

rent source output to external analog modules (such as

the A/D Converter). Current is only supplied to external

modules when only one (but not both) of the status bits

is set, and shuts current off when both bits are either

set or cleared. This allows the CTMU to measure cur-

rent only during the interval between edges. After both

status bits are set, it is necessary to clear them before

another measurement is taken. Both bits should be

cleared simultaneously, if possible, to avoid re-enabling

the CTMU current source.

In addition to being set by the CTMU hardware, the

edge status bits can also be set by software. This is

also the user’s application to manually enable or dis-

able the current source. Setting either one (but not

both) of the bits enables the current source. Setting or

clearing both bits at once disables the source.

-------=

ItCV.=

tCVI=

CItV=

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25.1.5 INTERRUPTS

The CTMU sets its interrupt flag (PIR3<2>) whenever

the current source is enabled, then disabled. An inter-

rupt is generated only if the corresponding interrupt

enable bit (PIE3<2>) is also set. If edge sequencing is

not enabled (i.e., Edge 1 must occur before Edge 2), it

is necessary to monitor the edge status bits and

determine which edge occurred last and caused the

interrupt.

25.2 CTMU Module Initialization

The following sequence is a general guideline used to

initialize the CTMU module:

1. Select the current source range using the IRNG

bits (CTMUICON<1:0>).

2. Adjust the current source trim using the ITRIM

bits (CTMUICON<7:2>).

3. Configure the edge input sources for Edge 1 and

Edge 2 by setting the EDG1SEL and EDG2SEL

bits (CTMUCONL<3:2 and 6:5>).

4. Configure the input polarities for the edge inputs

using the EDG1POL and EDG2POL bits

(CTMUCONL<4,7>). The default configuration

is for negative edge polarity (high-to-low

transitions).

5. Enable edge sequencing using the EDGSEQEN

bit (CTMUCONH<2>). By default, edge

sequencing is disabled.

6. Select the operating mode (Measurement or

Time Delay) with the TGEN bit. The default

mode is Time/Capacitance Measurement.

7. Configure the module to automatically trigger

an A/D conversion when the second edge

event has occurred using the CTTRIG bit

(CTMUCONH<0>). The conversion trigger is

disabled by default.

8. Discharge the connected circuit by setting the

IDISSEN bit (CTMUCONH<1>); after waiting a

sufficient time for the circuit to discharge, clear

IDISSEN.

9. Disable the module by clearing the CTMUEN bit

(CTMUCONH<7>).

10. Clear the Edge Status bits, EDG2STAT and

EDG1STAT (CTMUCONL<1:0>).

11. Enable both edge inputs by setting the EDGEN

bit (CTMUCONH<3>).

12. Enable the module by setting the CTMUEN bit.

Depending on the type of measurement or pulse

generation being performed, one or more additional

modules may also need to be initialized and configured

with the CTMU module:

• Edge Source Generation: In addition to the

external edge input pins, CCPx Special Event

Triggers can be used as edge sources for the

CTMU.

• Capacitance or Time Measurement: The CTMU

module uses the A/D Converter to measure the

voltage across a capacitor that is connected to one

of the analog input channels.

• Pulse Generation: When generating system clock

independent output pulses, the CTMU module

uses Comparator 2 and the associated

comparator voltage reference.

25.3 Calibrating the CTMU Module

The CTMU requires calibration for precise measure-

ments of capacitance and time, as well as for accurate

time delay. If the application only requires measurement

of a relative change in capacitance or time, calibration is

usually not necessary. An example of this type of appli-

cation would include a capacitive touch switch, in which

the touch circuit has a baseline capacitance, and the

added capacitance of the human body changes the

overall capacitance of a circuit.

If actual capacitance or time measurement is required,

two hardware calibrations must take place: the current

source needs calibration to set it to a precise current,

and the circuit being measured needs calibration to

measure and/or nullify all other capacitance other than

that to be measured.

25.3.1 CURRENT SOURCE CALIBRATION

The current source onboard the CTMU module has a

range of ±60% nominal for each of three current

ranges. Therefore, for precise measurements, it is

possible to measure and adjust this current source by

placing a high-precision resistor, RCAL, onto an unused

analog channel. An example circuit is shown in

Figure 25-2. The current source measurement is

performed using the following steps:

1. Initialize the A/D Converter.

2. Initialize the CTMU.

3. Enable the current source by setting EDG1STAT

(CTMUCONL<0>).

4. Issue settling time delay.

5. Perform A/D conversion.

6. Calculate the current source current using

I=V/RCAL, where RCAL is a high-precision

resistance and V is measured by performing an

A/D conversion.

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The CTMU current source may be trimmed with the

trim bits in CTMUICON using an iterative process to get

an exact desired current. Alternatively, the nominal

value without adjustment may be used; it may be

stored by the software for use in all subsequent

capacitive or time measurements.

To calculate the value for RCAL, the nominal current

must be chosen, and then the resistance can be

calculated. For example, if the A/D Converter reference

voltage is 3.3V, use 70% of full scale or 2.31V as the

desired approximate voltage to be read by the A/D

Converter. If the range of the CTMU current source is

selected to be 0.55 A, the resistor value needed is cal-

culated as RCAL = 2.31V/0.55 A, for a value of 4.2 MΩ.

Similarly, if the current source is chosen to be 5.5 A,

RCAL would be 420,000Ω, and 42,000Ω if the current

source is set to 55 A.

FIGURE 25-2: CTMU CURRENT SOURCE

CALIBRATION CIRCUIT

A value of 70% of full-scale voltage is chosen to make

sure that the A/D Converter was in a range that is well

above the noise floor. Keep in mind that if an exact cur-

rent is chosen to incorporate the trimming bits from

CTMUICON, the resistor value of RCAL may need to be

adjusted accordingly. RCAL may be also adjusted to

allow for available resistor values. RCAL should be of

the highest precision available, keeping in mind the

amount of precision needed for the circuit that the

CTMU will be used to measure. A recommended

minimum would be 0.1% tolerance.

The following examples show one typical method for

performing a CTMU current calibration. Example 25-1

demonstrates how to initialize the A/D Converter and the

CTMU. This routine is typical for applications using both

modules. Example 25-2 demonstrates one method for

the actual calibration routine. Note that this method

manually triggers the A/D Converter, which is done to

demonstrate the entire stepwise process. It is also

possible to automatically trigger the conversion by

setting the CTMU’s CTTRIG bit (CTMUCONH<0>).

A/D Converter

CTMU

ANx

RCAL

Current Source

A/D

Trigger

MUX

A/D

PIC18F87J72

 2010 Microchip Technology Inc. Preliminary DS39979A-page 307

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EXAMPLE 25-1: SETUP FOR CTMU CALIBRATION ROUTINES

#include "p18cxxx.h"

/**************************************************************************/

/*Setup CTMU *****************************************************************/

/**************************************************************************/

void setup(void)

{ //CTMUCON - CTMU Control register

CTMUCONH = 0x00; //make sure CTMU is disabled

CTMUCONL = 0X90;

//CTMU continues to run when emulator is stopped,CTMU continues

//to run in idle mode,Time Generation mode disabled, Edges are blocked

//No edge sequence order, Analog current source not grounded, trigger

//output disabled, Edge2 polarity = positive level, Edge2 source =

//source 0, Edge1 polarity = positive level, Edge1 source = source 0,

// Set Edge status bits to zero

//CTMUICON - CTMU Current Control Register

CTMUICON = 0x01; //0.55uA, Nominal - No Adjustment

/**************************************************************************/

//Setup AD converter;

/**************************************************************************/

TRISA=0x04; //set channel 2 as an input

// Configured AN2 as an analog channel

// ANCON0

ANCON0 = 0XFB;

// ANCON1

ANCON1 = 0X1F;

// ADCON1

ADCON1bits.ADFM=1; // Resulst format 1= Right justified

ADCON1bits.ADCAL=0; // Normal A/D conversion operation

ADCON1bits.ACQT=1; // Acquition time 7 = 20TAD 2 = 4TAD 1=2TAD

ADCON1bits.ADCS=2; // Clock conversion bits 6= FOSC/64 2=FOSC/32

ANCON1bits.VBGEN=1; // Turn on the Bandgap needed for Rev A0 parts

// ADCON0

ADCON0bits.VCFG0 =0; // Vref+ = AVdd

ADCON0bits.VCFG1 =0; // Vref- = AVss

ADCON0bits.CHS=2; // Select ADC channel

ADCON0bits.ADON=1; // Turn on ADC

}

PIC18F87J72 FAMILY

DS39979A-page 308 Preliminary  2010 Microchip Technology Inc.

EXAMPLE 25-2: CURRENT CALIBRATION ROUTINE

#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)

#define RCAL .027 //R value is 4200000 (4.2M)

//scaled so that result is in

//1/100th of uA

#define ADSCALE 1023 //for unsigned conversion 10 sig bits

#define ADREF 3.3 //Vdd connected to A/D Vr+

int main(void)

{

int i;

int j = 0; //index for loop

unsigned int Vread = 0;

double VTot = 0;

float Vavg=0, Vcal=0, CTMUISrc = 0; //float values stored for calcs

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

for(j=0;j<10;j++)

{

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag

VTot += Vread; //Add the reading to the total

}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);

CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA

}

 2010 Microchip Technology Inc. Preliminary DS39979A-page 309

PIC18F87J72 FAMILY

25.3.2 CAPACITANCE CALIBRATION

There is a small amount of capacitance from the inter-

nal A/D Converter sample capacitor as well as stray

capacitance from the circuit board traces and pads that

affect the precision of capacitance measurements. A

measurement of the stray capacitance can be taken by

making sure the desired capacitance to be measured

has been removed. The measurement is then

performed using the following steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT (= 1).

3. Wait for a fixed delay of time, t.

4. Clear EDG1STAT.

5. Perform an A/D conversion.

6. Calculate the stray and A/D sample capacitances:

where I is known from the current source measurement

step, t is a fixed delay and V is measured by performing

an A/D conversion.

This measured value is then stored and used for

calculations of time measurement, or subtracted for

capacitance measurement. For calibration, it is

expected that the capacitance of CSTRAY +CAD is

approximately known. CAD is approximately 4 pF.

An iterative process may need to be used to adjust the

time, t, that the circuit is charged to obtain a reasonable

voltage reading from the A/D Converter. The value of t

may be determined by setting COFFSET to a theoretical

value, then solving for t. For example, if CSTRAY is

theoretically calculated to be 11 pF, and V is expected

to be 70% of VDD, or 2.31V, then t would be:

or 63 s.

See Example 25-3 for a typical routine for CTMU

capacitance calibration.

COFFSET CSTRAY CAD

+ItV==

(4 pF + 11 pF) • 2.31V/0.55 A

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DS39979A-page 310 Preliminary  2010 Microchip Technology Inc.

EXAMPLE 25-3: CAPACITANCE CALIBRATION ROUTINE

#include "p18cxxx.h"

#define COUNT 25 //@ 8MHz INTFRC = 62.5 us.

#define ETIME COUNT*2.5 //time in uS

#define DELAY for(i=0;i<COUNT;i++)

#define ADSCALE 1023 //for unsigned conversion 10 sig bits

#define ADREF 3.3 //Vdd connected to A/D Vr+

#define RCAL .027 //R value is 4200000 (4.2M)

//scaled so that result is in

//1/100th of uA

int main(void)

{

int i;

int j = 0; //index for loop

unsigned int Vread = 0;

float CTMUISrc, CTMUCap, Vavg, VTot, Vcal;

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

for(j=0;j<10;j++)

{

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

PIR1bits.ADIF = 0; //Clear A/D Interrupt Flag

VTot += Vread; //Add the reading to the total

}

Vavg = (float)(VTot/10.000); //Average of 10 readings

Vcal = (float)(Vavg/ADSCALE*ADREF);

CTMUISrc = Vcal/RCAL; //CTMUISrc is in 1/100ths of uA

CTMUCap = (CTMUISrc*ETIME/Vcal)/100;

}

 2010 Microchip Technology Inc. Preliminary DS39979A-page 311

PIC18F87J72 FAMILY

25.4 Measuring Capacitance with the

CTMU

There are two separate methods of measuring capaci-

tance with the CTMU. The first is the absolute method,

in which the actual capacitance value is desired. The

second is the relative method, in which the actual

capacitance is not needed, rather an indication of a

change in capacitance is required.

25.4.1 ABSOLUTE CAPACITANCE

MEASUREMENT

For absolute capacitance measurements, both the

current and capacitance calibration steps found in

Section 25.3 “Calibrating the CTMU Module” should

be followed. Capacitance measurements are then

performed using the following steps:

1. Initialize the A/D Converter.

2. Initialize the CTMU.

3. Set EDG1STAT.

4. Wait for a fixed delay, T.

5. Clear EDG1STAT.

6. Perform an A/D conversion.

7. Calculate the total capacitance, CTOTAL = (I * T)/V,

where I is known from the current source

measurement step (Section 25.3.1 “Current

Source Calibration”), T is a fixed delay and V is

measured by performing an A/D conversion.

8. Subtract the stray and A/D capacitance

(COFFSET from Section 25.3.2 “Capacitance

Calibration”) from CTOTAL to determine the

measured capacitance.

25.4.2 RELATIVE CHARGE

MEASUREMENT

An application may not require precise capacitance

measurements. For example, when detecting a valid

press of a capacitance-based switch, detecting a relative

change of capacitance is of interest. In this type of appli-

cation, when the switch is open (or not touched), the total

capacitance is the capacitance of the combination of the

board traces, the A/D Converter, etc. A larger voltage will

be measured by the A/D Converter. When the switch is

closed (or is touched), the total capacitance is larger due

to the addition of the capacitance of the human body to

the above listed capacitances and a smaller voltage will

be measured by the A/D Converter.

Detecting capacitance changes is easily accomplished

with the CTMU using these steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT.

3. Wait for a fixed delay.

4. Clear EDG1STAT.

5. Perform an A/D conversion.

The voltage measured by performing the A/D conver-

sion is an indication of the relative capacitance. Note

that in this case, no calibration of the current source or

circuit capacitance measurement is needed. See

Example 25-4 for a sample software routine for a

capacitive touch switch.

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DS39979A-page 312 Preliminary  2010 Microchip Technology Inc.

EXAMPLE 25-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH

#include "p18cxxx.h"

#define COUNT 500 //@ 8MHz = 125uS.

#define DELAY for(i=0;i<COUNT;i++)

#define OPENSW 1000 //Un-pressed switch value

#define TRIP 300 //Difference between pressed

//and un-pressed switch

#define HYST 65 //amount to change

//from pressed to un-pressed

#define PRESSED 1

#define UNPRESSED 0

int main(void)

{

unsigned int Vread; //storage for reading

unsigned int switchState;

int i;

//assume CTMU and A/D have been setup correctly

//see Example 25-1 for CTMU & A/D setup

setup();

CTMUCONHbits.CTMUEN = 1; //Enable the CTMU

CTMUCONHbits.IDISSEN = 1; //drain charge on the circuit

DELAY; //wait 125us

CTMUCONHbits.IDISSEN = 0; //end drain of circuit

CTMUCONLbits.EDG1STAT = 1; //Begin charging the circuit

//using CTMU current source

DELAY; //wait for 125us

CTMUCONLbits.EDG1STAT = 0; //Stop charging circuit

PIR1bits.ADIF = 0; //make sure A/D Int not set

ADCON0bits.GO=1; //and begin A/D conv.

while(!PIR1bits.ADIF); //Wait for A/D convert complete

Vread = ADRES; //Get the value from the A/D

if(Vread < OPENSW - TRIP)

{

switchState = PRESSED;

}

else if(Vread > OPENSW - TRIP + HYST)

{

switchState = UNPRESSED;

}

 2010 Microchip Technology Inc. Preliminary DS39979A-page 313

PIC18F87J72 FAMILY

25.5 Measuring Time with the CTMU

Module

Time can be precisely measured after the ratio (C/I) is

measured from the current and capacitance calibration

step by following these steps:

1. Initialize the A/D Converter and the CTMU.

2. Set EDG1STAT.

3. Set EDG2STAT.

4. Perform an A/D conversion.

5. Calculate the time between edges as T = (C/I) * V,

where I is calculated in the current calibration step

(Section 25.3.1 “Current Source Calibration”),

C is calculated in the capacitance calibration step

(Section 25.3.2 “Capacitance Calibration”) and

V is measured by performing the A/D conversion.

It is assumed that the time measured is small enough

that the capacitance COFFSET provides a valid voltage to

the A/D Converter. For the smallest time measurement,

always set the A/D Channel Select register (AD1CHS)

to an unused A/D channel; the corresponding pin for

which is not connected to any circuit board trace. This

minimizes added stray capacitance, keeping the total

circuit capacitance close to that of the A/D Converter

itself (25 pF). To measure longer time intervals, an

external capacitor may be connected to an A/D

channel, and this channel selected when making a time

measurement.

FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME

MEASUREMENT

A/D Converter

CTMU

CTEDG1

CTEDG2

ANX

Output

Pulse

EDG1

EDG2

CAD

RPR

Current Source

PIC18F87J72

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DS39979A-page 314 Preliminary  2010 Microchip Technology Inc.

25.6 Creating a Delay with the CTMU

Module

A unique feature on board the CTMU module is its ability

to generate system clock independent output pulses

based on an external capacitor value. This is accom-

plished using the internal comparator voltage reference

module, Comparator 2 input pin and an external capaci-

tor. The pulse is output onto the CTPLS pin. To enable

this mode, set the TGEN bit.

See Figure 25-4 for an example circuit. CPULSE is

chosen by the user to determine the output pulse width

on CTPLS. The pulse width is calculated by

T=(CPULSE /I)*V, where I is known from the current

source measurement step (Section 25.3.1 “Current

Source Calibration”) and V is the internal reference

voltage (CVREF).

An example use of this feature is for interfacing with

variable capacitive-based sensors, such as a humidity

sensor. As the humidity varies, the pulse-width output

on CTPLS will vary. The CTPLS output pin can be con-

nected to an input capture pin and the varying pulse

width is measured to determine the humidity in the

application.

Follow these steps to use this feature:

1. Initialize Comparator 2.

2. Initialize the comparator voltage reference.

3. Initialize the CTMU and enable time delay

generation by setting the TGEN bit.

4. Set EDG1STAT.

5. When CPULSE charges to the value of the voltage

reference trip point, an output pulse is generated

on CTPLS.

FIGURE 25-4: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY

GENERATION

25.7 Operation During Sleep/Idle Modes

25.7.1 SLEEP MODE AND DEEP SLEEP

MODES

When the device enters any Sleep mode, the CTMU

module current source is always disabled. If the CTMU

is performing an operation that depends on the current

source when Sleep mode is invoked, the operation may

not terminate correctly. Capacitance and time

measurements may return erroneous values.

25.7.2 IDLE MODE

The behavior of the CTMU in Idle mode is determined

by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL

is cleared, the module will continue to operate in Idle

mode. If CTMUSIDL is set, the module’s current source

is disabled when the device enters Idle mode. If the

module is performing an operation when Idle mode is

invoked, in this case, the results will be similar to those

with Sleep mode.

25.8 Effects of a Reset on CTMU

Upon Reset, all registers of the CTMU are cleared. This

leaves the CTMU module disabled, its current source is

turned off and all configuration options return to their

default settings. The module needs to be re-initialized

following any Reset.

If the CTMU is in the process of taking a measurement

at the time of Reset, the measurement will be lost. A

partial charge may exist on the circuit that was being

measured, and should be properly discharged before

the CTMU makes subsequent attempts to make a

measurement. The circuit is discharged by setting and

then clearing the IDISSEN bit (CTMUCONH<1>) while

the A/D Converter is connected to the appropriate

channel.

CVREF

CTPLS

Current Source

Comparator

CTMU

CTEDG1

C2INB

CDELAY

EDG1

PIC18F87J72

 2010 Microchip Technology Inc. Preliminary DS39979A-page 315

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25.9 Registers

There are three control registers for the CTMU:

• CTMUCONH

• CTMUCONL

• CTMUICON

The CTMUCONH and CTMUCONL registers

(Register 25-1 and Register 25-2) contain control bits

for configuring the CTMU module edge source selec-

tion, edge source polarity selection, edge sequencing,

A/D trigger, analog circuit capacitor discharge and

enables. The CTMUICON register (Register 25-3) has

bits for selecting the current source range and current

source trim.

R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 CTMUEN: CTMU Enable bit

1 = Module is enabled

0 = Module is disabled

bit 6 Unimplemented: Read as ‘0’

bit 5 CTMUSIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

bit 4 TGEN: Time Generation Enable bit

1 = Enables edge delay generation

0 = Disables edge delay generation

bit 3 EDGEN: Edge Enable bit

1 = Edges are not blocked

0 = Edges are blocked

bit 2 EDGSEQEN: Edge Sequence Enable bit

1 = Edge 1 event must occur before Edge 2 event can occur

0 = No edge sequence is needed

bit 1 IDISSEN: Analog Current Source Control bit

1 = Analog current source output is grounded

0 = Analog current source output is not grounded

bit 0 CTTRIG: Trigger Control bit

1 = Trigger output is enabled

0 = Trigger output is disabled

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DS39979A-page 316 Preliminary  2010 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EDG2POL: Edge 2 Polarity Select bit

1 = Edge 2 is programmed for a positive edge response

0 = Edge 2 is programmed for a negative edge response

bit 6-5 EDG2SEL<1:0>: Edge 2 Source Select bits

11 = CTEDG1 pin

10 = CTEDG2 pin

01 = CCP1 Special Event Trigger

00 = CCP2 Special Event Trigger

bit 4 EDG1POL: Edge 1 Polarity Select bit

1 = Edge 1 is programmed for a positive edge response

0 = Edge 1 is programmed for a negative edge response

bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits

11 = CTEDG1 pin

10 = CTEDG2 pin

01 = CCP1 Special Event Trigger

00 = CCP2 Special Event Trigger

bit 1 EDG2STAT: Edge 2 Status bit

1 = Edge 2 event has occurred

0 = Edge 2 event has not occurred

bit 0 EDG1STAT: Edge 1 Status bit

1 = Edge 1 event has occurred

0 = Edge 1 event has not occurred

 2010 Microchip Technology Inc. Preliminary DS39979A-page 317

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TABLE 25-1: REGISTERS ASSOCIATED WITH CTMU MODULE

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 ITRIM<5:0>: Current Source Trim bits

011111 = Maximum positive change from nominal current

011110

000001 = Minimum positive change from nominal current

000000 = Nominal current output specified by IRNG<1:0>

111111 = Minimum negative change from nominal current

100010

100001 = Maximum negative change from nominal current

bit 1-0 IRNG<1:0>: Current Source Range Select bits

11 = 100 x Base current

10 = 10 x Base current

01 = Base current level (0.55 A nominal)

00 = Current source disabled

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset

Values

on page:

CTMUCONH CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG —

CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT —

CTMUICON ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 —

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during CCP operation.

PIC18F87J72 FAMILY

DS39979A-page 318 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 319

PIC18F87J72 FAMILY

26.0 SPECIAL FEATURES OF THE

CPU

PIC18F87J72 family devices include several features

intended to maximize reliability and minimize cost

through elimination of external components. These are:

• Oscillator Selection

• Resets:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Fail-Safe Clock Monitor

• Two-Speed Start-up

• Code Protection

• In-Circuit Serial Programming

The oscillator can be configured for the application

depending on frequency, power, accuracy and cost. All

of the options are discussed in detail in Section 3.0

“Oscillator Configurations”.

A complete discussion of device Resets and interrupts

is available in previous sections of this data sheet.

In addition to their Power-up and Oscillator Start-up

Timers provided for Resets, the PIC18F87J72 family of

devices has a configurable Watchdog Timer which is

controlled in software.

The inclusion of an internal RC oscillator also provides

the additional benefits of a Fail-Safe Clock Monitor

(FSCM) and Two-Speed Start-up. FSCM provides for

background monitoring of the peripheral clock and

automatic switchover in the event of its failure.

Two-Speed Start-up enables code to be executed

almost immediately on start-up, while the primary clock

source completes its start-up delays.

All of these features are enabled and configured by

setting the appropriate Configuration register bits.

26.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’), to select

various device configurations. These bits are mapped

starting at program memory location, 300000h. A

complete list is shown in Table 26-2. A detailed

explanation of the various bit functions is provided in

26.1.1 CONSIDERATIONS FOR

CONFIGURING PIC18F87J72

FAMILY DEVICES

Devices of the PIC18F87J72 family do not use persis-

tent memory registers to store configuration information.

The configuration bytes are implemented as volatile

memory which means that configuration data must be

programmed each time the device is powered up.

Configuration data is stored in the three words at the

top of the on-chip program memory space, known as

the Flash Configuration Words. It is stored in program

memory in the same order shown in Table 26-2, with

CONFIG1L at the lowest address and CONFIG3H at

the highest. The data is automatically loaded in the

proper Configuration registers during device power-up.

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Word for configuration data. This is

to make certain that program code is not stored in this

address when the code is compiled.

The volatile memory cells used for the Configuration

bits always reset to ‘1’ on Power-on Resets. For all

other types of Reset events, the previously

programmed values are maintained and used without

reloading from program memory.

The four Most Significant bits of CONFIG1H,

CONFIG2H and CONFIG3H in program memory

should also be ‘1111’. This makes these Configuration

Words appear to be NOP instructions in the remote

event that their locations are ever executed by

accident. Since Configuration bits are not implemented

in the corresponding locations, writing ‘1’s to these

locations has no effect on device operation.

To prevent inadvertent configuration changes during

code execution, all programmable Configuration bits

are write-once. After a bit is initially programmed during

a power cycle, it cannot be written to again. Changing

a device configuration requires that power to the device

be cycled.

TABLE 26-1: MAPPING OF THE FLASH

CONFIGURATION WORDS TO

THE CONFIGURATION

REGISTERS

Configuration

Byte

Code Space

Address

Configuration

Address

CONFIG1L XXXF8h 300000h

CONFIG1H XXXF9h 300001h

CONFIG2L XXXFAh 300002h

CONFIG2H XXXFBh 300003h

CONFIG3L XXXFCh 300004h

CONFIG3H XXXFDh 300005h

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DS39979A-page 320 Preliminary  2010 Microchip Technology Inc.

TABLE 26-2: CONFIGURATION BITS AND DEVICE IDs

File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default/

Unprogrammed

Value(1)

300000h CONFIG1L DEBUG XINST STVREN ————WDTEN111- ---1

300001h CONFIG1H —(2) —(2) —(2) —(2) —(3) CP0 — — ---- 01--

300002h CONFIG2L IESO FCMEN — LPT1OSC T1DIG FOSC2 FOSC1 FOSC0 11-1 1111

300003h CONFIG2H —(2) —(2) —(2) —(2) WDTPS3 WDTPS2 WDTPS1 WDTPS0 ---- 1111

300004h CONFIG3L —(2) —(2) —(2) —(2) ——RTCOSC—---- --1-

300005h CONFIG3H —(2) —(2) —(2) —(2) — — — CCP2MX ---- ---1

3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 01xx xxxx(4)

3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0101 0000(4)

Legend: x = unknown, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.

Note 1: Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset

states, the configuration bytes maintain their previously programmed states.

2: The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it

is accidentally executed.

3: This bit should always be maintained as ‘0’.

4: These registers are read-only and cannot be programmed by the user. See Register 26-7 for device-specific values for

DEVID1.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 321

PIC18F87J72 FAMILY

R/WO-1 R/WO-1 R/WO-1 U-0 U-0 U-0 U-0 R/WO-1

DEBUG XINST STVREN ————WDTEN

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 DEBUG: Background Debugger Enable bit

1 = Background debugger is disabled; RB6 and RB7 are configured as general purpose I/O pins

0 = Background debugger is enabled; RB6 and RB7 are dedicated to In-Circuit Debug

bit 6 XINST: Extended Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode are enabled

0 = Instruction set extension and Indexed Addressing mode are disabled (Legacy mode)

bit 5 STVREN: Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow is enabled

0 = Reset on stack overflow/underflow is disabled

bit 4-1 Unimplemented: Read as ‘0’

bit 0 WDTEN: Watchdog Timer Enable bit

1 = WDT is enabled

0 = WDT is disabled (control is placed on SWDTEN bit)

U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0 U-0

—(1) —(1) —(1) —(1) —(2) CP0 — —

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-3 Unimplemented: Read as ‘0’

bit 2 CP0: Code Protection bit

1 = Program memory is not code-protected

0 = Program memory is code-protected

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

2: This bit should always be maintained as ‘0’.

PIC18F87J72 FAMILY

DS39979A-page 322 Preliminary  2010 Microchip Technology Inc.

R/WO-1 R/WO-1 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1 R/WO-1

IESO FCMEN — LPT1OSC T1DIG FOSC2 FOSC1 FOSC0

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7 IESO: Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Two-Speed Start-up is enabled

0 = Two-Speed Start-up is disabled

bit 6 FCMEN: Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor is enabled

0 = Fail-Safe Clock Monitor is disabled

bit 5 Unimplemented: Read as ‘0’

bit 4 LPT1OSC: T1OSC/SOSC Power Selection Configuration bit

1 = High-power T1OSC/SOSC circuit is selected

0 = Low-power T1OSC/SOSC circuit is selected

bit 3 T1DIG: T1CKI for Digital Input Clock Enable bit

1 = T1CKI is available as a digital input without enabling T1OSCEN

0 = T1CKI is not available as a digital input without enabling T1OSCEN

bit 2-0 FOSC<2:0>: Oscillator Selection bits

111 = ECPLL OSC1/OSC2 as primary; ECPLL oscillator with PLL is enabled; CLKO on RA6

110 = EC OSC1/OSC2 as primary; external clock with FOSC/4 output

101 = HSPLL OSC1/OSC2 as primary; high-speed crystal/resonator with software PLL control

100 = HS OSC1/OSC2 as primary; high-speed crystal/resonator

011 = INTPLL1 internal oscillator block with software PLL control; FOSC/4 output

010 = INTIO1 internal oscillator block with FOSC/4 output on RA6 and I/O on RA7

001 = INTPLL2 internal oscillator block with software PLL control and I/O on RA6 and RA7

000 = INTIO2 internal oscillator block with I/O on RA6 and RA7

 2010 Microchip Technology Inc. Preliminary DS39979A-page 323

PIC18F87J72 FAMILY

U-0 U-0 U-0 U-0 R/WO-1 R/WO-1 R/WO-1 R/WO-1

—(1) —(1) —(1) —(1) WDTPS3 WDTPS2 WDTPS1 WDTPS0

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-4 Unimplemented: Read as ‘0’

bit 3-0 WDTPS<3:0>: Watchdog Timer Postscale Select bits

1111 = 1:32,768

1110 = 1:16,384

1101 = 1:8,192

1100 = 1:4,096

1011 = 1:2,048

1010 = 1:1,024

1001 = 1:512

1000 = 1:256

0111 = 1:128

0110 = 1:64

0101 = 1:32

0100 = 1:16

0011 = 1:8

0010 = 1:4

0001 = 1:2

0000 = 1:1

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1 U-0

—(1) —(1) —(1) —(1) ——RTCOSC—

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-2 Unimplemented: Read as ‘0’

bit 1 RTCOSC: RTCC Reference Clock Select bit

1 = RTCC uses T1OSC/T1CKI as the reference clock

0 = RTCC uses INTRC as the reference clock

bit 0 Unimplemented: Read as ‘0’

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

PIC18F87J72 FAMILY

DS39979A-page 324 Preliminary  2010 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/WO-1

—(1) —(1) —(1) —(1) — — — CCP2MX

bit 7 bit 0

Legend:

R = Readable bit WO = Write-Once bit U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 7-1 Unimplemented: Read as ‘0’

bit 0 CCP2MX: CCP2 MUX bit

1 = CCP2 is multiplexed with RC1

0 = CCP2 is multiplexed with RE7

Note 1: The value of these bits in program memory should always be ‘1’. This ensures that the location is

executed as a NOP if it is accidentally executed.

RRRRRRRR

DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0

bit 7 bit 0

Legend:

R = Read-only bit

bit 7-5 DEV<2:0>: Device ID bits

011 = PIC18F87J72

010 = PIC18F86J72

bit 4-0 REV<4:0>: Revision ID bits

These bits are used to indicate the device revision.

RRRRRRRR

DEV10(1) DEV9(1) DEV8(1) DEV7(1) DEV6(1) DEV5(1) DEV4(1) DEV3(1)

bit 7 bit 0

Legend:

R = Read-only bit

bit 7-0 DEV<10:3>: Device ID bits(1)

These bits are used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.

0101 0000 = PIC18F87J72 family devices

Note 1: The values for DEV<10:3> may be shared with other device families. The specific device is always

identified by using the entire DEV<10:0> bit sequence.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 325

PIC18F87J72 FAMILY

26.2 Watchdog Timer (WDT)

For PIC18F87J72 family devices, the WDT is driven by

the INTRC oscillator. When the WDT is enabled, the

clock source is also enabled. The nominal WDT period is

4 ms and has the same stability as the INTRC oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by the WDTPS bits

in Configuration Register 2H. Available periods range

from 4 ms to 131.072 seconds (2.18 minutes). The

WDT and postscaler are cleared whenever a SLEEP or

CLRWDT instruction is executed, or a clock failure

(primary or Timer1 oscillator) has occurred.

26.2.1 CONTROL REGISTER

The WDTCON register (Register 26-9) is a readable

and writable register. The SWDTEN bit enables or dis-

ables WDT operation. This allows software to override

the WDTEN Configuration bit and enable the WDT only

if it has been disabled by the Configuration bit.

FIGURE 26-1: WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: When a CLRWDT instruction is executed,

the postscaler count will be cleared.

INTRC Oscillator

WDT

Wake-up from

Reset

WDT

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

CLRWDT

Power-Managed

Reset

All Device Resets

Sleep

INTRC Control

128 Modes

PIC18F87J72 FAMILY

DS39979A-page 326 Preliminary  2010 Microchip Technology Inc.

TABLE 26-3: SUMMARY OF WATCHDOG TIMER REGISTERS

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

REGSLP(1) — — — — — —SWDTEN

(2)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 REGSLP: Voltage Regulator Low-Power Operation Enable bit(1)

1 = On-chip regulator enters low-power operation when device enters Sleep mode

0 = On-chip regulator continues to operate normally in Sleep mode

bit 6-1 Unimplemented: Read as ‘0’

bit 0 SWDTEN: Software Controlled Watchdog Timer Enable bit(2)

1 = Watchdog Timer is on

0 = Watchdog Timer is off

Note 1: The REGSLP bit is automatically cleared when a Low-Voltage Detect condition occurs.

2: This bit has no effect if the Configuration bit, WDTEN, is enabled.

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values

on page

RCON IPEN —CM RI TO PD POR BOR 50

WDTCON REGSLP — — — — — —SWDTEN 50

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Watchdog Timer.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 327

PIC18F87J72 FAMILY

26.3 On-Chip Voltage Regulator

All of the PIC18F87J72 family devices power their core

digital logic at a nominal 2.5V. For designs that are

required to operate at a higher typical voltage, such as

3.3V, all devices in the PIC18F87J72 family incorporate

an on-chip regulator that allows the device to run its

core logic from VDD.

The regulator is controlled by the ENVREG pin. Tying

VDD to the pin enables the regulator, which in turn, pro-

vides power to the core from the other VDD pins. When

the regulator is enabled, a low-ESR filter capacitor

must be connected to the VDDCORE/VCAP pin

(Figure 26-2). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in Section 29.3 “DC Characteristics:

PIC18F87J72 Family (Industrial)”.

If ENVREG is tied to VSS, the regulator is disabled. In

this case, separate power for the core logic, at a nomi-

nal 2.5V, must be supplied to the device on the

VDDCORE/VCAP pin to run the I/O pins at higher voltage

levels, typically 3.3V. Alternatively, the VDDCORE/VCAP

and VDD pins can be tied together to operate at a lower

nominal voltage. Refer to Figure 26-2 for possible

configurations.

26.3.1 VOLTAGE REGULATION AND

LOW-VOLTAGE DETECTION

When it is enabled, the on-chip regulator provides a

constant voltage of 2.5V nominal to the digital core

logic. The regulator can provide this level from a VDD of

about 2.5V, all the way up to the device’s VDDMAX. It

does not have the capability to boost VDD levels below

2.5V.

In order to prevent “brown-out” conditions, when the

voltage drops too low for the regulator, the regulator

enters Tracking mode. In Tracking mode, the regulator

output follows VDD, with a typical voltage drop of

100 mV.

The on-chip regulator includes a simple Low-Voltage

Detect (LVD) circuit. If VDD drops too low to maintain

approximately 2.45V on VDDCORE, the circuit sets the

Low-Voltage Detect Interrupt Flag, LVDIF (PIR2<2>),

and clears the REGSLP (WDTCON<7>) bit if it was set.

This can be used to generate an interrupt and puts the

application into a low-power operational mode or

triggers an orderly shutdown. Low-Voltage Detection is

only available when the regulator is enabled.

FIGURE 26-2: CONNECTIONS FOR THE

ON-CHIP REGULATOR

VDD

ENVREG

VDDCORE/VCAP

VSS

3.3V(1)

2.5V(1)

VDD

ENVREG

VDDCORE/VCAP

VSS

3.3V

Regulator Enabled (ENVREG tied to VDD):

Regulator Disabled (ENVREG tied to ground):

VDD

ENVREG

VDDCORE/VCAP

VSS

2.5V(1)

Regulator Disabled (VDD tied to VDDCORE):

Note 1: These are typical operating voltages. For

the full operating ranges of VDD and

VDDCORE, refer to Section 29.1 “DC

Characteristics: Supply Voltage

PIC18F87J72 Family (Industrial)”.

PIC18F87J72

PIC18F87J72 FAMILY

DS39979A-page 328 Preliminary  2010 Microchip Technology Inc.

26.3.2 ON-CHIP REGULATOR AND BOR

When the on-chip regulator is enabled, PIC18F87J72

family devices also have a simple Brown-out Reset

capability. If the voltage supplied to the regulator falls to

a level that is inadequate to maintain a regulated output

for full-speed operation, the regulator Reset circuitry

will generate a Brown-out Reset. This event is captured

by the BOR flag bit (RCON<0>).

The operation of the BOR is described in more detail in

Section 5.4 “Brown-out Reset (BOR)” and

Section 5.4.1 “Detecting BOR”.

26.3.3 POWER-UP REQUIREMENTS

The on-chip regulator is designed to meet the power-up

requirements for the device. If the application does not

use the regulator, then strict power-up conditions must

be adhered to. While powering up, VDDCORE must

never exceed VDD by 0.3 volts.

26.3.4 OPERATION IN SLEEP MODE

When enabled, the on-chip regulator always consumes

a small incremental amount of current over IDD. This

includes when the device is in Sleep mode, even

though the core digital logic does not require power. To

provide additional savings in applications where power

resources are critical, the regulator can be configured

to automatically disable itself whenever the device

goes into Sleep mode. This feature is controlled by the

REGSLP bit (WDTCON<7>). Setting this bit disables

the regulator in Sleep mode and reduces its current

consumption to a minimum.

Substantial Sleep mode power savings can be

obtained by setting the REGSLP bit, but device

wake-up time will increase in order to ensure the

regulator has enough time to stabilize.

The REGSLP bit is automatically cleared by hardware

when a Low-Voltage Detect condition occurs. The

REGSLP bit can be set again in software, which would

continue to keep the voltage regulator in Low-Power

mode. This, however, is not recommended if any write

operations to the Flash will be performed.

26.4 Two-Speed Start-up

The Two-Speed Start-up feature helps to minimize the

latency period, from oscillator start-up to code execu-

tion, by allowing the microcontroller to use the INTRC

oscillator as a clock source until the primary clock

source is available. It is enabled by setting the IESO

Configuration bit.

Two-Speed Start-up should be enabled only if the

primary oscillator mode is HS or HSPLL

(Crystal-Based) modes. Since the EC and ECPLL

modes do not require an OST start-up delay,

Two-Speed Start-up should be disabled.

When enabled, Resets and wake-ups from Sleep mode

cause the device to configure itself to run from the inter-

nal oscillator block as the clock source, following the

time-out of the Power-up Timer after a Power-on Reset

is enabled. This allows almost immediate code

execution while the primary oscillator starts and the

OST is running. Once the OST times out, the device

automatically switches to PRI_RUN mode.

In all other power-managed modes, Two-Speed

Start-up is not used. The device will be clocked by the

currently selected clock source until the primary clock

source becomes available. The setting of the IESO bit

is ignored.

FIGURE 26-3: TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)

Q1 Q3 Q4

OSC1

Peripheral

Program PC PC + 2

INTRC

PLL Clock

PC + 6

Output

Q3 Q4 Q1

CPU Clock

PC + 4

Clock

Counter

Q2 Q2 Q3

Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.

Wake from Interrupt Event

TPLL(1)

12 n-1n

Clock

OSTS bit Set

Transition

TOST(1)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 329

PIC18F87J72 FAMILY

26.4.1 SPECIAL CONSIDERATIONS FOR

USING TWO-SPEED START-UP

While using the INTRC oscillator in Two-Speed

Start-up, the device still obeys the normal command

sequences for entering power-managed modes,

including serial SLEEP instructions (refer to

Section 4.1.4 “Multiple Sleep Commands”). In prac-

tice, this means that user code can change the

SCS<1:0> bit settings or issue SLEEP instructions

before the OST times out. This would allow an applica-

tion to briefly wake-up, perform routine “housekeeping”

tasks and return to Sleep before the device starts to

operate from the primary oscillator.

User code can also check if the primary clock source is

currently providing the device clocking by checking the

status of the OSTS bit (OSCCON<3>). If the bit is set,

the primary oscillator is providing the clock. Otherwise,

the internal oscillator block is providing the clock during

wake-up from Reset or Sleep mode.

26.5 Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) allows the

microcontroller to continue operation in the event of an

external oscillator failure by automatically switching the

device clock to the internal oscillator block. The FSCM

function is enabled by setting the FCMEN Configuration

bit.

When FSCM is enabled, the INTRC oscillator runs at

all times to monitor clocks to peripherals and provides

a backup clock in the event of a clock failure. Clock

monitoring (shown in Figure 26-4) is accomplished by

creating a sample clock signal, which is the INTRC out-

put divided by 64. This allows ample time between

FSCM sample clocks for a peripheral clock edge to

occur. The peripheral device clock and the sample

clock are presented as inputs to the Clock Monitor

(CM) latch. The CM is set on the falling edge of the

device clock source but cleared on the rising edge of

the sample clock.

FIGURE 26-4: FSCM BLOCK DIAGRAM

Clock failure is tested for on the falling edge of the

sample clock. If a sample clock falling edge occurs

while CM is still set, a clock failure has been detected

(Figure 26-5). This causes the following:

• the FSCM generates an oscillator fail interrupt by

setting bit, OSCFIF (PIR2<7>);

• the device clock source is switched to the internal

oscillator block (OSCCON is not updated to show

the current clock source – this is the fail-safe

condition); and

• the WDT is reset.

During switchover, the postscaler frequency from the

internal oscillator block may not be sufficiently stable

for timing-sensitive applications. In these cases, it may

be desirable to select another clock configuration and

enter an alternate power-managed mode. This can be

done to attempt a partial recovery or execute a

controlled shutdown. See Section 4.1.4 “Multiple

Sleep Commands” and Section 26.4.1 “Special

Considerations for Using Two-Speed Start-up” for

more details.

The FSCM will detect failures of the primary or secondary

clock sources only. If the internal oscillator block fails, no

failure would be detected, nor would any action be

possible.

26.5.1 FSCM AND THE WATCHDOG TIMER

Both the FSCM and the WDT are clocked by the

INTRC oscillator. Since the WDT operates with a

separate divider and counter, disabling the WDT has

no effect on the operation of the INTRC oscillator when

the FSCM is enabled.

As already noted, the clock source is switched to the

INTRC clock when a clock failure is detected. This may

mean a substantial change in the speed of code execu-

tion. If the WDT is enabled with a small prescale value,

a decrease in clock speed allows a WDT time-out to

occur and a subsequent device Reset. For this reason,

Fail-Safe Clock Monitor events also reset the WDT and

postscaler, allowing it to start timing from when execu-

tion speed was changed and decreasing the likelihood

of an erroneous time-out.

If the interrupt is disabled, subsequent interrupts while

in Idle mode will cause the CPU to begin executing

instructions while being clocked by the INTRC source.

Peripheral

INTRC ÷ 64

(32 s) 488 Hz

(2.048 ms)

Clock Monitor

Latch (CM)

(edge-triggered)

Clock

Failure

Detected

Source

Clock

PIC18F87J72 FAMILY

DS39979A-page 330 Preliminary  2010 Microchip Technology Inc.

FIGURE 26-5: FSCM TIMING DIAGRAM

26.5.2 EXITING FAIL-SAFE OPERATION

The fail-safe condition is terminated by either a device

Reset or by entering a power-managed mode. On

Reset, the controller starts the primary clock source

specified in Configuration Register 2H (with any

required start-up delays that are required for the oscil-

lator mode, such as OST or PLL timer). The INTRC

oscillator provides the device clock until the primary

clock source becomes ready (similar to a Two-Speed

Start-up). The clock source is then switched to the

primary clock (indicated by the OSTS bit in the

OSCCON register becoming set). The Fail-Safe Clock

Monitor then resumes monitoring the peripheral clock.

The primary clock source may never become ready

during start-up. In this case, operation is clocked by the

INTOSC multiplexer. The OSCCON register will remain

in its Reset state until a power-managed mode is

entered.

26.5.3 FSCM INTERRUPTS IN

POWER-MANAGED MODES

By entering a power-managed mode, the clock

multiplexer selects the clock source selected by the

OSCCON register. Fail-Safe Clock Monitoring of the

power-managed clock source resumes in the

power-managed mode.

If an oscillator failure occurs during power-managed

operation, the subsequent events depend on whether

or not the oscillator failure interrupt is enabled. If

enabled (OSCFIF = 1), code execution will be clocked

by the INTRC multiplexer. An automatic transition back

to the failed clock source will not occur.

26.5.4 POR OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited Power-on Reset

(POR) or low-power Sleep mode. When the primary

device clock is either EC or INTRC mode, monitoring

can begin immediately following these events.

For HS or HSPLL modes, the situation is somewhat dif-

ferent. Since the oscillator may require a start-up time

considerably longer than the FSCM sample clock time,

a false clock failure may be detected. To prevent this,

the internal oscillator block is automatically configured

as the device clock and functions until the primary clock

is stable (the OST and PLL timers have timed out). This

is identical to Two-Speed Start-up mode. Once the

primary clock is stable, the INTRC returns to its role as

the FSCM source.

As noted in Section 26.4.1 “Special Considerations

for Using Two-Speed Start-up”, it is also possible to

select another clock configuration and enter an alternate

power-managed mode while waiting for the primary

clock to become stable. When the new power-managed

mode is selected, the primary clock is disabled.

OSCFIF

CM Output

Device

Clock

Output

Sample Clock

Failure

Detected

Oscillator

Failure

Note: The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

(Q)

CM Test CM Test CM Test

Note: The same logic that prevents false

oscillator failure interrupts on POR, or

wake from Sleep, will also prevent the

detection of the oscillator’s failure to start

at all following these events. This can be

avoided by monitoring the OSTS bit and

using a timing routine to determine if the

oscillator is taking too long to start. Even

so, no oscillator failure interrupt will be

flagged.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 331

PIC18F87J72 FAMILY

26.6 Program Verification and

Code Protection

For all devices in the PIC18F87J72 family of devices,

the on-chip program memory space is treated as a

single block. Code protection for this block is controlled

by one Configuration bit, CP0. This bit inhibits external

reads and writes to the program memory space. It has

no direct effect in normal execution mode.

26.6.1 CONFIGURATION REGISTER

PROTECTION

The Configuration registers are protected against

untoward changes or reads in two ways. The primary

protection is the write-once feature of the Configuration

bits, which prevents reconfiguration once the bit has

been programmed during a power cycle. To safeguard

against unpredictable events, Configuration bit

changes resulting from individual cell-level disruptions

(such as ESD events) will cause a parity error and

trigger a device Reset.

The data for the Configuration registers is derived from

the Flash Configuration Words in program memory.

When the CP0 bit set, the source data for device

configuration is also protected as a consequence.

26.7 In-Circuit Serial Programming

PIC18F87J72 family microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

26.8 In-Circuit Debugger

When the DEBUG Configuration bit is programmed to

a ‘0’, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB® IDE. When the microcontroller has

this feature enabled, some resources are not available

for general use. Table 26-4 shows which resources are

required by the background debugger.

TABLE 26-4: DEBUGGER RESOURCES

I/O Pins: RB6, RB7

Stack: 2 levels

Program Memory: 512 bytes

Data Memory: 10 bytes

PIC18F87J72 FAMILY

DS39979A-page 332 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 333

PIC18F87J72 FAMILY

27.0 INSTRUCTION SET SUMMARY

The PIC18F87J72 family of devices incorporates the

standard set of 75 PIC18 core instructions, as well as

an extended set of 8 new instructions for the optimiza-

tion of code that is recursive or that utilizes a software

stack. The extended set is discussed later in this

section.

27.1 Standard Instruction Set

The standard PIC18 MCU instruction set adds many

enhancements to the previous PIC® MCU instruction

sets, while maintaining an easy migration from these

PIC MCU instruction sets. Most instructions are a

single program memory word (16 bits), but there are

four instructions that require two program memory

locations.

Each single-word instruction is a 16-bit word divided

into an opcode, which specifies the instruction type and

one or more operands, which further specify the

operation of the instruction.

The instruction set is highly orthogonal and is grouped

into four basic categories:

•Byte-oriented operations

•Bit-oriented operations

•Literal operations

•Control operations

The PIC18 instruction set summary in Table 27-2 lists

byte-oriented, bit-oriented, literal and control

operations. Table 27-1 shows the opcode field

descriptions.

Most byte-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The destination of the result (specified by ‘d’)

3. The accessed memory (specified by ‘a’)

The file register designator, ‘f’, specifies which file reg-

ister is to be used by the instruction. The destination

designator, ‘d’, specifies where the result of the

operation is to be placed. If ‘d’ is zero, the result is

placed in the WREG register. If ‘d’ is one, the result is

placed in the file register specified in the instruction.

All bit-oriented instructions have three operands:

1. The file register (specified by ‘f’)

2. The bit in the file register (specified by ‘b’)

3. The accessed memory (specified by ‘a’)

The bit field designator, ‘b’, selects the number of the bit

affected by the operation, while the file register desig-

nator, ‘f’, represents the number of the file in which the

bit is located.

The literal instructions may use some of the following

operands:

• A literal value to be loaded into a file register

(specified by ‘k’)

• The desired FSR register to load the literal value

into (specified by ‘f’)

• No operand required

(specified by ‘—’)

The control instructions may use some of the following

operands:

• A program memory address (specified by ‘n’)

• The mode of the CALL or RETURN instructions

(specified by ‘s’)

• The mode of the table read and table write

instructions (specified by ‘m’)

• No operand required

(specified by ‘—’)

All instructions are a single word, except for four

double-word instructions. These instructions were

made double-word to contain the required information

in 32 bits. In the second word, the 4 MSbs are ‘1’s. If

this second word is executed as an instruction (by

itself), it will execute as a NOP.

All single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of the instruc-

tion. In these cases, the execution takes two instruction

cycles with the additional instruction cycle(s) executed

as a NOP.

The double-word instructions execute in two instruction

cycles.

One instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 s. If a conditional test is

true, or the program counter is changed as a result of

an instruction, the instruction execution time is 2 s.

Two-word branch instructions (if true) would take 3 s.

Figure 27-1 shows the general formats that the instruc-

tions can have. All examples use the convention ‘nnh’

to represent a hexadecimal number.

The Instruction Set Summary, shown in Table 27-2,

lists the standard instructions recognized by the

Microchip MPASMTM Assembler.

Section 27.1.1 “Standard Instruction Set” provides

a description of each instruction.

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TABLE 27-1: OPCODE FIELD DESCRIPTIONS

Field Description

aRAM access bit:

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb Bit address within an 8-bit file register (0 to 7).

BSR Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

dDestination select bit:

d = 0: store result in WREG

d = 1: store result in file register f

dest Destination: either the WREG register or the specified register file location.

f8-bit register file address (00h to FFh), or 2-bit FSR designator (0h to 3h).

fs12-bit register file address (000h to FFFh). This is the source address.

fd12-bit register file address (000h to FFFh). This is the destination address.

GIE Global Interrupt Enable bit.

kLiteral field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label Label name.

mm The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

*No Change to register (such as TBLPTR with table reads and writes)

*+ Post-Increment register (such as TBLPTR with table reads and writes)

*- Post-Decrement register (such as TBLPTR with table reads and writes)

+* Pre-Increment register (such as TBLPTR with table reads and writes)

nThe relative address (2’s complement number) for relative branch instructions or the direct address for

Call/Branch and Return instructions.

PC Program Counter.

PCL Program Counter Low Byte.

PCH Program Counter High Byte.

PCLATH Program Counter High Byte Latch.

PCLATU Program Counter Upper Byte Latch.

PD Power-Down bit.

PRODH Product of Multiply High Byte.

PRODL Product of Multiply Low Byte.

sFast Call/Return mode select bit:

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR 21-bit Table Pointer (points to a Program Memory location).

TABLAT 8-bit Table Latch.

TO Time-out bit.

TOS Top-of-Stack.

uUnused or Unchanged.

WDT Watchdog Timer.

WREG Working register (accumulator).

xDon’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

zs7-bit offset value for Indirect Addressing of register files (source).

zd7-bit offset value for Indirect Addressing of register files (destination).

{ } Optional argument.

[text] Indicates an Indexed Address.

(text) The contents of text.

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PIC18F87J72 FAMILY

[expr]<n> Specifies bit n of the register indicated by the pointer expr.

Assigned to.

< > Register bit field.

In the set of.

italics User-defined term (font is Courier New).

TABLE 27-1: OPCODE FIELD DESCRIPTIONS (CONTINUED)

Field Description

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FIGURE 27-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations

15 10 9 8 7 0

d = 0 for result destination to be WREG register

OPCODE d a f (FILE #)

d = 1 for result destination to be file register (f)

a = 0 to force Access Bank

Bit-oriented file register operations

15 12 11 9 8 7 0

OPCODE b (BIT #) a f (FILE #)

b = 3-bit position of bit in file register (f)

Literal operations

15 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Byte to Byte move operations (2-word)

15 12 11 0

OPCODE f (Source FILE #)

CALL, GOTO and Branch operations

15 8 7 0

OPCODE n<7:0> (literal)

n = 20-bit immediate value

a = 1 for BSR to select bank

f = 8-bit file register address

a = 0 to force Access Bank

a = 1 for BSR to select bank

f = 8-bit file register address

15 12 11 0

1111 n<19:8> (literal)

15 12 11 0

1111 f (Destination FILE #)

f = 12-bit file register address

Control operations

Example Instruction

ADDWF MYREG, W, B

MOVFF MYREG1, MYREG2

BSF MYREG, bit, B

MOVLW 7Fh

GOTO Label

15 8 7 0

OPCODE S n<7:0> (literal)

15 12 11 0

1111 n<19:8> (literal)

CALL MYFUNC

15 11 10 0

OPCODE n<10:0> (literal)

S = Fast bit

BRA MYFUNC

15 8 7 0

OPCODE n<7:0> (literal) BC MYFUNC

 2010 Microchip Technology Inc. Preliminary DS39979A-page 337

PIC18F87J72 FAMILY

TABLE 27-2: PIC18F87J72 FAMILY INSTRUCTION SET

Mnemonic,

Operands Description Cycles

16-Bit Instruction Word Status

Affected Notes

MSb LSb

BYTE-ORIENTED OPERATIONS

ADDWF

ADDWFC

ANDWF

CLRF

COMF

CPFSEQ

CPFSGT

CPFSLT

DECF

DECFSZ

DCFSNZ

INCF

INCFSZ

INFSNZ

IORWF

MOVF

MOVFF

MOVWF

MULWF

NEGF

RLCF

RLNCF

RRCF

RRNCF

SETF

SUBFWB

SUBWF

SUBWFB

SWAPF

TSTFSZ

XORWF

f, d, a

f, a

f, d, a

f, a

f, d, a

fs, fd

f, a

f, d, a

f, a

f, d, a

f, a

f, d, a

Add WREG and f

Add WREG and Carry bit to f

AND WREG with f

Clear f

Complement f

Compare f with WREG, Skip =

Compare f with WREG, Skip >

Compare f with WREG, Skip <

Decrement f

Decrement f, Skip if 0

Decrement f, Skip if Not 0

Increment f

Increment f, Skip if 0

Increment f, Skip if Not 0

Inclusive OR WREG with f

Move f

Move fs (source) to 1st word

fd (destination) 2nd word

Move WREG to f

Multiply WREG with f

Negate f

Rotate Left f through Carry

Rotate Left f (No Carry)

Rotate Right f through Carry

Rotate Right f (No Carry)

Set f

Subtract f from WREG with

Borrow

Subtract WREG from f

Subtract WREG from f with

Borrow

Swap Nibbles in f

Test f, Skip if 0

Exclusive OR WREG with f

1 (2 or 3)

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da

00da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

None

C, DC, Z, OV, N

None

Z, N

None

C, DC, Z, OV, N

C, Z, N

Z, N

C, Z, N

Z, N

None

C, DC, Z, OV, N

None

Z, N

1, 2

1,2

1, 2

1, 2, 3, 4

1, 2

1, 2, 3, 4

1, 2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

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BIT-ORIENTED OPERATIONS

BCF

BSF

BTFSC

BTFSS

BTG

f, b, a

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

Bit Toggle f

1 (2 or 3)

1001

1000

1011

1010

0111

bbba

ffff

None

1, 2

3, 4

1, 2

CONTROL OPERATIONS

BNC

BNN

BNOV

BNZ

BOV

BRA

CALL

CLRWDT

DAW

GOTO

NOP

POP

PUSH

RCALL

RESET

RETFIE

RETLW

RETURN

SLEEP

n, s

—

Branch if Carry

Branch if Negative

Branch if Not Carry

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

Branch if Overflow

Branch Unconditionally

Branch if Zero

Call Subroutine 1st word

2nd word

Clear Watchdog Timer

Decimal Adjust WREG

Go to Address 1st word

2nd word

No Operation

Pop Top of Return Stack (TOS)

Push Top of Return Stack (TOS)

Relative Call

Software Device Reset

Return from Interrupt Enable

Return with Literal in WREG

Return from Subroutine

Go into Standby mode

1 (2)

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None

TO, PD

None

All

GIE/GIEH,

PEIE/GIEL

None

TO, PD

TABLE 27-2: PIC18F87J72 FAMILY INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles

16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

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LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

LFSR

MOVLB

MOVLW

MULLW

RETLW

SUBLW

XORLW

f, k

Add Literal and WREG

AND Literal with WREG

Inclusive OR Literal with WREG

Move literal (12-bit) 2nd word

to FSR(f) 1st word

Move Literal to BSR<3:0>

Move Literal to WREG

Multiply Literal with WREG

Return with Literal in WREG

Subtract WREG from Literal

Exclusive OR Literal with WREG

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, DC, Z, OV, N

Z, N

None

C, DC, Z, OV, N

Z, N

DATA MEMORY  PROGRAM MEMORY OPERATIONS

TBLRD*

TBLRD*+

TBLRD*-

TBLRD+*

TBLWT*

TBLWT*+

TBLWT*-

TBLWT+*

Table Read

Table Read with Post-Increment

Table Read with Post-Decrement

Table Read with Pre-Increment

Table Write

Table Write with Post-Increment

Table Write with Post-Decrement

Table Write with Pre-Increment

0000

1000

1001

1010

1011

1100

1101

1110

1111

None

TABLE 27-2: PIC18F87J72 FAMILY INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands Description Cycles

16-Bit Instruction Word Status

Affected Notes

MSb LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be

that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

if assigned.

3: If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP

unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that

all program memory locations have a valid instruction.

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27.1.1 STANDARD INSTRUCTION SET

ADDLW ADD Literal to W

Syntax: ADDLW k

Operands: 0  k  255

Operation: (W) + k  W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1111 kkkk kkkk

Description: The contents of W are added to the

8-bit literal ‘k’ and the result is placed in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

Example: ADDLW 15h

Before Instruction

W = 10h

After Instruction

W = 25h

ADDWF ADD W to f

Syntax: ADDWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) + (f)  dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01da ffff ffff

Description: Add W to register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ADDWF REG, 0, 0

Before Instruction

W = 17h

REG = 0C2h

After Instruction

W = 0D9h

REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 341

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ADDWFC ADD W and Carry bit to f

Syntax: ADDWFC f {,d {,a}}

Operands: 0  f  255

d [0,1]

a [0,1]

Operation: (W) + (f) + (C)  dest

Status Affected: N,OV, C, DC, Z

Encoding: 0010 00da ffff ffff

Description: Add W, the Carry flag and data memory

location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ADDWFC REG, 0, 1

Before Instruction

Carry bit = 1

REG = 02h

W=4Dh

After Instruction

Carry bit = 0

REG = 02h

W = 50h

ANDLW AND Literal with W

Syntax: ANDLW k

Operands: 0  k  255

Operation: (W) .AND. k  W

Status Affected: N, Z

Encoding: 0000 1011 kkkk kkkk

Description: The contents of W are ANDed with the

8-bit literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’

Process

Data

Write to

Example: ANDLW 05Fh

Before Instruction

W=A3h

After Instruction

W = 03h

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ANDWF AND W with f

Syntax: ANDWF f {,d {,a}}

Operands: 0  f  255

d [0,1]

a [0,1]

Operation: (W) .AND. (f)  dest

Status Affected: N, Z

Encoding: 0001 01da ffff ffff

Description: The contents of W are ANDed with

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: ANDWF REG, 0, 0

Before Instruction

W = 17h

REG = C2h

After Instruction

W = 02h

REG = C2h

BC Branch if Carry

Syntax: BC n

Operands: -128  n  127

Operation: if Carry bit is ‘1’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0010 nnnn nnnn

Description: If the Carry bit is ’1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BC 5

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 1;

PC = address (HERE + 12)

If Carry = 0;

PC = address (HERE + 2)

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BCF Bit Clear f

Syntax: BCF f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: 0  f

Status Affected: None

Encoding: 1001 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is cleared.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: BCF FLAG_REG, 7, 0

Before Instruction

FLAG_REG = C7h

After Instruction

FLAG_REG = 47h

BN Branch if Negative

Syntax: BN n

Operands: -128  n  127

Operation: if Negative bit is ‘1’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0110 nnnn nnnn

Description: If the Negative bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 1;

PC = address (Jump)

If Negative = 0;

PC = address (HERE + 2)

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BNC Branch if Not Carry

Syntax: BNC n

Operands: -128  n  127

Operation: if Carry bit is ‘0’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0011 nnnn nnnn

Description: If the Carry bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNC Jump

Before Instruction

PC = address (HERE)

After Instruction

If Carry = 0;

PC = address (Jump)

If Carry = 1;

PC = address (HERE + 2)

BNN Branch if Not Negative

Syntax: BNN n

Operands: -128  n  127

Operation: if Negative bit is ‘0’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0111 nnnn nnnn

Description: If the Negative bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNN Jump

Before Instruction

PC = address (HERE)

After Instruction

If Negative = 0;

PC = address (Jump)

If Negative = 1;

PC = address (HERE + 2)

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BNOV Branch if Not Overflow

Syntax: BNOV n

Operands: -128  n  127

Operation: if Overflow bit is ‘0’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0101 nnnn nnnn

Description: If the Overflow bit is ‘0’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 0;

PC = address (Jump)

If Overflow = 1;

PC = address (HERE + 2)

BNZ Branch if Not Zero

Syntax: BNZ n

Operands: -128  n  127

Operation: if Zero bit is ‘0’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0001 nnnn nnnn

Description: If the Zero bit is ‘0’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BNZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 0;

PC = address (Jump)

If Zero = 1;

PC = address (HERE + 2)

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BRA Unconditional Branch

Syntax: BRA n

Operands: -1024  n  1023

Operation: (PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1101 0nnn nnnn nnnn

Description: Add the 2’s complement number ‘2n’ to

the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

Example: HERE BRA Jump

Before Instruction

PC = address (HERE)

After Instruction

PC = address (Jump)

BSF Bit Set f

Syntax: BSF f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: 1  f

Status Affected: None

Encoding: 1000 bbba ffff ffff

Description: Bit ‘b’ in register ‘f’ is set.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: BSF FLAG_REG, 7, 1

Before Instruction

FLAG_REG = 0Ah

After Instruction

FLAG_REG = 8Ah

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BTFSC Bit Test File, Skip if Clear

Syntax: BTFSC f, b {,a}

Operands: 0  f  255

0  b  7

a [0,1]

Operation: skip if (f) = 0

Status Affected: None

Encoding: 1011 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next

instruction is skipped. If bit ‘b’ is ‘0’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction set

is enabled, this instruction operates in

Indexed Literal Offset Addressing mode

whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (TRUE)

If FLAG<1> = 1;

PC = address (FALSE)

BTFSS Bit Test File, Skip if Set

Syntax: BTFSS f, b {,a}

Operands: 0  f  255

0  b < 7

a [0,1]

Operation: skip if (f) = 1

Status Affected: None

Encoding: 1010 bbba ffff ffff

Description: If bit ‘b’ in register ‘f’ is ‘1’, then the next

instruction is skipped. If bit ‘b’ is ‘1’, then

the next instruction fetched during the

current instruction execution is discarded

and a NOP is executed instead, making

this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing mode

whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0;

PC = address (FALSE)

If FLAG<1> = 1;

PC = address (TRUE)

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BTG Bit Toggle f

Syntax: BTG f, b {,a}

Operands: 0  f  255

0  b < 7

a [0,1]

Operation: (f)  f

Status Affected: None

Encoding: 0111 bbba ffff ffff

Description: Bit ‘b’ in data memory location ‘f’ is

inverted.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: BTG PORTC, 4, 0

Before Instruction:

PORTC = 0111 0101 [75h]

After Instruction:

PORTC = 0110 0101 [65h]

BOV Branch if Overflow

Syntax: BOV n

Operands: -128  n  127

Operation: if Overflow bit is ‘1’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0100 nnnn nnnn

Description: If the Overflow bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BOV Jump

Before Instruction

PC = address (HERE)

After Instruction

If Overflow = 1;

PC = address (Jump)

If Overflow = 0;

PC = address (HERE + 2)

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BZ Branch if Zero

Syntax: BZ n

Operands: -128  n  127

Operation: if Zero bit is ‘1’,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1110 0000 nnnn nnnn

Description: If the Zero bit is ‘1’, then the program

will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then a

two-cycle instruction.

Words: 1

Cycles: 1(2)

Q Cycle Activity:

If Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

Write to

operation

If No Jump:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

Process

Data

operation

Example: HERE BZ Jump

Before Instruction

PC = address (HERE)

After Instruction

If Zero = 1;

PC = address (Jump)

If Zero = 0;

PC = address (HERE + 2)

CALL Subroutine Call

Syntax: CALL k {,s}

Operands: 0  k  1048575

s [0,1]

Operation: (PC) + 4  TOS,

k  PC<20:1>;

if s = 1

(W)  WS,

(STATUS)  STATUSS,

(BSR)  BSRS

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: Subroutine call of entire 2-Mbyte

memory range. First, return address

(PC+ 4) is pushed onto the return stack.

If ‘s’ = 1, the W, STATUS and BSR

registers are also pushed into their

respective shadow registers, WS,

STATUSS and BSRS. If ‘s’ = 0, no

update occurs. Then, the 20-bit value ‘k’

is loaded into PC<20:1>. CALL is a

two-cycle instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>,

Push PC to

stack

Read literal

’k’<19:8>,

Write to PC

operation

Example: HERE CALL THERE,1

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE)

TOS = address (HERE + 4)

WS = W

BSRS = BSR

STATUSS = STATUS

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CLRF Clear f

Syntax: CLRF f {,a}

Operands: 0  f  255

a [0,1]

Operation: 000h  f,

1  Z

Status Affected: Z

Encoding: 0110 101a ffff ffff

Description: Clears the contents of the specified

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: CLRF FLAG_REG,1

Before Instruction

FLAG_REG = 5Ah

After Instruction

FLAG_REG = 00h

CLRWDT Clear Watchdog Timer

Syntax: CLRWDT

Operands: None

Operation: 000h  WDT,

000h  WDT postscaler,

1  TO,

1  PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0100

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets the post-

scaler of the WDT. Status bits, TO and

PD, are set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

operation

Example: CLRWDT

Before Instruction

WDT Counter = ?

After Instruction

WDT Counter = 00h

WDT Postscaler = 0

TO =1

PD =1

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COMF Complement f

Syntax: COMF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: f  dest

Status Affected: N, Z

Encoding: 0001 11da ffff ffff

Description: The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: COMF REG, 0, 0

Before Instruction

REG = 13h

After Instruction

REG = 13h

W=ECh

CPFSEQ Compare f with W, Skip if f = W

Syntax: CPFSEQ f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) – (W),

skip if (f) = (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 001a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If ‘f’ = W, then the fetched instruction is

discarded and a NOP is executed

instead, making this a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address = HERE

W=?

REG = ?

After Instruction

If REG = W;

PC = Address (EQUAL)

If REG  W;

PC = Address (NEQUAL)

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CPFSGT Compare f with W, Skip if f > W

Syntax: CPFSGT f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) –W),

skip if (f) > (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 010a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of the W by

performing an unsigned subtraction.

If the contents of ‘f’ are greater than the

contents of WREG, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG  W;

PC = Address (GREATER)

If REG  W;

PC = Address (NGREATER)

CPFSLT Compare f with W, Skip if f < W

Syntax: CPFSLT f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) –W),

skip if (f) < (W)

(unsigned comparison)

Status Affected: None

Encoding: 0110 000a ffff ffff

Description: Compares the contents of data memory

location ‘f’ to the contents of W by

performing an unsigned subtraction.

If the contents of ‘f’ are less than the

contents of W, then the fetched

instruction is discarded and a NOP is

executed instead, making this a

two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC = Address (HERE)

W= ?

After Instruction

If REG < W;

PC = Address (LESS)

If REG  W;

PC = Address (NLESS)

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DAW Decimal Adjust W Register

Syntax: DAW

Operands: None

Operation: If [W<3:0> > 9] or [DC = 1], then

(W<3:0>) + 6  W<3:0>;

else

(W<3:0>)  W<3:0>

If [W<7:4> > 9] or [C = 1], then

(W<7:4>) + 6  W<7:4>;

C =1;

else

(W<7:4>)  W<7:4>

Status Affected: C

Encoding: 0000 0000 0000 0111

Description: DAW adjusts the eight-bit value in W,

resulting from the earlier addition of two

variables (each in packed BCD format)

and produces a correct packed BCD

result.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example 1: DAW

Before Instruction

W=A5h

C=0

DC = 0

After Instruction

W = 05h

C=1

DC = 0

Example 2:

Before Instruction

W=CEh

C=0

DC = 0

After Instruction

W = 34h

C=1

DC = 0

DECF Decrement f

Syntax: DECF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest

Status Affected: C, DC, N, OV, Z

Encoding: 0000 01da ffff ffff

Description: Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: DECF CNT, 1, 0

Before Instruction

CNT = 01h

Z=0

After Instruction

CNT = 00h

Z=1

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DECFSZ Decrement f, Skip if 0

Syntax: DECFSZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest,

skip if result = 0

Status Affected: None

Encoding: 0010 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is ‘0’, the next instruction

which is already fetched is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT – 1

If CNT = 0;

PC = Address (CONTINUE)

If CNT 0;

PC = Address (HERE + 2)

DCFSNZ Decrement f, Skip if Not 0

Syntax: DCFSNZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – 1  dest,

skip if result  0

Status Affected: None

Encoding: 0100 11da ffff ffff

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is not ‘0’, the next

instruction which is already fetched is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP = ?

After Instruction

TEMP = TEMP – 1,

If TEMP = 0;

PC = Address (ZERO)

If TEMP 0;

PC = Address (NZERO)

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GOTO Unconditional Branch

Syntax: GOTO k

Operands: 0  k  1048575

Operation: k  PC<20:1>

Status Affected: None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description: GOTO allows an unconditional branch

anywhere within entire 2-Mbyte memory

range. The 20-bit value ‘k’ is loaded into

PC<20:1>. GOTO is always a two-cycle

instruction.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’<7:0>,

operation

Read literal

‘k’<19:8>,

Write to PC

operation

Example: GOTO THERE

After Instruction

PC = Address (THERE)

INCF Increment f

Syntax: INCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest

Status Affected: C, DC, N, OV, Z

Encoding: 0010 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: INCF CNT, 1, 0

Before Instruction

CNT = FFh

Z=0

C=?

DC = ?

After Instruction

CNT = 00h

Z=1

C=1

DC = 1

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INCFSZ Increment f, Skip if 0

Syntax: INCFSZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest,

skip if result = 0

Status Affected: None

Encoding: 0011 11da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is ‘0’, the next instruction

which is already fetched is discarded

and a NOP is executed instead, making

it a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE INCFSZ CNT, 1, 0

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

CNT = CNT + 1

If CNT = 0;

PC = Address (ZERO)

If CNT 0;

PC = Address (NZERO)

INFSNZ Increment f, Skip if Not 0

Syntax: INFSNZ f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) + 1  dest,

skip if result  0

Status Affected: None

Encoding: 0100 10da ffff ffff

Description: The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If the result is not ‘0’, the next

instruction which is already fetched is

discarded and a NOP is executed

instead, making it a two-cycle

instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE INFSNZ REG, 1, 0

ZERO

NZERO

Before Instruction

PC = Address (HERE)

After Instruction

REG = REG + 1

If REG 0;

PC = Address (NZERO)

If REG = 0;

PC = Address (ZERO)

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IORLW Inclusive OR Literal with W

Syntax: IORLW k

Operands: 0  k  255

Operation: (W) .OR. k  W

Status Affected: N, Z

Encoding: 0000 1001 kkkk kkkk

Description: The contents of W are ORed with the

eight-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

Example: IORLW 35h

Before Instruction

W=9Ah

After Instruction

W=BFh

IORWF Inclusive OR W with f

Syntax: IORWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) .OR. (f)  dest

Status Affected: N, Z

Encoding: 0001 00da ffff ffff

Description: Inclusive OR W with register ‘f’. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is placed back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: IORWF RESULT, 0, 1

Before Instruction

RESULT = 13h

W = 91h

After Instruction

RESULT = 13h

W = 93h

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LFSR Load FSR

Syntax: LFSR f, k

Operands: 0  f  2

0  k  4095

Operation: k  FSRf

Status Affected: None

Encoding: 1110

1111

1110

0000

00ff

k7kkk

k11kkk

kkkk

Description: The 12-bit literal ‘k’ is loaded into the

file select register pointed to by ‘f’.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘k’ MSB

Process

Data

Write

literal ‘k’

MSB to

FSRfH

Decode Read literal

‘k’ LSB

Process

Data

Write literal

‘k’ to FSRfL

Example: LFSR 2, 3ABh

After Instruction

FSR2H = 03h

FSR2L = ABh

MOVF Move f

Syntax: MOVF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: f  dest

Status Affected: N, Z

Encoding: 0101 00da ffff ffff

Description: The contents of register ‘f’ are moved to

a destination dependent upon the

status of ‘d’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’. Location ‘f’

can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: MOVF REG, 0, 0

Before Instruction

REG = 22h

W=FFh

After Instruction

REG = 22h

W = 22h

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MOVFF Move f to f

Syntax: MOVFF fs,fd

Operands: 0  fs  4095

0  fd  4095

Operation: (fs)  fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.)

1100

1111

ffff

ffffs

ffffd

Description: The contents of source register ‘fs’ are

moved to destination register ‘fd’.

Location of source ‘fs’ can be anywhere

in the 4096-byte data space (000h to

FFFh) and location of destination ‘fd’

can also be anywhere from 000h to

FFFh.

Either source or destination can be W

(a useful special situation).

MOVFF is particularly useful for

transferring a data memory location to a

peripheral register (such as the transmit

buffer or an I/O port).

The MOVFF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

(src)

Process

Data

operation

Decode No

operation

No dummy

read

operation

Write

(dest)

Example: MOVFF REG1, REG2

Before Instruction

REG1 = 33h

REG2 = 11h

After Instruction

REG1 = 33h

REG2 = 33h

MOVLB Move Literal to Low Nibble in BSR

Syntax: MOVLW k

Operands: 0  k  255

Operation: k  BSR

Status Affected: None

Encoding: 0000 0001 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into the

Bank Select Register (BSR). The value

of BSR<7:4> always remains ‘0’

regardless of the value of k7:k4.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write literal

‘k’ to BSR

Example: MOVLB 5

Before Instruction

BSR Register = 02h

After Instruction

BSR Register = 05h

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MOVLW Move Literal to W

Syntax: MOVLW k

Operands: 0  k  255

Operation: k  W

Status Affected: None

Encoding: 0000 1110 kkkk kkkk

Description: The eight-bit literal ‘k’ is loaded into W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

Example: MOVLW 5Ah

After Instruction

W=5Ah

MOVWF Move W to f

Syntax: MOVWF f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (W)  f

Status Affected: None

Encoding: 0110 111a ffff ffff

Description: Move data from W to register ‘f’.

Location ‘f’ can be anywhere in the

256-byte bank.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: MOVWF REG, 0

Before Instruction

W=4Fh

REG = FFh

After Instruction

W=4Fh

REG = 4Fh

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MULLW Multiply Literal with W

Syntax: MULLW k

Operands: 0  k  255

Operation: (W) x k  PRODH:PRODL

Status Affected: None

Encoding: 0000 1101 kkkk kkkk

Description: An unsigned multiplication is carried

out between the contents of W and the

8-bit literal ‘k’. The 16-bit result is

placed in the PRODH:PRODL register

pair. PRODH contains the high byte.

W is unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A Zero result

is possible but not detected.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write

registers

PRODH:

PRODL

Example: MULLW 0C4h

Before Instruction

W=E2h

PRODH = ?

PRODL = ?

After Instruction

W=E2h

PRODH = ADh

PRODL = 08h

MULWF Multiply W with f

Syntax: MULWF f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (W) x (f)  PRODH:PRODL

Status Affected: None

Encoding: 0000 001a ffff ffff

Description: An unsigned multiplication is carried out

between the contents of W and the

stored in the PRODH:PRODL register

pair. PRODH contains the high byte. Both

W and ‘f’ are unchanged.

None of the Status flags are affected.

Note that neither Overflow nor Carry is

possible in this operation. A Zero result is

possible but not detected.

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction set

is enabled, this instruction operates in

Indexed Literal Offset Addressing mode

whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

registers

PRODH:

PRODL

Example: MULWF REG, 1

Before Instruction

W=C4h

REG = B5h

PRODH = ?

PRODL = ?

After Instruction

W=C4h

REG = B5h

PRODH = 8Ah

PRODL = 94h

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NEGF Negate f

Syntax: NEGF f {,a}

Operands: 0  f  255

a  [0,1]

Operation: (f) + 1  f

Status Affected: N, OV, C, DC, Z

Encoding: 0110 110a ffff ffff

Description: Location ‘f’ is negated using two’s

complement. The result is placed in the

data memory location ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: NEGF REG, 1

Before Instruction

REG = 0011 1010 [3Ah]

After Instruction

REG = 1100 0110 [C6h]

NOP No Operation

Syntax: NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 0000

1111

0000

xxxx

0000

xxxx

0000

xxxx

Description: No operation.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Example:

None.

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POP Pop Top of Return Stack

Syntax: POP

Operands: None

Operation: (TOS)  bit bucket

Status Affected: None

Encoding: 0000 0000 0000 0110

Description: The TOS value is pulled off the return

stack and is discarded. The TOS value

then becomes the previous value that

was pushed onto the return stack.

This instruction is provided to enable

the user to properly manage the return

stack to incorporate a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

POP TOS

value

operation

Example: POP

GOTO NEW

Before Instruction

TOS = 0031A2h

Stack (1 level down) = 014332h

After Instruction

TOS = 014332h

PC = NEW

PUSH Push Top of Return Stack

Syntax: PUSH

Operands: None

Operation: (PC + 2)  TOS

Status Affected: None

Encoding: 0000 0000 0000 0101

Description: The PC + 2 is pushed onto the top of

the return stack. The previous TOS

value is pushed down on the stack.

This instruction allows implementing a

software stack by modifying TOS and

then pushing it onto the return stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode PUSH

PC + 2 onto

return stack

operation

Example: PUSH

Before Instruction

TOS = 345Ah

PC = 0124h

After Instruction

PC = 0126h

TOS = 0126h

Stack (1 level down) = 345Ah

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RCALL Relative Call

Syntax: RCALL n

Operands: -1024  n  1023

Operation: (PC) + 2  TOS,

(PC) + 2 + 2n  PC

Status Affected: None

Encoding: 1101 1nnn nnnn nnnn

Description: Subroutine call with a jump up to 1K

from the current location. First, return

address (PC + 2) is pushed onto the

stack. Then, add the 2’s complement

number ‘2n’ to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is a

two-cycle instruction.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read literal

‘n’

PUSH PC

to stack

Process

Data

Write to PC

operation

Example: HERE RCALL Jump

Before Instruction

PC = Address (HERE)

After Instruction

PC = Address (Jump)

TOS = Address (HERE + 2)

RESET Reset

Syntax: RESET

Operands: None

Operation: Reset all registers and flags that are

affected by a MCLR Reset.

Status Affected: All

Encoding: 0000 0000 1111 1111

Description: This instruction provides a way to

execute a MCLR Reset in software.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Start

reset

operation

Example: RESET

After Instruction

Registers = Reset Value

Flags* = Reset Value

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RETFIE Return from Interrupt

Syntax: RETFIE {s}

Operands: s  [0,1]

Operation: (TOS)  PC,

1  GIE/GIEH or PEIE/GIEL;

if s = 1,

(WS)  W,

(STATUSS)  STATUS,

(BSRS)  BSR,

PCLATU, PCLATH are unchanged

Status Affected: GIE/GIEH, PEIE/GIEL.

Encoding: 0000 0000 0001 000s

Description: Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low-priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers WS,

STATUSS and BSRS are loaded into

their corresponding registers W,

STATUS and BSR. If ‘s’ = 0, no update

of these registers occurs.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

POP PC

from stack

Set GIEH or

GIEL

operation

Example: RETFIE 1

After Interrupt

PC = TOS

W=WS

BSR = BSRS

STATUS = STATUSS

GIE/GIEH, PEIE/GIEL = 1

RETLW Return Literal to W

Syntax: RETLW k

Operands: 0  k  255

Operation: k  W,

(TOS)  PC,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 1100 kkkk kkkk

Description: W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

POP PC

from stack,

write to W

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL ; W = offset

RETLW k0 ; Begin table

RETLW k1 ;

RETLW kn ; End of table

Before Instruction

W = 07h

After Instruction

W = value of kn

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RETURN Return from Subroutine

Syntax: RETURN {s}

Operands: s  [0,1]

Operation: (TOS)  PC;

if s = 1,

(WS)  W,

(STATUSS)  STATUS,

(BSRS)  BSR,

PCLATU, PCLATH are unchanged

Status Affected: None

Encoding: 0000 0000 0001 001s

Description: Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers WS, STATUSS and BSRS are

loaded into their corresponding

registers W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

POP PC

from stack

operation

Example: RETURN

After Instruction:

PC = TOS

RLCF Rotate Left f through Carry

Syntax: RLCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n + 1>,

(f<7>)  C,

Status Affected: C, N, Z

Encoding: 0011 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left through the Carry flag.

If ‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in register

‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RLCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=1100 1100

C=1

Cregister f

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RLNCF Rotate Left f (No Carry)

Syntax: RLNCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n + 1>,

(f<7>)  dest<0>

Status Affected: N, Z

Encoding: 0100 01da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the left. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RLNCF REG, 1, 0

Before Instruction

REG = 1010 1011

After Instruction

REG = 0101 0111

RRCF Rotate Right f through Carry

Syntax: RRCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n – 1>,

(f<0>)  C,

Status Affected: C, N, Z

Encoding: 0011 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in W.

If ‘d’ is ‘1’, the result is placed back in

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: RRCF REG, 0, 0

Before Instruction

REG = 1110 0110

C=0

After Instruction

REG = 1110 0110

W=0111 0011

C=0

Cregister f

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RRNCF Rotate Right f (No Carry)

Syntax: RRNCF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<n>)  dest<n – 1>,

(f<0>)  dest<7>

Status Affected: N, Z

Encoding: 0100 00da ffff ffff

Description: The contents of register ‘f’ are rotated

one bit to the right. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank will be

selected, overriding the BSR value. If ‘a’

is ‘1’, then the bank will be selected as

per the BSR value.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: RRNCF REG, 1, 0

Before Instruction

REG = 1101 0111

After Instruction

REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction

W=?

REG = 1101 0111

After Instruction

W=1110 1011

REG = 1101 0111

SETF Set f

Syntax: SETF f {,a}

Operands: 0  f  255

a [0,1]

Operation: FFh  f

Status Affected: None

Encoding: 0110 100a ffff ffff

Description: The contents of the specified register

are set to FFh.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write

Example: SETF REG,1

Before Instruction

REG = 5Ah

After Instruction

REG = FFh

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SLEEP Enter Sleep Mode

Syntax: SLEEP

Operands: None

Operation: 00h  WDT,

0  WDT postscaler,

1  TO,

0  PD

Status Affected: TO, PD

Encoding: 0000 0000 0000 0011

Description: The Power-Down status bit (PD) is

cleared. The Time-out status bit (TO)

is set. The Watchdog Timer and its

postscaler are cleared.

The processor is put into Sleep mode

with the oscillator stopped.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

Process

Data

Go to

Sleep

Example: SLEEP

Before Instruction

TO =?

PD =?

After Instruction

TO =1 †

PD =0

† If WDT causes wake-up, this bit is cleared.

SUBFWB Subtract f from W with Borrow

Syntax: SUBFWB f {,d {,a}}

Operands: 0 f 255

d  [0,1]

a  [0,1]

Operation: (W) – (f) – (C) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 01da ffff ffff

Description: Subtract register ‘f’ and Carry flag

(borrow) from W (2’s complement

method). If ‘d’ is ‘0’, the result is stored in

W. If ‘d’ is ‘1’, the result is stored in

If ‘a’ is ‘0’, the Access Bank is selected. If

‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates in

Indexed Literal Offset Addressing mode

whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBFWB REG, 1, 0

Before Instruction

REG = 3

W=2

C=1

After Instruction

REG = FF

W=2

C=0

Z=0

N = 1 ; result is negative

Example 2: SUBFWB REG, 0, 0

Before Instruction

REG = 2

W=5

C=1

After Instruction

REG = 2

W=3

C=1

Z=0

N = 0 ; result is positive

Example 3: SUBFWB REG, 1, 0

Before Instruction

REG = 1

W=2

C=0

After Instruction

REG = 0

W=2

C=1

Z = 1 ; result is zero

N=0

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SUBLW Subtract W from Literal

Syntax: SUBLW k

Operands: 0 k 255

Operation: k – (W) W

Status Affected: N, OV, C, DC, Z

Encoding: 0000 1000 kkkk kkkk

Description: W is subtracted from the eight-bit

literal ‘k’. The result is placed in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

Example 1: SUBLW 02h

Before Instruction

W = 01h

C=?

After Instruction

W = 01h

C=1 ; result is positive

Z=0

N=0

Example 2: SUBLW 02h

Before Instruction

W = 02h

C=?

After Instruction

W = 00h

C=1 ; result is zero

Z=1

N=0

Example 3: SUBLW 02h

Before Instruction

W = 03h

C=?

After Instruction

W = FFh ; (2’s complement)

C=0 ; result is negative

Z=0

N=1

SUBWF Subtract W from f

Syntax: SUBWF f {,d {,a}}

Operands: 0 f 255

d  [0,1]

a  [0,1]

Operation: (f) – (W) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 11da ffff ffff

Description: Subtract W from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the result

is stored back in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBWF REG, 1, 0

Before Instruction

REG = 3

W=2

C=?

After Instruction

REG = 1

W=2

C = 1 ; result is positive

Z=0

N=0

Example 2: SUBWF REG, 0, 0

Before Instruction

REG = 2

W=2

C=?

After Instruction

REG = 2

W=0

C = 1 ; result is zero

Z=1

N=0

Example 3: SUBWF REG, 1, 0

Before Instruction

REG = 1

W=2

C=?

After Instruction

REG = FFh ;(2’s complement)

W=2

C = 0 ; result is negative

Z=0

N=1

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SUBWFB Subtract W from f with Borrow

Syntax: SUBWFB f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f) – (W) – (C) dest

Status Affected: N, OV, C, DC, Z

Encoding: 0101 10da ffff ffff

Description: Subtract W and the Carry flag (borrow)

from register ‘f’ (2’s complement

method). If ‘d’ is ‘0’, the result is stored

in W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example 1: SUBWFB REG, 1, 0

Before Instruction

REG = 19h (0001 1001)

W=0Dh (0000 1101)

C=1

After Instruction

REG = 0Ch (0000 1011)

W=0Dh (0000 1101)

C=1

Z=0

N=0 ; result is positive

Example 2: SUBWFB REG, 0, 0

Before Instruction

REG = 1Bh (0001 1011)

W=1Ah (0001 1010)

C=0

After Instruction

REG = 1Bh (0001 1011)

W = 00h

C=1

Z=1 ; result is zero

N=0

Example 3: SUBWFB REG, 1, 0

Before Instruction

REG = 03h (0000 0011)

W=0Eh (0000 1101)

C=1

After Instruction

REG = F5h (1111 0100)

; [2’s comp]

W=0Eh (0000 1101)

C=0

Z=0

N=1 ; result is negative

SWAPF Swap f

Syntax: SWAPF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (f<3:0>)  dest<7:4>,

(f<7:4>)  dest<3:0>

Status Affected: None

Encoding: 0011 10da ffff ffff

Description: The upper and lower nibbles of register

‘f’ are exchanged. If ‘d’ is ‘0’, the result

is placed in W. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: SWAPF REG, 1, 0

Before Instruction

REG = 53h

After Instruction

REG = 35h

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TBLRD Table Read

Syntax: TBLRD ( *; *+; *-; +*)

Operands: None

Operation: if TBLRD *,

(Prog Mem (TBLPTR))  TABLAT;

TBLPTR – No Change

if TBLRD *+,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) + 1  TBLPTR

if TBLRD *-,

(Prog Mem (TBLPTR))  TABLAT;

(TBLPTR) – 1  TBLPTR

if TBLRD +*,

(TBLPTR) + 1  TBLPTR;

(Prog Mem (TBLPTR))  TABLAT

Status Affected: None

Encoding: 0000 0000 0000 10nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction is used to read the contents

of Program Memory (P.M.). To address the

program memory, a pointer called Table

Pointer (TBLPTR) is used.

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory. TBLPTR

has a 2-Mbyte address range.

TBLPTR<0> = 0:Least Significant Byte of

Program Memory Word

TBLPTR<0> = 1:Most Significant Byte of

Program Memory Word

The TBLRD instruction can modify the value

of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

No operation

(Read Program

Memory)

operation

No operation

(Write

TABLAT)

TBLRD Table Read (Continued)

Example 1: TBLRD *+ ;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

MEMORY(00A356h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 00A357h

Example 2: TBLRD +* ;

Before Instruction

TABLAT = AAh

TBLPTR = 01A357h

MEMORY(01A357h) = 12h

MEMORY(01A358h) = 34h

After Instruction

TABLAT = 34h

TBLPTR = 01A358h

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TBLWT Table Write

Syntax: TBLWT ( *; *+; *-; +*)

Operands: None

Operation: if TBLWT*,

(TABLAT)  Holding Register;

TBLPTR – No Change

if TBLWT*+,

(TABLAT)  Holding Register;

(TBLPTR) + 1  TBLPTR

if TBLWT*-,

(TABLAT)  Holding Register;

(TBLPTR) – 1  TBLPTR

if TBLWT+*,

(TBLPTR) + 1  TBLPTR;

(TABLAT)  Holding Register

Status Affected: None

Encoding: 0000 0000 0000 11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description: This instruction uses the 3 LSBs of

TBLPTR to determine which of the

8 holding registers the TABLAT is written

to. The holding registers are used to

program the contents of Program Memory

(P.M.). (Refer to Section 6.0 “Memory

Organization” for additional details on

programming Flash memory.)

The TBLPTR (a 21-bit pointer) points to

each byte in the program memory.

TBLPTR has a 2-Mbyte address range.

The LSb of the TBLPTR selects which

byte of the program memory location to

access.

TBLPTR[0] = 0:Least Significant Byte

of Program Memory

Word

TBLPTR[0] = 1:Most Significant Byte of

Program Memory

Word

The TBLWT instruction can modify the

value of TBLPTR as follows:

• no change

• post-increment

• post-decrement

• pre-increment

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode No

operation

(Read

TABLAT)

operation

(Write to

Holding

TBLWT Table Write (Continued)

Example 1: TBLWT *+;

Before Instruction

TABLAT = 55h

TBLPTR = 00A356h

HOLDING REGISTER

(00A356h) = FFh

After Instructions (table write completion)

TABLAT = 55h

TBLPTR = 00A357h

HOLDING REGISTER

(00A356h) = 55h

Example 2: TBLWT +*;

Before Instruction

TABLAT = 34h

TBLPTR = 01389Ah

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = FFh

After Instruction (table write completion)

TABLAT = 34h

TBLPTR = 01389Bh

HOLDING REGISTER

(01389Ah) = FFh

HOLDING REGISTER

(01389Bh) = 34h

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TSTFSZ Test f, Skip if 0

Syntax: TSTFSZ f {,a}

Operands: 0  f  255

a  [0,1]

Operation: skip if f = 0

Status Affected: None

Encoding: 0110 011a ffff ffff

Description: If ‘f’ = 0, the next instruction fetched

during the current instruction execution

is discarded and a NOP is executed,

making this a two-cycle instruction.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1(2)

Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

operation

If skip:

Q1 Q2 Q3 Q4

operation

If skip and followed by 2-word instruction:

Q1 Q2 Q3 Q4

operation

Example: HERE TSTFSZ CNT, 1

NZERO :

ZERO :

Before Instruction

PC = Address (HERE)

After Instruction

If CNT = 00h,

PC = Address (ZERO)

If CNT 00h,

PC = Address (NZERO)

XORLW Exclusive OR Literal with W

Syntax: XORLW k

Operands: 0 k 255

Operation: (W) .XOR. k W

Status Affected: N, Z

Encoding: 0000 1010 kkkk kkkk

Description: The contents of W are XORed with

the 8-bit literal ‘k’. The result is placed

in W.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

Example: XORLW 0AFh

Before Instruction

W=B5h

After Instruction

W=1Ah

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XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}

Operands: 0  f  255

d  [0,1]

a  [0,1]

Operation: (W) .XOR. (f) dest

Status Affected: N, Z

Encoding: 0001 10da ffff ffff

Description: Exclusive OR the contents of W with

in W. If ‘d’ is ‘1’, the result is stored back

in the register ‘f’.

If ‘a’ is ‘0’, the Access Bank is selected.

If ‘a’ is ‘1’, the BSR is used to select the

GPR bank.

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction operates

in Indexed Literal Offset Addressing

mode whenever f 95 (5Fh). See

Section 27.2.3 “Byte-Oriented and

Bit-Oriented Instructions in Indexed

Literal Offset Mode” for details.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: XORWF REG, 1, 0

Before Instruction

REG = AFh

W=B5h

After Instruction

REG = 1Ah

W=B5h

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27.2 Extended Instruction Set

In addition to the standard 75 instructions of the PIC18

instruction set, the PIC18F87J72 family of devices also

provides an optional extension to the core CPU func-

tionality. The added features include eight additional

instructions that augment Indirect and Indexed

Addressing operations and the implementation of

Indexed Literal Offset Addressing for many of the

standard PIC18 instructions.

The additional features of the extended instruction set

are enabled by default on unprogrammed devices.

Users must properly set or clear the XINST Configura-

tion bit during programming to enable or disable these

features.

The instructions in the extended set can all be

classified as literal operations, which either manipulate

the File Select Registers, or use them for Indexed

Addressing. Two of the instructions, ADDFSR and

SUBFSR, each have an additional special instantiation

for using FSR2. These versions (ADDULNK and

SUBULNK) allow for automatic return after execution.

The extended instructions are specifically implemented

to optimize re-entrant program code (that is, code that

is recursive or that uses a software stack) written in

high-level languages, particularly C. Among other

things, they allow users working in high-level

languages to perform certain operations on data

structures more efficiently. These include:

• Dynamic allocation and deallocation of software

stack space when entering and leaving

subroutines

• Function Pointer invocation

• Software Stack Pointer manipulation

• Manipulation of variables located in a software

stack

A summary of the instructions in the extended instruc-

tion set is provided in Table 27-3. Detailed descriptions

are provided in Section 27.2.2 “Extended Instruction

Set”. The opcode field descriptions in Table 27-1

(page 334) apply to both the standard and extended

PIC18 instruction sets.

27.2.1 EXTENDED INSTRUCTION SYNTAX

Most of the extended instructions use indexed argu-

ments, using one of the File Select Registers and some

offset to specify a source or destination register. When

an argument for an instruction serves as part of

Indexed Addressing, it is enclosed in square brackets

(“[ ]”). This is done to indicate that the argument is used

as an index or offset. The MPASM™ Assembler will

flag an error if it determines that an index or offset value

is not bracketed.

When the extended instruction set is enabled, brackets

are also used to indicate index arguments in

byte-oriented and bit-oriented instructions. This is in

addition to other changes in their syntax. For more

details, see Section 27.2.3.1 “Extended Instruction

Syntax with Standard PIC18 Commands”.

TABLE 27-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Note: The instruction set extension and the

Indexed Literal Offset Addressing mode

were designed for optimizing applications

written in C; the user may likely never use

these instructions directly in assembler.

The syntax for these commands is

provided as a reference for users who may

be reviewing code that has been

generated by a compiler.

Note: In the past, square brackets have been

used to denote optional arguments in the

PIC18 and earlier instruction sets. In this

text and going forward, optional

arguments are denoted by braces (“{ }”).

Mnemonic,

Operands Description Cycles

16-Bit Instruction Word Status

Affected

MSb LSb

ADDFSR

ADDULNK

CALLW

MOVSF

MOVSS

PUSHL

SUBFSR

SUBULNK

f, k

zs, fd

zs, zd

f, k

Add Literal to FSR

Add Literal to FSR2 and Return

Call Subroutine using WREG

Move zs (source) to 1st word

fd (destination) 2nd word

Move zs (source) to 1st word

zd (destination) 2nd word

Store Literal at FSR2,

Decrement FSR2

Subtract Literal from FSR

Subtract Literal from FSR2 and

return

1110

0000

1110

1111

1110

1111

1110

1000

0000

1011

ffff

1011

xxxx

1010

1001

ffkk

11kk

0001

0zzz

ffff

1zzz

xzzz

kkkk

ffkk

11kk

kkkk

0100

zzzz

ffff

zzzz

kkkk

None

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27.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR

Syntax: ADDFSR f, k

Operands: 0  k  63

f  [ 0, 1, 2 ]

Operation: FSR(f) + k  FSR(f)

Status Affected: None

Encoding: 1110 1000 ffkk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of the FSR specified by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

FSR

Example: ADDFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 0422h

ADDULNK Add Literal to FSR2 and Return

Syntax: ADDULNK k

Operands: 0  k  63

Operation: FSR2 + k  FSR2,

(TOS) PC

Status Affected: None

Encoding: 1110 1000 11kk kkkk

Description: The 6-bit literal ‘k’ is added to the

contents of FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during

the second cycle.

This may be thought of as a special

case of the ADDFSR instruction,

where f = 3 (binary ‘11’); it operates

only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

literal ‘k’

Process

Data

Write to

FSR

Operation

Example: ADDULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 0422h

PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in

symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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CALLW Subroutine Call Using WREG

Syntax: CALLW

Operands: None

Operation: (PC + 2)  TOS,

(W)  PCL,

(PCLATH)  PCH,

(PCLATU)  PCU

Status Affected: None

Encoding: 0000 0000 0001 0100

Description First, the return address (PC + 2) is

pushed onto the return stack. Next, the

contents of W are written to PCL; the

existing value is discarded. Then, the

contents of PCLATH and PCLATU are

latched into PCH and PCU,

respectively. The second cycle is

executed as a NOP instruction while the

new next instruction is fetched.

Unlike CALL, there is no option to

update W, STATUS or BSR.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

WREG

Push PC to

stack

operation

Example: HERE CALLW

Before Instruction

PC = address (HERE)

PCLATH = 10h

PCLATU = 00h

W = 06h

After Instruction

PC = 001006h

TOS = address (HERE + 2)

PCLATH = 10h

PCLATU = 00h

W = 06h

MOVSF Move Indexed to f

Syntax: MOVSF [zs], fd

Operands: 0  zs  127

0  fd  4095

Operation: ((FSR2) + zs)  fd

Status Affected: None

Encoding:

1st word (source)

2nd word (destin.)

1110

1111

1011

ffff

0zzz

ffff

zzzzs

ffffd

Description: The contents of the source register are

moved to destination register ‘fd’. The

actual address of the source register is

determined by adding the 7-bit literal

offset ‘zs’, in the first word, to the value

of FSR2. The address of the destination

‘fd’ in the second word. Both addresses

can be anywhere in the 4096-byte data

space (000h to FFFh).

The MOVSF instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an Indirect Addressing register, the

value returned will be 00h.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr

Determine

source addr

Read

source reg

Decode No

operation

No dummy

read

operation

Write

(dest)

Example: MOVSF [05h], REG2

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

REG2 = 33h

 2010 Microchip Technology Inc. Preliminary DS39979A-page 379

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MOVSS Move Indexed to Indexed

Syntax: MOVSS [zs], [zd]

Operands: 0  zs  127

0  zd  127

Operation: ((FSR2) + zs)  ((FSR2) + zd)

Status Affected: None

Encoding:

1st word (source)

2nd word (dest.)

1110

1111

1011

xxxx

1zzz

xzzz

zzzzs

zzzzd

Description The contents of the source register are

moved to the destination register. The

addresses of the source and destination

registers are determined by adding the

7-bit literal offsets, ‘zs’ or ‘zd’,

respectively, to the value of FSR2. Both

registers can be located anywhere in

the 4096-byte data memory space

(000h to FFFh).

The MOVSS instruction cannot use the

PCL, TOSU, TOSH or TOSL as the

destination register.

If the resultant source address points to

an Indirect Addressing register, the

value returned will be 00h. If the

resultant destination address points to

an Indirect Addressing register, the

instruction will execute as a NOP.

Words: 2

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Determine

source addr

Determine

source addr

Read

source reg

Decode Determine

dest addr

Determine

dest addr

Write

to dest reg

Example: MOVSS [05h], [06h]

Before Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 11h

After Instruction

FSR2 = 80h

Contents

of 85h = 33h

Contents

of 86h = 33h

PUSHL Store Literal at FSR2, Decrement FSR2

Syntax: PUSHL k

Operands: 0k  255

Operation: k  (FSR2),

FSR2 – 1  FSR2

Status Affected: None

Encoding: 1111 1010 kkkk kkkk

Description: The 8-bit literal ‘k’ is written to the data

memory address specified by FSR2.

FSR2 is decremented by 1 after the

operation.

This instruction allows users to push

values onto a software stack.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

data

Write to

destination

Example: PUSHL 08h

Before Instruction

FSR2H:FSR2L = 01ECh

Memory (01ECh) = 00h

After Instruction

FSR2H:FSR2L = 01EBh

Memory (01ECh) = 08h

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DS39979A-page 380 Preliminary  2010 Microchip Technology Inc.

SUBFSR Subtract Literal from FSR

Syntax: SUBFSR f, k

Operands: 0  k  63

f  [ 0, 1, 2 ]

Operation: FSRf – k  FSRf

Status Affected: None

Encoding: 1110 1001 ffkk kkkk

Description: The 6-bit literal ‘k’ is subtracted from

the contents of the FSR specified

by ‘f’.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: SUBFSR 2, 23h

Before Instruction

FSR2 = 03FFh

After Instruction

FSR2 = 03DCh

SUBULNK Subtract Literal from FSR2 and Return

Syntax: SUBULNK k

Operands: 0  k  63

Operation: FSR2 – k  FSR2,

(TOS) PC

Status Affected: None

Encoding: 1110 1001 11kk kkkk

Description: The 6-bit literal ‘k’ is subtracted from the

contents of the FSR2. A RETURN is then

executed by loading the PC with the

TOS.

The instruction takes two cycles to

execute; a NOP is performed during the

second cycle.

This may be thought of as a special case

of the SUBFSR instruction, where f = 3

(binary ‘11’); it operates only on FSR2.

Words: 1

Cycles: 2

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Operation

Example: SUBULNK 23h

Before Instruction

FSR2 = 03FFh

PC = 0100h

After Instruction

FSR2 = 03DCh

PC = (TOS)

 2010 Microchip Technology Inc. Preliminary DS39979A-page 381

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27.2.3 BYTE-ORIENTED AND

BIT-ORIENTED INSTRUCTIONS IN

INDEXED LITERAL OFFSET MODE

In addition to eight new commands in the extended set,

enabling the extended instruction set also enables

Indexed Literal Offset Addressing (Section 6.6.1

“Indexed Addressing with Literal Offset”). This has

a significant impact on the way that many commands of

the standard PIC18 instruction set are interpreted.

When the extended set is disabled, addresses embed-

ded in opcodes are treated as literal memory locations:

either as a location in the Access Bank (a = 0) or in a

GPR bank designated by the BSR (a = 1). When the

extended instruction set is enabled and a = 0, however,

a file register argument of 5Fh or less is interpreted as

an offset from the pointer value in FSR2 and not as a

literal address. For practical purposes, this means that

all instructions that use the Access RAM bit as an

argument – that is, all byte-oriented and bit-oriented

instructions, or almost half of the core PIC18 instruc-

tions – may behave differently when the extended

instruction set is enabled.

When the content of FSR2 is 00h, the boundaries of the

Access RAM are essentially remapped to their original

values. This may be useful in creating

backward-compatible code. If this technique is used, it

may be necessary to save the value of FSR2 and

restore it when moving back and forth between C and

assembly routines in order to preserve the Stack

Pointer. Users must also keep in mind the syntax

requirements of the extended instruction set (see

Section 27.2.3.1 “Extended Instruction Syntax with

Standard PIC18 Commands”).

Although the Indexed Literal Offset mode can be very

useful for dynamic stack and pointer manipulation, it

can also be very annoying if a simple arithmetic opera-

tion is carried out on the wrong register. Users who are

accustomed to the PIC18 programming must keep in

mind that, when the extended instruction set is

enabled, register addresses of 5Fh or less are used for

Indexed Literal Offset Addressing.

Representative examples of typical byte-oriented and

bit-oriented instructions in the Indexed Literal Offset

mode are provided on the following page to show how

execution is affected. The operand conditions shown in

the examples are applicable to all instructions of these

types.

27.2.3.1 Extended Instruction Syntax with

Standard PIC18 Commands

When the extended instruction set is enabled, the file

bit-oriented commands is replaced with the literal offset

value ‘k’. As already noted, this occurs only when ‘f’ is

less than or equal to 5Fh. When an offset value is used,

it must be indicated by square brackets (“[ ]”). As with

the extended instructions, the use of brackets indicates

to the compiler that the value is to be interpreted as an

index or an offset. Omitting the brackets, or using a

value greater than 5Fh within the brackets, will

generate an error in the MPASM™ Assembler.

If the index argument is properly bracketed for Indexed

Literal Offset Addressing, the Access RAM argument is

never specified; it will automatically be assumed to be

‘0’. This is in contrast to standard operation (extended

instruction set disabled), when ‘a’ is set on the basis of

the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM

Assembler.

The destination argument ‘d’ functions as before.

In the latest versions of the MPASM Assembler,

language support for the extended instruction set must

be explicitly invoked. This is done with either the

command line option, /y, or the PE directive in the

source listing.

27.2.4 CONSIDERATIONS WHEN

ENABLING THE EXTENDED

INSTRUCTION SET

It is important to note that the extensions to the instruc-

tion set may not be beneficial to all users. In particular,

users who are not writing code that uses a software

stack may not benefit from using the extensions to the

instruction set.

Additionally, the Indexed Literal Offset Addressing

mode may create issues with legacy applications

written to the PIC18 assembler. This is because

instructions in the legacy code may attempt to address

registers in the Access Bank below 5Fh. Since these

addresses are interpreted as literal offsets to FSR2

when the instruction set extension is enabled, the

application may read or write to the wrong data

addresses.

When porting an application to the PIC18F87J72

family, it is very important to consider the type of code.

A large, re-entrant application that is written in C and

would benefit from efficient compilation will do well

when using the instruction set extensions. Legacy

applications that heavily use the Access Bank will most

likely not benefit from using the extended instruction

set.

Note: Enabling the PIC18 instruction set exten-

sion may cause legacy applications to

behave erratically or fail entirely.

PIC18F87J72 FAMILY

DS39979A-page 382 Preliminary  2010 Microchip Technology Inc.

ADDWF ADD W to Indexed

(Indexed Literal Offset mode)

Syntax: ADDWF [k] {,d}

Operands: 0  k  95

d  [0,1]

Operation: (W) + ((FSR2) + k)  dest

Status Affected: N, OV, C, DC, Z

Encoding: 0010 01d0 kkkk kkkk

Description: The contents of W are added to the

contents of the register indicated by

FSR2, offset by the value ‘k’.

If ‘d’ is ‘0’, the result is stored in W. If ‘d’

is ‘1’, the result is stored back in

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data

Write to

destination

Example: ADDWF [OFST] ,0

Before Instruction

W = 17h

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 20h

After Instruction

W = 37h

Contents

of 0A2Ch = 20h

BSF Bit Set Indexed

(Indexed Literal Offset mode)

Syntax: BSF [k], b

Operands: 0  f  95

0  b  7

Operation: 1  ((FSR2) + k)

Status Affected: None

Encoding: 1000 bbb0 kkkk kkkk

Description: Bit ‘b’ of the register indicated by FSR2,

offset by the value ‘k’, is set.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read

Process

Data

Write to

destination

Example: BSF [FLAG_OFST], 7

Before Instruction

FLAG_OFST = 0Ah

FSR2 = 0A00h

Contents

of 0A0Ah = 55h

After Instruction

Contents

of 0A0Ah = D5h

SETF Set Indexed

(Indexed Literal Offset mode)

Syntax: SETF [k]

Operands: 0  k  95

Operation: FFh  ((FSR2) + k)

Status Affected: None

Encoding: 0110 1000 kkkk kkkk

Description: The contents of the register indicated by

FSR2, offset by ‘k’, are set to FFh.

Words: 1

Cycles: 1

Q Cycle Activity:

Q1 Q2 Q3 Q4

Decode Read ‘k’ Process

Data

Write

Example: SETF [OFST]

Before Instruction

OFST = 2Ch

FSR2 = 0A00h

Contents

of 0A2Ch = 00h

After Instruction

Contents

of 0A2Ch = FFh

 2010 Microchip Technology Inc. Preliminary DS39979A-page 383

PIC18F87J72 FAMILY

27.2.5 SPECIAL CONSIDERATIONS WITH

MICROCHIP MPLAB® IDE TOOLS

The latest versions of Microchip’s software tools have

been designed to fully support the extended instruction

set for the PIC18F87J72 family. This includes the

MPLAB C18 C Compiler, MPASM assembly language

and MPLAB Integrated Development Environment

(IDE).

When selecting a target device for software

development, MPLAB IDE will automatically set default

Configuration bits for that device. The default setting for

the XINST Configuration bit is ‘1’, enabling the

extended instruction set and Indexed Literal Offset

Addressing. For proper execution of applications

developed to take advantage of the extended

instruction set, XINST must be set during

programming.

To develop software for the extended instruction set,

the user must enable support for the instructions and

the Indexed Addressing mode in their language tool(s).

Depending on the environment being used, this may be

done in several ways:

• A menu option or dialog box within the

environment that allows the user to configure the

language tool and its settings for the project

• A command line option

• A directive in the source code

These options vary between different compilers,

assemblers and development environments. Users are

encouraged to review the documentation accompany-

ing their development systems for the appropriate

information.

PIC18F87J72 FAMILY

DS39979A-page 384 Preliminary  2010 Microchip Technology Inc.

NOTES:

 2010 Microchip Technology Inc. Preliminary DS39979A-page 385

PIC18F87J72 FAMILY

28.0 DEVELOPMENT SUPPORT

The PIC® microcontrollers and dsPIC® digital signal

controllers are supported with a full range of software

and hardware development tools:

• Integrated Development Environment

- MPLAB® IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASMTM Assembler

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

•Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

28.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16/32-bit

microcontroller market. The MPLAB IDE is a Windows®

operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch

windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to

emulator and simulator tools (automatically

updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

PIC18F87J72 FAMILY

DS39979A-page 386 Preliminary  2010 Microchip Technology Inc.

28.2 MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the

dsPIC30 and dsPIC33 families of digital signal control-

lers. These compilers provide powerful integration

capabilities, superior code optimization and ease of

use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

28.3 HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems

are complete ANSI C compilers for Microchip’s PIC

family of microcontrollers and the dsPIC family of digital

signal controllers. These compilers provide powerful

integration capabilities, omniscient code generation

and ease of use.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The compilers include a macro assembler, linker, pre-

processor, and one-step driver, and can run on multiple

platforms.

28.4 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel® standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multi-purpose

source files

• Directives that allow complete control over the

assembly process

28.5 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

28.6 MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses

the assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

 2010 Microchip Technology Inc. Preliminary DS39979A-page 387

PIC18F87J72 FAMILY

28.7 MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC® DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

28.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs PIC® Flash MCUs and dsPIC® Flash DSCs

with the easy-to-use, powerful graphical user interface of

the MPLAB Integrated Development Environment (IDE),

included with each kit.

The emulator is connected to the design engineer’s PC

using a high-speed USB 2.0 interface and is connected

to the target with either a connector compatible with in-

circuit debugger systems (RJ11) or with the new high-

speed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware

downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new

features will be added. MPLAB REAL ICE offers signifi-

cant advantages over competitive emulators including

low-cost, full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, a rugge-

dized probe interface and long (up to three meters) inter-

connection cables.

28.9 MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Micro-

chip’s most cost effective high-speed hardware

debugger/programmer for Microchip Flash Digital Sig-

nal Controller (DSC) and microcontroller (MCU)

devices. It debugs and programs PIC® Flash microcon-

trollers and dsPIC® DSCs with the powerful, yet easy-

to-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is con-

nected to the design engineer’s PC using a high-speed

USB 2.0 interface and is connected to the target with a

connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

28.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and program-

ming of PIC® and dsPIC® Flash microcontrollers at a

most affordable price point using the powerful graphical

user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected

to the design engineer’s PC using a full speed USB

interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector

uses two device I/O pins and the reset line to imple-

ment in-circuit debugging and In-Circuit Serial Pro-

gramming™.

The PICkit 3 Debug Express include the PICkit 3, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

PIC18F87J72 FAMILY

DS39979A-page 388 Preliminary  2010 Microchip Technology Inc.

28.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is

a low-cost development tool with an easy to use inter-

face for programming and debugging Microchip’s Flash

families of microcontrollers. The full featured

Windows® programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,

dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit

microcontrollers, and many Microchip Serial EEPROM

products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2

enables in-circuit debugging on most PIC® microcon-

trollers. In-Circuit-Debugging runs, halts and single

steps the program while the PIC microcontroller is

embedded in the application. When halted at a break-

point, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo

board and microcontroller, hookup cables and CDROM

with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

28.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an MMC card for file

storage and data applications.

28.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

for analog filter design, KEELOQ® security ICs, CAN,

IrDA®, PowerSmart battery management, SEEVAL®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 389

PIC18F87J72 FAMILY

29.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(†)

Ambient temperature under bias.............................................................................................................-40°C to +100°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any digital only I/O pin or MCLR with respect to VSS (except VDD) ........................................... -0.3V to 5.6V

Voltage on any combined digital and analog pin with respect to VSS (except VDD and MCLR)...... -0.3V to (VDD + 0.3V)

Voltage on VDDCORE with respect to VSS................................................................................................... -0.3V to 2.75V

Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to 3.6V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Maximum output current sunk by PORTA<7:6> and any PORTB and PORTC I/O pins.........................................25 mA

Maximum output current sunk by any PORTD, PORTE and PORTJ I/O pins ..........................................................8 mA

Maximum output current sunk by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins ............................2 mA

Maximum output current sourced by PORTA<7:6> and any PORTB and PORTC I/O pins ...................................25 mA

Maximum output current sourced by any PORTD, PORTE and PORTJ I/O pins.....................................................8 mA

Maximum output current sourced by PORTA<5:0> and any PORTF, PORTG and PORTH I/O pins .......................2 mA

Maximum current sunk byall ports combined.......................................................................................................200 mA

Voltage on AFE SVDD ................................................................................................................................................7.0V

AFE digital inputs and outputs with respect to SAVSS ..................................................................-0.6V to (SVDD + 0.6V)

AFE analog input with respect to SAVSS...................................................................................................... ....-6V to +6V

AFE VREF input with respect to SAVSS .........................................................................................-0.6V to (SVDD + 0.6V)

ESD on the AFE analog inputs (HBM(2),MM(3)) ............................................................................................7.0 kV, 400V

ESD on all other AFE pins (HBM(2),MM(3))................................................................................................... 7.0 kV, 400V

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD –  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL)

2: Human Body Model for ESD testing.

3: Machine Model for ESD testing.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC18F87J72 FAMILY

DS39979A-page 390 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-1: VOLTAGE-FREQUENCY GRAPH,

REGULATOR ENABLED (INDUSTRIAL)(1)

FIGURE 29-2: VOLTAGE-FREQUENCY GRAPH,

REGULATOR DISABLED (INDUSTRIAL)(1,2)

Frequency

Voltage (VDD)

4.0V

2.0V

48 MHz

3.5V

3.0V

2.5V

3.6V

2.35V

Note 1: When the on-chip regulator is enabled, its BOR circuit will automatically trigger a device Reset

before VDD reaches a level at which full-speed operation is not possible.

8 MHz

PIC18F8XJ72

Frequency

Voltage (VDDCORE)

3.00V

2.00V

48 MHz

2.75V

2.50V

2.25V

2.7V

8 MHz

2.35V

Note 1: When the on-chip voltage regulator is disabled, VDD and VDDCORE must be maintained so that

VDDCORE VDD 3.6V.

PIC18F8XJ72

 2010 Microchip Technology Inc. Preliminary DS39979A-page 391

PIC18F87J72 FAMILY

29.1 DC Characteristics: Supply Voltage

PIC18F87J72 Family (Industrial)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for industrial

Param

No. Symbol Characteristic Min Typ Max Units Conditions

D001 VDD Supply Voltage VDDCORE

2.0

—

3.6

ENVREG tied to VSS

ENVREG tied to VDD

D001B VDDCORE External Supply for

Microcontroller Core

2.0 — 2.70 V ENVREG tied to VSS

D001C AVDD Analog Supply Voltage VDD – 0.3 — VDD + 0.3 V

D001D AVSS Analog Ground Potential VSS – 0.3 — VSS + 0.3 V

D002 VDR RAM Data Retention

Voltage(1)

1.5 — — V

D003 VPOR VDD Start Voltage

to Ensure Internal

Power-on Reset Signal

——0.7VSee Section 5.3 “Power-on

Reset (POR)” for details

D004 SVDD VDD Rise Rate

to Ensure Internal

Power-on Reset Signal

0.05 — — V/ms See Section 5.3 “Power-on

Reset (POR)” for details

D005 VBOR Brown-out Reset Voltage —1.8—V

Note 1: This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data.

PIC18F87J72 FAMILY

DS39979A-page 392 Preliminary  2010 Microchip Technology Inc.

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Power-Down Current (IPD)(1)

All devices 0.5 1.4 A -40°C

VDD = 2.0V(4)

(Sleep mode)

0.1 1.4 A+25°C

0.8 6 A+60°C

5.5 10.2 A+85°C

All devices 0.5 1.5 A -40°C

VDD = 2.5V(4)

(Sleep mode)

0.1 1.5 A+25°C

18A+60°C

6.8 12.6 A+85°C

All devices 2.9 7 A -40°C

VDD = 3.3V(5)

(Sleep mode)

3.6 7 A+25°C

4.1 10 A+60°C

9.6 19 A+85°C

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 393

PIC18F87J72 FAMILY

Supply Current (IDD)(2,3)

All devices 5 14.2 A -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 31 kHz

(RC_RUN mode,

internal oscillator source)

5.5 14.2 A +25°C

10 19.0 A +85°C

All devices 6.8 16.5 A -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

7.6 16.5 A +25°C

14 22.4 A +85°C

All devices 37 84 A -40°C

51 84 A +25°C VDD = 3.3V(5)

72 108 A +85°C

All devices 0.43 0.82 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 1 MHz

(RC_RUN mode,

internal oscillator source)

0.47 0.82 mA +25°C

0.52 0.95 mA +85°C

All devices 0.52 0.98 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.57 0.98 mA +25°C

0.63 1.10 mA +85°C

All devices 0.59 0.96 mA -40°C

0.65 0.96 mA +25°C VDD = 3.3V(5)

0.72 1.18 mA +85°C

All devices 0.88 1.45 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 4 MHz

(RC_RUN mode,

internal oscillator source)

1 1.45 mA +25°C

1.1 1.58 mA +85°C

All devices 1.2 1.72 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

1.3 1.72 mA +25°C

1.4 1.85 mA +85°C

All devices 1.3 2.87 mA -40°C

1.4 2.87 mA +25°C VDD = 3.3V(5)

1.5 2.96 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

PIC18F87J72 FAMILY

DS39979A-page 394 Preliminary  2010 Microchip Technology Inc.

Supply Current (IDD) Cont.(2,3)

All devices 3 9.4 A -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 31 kHz

(RC_IDLE mode,

internal oscillator source)

3.3 9.4 A +25°C

8.5 17.2 A +85°C

All devices 4 10.5 A -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

4.3 10.5 A +25°C

10.3 19.5 A +85°C

All devices 34 82 A -40°C

48 82 A +25°C VDD = 3.3V(5)

69 105 A +85°C

All devices 0.33 0.75 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 1 MHz

(RC_IDLE mode,

internal oscillator source)

0.37 0.75 mA +25°C

0.41 0.84 mA +85°C

All devices 0.39 0.78 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.42 0.78 mA +25°C

0.47 0.91 mA +85°C

All devices 0.43 0.82 mA -40°C

0.48 0.82 mA +25°C VDD = 3.3V(5)

0.54 0.95 mA +85°C

All devices 0.53 0.98 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 4 MHz

(RC_IDLE mode,

internal oscillator source)

0.57 0.98 mA +25°C

0.61 1.12 mA +85°C

All devices 0.63 1.14 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.67 1.14 mA +25°C

0.72 1.25 mA +85°C

All devices 0.7 1.27 mA -40°C

0.76 1.27 mA +25°C VDD = 3.3V(5)

0.82 1.45 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 395

PIC18F87J72 FAMILY

Supply Current (IDD) Cont.(2,3)

All devices 0.17 0.35 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 1 MHZ

(PRI_RUN mode,

EC oscillator)

0.18 0.35 mA +25°C

0.20 0.42 mA +85°C

All devices 0.29 0.52 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.31 0.52 mA +25°C

0.34 0.61 mA +85°C

All devices 0.59 1.1 mA -40°C

0.44 0.85 mA +25°C VDD = 3.3V(5)

0.42 0.85 mA +85°C

All devices 0.70 1.25 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 4 MHz

(PRI_RUN mode,

EC oscillator)

0.75 1.25 mA +25°C

0.79 1.36 mA +85°C

All devices 1.10 1.7 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

1.10 1.7 mA +25°C

1.12 1.82 mA +85°C

All devices 1.55 1.95 mA -40°C

1.47 1.89 mA +25°C VDD = 3.3V(5)

1.54 1.92 mA +85°C

All devices 9.9 14.8 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

FOSC = 48 MHZ

(PRI_RUN mode,

EC oscillator)

9.5 14.8 mA +25°C

10.1 15.2 mA +85°C

All devices 13.3 23.2 mA -40°C

12.2 22.7 mA +25°C VDD = 3.3V(5)

12.1 22.7 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

PIC18F87J72 FAMILY

DS39979A-page 396 Preliminary  2010 Microchip Technology Inc.

Supply Current (IDD) Cont.(2,3)

All devices 4.5 5.2 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

FOSC = 4 MHZ,

16 MHz internal

(PRI_RUN HSPLL mode)

4.4 5.2 mA +25°C

4.5 5.2 mA +85°C

All devices 5.7 6.7 mA -40°C

VDD = 3.3V(5)

5.5 6.3 mA +25°C

5.3 6.3 mA +85°C

All devices 10.8 13.5 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

FOSC = 10 MHZ,

40 MHz internal

(PRI_RUN HSPLL mode)

10.8 13.5 mA +25°C

9.9 13.0 mA +85°C

All devices 13.4 24.1 mA -40°C

VDD = 3.3V(5)

12.3 20.2 mA +25°C

11.2 19.5 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 397

PIC18F87J72 FAMILY

Supply Current (IDD) Cont.(2,3)

All devices 0.10 0.26 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 1 MHz

(PRI_IDLE mode,

EC oscillator)

0.07 0.18 mA +25°C

0.09 0.22 mA +85°C

All devices 0.25 0.48 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.13 0.30 mA +25°C

0.10 0.26 mA +85°C

All devices 0.45 0.68 mA -40°C

0.26 0.45 mA +25°C VDD = 3.3V(5)

0.30 0.54 mA +85°C

All devices 0.36 0.60 mA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 4 MHz

(PRI_IDLE mode,

EC oscillator)

0.33 0.56 mA +25°C

0.35 0.56 mA +85°C

All devices 0.52 0.81 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

0.45 0.70 mA +25°C

0.46 0.70 mA +85°C

All devices 0.80 1.15 mA -40°C

0.66 0.98 mA +25°C VDD = 3.3V(5)

0.65 0.98 mA +85°C

All devices 5.2 6.5 mA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

FOSC = 48 MHz

(PRI_IDLE mode,

EC oscillator)

4.9 5.9 mA +25°C

3.4 4.5 mA +85°C

All devices 6.2 12.4 mA -40°C

5.9 11.5 mA +25°C VDD = 3.3V(5)

5.8 11.5 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

PIC18F87J72 FAMILY

DS39979A-page 398 Preliminary  2010 Microchip Technology Inc.

Supply Current (IDD) Cont.(2,3)

All devices 18 35 µA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 32 kHz(3)

(SEC_RUN mode,

Timer1 as clock)

19 35 µA +25°C

28 49 µA +85°C

All devices 20 45 µA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

21 45 µA +25°C

32 61 µA +85°C

All devices 0.06 0.11 mA -40°C

0.07 0.11 mA +25°C VDD = 3.3V(5)

0.09 0.15 mA +85°C

All devices 14 28 µA -40°C

VDD = 2.0V,

VDDCORE = 2.0V(4)

FOSC = 32 kHz(3)

(SEC_IDLE mode,

Timer1 as clock)

15 28 µA +25°C

24 43 µA +85°C

All devices 15 31 µA -40°C

VDD = 2.5V,

VDDCORE = 2.5V(4)

16 31 µA +25°C

27 50 µA +85°C

All devices 0.05 0.10 mA -40°C

0.06 0.10 mA +25°C VDD = 3.3V(5)

0.08 0.14 mA +85°C

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

 2010 Microchip Technology Inc. Preliminary DS39979A-page 399

PIC18F87J72 FAMILY

D022 Module Differential Currents (IWDT, IOSCB, IAD)

Watchdog Timer 2.1 7.0 A -40°C VDD = 2.0V,

VDDCORE = 2.0V(4)

2.2 7.0 A +25°C

4.3 9.5 A +85°C

3.0 8.0 A -40°C VDD = 2.5V,

VDDCORE = 2.5V(4)

3.1 8.0 A +25°C

5.5 10.4 A +85°C

5.9 12.1 A -40°C

VDD = 3.3V

6.2 12.1 A +25°C

6.9 13.6 A +85°C

D024

(ILCD)

LCD Module 2(6,7) 5 µA +25°C VDD = 2.0V Resistive Ladder

CPEN = 0;

CKSEL<1:0> = 00;

CS<1:0> = 10;

LP<3:0> = 0100

2.7(6,7) 5 µA +25°C VDD = 2.5V

3.5(6,7) 7 µA +25°C VDD = 3.0V

16(7) 25 µA +25°C VDD = 2.0V Charge Pump

BIAS<2:0> = 111;

CPEN = 1;

CKSEL<1:0> = 11;

CS<1:0> = 10

17(7) 25 µA +25°C VDD = 2.5V

24(7) 40 µA +25°C VDD = 3.0V

D025

(IOSCB)

RTCC + Timer1 Osc. with

32 kHz Crystal(6)

0.9 4.0 A -10°C VDD = 2.0V,

VDDCORE = 2.0V(4) 32 kHz on Timer1(3)

1.0 4.5 A +25°C

1.1 4.5 A +85°C

1.1 4.5 A -10°C VDD = 2.5V,

VDDCORE = 2.5V(4) 32 kHz on Timer1(3)

1.2 5.0 A +25°C

1.2 5.0 A +85°C

1.6 6.5 A -10°C

VDD = 3.3V 32 kHz on Timer1(3)

1.6 6.5 A +25°C

2.1 8.0 A +85°C

D026

(IAD)

A/D Converter 3.0 10.0 A -40°C to +85°C VDD = 2.0V,

VDDCORE = 2.0V(4) A/D on, not converting

3.0 10.0 A -40°C to +85°C VDD = 2.5V,

29.2 DC Characteristics: Power-Down and Supply Current

PIC18F87J72 Family (Industrial) (Continued)

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Typ Max Units Conditions

Note 1: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta

current disabled (such as WDT, Timer1 oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on

the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;

MCLR = VDD; WDT enabled/disabled as specified.

3: Standard, low-cost 32 kHz crystals have an operating temperature range of -10°C to +70°C. Extended temperature

crystals are available at a much higher cost.

4: Voltage regulator is disabled (ENVREG = 0, tied to VSS).

5: Voltage regulator is enabled (ENVREG = 1, tied to VDD, REGSLP = 1).

PIC18F87J72 FAMILY

DS39979A-page 400 Preliminary  2010 Microchip Technology Inc.

29.3 DC Characteristics: PIC18F87J72 Family (Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C T

A  +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

VIL Input Low Voltage

All I/O Ports:

D030 with TTL Buffer VSS 0.15 VDD VVDD < 3.3V

D030A — 0.8 V 3.3V  VDD 3.6V

D031 with Schmitt Trigger Buffer VSS 0.2 VDD V

D031A RC3 and RC4 only VSS 0.3 VDD VI

2C™ enabled

D031B VSS 0.8 V SMBus

D032 MCLR VSS 0.2 VDD V

D033 OSC1 VSS 0.3 VDD V HS, HSPLL modes

D033A OSC1 VSS 0.2 VDD V EC, ECPLL modes

D034 T13CKI VSS 0.3 V

VIH Input High Voltage

I/O Ports (not 5.5V tolerant):

D040 with TTL Buffer 0.25 VDD + 0.8V VDD VVDD < 3.3V

D040A 2.0 VDD 3.3V  VDD 3.6V

D041 with Schmitt Trigger Buffer 0.8 VDD VDD V

D041A RC3 and RC4 only 0.7 VDD VDD VI

2C enabled

D041B 2.1 VDD VSMBus

I/O Ports (5.5V tolerant):

with TTL Buffer 0.25 VDD + 0.8V 5.5 V VDD < 3.3V

2.0 5.5 V 3.3V  VDD 3.6V

with Schmitt Trigger Buffer 0.8 VDD 5.5 V

D042 MCLR 0.8 VDD VDD V

D043 OSC1 0.7 VDD VDD V HS, HSPLL modes

D043A

D044

OSC1

T13CKI

0.8 VDD

1.6

VDD

EC, ECPLL modes

IIL Input Leakage Current(1)

D060 I/O Ports with Analog Functions — 200 nA VSS VPIN VDD,

Pin at high-impedance

Digital Only I/O Ports — 200 nA VSS VPIN 5.5V,

Pin at high-impedance

D061 MCLR —1AVss VPIN VDD

D063 OSC1 — 1AVss VPIN VDD

IPU Weak Pull-up Current

D070 IPURB PORTB Weak Pull-up Current 80 400 AVDD = 3.3V, VPIN = VSS

Note 1: Negative current is defined as current sourced by the pin.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 401

PIC18F87J72 FAMILY

29.4 DC Characteristics: CTMU Current Source Specifications

VOL Output Low Voltage

D080 I/O Ports:

PORTA, PORTF, PORTG, — 0.4 V IOL = 2 mA, VDD = 3.3V,

-40C to +85C

PORTD, PORTE — 0.4 V IOL = 3.4 mA, VDD = 3.3V,

-40C to +85C

PORTB, PORTC — 0.4 V IOL = 3.4 mA, VDD = 3.3V,

-40C to +85C

D083 OSC2/CLKO

(EC, ECPLL modes)

—0.4VI

OL = 1.6 mA, VDD = 3.3V,

-40C to +85C

VOH Output High Voltage(1)

D090 I/O Ports: V

PORTA, PORTF, PORTG 2.4 — V IOH = -2 mA, VDD = 3.3V,

-40C to +85C

PORTD, PORTE 2.4 — V IOH = -2 mA, VDD = 3.3V,

-40C to +85C

PORTB, PORTC 2.4 — V IOH = -2 mA, VDD = 3.3V,

-40C to +85C

D092 OSC2/CLKO

(INTOSC, EC, ECPLL modes)

2.4 — V IOH = -1 mA, VDD = 3.3V,

-40C to +85C

Capacitive Loading Specs

on Output Pins

D100(4) COSC2 OSC2 Pin — 15 pF In HS mode when

external clock is used to drive

OSC1

D101 CIO All I/O Pins and OSC2 — 50 pF To meet the AC Timing

Specifications

D102 CBSCL, SDA — 400 pF I2C™ Specification

DC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)

Operating temperature -40°C  TA  +85°C for Industrial

Param

No. Sym Characteristic Min Typ(1) Max Units Conditions

IOUT1 CTMU Current Source,

Base Range

— 550 — nA CTMUICON<1:0> = 01

IOUT2 CTMU Current Source,

10x Range

—5.5—A CTMUICON<1:0> = 10

IOUT3 CTMU Current Source,

100x Range

—55—A CTMUICON<1:0> = 11

Note 1: Nominal value at center point of current trim range (CTMUICON<7:2> = 000000).

29.3 DC Characteristics: PIC18F87J72 Family (Industrial) (Continued)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C T

A  +85°C for industrial

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: Negative current is defined as current sourced by the pin.

PIC18F87J72 FAMILY

DS39979A-page 402 Preliminary  2010 Microchip Technology Inc.

TABLE 29-1: MEMORY PROGRAMMING REQUIREMENTS

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Program Flash Memory

D130 EPCell Endurance 10K — — E/W -40C to +85C

D131 VPR VDD for Read VMIN —3.6VVMIN = Minimum operating

voltage

D132B VPEW Voltage for Self-Timed Erase or

Write operations

VDD

VDDCORE

2.35

2.25

—

3.6

2.7

ENVREG tied to VDD

ENVREG tied to VSS

D133A TIW Self-Timed Write Cycle Time — 2.8 — ms

D133B TIE Self-Timed Block Erased Cycle

Time

—33—ms

D134 TRETD Characteristic Retention 20 — — Year Provided no other

specifications are violated

D135 IDDP Supply Current during

Programming

—314mA

D140 TWE Writes per Erase Cycle — — 1 For each physical address

† Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 403

PIC18F87J72 FAMILY

TABLE 29-2: COMPARATOR SPECIFICATIONS

TABLE 29-3: VOLTAGE REFERENCE SPECIFICATIONS

TABLE 29-4: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

TABLE 29-5: INTERNAL LCD VOLTAGE REGULATOR SPECIFICATIONS

Operating Conditions: 3.0V  VDD  3.6V, -40°C  TA  +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D300 VIOFF Input Offset Voltage — ±5.0 ±25 mV

D301 VICM Input Common-Mode Voltage 0 — AVDD – 1.5 V

D302 CMRR Common-Mode Rejection Ratio 55 — — dB

D303 TRESP Response Time(1) —150400 ns

D304 TMC2OV Comparator Mode Change to

Output Valid*

—— 10 s

Note 1: Response time measured with one comparator input at (AVDD – 1.5)/2, while the other input transitions

from VSS to VDD.

Operating Conditions: 3.0V  VDD  3.6V, -40°C  TA  +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

D310 VRES Resolution VDD/24 — VDD/32 LSb

D311 VRAA Absolute Accuracy — — 1/2 LSb

D312 VRUR Unit Resistor Value (R) — 2k — 

310 TSET Settling Time(1) — — 10 s

Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’.

Operating Conditions: -40°C  TA  +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

VRGOUT Regulator Output Voltage* — 2.5 — V

CEFC External Filter Capacitor Value* 4.7 10 — F Capacitor must be

low-ESR, a low series

resistance (< 5)

Operating Conditions: 2.0V  VDD  3.6V, -40°C  TA  +85°C (unless otherwise stated)

Param

No. Sym Characteristics Min Typ Max Units Comments

CFLY Fly Back Capacitor 0.47 4.7 — F Capacitor must be low-ESR

VBIAS VPK-PK between LCDBIAS0 &

LCDBIAS3

— 3.40 3.6 V BIAS<2:0> = 111

— 3.27 — V BIAS<2:0> = 110

— 3.14 — V BIAS<2:0> = 101

— 3.01 — V BIAS<2:0> = 100

— 2.88 — V BIAS<2:0> = 011

— 2.75 — V BIAS<2:0> = 010

— 2.62 — V BIAS<2:0> = 001

— 2.49 — V BIAS<2:0> = 000

PIC18F87J72 FAMILY

DS39979A-page 404 Preliminary  2010 Microchip Technology Inc.

29.5 AC (Timing) Characteristics

29.5.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

F Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T13CKI

mc MCLR wr WR

Uppercase letters and their meanings:

F Fall P Period

HHigh RRise

I Invalid (High-impedance) V Valid

L Low Z High-impedance

I2C only

AA output access High High

BUF Bus free Low Low

CC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO Stop condition

STA Start condition

 2010 Microchip Technology Inc. Preliminary DS39979A-page 405

PIC18F87J72 FAMILY

29.5.2 TIMING CONDITIONS

The temperature and voltages specified in Table 29-6

apply to all timing specifications unless otherwise

noted. Figure 29-3 specifies the load conditions for the

timing specifications.

TABLE 29-6: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 29-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  TA +85°C for industrial

Operating voltage VDD range as described in Section 29.1 and Section 29.3.

VDD/2

Pin Pin

VSS VSS

RL= 464

CL= 50 pF for all pins except OSC2/CLKO/RA6

and including D and E outputs as ports

CL= 15 pF for OSC2/CLKO/RA6

Load Condition 1 Load Condition 2

PIC18F87J72 FAMILY

DS39979A-page 406 Preliminary  2010 Microchip Technology Inc.

29.5.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 29-4: EXTERNAL CLOCK TIMING

TABLE 29-7: EXTERNAL CLOCK TIMING REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FOSC External CLKI Frequency(1) DC 48 MHz EC Oscillator mode

DC 10 ECPLL Oscillator mode

Oscillator Frequency(1) 4 25 MHz HS Oscillator mode

4 10 HSPLL Oscillator mode

OSC External CLKI Period(1) 20.8 — ns EC Oscillator mode

100 — ECPLL Oscillator mode

Oscillator Period(1) 40.0 250 ns HS Oscillator mode

100 250 HSPLL Oscillator mode

CY Instruction Cycle Time(1) 83.3 — ns TCY = 4/FOSC, Industrial

3TOSL,

TOSH

External Clock in (OSC1)

High or Low Time

10 — ns HS Oscillator mode

4TOSR,

TOSF

External Clock in (OSC1)

Rise or Fall Time

— 7.5 ns HS Oscillator mode

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations

except PLL. All specified values are based on characterization data for that particular oscillator type under

standard operating conditions with the device executing code. Exceeding these specified limits may result

in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested

to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock

input is used, the “max.” cycle time limit is “DC” (no clock) for all devices.

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

3344

 2010 Microchip Technology Inc. Preliminary DS39979A-page 407

PIC18F87J72 FAMILY

TABLE 29-8: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.15V TO 3.6V)

TABLE 29-9: INTERNAL RC ACCURACY (INTOSC AND INTRC SOURCES)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

F10 FOSC Oscillator Frequency Range 4 — 10 MHz HS mode only

F11 FSYS On-Chip VCO System Frequency 16 — 40 MHz HS mode only

F12 trc PLL Start-up Time (Lock Time) — — 2 ms

F13 CLK CLKO Stability (Jitter) -2 — +2 %

† Data in “Typ” column is at 3.3V, 25C, unless otherwise stated. These parameters are for design guidance

only and are not tested.

PIC18F87J72 Family

(Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C  T

A  +85°C for industrial

Param

No. Device Min Typ Max Units Conditions

INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1)

All Devices -2 +/-1 2 % +25°C VDD = 2.7-3.3V

-5 — 5 % -10°C to +85°C VDD = 2.0-3.3V

-10 +/-1 10 % -40°C to +85°C VDD = 2.0-3.3V

INTRC Accuracy @ Freq = 31 kHz(1)

All Devices 21.7 — 40.3 kHz -40°C to +85°C VDD = 2.0-3.3V

Note 1: The accuracy specification of the 31 kHz clock is determined by which source is providing it at a given

time. When INTSRC (OSCTUNE<7>) is ‘1’, use the INTOSC accuracy specification. When INTSRC is ‘0’,

use the INTRC accuracy specification.

PIC18F87J72 FAMILY

DS39979A-page 408 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-5: CLKO AND I/O TIMING

TABLE 29-10: CLKO AND I/O TIMING REQUIREMENTS

Param

No. Symbol Characteristic Min Typ Max Units Conditions

10 TOSH2CKLOSC1  to CLKO  —75200ns(Note 1)

11 TOSH2CKHOSC1  to CLKO  —75200ns(Note 1)

12 TCKRCLKO Rise Time — 15 30 ns(Note 1)

13 TCKF CLKO Fall Time — 15 30 ns (Note 1)

14 TCKL2IOVCLKO  to Port Out Valid — — 0.5 TCY + 20 ns

15 TIOV2CKH Port In Valid before CLKO  0.25 TCY + 25 — — ns

16 TCKH2IOI Port In Hold after CLKO  0——ns

17 TOSH2IOVOSC1  (Q1 cycle) to Port Out Valid — 50 150 ns

18 TOSH2IOIOSC1  (Q2 cycle) to Port Input Invalid

(I/O in hold time)

100 — — ns

19 TIOV2OSH Port Input Valid to OSC1 

(I/O in setup time)

0——ns

20 TIOR Port Output Rise Time — — 6 ns

21 TIOF Port Output Fall Time — — 5 ns

22† TINP INTx Pin High or Low Time TCY ——ns

23† TRBP RB<7:4> Change INTx High or Low

Time

TCY ——ns

† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in EC mode, where CLKO output is 4 x TOSC.

Note: Refer to Figure 29-3 for load conditions.

OSC1

CLKO

I/O pin

(Input)

I/O pin

(Output)

Q4 Q1 Q2 Q3

20, 21

19 18

Old Value New Value

 2010 Microchip Technology Inc. Preliminary DS39979A-page 409

PIC18F87J72 FAMILY

FIGURE 29-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

TABLE 29-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param.

No. Symbol Characteristic Min Typ Max Units Conditions

30 TMCLMCLR Pulse Width (low) 2 TCY 10

—(Note 1)

31 TWDT Watchdog Timer Time-out Period

(no postscaler)

3.4 4.0 4.6 ms

32 T

OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC TOSC = OSC1 period

33 TPWRT Power-up Timer Period 45.8 65.5 85.2 ms

34 TIOZ I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

—2—µs

38 T

CSD CPU Start-up Time — 10 — µs

200 µs Voltage Regulator

enabled and put to

sleep

39 TIOBST Time for INTOSC to Stabilize — 1 — µs

Note 1: To ensure device Reset, MCLR must be low for at least 2 TCY or 400 s, whichever is lower.

VDD

MCLR

Internal

POR

PWRT

Time-out

Oscillator

Time-out

Internal

Reset

Watchdog

Timer

Reset

I/O pins

Note: Refer to Figure 29-3 for load conditions.

PIC18F87J72 FAMILY

DS39979A-page 410 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 29-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

40 TT0H T0CKI High Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

41 TT0L T0CKI Low Pulse Width No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

42 TT0P T0CKI Period No prescaler TCY + 10 — ns

With prescaler Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value

(1, 2, 4,..., 256)

45 TT1H T13CKI High

Time

Synchronous, no prescaler 0.5 TCY + 20 — ns

Synchronous, with prescaler 10 — ns

Asynchronous 30 — ns

46 TT1L T13CKI Low

Time

Synchronous, no prescaler 0.5 TCY + 5 — ns

Synchronous, with prescaler 10 — ns

Asynchronous 30 — ns

47 TT1P T13CKI Input

Period

Synchronous Greater of:

20 ns or

(TCY + 40)/N

—nsN = prescale

value

(1, 2, 4, 8)

Asynchronous 60 — ns

FT1 T13CKI Oscillator Input Frequency Range DC 50 kHz

48 T

CKE2TMRI Delay from External T13CKI Clock Edge to

Timer Increment

2 TOSC 7 TOSC —

Note: Refer to Figure 29-3 for load conditions.

T0CKI

T1OSO/T13CKI

TMR0 or

TMR1

 2010 Microchip Technology Inc. Preliminary DS39979A-page 411

PIC18F87J72 FAMILY

FIGURE 29-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1, CCP2 MODULES)

TABLE 29-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1, CCP2 MODULES)

Param

No. Symbol Characteristic Min Max Units Conditions

50 TCCL CCPx Input Low

Time

No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

51 TCCH CCPx Input

High Time

No prescaler 0.5 TCY + 20 — ns

With prescaler 10 — ns

52 TCCP CCPx Input Period 3 TCY + 40

— ns N = prescale

value (1, 4 or 16)

53 TCCR CCPx Output Fall Time — 25 ns

54 TCCF CCPx Output Fall Time — 25 ns

Note: Refer to Figure 29-3 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

PIC18F87J72 FAMILY

DS39979A-page 412 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 29-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDI Data Input to SCK Edge 20 — ns

73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40 — ns

74 T

SCH2DIL,

SCL2DIL

Hold Time of SDI Data Input to SCK Edge 40 — ns

75 TDOR SDO Data Output Rise Time — 25 ns

76 TDOF SDO Data Output Fall Time — 25 ns

78 TSCR SCK Output Rise Time (Master mode) — 25 ns

79 T

SCF SCK Output Fall Time (Master mode) — 25 ns

80 T

SCH2DOV,

SCL2DOV

SDO Data Output Valid after SCK Edge — 50 ns

Note 1: Requires the use of Parameter #73A.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb LSb

bit 6 - - - - - - 1

LSb In

bit 6 - - - - 1

Note: Refer to Figure 29-3 for load conditions.

MSb In

 2010 Microchip Technology Inc. Preliminary DS39979A-page 413

PIC18F87J72 FAMILY

FIGURE 29-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 29-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No. Symbol Characteristic Min Max Units Conditions

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDI Data Input to SCK Edge 20 — ns

73A TB2BLast Clock Edge of Byte 1 to the 1st Clock Edge

of Byte 2

1.5 TCY + 40 — ns (Note 2)

74 T

SCH2DIL,

SCL2DIL

Hold Time of SDI Data Input to SCK Edge 40 — ns

75 TDOR SDO Data Output Rise Time — 25 ns

76 TDOF SDO Data Output Fall Time — 25 ns

78 T

SCR SCK Output Rise Time (Master mode) — 25 ns

79 T

SCF SCK Output Fall Time (Master mode) — 25 ns

80 TSCH2DOV,

SCL2DOV

SDO Data Output Valid after SCK Edge — 50 ns

81 TDOV2SCH,

TDOV2SCL

SDO Data Output Setup to SCK Edge T

CY —ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

75, 76

MSb

bit 6 - - - - - - 1

LSb In

bit 6 - - - - 1

LSb

Note: Refer to Figure 29-3 for load conditions.

MSb In

PIC18F87J72 FAMILY

DS39979A-page 414 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 29-16: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)

Param

No. Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

SS  to SCK  or SCK  Input 3 TCY —ns

70A T

SSL2WB SS to write to SSPBUF 3 TCY —ns

71 T

SCH SCK Input High Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 TSCL SCK Input Low Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73 TDIV2SCH,

TDIV2SCL

Setup Time of SDI Data Input to SCK Edge 100 — ns

73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TSCH2DIL,

SCL2DIL

Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TDOR SDO Data Output Rise Time — 25 ns

76 TDOF SDO Data Output Fall Time — 25 ns

77 T

SSH2DOZSS  to SDO Output High-Impedance 10 50 ns

78 TSCR SCK Output Rise Time (Master mode) — 25 ns

79 T

SCF SCK Output Fall Time (Master mode) — 25 ns

80 TSCH2DOV,

SCL2DOV

SDO Data Output Valid after SCK Edge — 50 ns

83 T

SCH2SSH,

SCL2SSH

SS  after SCK Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76 77

MSb LSb

bit 6 - - - - - - 1

bit 6 - - - - 1 LSb In

Note: Refer to Figure 29-3 for load conditions.

MSb In

 2010 Microchip Technology Inc. Preliminary DS39979A-page 415

PIC18F87J72 FAMILY

FIGURE 29-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 29-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param

No. Symbol Characteristic Min Max Units Conditions

70 T

SSL2SCH,

SSL2SCL

SS  to SCK  or SCK  Input 3 TCY —ns

70A TSSL2WB SS to Write to SSPBUF 3 TCY —ns

71 TSCH SCK Input High Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

71A Single Byte 40 — ns (Note 1)

72 T

SCL SCK Input Low Time

(Slave mode)

Continuous 1.25 TCY + 30 — ns

72A Single Byte 40 — ns (Note 1)

73A TB2BLast Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)

74 TSCH2DIL,

SCL2DIL

Hold Time of SDI Data Input to SCK Edge 100 — ns

75 TDOR SDO Data Output Rise Time — 25 ns

76 TDOF SDO Data Output Fall Time — 25 ns

77 T

SSH2DOZSS  to SDO Output High-Impedance 10 50 ns

78 T

SCR SCK Output Rise Time (Master mode) — 25 ns

79 TSCF SCK Output Fall Time (Master mode) — 25 ns

80 TSCH2DOV,

SCL2DOV

SDO Data Output Valid after SCK Edge — 50 ns

82 T

SSL2DOV SDO Data Output Valid after SS  Edge — 50 ns

83 T

SCH2SSH,

SCL2SSH

SS  after SCK Edge 1.5 TCY + 40 — ns

Note 1: Requires the use of Parameter #73A.

2: Only if Parameter #71A and #72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb bit 6 - - - - - - 1 LSb

bit 6 - - - - 1 LSb In

Note: Refer to Figure 29-3 for load conditions.

MSb In

PIC18F87J72 FAMILY

DS39979A-page 416 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-13: I2C™ BUS START/STOP BITS TIMING

TABLE 29-18: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition

Setup Time

100 kHz mode 4700 — ns Only relevant for Repeated

Start condition

400 kHz mode 600 —

91 THD:STA Start Condition

Hold Time

100 kHz mode 4000 — ns After this period, the first

clock pulse is generated

400 kHz mode 600 —

92 TSU:STO Stop Condition

Setup Time

100 kHz mode 4700 — ns

400 kHz mode 600 —

93 THD:STO Stop Condition

Hold Time

100 kHz mode 4000 — ns

400 kHz mode 600 —

Note: Refer to Figure 29-3 for load conditions.

SCL

SDA

Start

Condition

Stop

Condition

 2010 Microchip Technology Inc. Preliminary DS39979A-page 417

PIC18F87J72 FAMILY

FIGURE 29-14: I2C™ BUS DATA TIMING

TABLE 29-19: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High Time 100 kHz mode 4.0 — s

400 kHz mode 0.6 — s

MSSP Module 1.5 TCY —

101 TLOW Clock Low Time 100 kHz mode 4.7 — s

400 kHz mode 1.3 — s

MSSP Module 1.5 TCY —

102 TRSDA and SCL Rise Time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

103 TFSDA and SCL Fall Time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1 CB300 ns CB is specified to be from

10 to 400 pF

90 TSU:STA Start Condition Setup Time 100 kHz mode 4.7 — s Only relevant for Repeated

Start condition

400 kHz mode 0.6 — s

91 THD:STA Start Condition Hold Time 100 kHz mode 4.0 — s After this period, the first clock

pulse is generated

400 kHz mode 0.6 — s

106 THD:DAT Data Input Hold Time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 s

107 TSU:DAT Data Input Setup Time 100 kHz mode 250 — ns (Note 2)

400 kHz mode 100 — ns

92 TSU:STO Stop Condition Setup Time 100 kHz mode 4.7 — s

400 kHz mode 0.6 — s

109 TAA Output Valid from Clock 100 kHz mode — 3500 ns (Note 1)

400 kHz mode — — ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before

a new transmission can start

400 kHz mode 1.3 — s

D102 CBBus Capacitive Loading — 400 pF

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode I2C™ bus device can be used in a Standard mode I2C bus system, but the requirement, TSU:DAT 250 ns,

must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If

such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line,

TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line

is released.

Note: Refer to Figure 29-3 for load conditions.

91 92

100

101

103

106 107

109 109

110

102

SCL

SDA

Out

PIC18F87J72 FAMILY

DS39979A-page 418 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-15: MSSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS

TABLE 29-20: MSSP I2C™ BUS START/STOP BITS REQUIREMENTS

FIGURE 29-16: MSSP I2C™ BUS DATA TIMING

Param.

No. Symbol Characteristic Min Max Units Conditions

90 TSU:STA Start Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — ns Only relevant for

Repeated Start

condition

400 kHz mode 2(T

OSC)(BRG + 1) —

1 MHz mode(1,2) 2(TOSC)(BRG + 1) —

91 THD:STA Start Condition

Hold Time

100 kHz mode 2(TOSC)(BRG + 1) — ns After this period, the

first clock pulse is

generated

400 kHz mode 2(T

OSC)(BRG + 1) —

1 MHz mode(1,2) 2(TOSC)(BRG + 1) —

92 TSU:STO Stop Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — ns

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1,2) 2(TOSC)(BRG + 1) —

93 THD:STO Stop Condition

Hold Time

100 kHz mode 2(TOSC)(BRG + 1) — ns

400 kHz mode 2(TOSC)(BRG + 1) —

1 MHz mode(1,2) 2(TOSC)(BRG + 1) —

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: FOSC must be at least 16 MHz for I2C bus operation at this speed.

Note: Refer to Figure 29-3 for load conditions.

91 93

SCL

SDA

Start

Condition

Stop

Condition

90 92

Note: Refer to Figure 29-3 for load conditions.

90 91 92

100

101

103

106 107

109 109 110

102

SCL

SDA

Out

 2010 Microchip Technology Inc. Preliminary DS39979A-page 419

PIC18F87J72 FAMILY

TABLE 29-21: MSSP I2C™ BUS DATA REQUIREMENTS

Param.

No. Symbol Characteristic Min Max Units Conditions

100 THIGH Clock High

Time

100 kHz mode 2(TOSC)(BRG + 1) — µs

400 kHz mode 2(TOSC)(BRG + 1) — µs

1 MHz mode(1,2) 2(TOSC)(BRG + 1) — µs

101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — µs

400 kHz mode 2(TOSC)(BRG + 1) — µs

1 MHz mode(1,2) 2(TOSC)(BRG + 1) — µs

102 TRSDA and SCL

Rise Time

100 kHz mode — 1000 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB300 ns

1 MHz mode(1,2) — 300 ns

103 TFSDA and SCL

Fall Time

100 kHz mode — 300 ns CB is specified to be

from 10 to 400 pF

400 kHz mode 20 + 0.1 CB 300 ns

1 MHz mode(1,2) — 100 ns

90 TSU:STA Start Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — µs Only relevant for

Repeated Start condition

400 kHz mode 2(TOSC)(BRG + 1) — µs

1 MHz mode(1,2) 2(TOSC)(BRG + 1) — µs

91 THD:STA Start Condition

Hold Time

100 kHz mode 2(TOSC)(BRG + 1) — µs After this period, the first

clock pulse is generated

400 kHz mode 2(TOSC)(BRG + 1) — µs

1 MHz mode(1,2) 2(TOSC)(BRG + 1) — µs

106 THD:DAT Data Input

Hold Time

100 kHz mode 0 — ns

400 kHz mode 0 0.9 µs

1 MHz mode(1,2) ——ns

107 TSU:DAT Data Input

Setup Time

100 kHz mode 250 — ns (Note 3)

400 kHz mode 100 — ns

1 MHz mode(1,2) ——ns

92 TSU:STO Stop Condition

Setup Time

100 kHz mode 2(TOSC)(BRG + 1) — µs

400 kHz mode 2(TOSC)(BRG + 1) — µs

1 MHz mode(1,2) 2(TOSC)(BRG + 1) — µs

109 TAA Output Valid

from Clock

100 kHz mode — 3500 ns

400 kHz mode — 1000 ns

1 MHz mode(1,2) ——ns

110 TBUF Bus Free Time 100 kHz mode 4.7 — µs Time the bus must be

free before a new trans-

mission can start

400 kHz mode 1.3 — µs

1 MHz mode(1,2) ——µs

D102 CBBus Capacitive Loading — 400 pF

Legend: TBD = To Be Determined

Note 1: Maximum pin capacitance = 10 pF for all I2C™ pins.

2: FOSC must be at least 16 MHz for I2C bus operation at this speed.

3: A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but parameter

#107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW

period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the

next data bit to the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz

mode), before the SCL line is released.

PIC18F87J72 FAMILY

DS39979A-page 420 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-17: EUSART/AUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 29-22: EUSART/AUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 29-18: EUSART/AUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 29-23: EUSART/AUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

120 T

CKH2DTV SYNC XMIT (MASTER and SLAVE)

Clock High to Data Out Valid — 40 ns

121 TCKRF Clock Out Rise Time and Fall Time (Master mode) — 20 ns

122 TDTRF Data Out Rise Time and Fall Time — 20 ns

Param.

No. Symbol Characteristic Min Max Units Conditions

125 TDTV2CKL SYNC RCV (MASTER and SLAVE)

Data Hold before CKx  (DTx hold time) 10 — ns

126 TCKL2DTL Data Hold after CKx  (DTx hold time) 15 — ns

121 121

120 122

TXx/CKx

RXx/DTx

Note: Refer to Figure 29-3 for load conditions.

125

126

TXx/CKx

RXx/DTx

Note: Refer to Figure 29-3 for load conditions.

 2010 Microchip Technology Inc. Preliminary DS39979A-page 421

PIC18F87J72 FAMILY

TABLE 29-24: A/D CONVERTER CHARACTERISTICS: PIC18F87J72 FAMILY (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ Max Units Conditions

A01 NRResolution — — 12 bit VREF  3.0V

A03 EIL Integral Linearity Error — <±1 ±2.0 LSB VREF  3.0V

A04 EDL Differential Linearity

Error

— <±1 ±1.5 LSB VREF  3.0V

A06 EOFF Offset Error — <±1 ±5 LSB VREF  3.0V

A07 EGN Gain Error — <±1 ±3 LSB VREF  3.0V

A10 — Monotonicity Guaranteed(1) —VSS  VAIN  VREF

A20 VREF Reference Voltage

Range (VREFH – VREFL)

3—V

DD – VSS V For 12-bit resolution

A21 VREFH Reference Voltage High VSS + 3.0V — VDD + 0.3V V For 12-bit resolution

A22 VREFL Reference Voltage Low VSS – 0.3V — VDD – 3.0V V For 12-bit resolution

A25 VAIN Analog Input Voltage VREFL —VREFH VNote 2

A30 ZAIN Recommended

Impedance of Analog

Voltage Source

——2.5k

A50 IREF VREF Input Current(2) —

—

150

A

During VAIN acquisition.

During A/D conversion cycle.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREFH current is from the RA3/AN3/VREF+ pin or VDD, whichever is selected as the VREFH source. VREFL

current is from the RA2/AN2/VREF- pin or VSS, whichever is selected as the VREFL source.

PIC18F87J72 FAMILY

DS39979A-page 422 Preliminary  2010 Microchip Technology Inc.

FIGURE 29-19: A/D CONVERSION TIMING

TABLE 29-25: A/D CONVERSION REQUIREMENTS

Param

No. Symbol Characteristic Min Max Units Conditions

130 TAD A/D Clock Period 0.8 12.5(1) sTOSC based, VREF  3.0V

131 TCNV Conversion Time

(not including acquisition time)(2)

13 14 TAD

132 TACQ Acquisition Time(3) 1.4 — s

135 TSWC Switching Time from Convert  Sample — (Note 4)

137 TDIS Discharge Time 0.2 — s

Note 1: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

2: ADRES registers may be read on the following T

CY cycle.

3: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale

after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50.

4: On the following cycle of the device clock.

131

130

132

BSF ADCON0, GO

A/D CLK(1)

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

11 10 9 3 2 1

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction

to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . . . . .

TCY

 2010 Microchip Technology Inc. Preliminary DS39979A-page 423

PIC18F87J72 FAMILY

TABLE 29-26: DUAL-CHANNEL AFE ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated: SAVDD = 4.5 to 5.5V, SVDD = 2.7 to 5.5V, -40°C < TA <+85°C,

MCLK = 4 MHz, PRESCALE = 1, OSR = 64, GAIN = 1, Dithering Off, VIN = -0.5, dBFS = 353 mVRMS @ 50/60 Hz

Parameters Symbol Min Typical Max Units Conditions

Internal Voltage Reference

To l e r a n ce

VREF -2% 2.37 +2% V VREFEXT = 0

Temperature Coefficient TCREF — 12 — ppm/°C VREFEXT = 0

Output Impedance ZOUTREF —7 —kSAVDD = 5V,

VREFEXT = 0

Voltage Reference Input

Input Capacitance — — — 10 pF

Differential Input Voltage Range

(VREF+ – VREF-)

VREF 2.2 — 2.6 V VREF = (VREF+ – VREF-),

VREFEXT = 1

Absolute Voltage on REFIN+ Pin VREF+ 1.9 — 2.9 V VREFEXT = 1

Absolute Voltage on REFIN- Pin VREF--0.3—0.3V

ADC Performance

Resolution (no missing codes) — 24 — — bits OSR = 256

Sampling Frequency fS125 — 1000 kHz fS = DMCLK = MCLK/

(4 x Prescale)

Output Data Rate fD0.4882 — 31.25 ksps fD = DRCLK = DMCLK/

OSR = MCLK/

(4 x Prescale x OSR)

Analog Input Absolute Voltage on

CH0+, CH0-, CH1+, CH1- Pins

CHn+/- -1 — +1 V All analog input channels,

measured to SAVss

(Note 1)

Analog Input Leakage Current AIN —1 —nA(Note 2)

Differential Input Voltage Range (CHn+ – CHn-) — — 500/GAIN mV (Note 3)

Offset Error (Note 4) VOS -3 — +3 mV (Note 5)

Offset Error Drift — — 3 — V/°C From -40°C to +125°C

Gain Error (Note 4) GE — -0.4 — % G = 1

-2.5 — +2.5 % All gains

Gain Error Drift — — 1 — ppm/°C From -40°C to +125°C

Note 1: Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied

continuously to the part with no risk of damage.

2: For these operating currents, the following bit settings apply: SHUTDOWN<1:0> = 00, RESET<1:0> = 00,

VREFEXT = 0, CLKEXT = 0.

3: This specification implies that the ADC output is valid over this entire differential range and that there is no

distortion or instability across this input range. Dynamic performance is specified at -0.5 dB below the maximum

signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, mVREF = 2.4V.

4: See Appendix B.3 “Terminology and Formulas” for definitions.

5: Applies to all gains. Offset error is dependent on PGA gain setting.

6: This parameter is established by characterization and is not 100% tested.

7: For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with

BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz.

AMCLK = MCLK/PRESCALE.

8: For these operating currents, the following Configuration bit settings apply: SHUTDOWN<1:0> = 11,

VREFEXT = 1, CLKEXT = 1.

PIC18F87J72 FAMILY

DS39979A-page 424 Preliminary  2010 Microchip Technology Inc.

ADC Performance (continued)

Integral Non-Linearity (Note 4) INL — 15 — ppm GAIN = 1,

DITHER = ON

Input Impedance ZIN 350——kProportional to

1/AMCLK

Signal-to-Noise and Distortion

Ratio (Notes 4, 6)

SINAD — 90 — dB OSR = 256,

DITHER = ON

—78 — dBOSR = 64,

DITHER = OFF

Total Harmonic Distortion

(Notes 4, 6)

THD — -101 — dB OSR = 256,

DITHER = ON

— -82 — dB OSR = 64,

DITHER = OFF

Signal-to-Noise Ratio

(Notes 4, 6)

SNR — 91 — dB OSR = 256,

DITHER = ON

—81 — dBOSR = 64,

DITHER = OFF

Spurious Free Dynamic Range

(Note 4)

SFDR — 103 — dB OSR = 256,

DITHER = ON

—83 — dBOSR = 64,

DITHER = OFF

Crosstalk (50/60 Hz) (Note 4) CTALK — -133 — dB OSR = 256,

DITHER = ON

AC Power Supply Rejection AC PSRR — -77 — dB SAVDD and SVDD = 5V +

PP @ 50/60 Hz

DC Power Supply Rejection DC PSRR — -77 — dB SAVDD and SVDD = 4.5 to

5.5V

DC Common-Mode Rejection

Ratio (Note 4)

CMRR — -72 — dB VCM varies from -1V to

+1V

TABLE 29-26: DUAL-CHANNEL AFE ELECTRICAL CHARACTERISTICS (CONTINUED)