Data Sheet
26185.201E
6276
16-BIT SERIAL-INPUT, CONSTANT-
CURRENT LATCHED LED DRIV ER
The A6276 is specifically designed for LED-display applications.
Each BiCMOS device includes a 16-bit CMOS shift register, accom-
panying data latches, and 16 npn constant-current sink drivers. Except
for package style and allowable package power dissipation, the device
options are identical.
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V logic supply, typical serial
data-input rates are up to 20 MHz. The LED drive current is de ter -
mined by the user’s selection of a single resistor. A CMOS serial data
output permits cascade connections in applications requiring additional
drive lines. For inter-digit blanking, all output drivers can be disabled
with an ENABLE input high. Similar 8-bit devices are available as the
A6275EA and A6275ELW.
Three package styles are provided: through-hole DIP (suffix A),
surface-mount SOIC (suffix LW) and TSSOP with exposed thermal pad
(suffix LP). Under normal applications, a copper lead frame and low
logic-power dissipation allow the dual in-line package to sink maxi-
mum rated current through all outputs con tin u ous ly over the operating
temperature range (90 mA, 0.75 V drop, +85°C).
Note that three packages offered are electrically
identical and share a common terminal number as-
signment.
ABSOLUTE MAXI MUM RATINGS
Supply Voltage, VDD ....................... 7.0 V
Output Voltage Range,
VO ............................. -0.5 V to +17 V
Output Current, IO ........................ 90 mA
Ground Current, IGND .............. 1475 mA
Input Voltage Range,
VI .................... -0.4 V to VDD + 0.4 V
Package Power Dissipation,
PD ..................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +85°C
Storage Temperature Range,
TS ........................... -55°C to +150°C
Caution: These CMOS devices have input static
protection (Class 2) but are still sus cep ti ble
to damage if exposed to extremely high static
electrical charges.
FEATURES
■To 90 mA Constant-Current Outputs
■Under-Voltage Lockout
■Low-Power CMOS Logic and Latches
■High Data Input Rate
■Functional Replacement for TB62706BN/BF
A6276ELW
GROUND
REGISTER
LATCHES
1
2
3
18
19
20
21
23
4
5
6
7
22
24
SERIAL
DATA OUT
LOGIC
SUPPLY
SERIAL
DATA IN
OUTPUT
ENABLE
LATCH
ENABLE
CLOCK CK
V
DD
OE
OUT
1
OUT
2
OUT
0
OUT
12
OUT
14
OUT
13
OUT
3
OUT
15
R
EXT
I
REGULATOR
L
O
12
9
10
11
OUT
5
OUT
6
OUT
4
OUT
7
13
14
15
16
817
Dwg. PP-029-11
OUT
8
OUT
10
OUT
9
OUT
11
Selection Guide
Part Number Pb-free* Package Packing Ambient
Temperature (°C)
A6276EA-T Yes 24-pin DIP 15 per tube –40 to 85
A6276ELP-T Yes 24-pin TSSOP 62 per tube –40 to 85
A6276ELPTR-T Yes 24-pin TSSOP 4000 per reel –40 to 85
A6276ELW-T Yes 24-pin SOICW 31 per tube –40 to 85
A6276ELWTR-T Yes 24-pin SOICW 1000 per reel –40 to 85
A6276SLW-T Yes 24-pin SOICW 31 per tube –20 to 85
A6276SLWTR-T Yes 24-pin SOICW 1000 per reel –20 to 85
*Pb-based variants are being phased out of the product line. The variants cited in this
footnote are in production but have been determined to be NOT FOR NEW DESIGN.
This classification indicates that sale of this device is currently restricted to existing
customer applications. The variants should not be purchased for new design applica-
tions because obsolescence in the near future is probable. Samples are no longer
available. Status change: May 1, 2006. These variants include:A6276EA, A6276ELW,
A6276EL WTR, A6276SA, A6276SLW , and A6276SLWTR.
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIV ER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
2
Copyright © 2000, 2003 Allegro MicroSystems, Inc.
FUNCTIONAL BLOCK DI A GRAM
2.5
0.5
2.0
3.5
3.0
4.0
1.5
1.0
050 75 100 125 150
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °°
°°C
25
24-PIN DIP, R
θJA
=50°C/W
24-PIN TSSOP*, R
θJA
=32°C/W
24-LEAD SOIC, R
θJA
= 85°C/W
*Mounted on single-layer, two-sided PCB, with 3.8 in
2
copper each side;
additional information on Allegro Web site
MOS
BIPOLAR
GROUND
LATCH
ENABLE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
CLOCK
SERIAL
DATA IN SERIAL-PARALLEL SHIFT REGISTER
LATCHES
VDD LOGIC
SUPPLY
R
EXT
OUT0OUT1
Dwg. FP-013-3
OUT2
OUTN
I
REGULATOR
O
UVLO
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
3
CLOCK and SERIAL DATA IN SERIAL DATA OUT
LATCH ENABLEOUTPUT ENABLE (active low)
Dwg. EP-010-11
IN
VDD
Dwg. EP-010-12
IN
VDD
Dw
g
. EP-010-13
IN
VDD
TRUTH TABLE
Serial Shift Register Contents Serial Latch Latch Contents Output Output Contents
Data Clock Data Enable Enable
Input Input I1I2I3... IN-1 INOutput Input I1I2I3... IN-1 INInput I1I2I3... IN-1 IN
HHR
1R2... RN-2 RN-1 RN-1
LLR
1R2... RN-2 RN-1 RN-1
XR
1R2R3... RN-1 RNRN
XXX...X X X L R
1R2R3... RN-1 RN
P1P2P3... PN-1 PNPNHP
1P2P3... PN-1 PNLP
1P2P3... PN-1 PN
XXX...X X H H H H ... H H
L = Low Logic (Voltage) Level H = High Logic (Voltage) Level X = Irrelevant P = Present State R = Previous State
V
DD
Dw
g
. EP-063-6
OUT
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
4
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V (unless otherwise noted).
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Supply Voltage Range VDD Operating 4.5 5.0 5.5 V
Under-Voltage Lockout VDD(UV) VDD = 0 → 5 V 3.4 – 4.0 V
Output Current IOVCE = 0.7 V, REXT = 250 Ω64.2 75.5 86.8 mA
(any single output) VCE = 0.7 V, REXT = 470 Ω34.1 40.0 45.9 mA
Output Current Matching ∆IO0.4 V ≤ VCE(A) = VCE(B) ≤ 0.7 V:
(difference between any REXT = 250 Ω–±1.5 ±6.0 %
two outputs at same VCE)REXT = 470 Ω–±1.5 ±6.0 %
Output Leakage Current ICEX VOH = 15 V – 1.0 5.0 µA
Logic Input Voltage VIH 0.7VDD –V
DD V
VIL GND – 0.3VDD V
SERIAL DATA OUT VOL IOL = 500 µA – – 0.4 V
Voltage VOH IOH = -500 µA 4.6 – – V
Input Resistance RIENABLE Input, Pull Up 150 300 600 kΩ
LATCH Input, Pull Down 100 200 400 kΩ
Supply Current IDD(OFF) REXT = open, VOE = 5 V – 0.8 1.4 mA
REXT = 470 Ω, VOE = 5 V 3.5 6.0 8.0 mA
REXT = 250 Ω, VOE = 5 V 6.5 11 15 mA
IDD(ON) REXT = 470 Ω, VOE = 0 V 7.0 13 20 mA
REXT = 250 Ω, VOE = 0 V 10 22 32 mA
Typical Data is at VDD = 5 V and is for design information only.
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
5
SWITCHING CHARACTERISTICS at TA = 25°C, VDD = VIH = 5 V, VCE = 0.4 V, VIL = 0 V,
REXT = 470 Ω, IO = 40 mA, VL = 3 V, RL = 65 Ω, CL = 10.5 pF.
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Unit
Propagation Delay Time tpHL CLOCK-OUTn– 350 1000 ns
LATCH-OUTn– 350 1000 ns
ENABLE-OUTn– 350 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Propagation Delay Time tpLH CLOCK-OUTn– 300 1000 ns
LATCH-OUTn– 300 1000 ns
ENABLE-OUTn– 300 1000 ns
CLOCK-SERIAL DATA OUT – 40 – ns
Output Fall Time tf90% to 10% voltage 150 350 1000 ns
Output Rise Time tr10% to 90% voltage 150 300 600 ns
RECOMMENDED OPERATING CONDITIONS
Characteristic Symbol Conditions Min. Typ. Max. Unit
Supply Voltage VDD 4.5 5.0 5.5 V
Output Voltage VO– 1.0 4.0 V
Output Current IOContinuous, any one output – – 90 mA
IOH SERIAL DATA OUT – – -1.0 mA
IOL SERIAL DATA OUT – – 1.0 mA
Logic Input Voltage VIH 0.7VDD –V
DD + 0.3 V
VIL -0.3 – 0.3VDD V
Clock Frequency fCK Cascade operation – – 10 MHz
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIV ER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
Serial data present at the input is transferred to the shift
register on the logic 0-to-logic 1 transition of the CLOCK input
pulse. On succeeding CLOCK pulses, the registers shift data in-
formation towards the SERIAL DATA OUTPUT. The serial data
must appear at the input prior to the rising edge of the CLOCK
input waveform.
Information present at any register is transferred to the
respective latch when the LATCH ENABLE is high (serial-to-
par al lel con ver sion). The latches continue to accept new data as
long as the LATCH ENABLE is held high. Ap pli ca tions where
the latches are bypassed (LATCH ENABLE tied high) will
require that the OUTPUT EN ABLE input be high during serial
data entry.
When the OUTPUT ENABLE input is high, the output sink
driv ers are disabled (OFF). The in for ma tion stored in the latches
is not affected by the OUTPUT ENABLE input. With the OUT-
PUT ENABLE input low, the outputs are con trolled by the state
of their re spec tive latches.
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ............................. 50 ns
B. Data Active T ime After Clock Pulse
(Data Hold Time), th(D) ................................. 20 ns
C. Clock Pulse Width, tw(CK) .................................. 50 ns
D. Time Between Clock Ac ti va tion
and Latch Enable, tsu(L) ............................... 100 ns
E. Latch Enable Pulse Width, tw(L) ...................... 100 ns
F. Output Enable Pulse Width, tw(OE) ................... 4.5 μs
NOTE: Timing is representative of a 10 MHz clock. Sig-
nif i cant ly higher speeds are attainable.
Max. Clock Transition Time, tr or tf ....................... 10 μs
CLOCK
SERIAL
DATA IN
LATCH
ENABLE
OUTPUT
ENABLE
OUTN
Dwg. WP-029-1
50%
SERIAL
DATA OUT
DATA
DATA
50%
50%
50%
C
A B
D E
LOW = ALL OUTPUTS ENABLED
p
t
DATA
50%
p
t
LOW = OUTPUT ON
HIGH = OUTPUT OFF
OUTPUT
ENABLE
OUT
N
Dwg. WP-030-1A
DATA
10%
50%
pHL
t
pLH
t
HIGH = ALL OUTPUTS DISABLED (BLANKED)
f
t
r
t
90%
F
50%
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
7
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE
A6276EA A6276ELW
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-11
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
V
CE
= 4 V
80
T
A
= +25°C
V
DD
= 5 V
R
θ
JA
= 50°C/W
0 20
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-10
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
T
A
= +50°C
V
DD
= 5 V
Rθ
JA
= 50°C/W
V
CE
= 3 V
V
CE
= 4 V
80
020
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-6
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
VCE = 1 V
VCE = 2 V
VCE = 3 V
80
VCE = 4 V
TA = +25°C
VDD = 5 V
RθJA = 75°C/W
VCE = 0.7 V
0 20
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-7
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
T
A
= +50°C
V
DD
= 5 V
R
θ
JA
= 75°C/W
V
CE
= 0.7 V
V
CE
= 4 V
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
8
0 20
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-9
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
T
A
= +85°C
V
DD
= 5 V
R
θJA
= 50°C/W
V
CE
= 3 V
V
CE
= 0.7 V
V
CE
= 4 V
80
ALLOWABLE OUTPUT CURRENT AS A FUNCTION OF DUTY CYCLE (cont.)
A6276EA A6276ELW
TYPICAL CHARACTERISTICS
0.5
Dwg. GP-063
1.0 2.0
1.5
VCE IN VOLTS
0
60
40
OUTPUT CURRENT IN mA/BIT
20
0
TA = +25°C
REXT = 500 Ω
0 20
DUTY CYCLE IN PER CENT
100
0
Dwg. GP-062-8
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
= 1 V
V
CE
= 2 V
V
CE
= 3 V
80
T
A
= +85°C
V
DD
= 5 V
R
θ
JA
= 75°C/W
V
CE
= 4 V
V
CE
= 0.7 V
V
CE
= 0.4 V
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIV ER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
9
ALLOWABLE OUTPUT CURRENT AS A FUNC TION OF DUTY CYCLE (cont.)
A6276ELP
020
DUTY CYCLE IN PER CENT
100
0
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
=1V
V
CE
=2V
V
CE
=3V
V
CE
=4V
80
T
A
=+25ı°C
V
DD
=5V
R
ˇ
θJA
=40ı°C/W
0 20
DUTY CYCLE IN PER CENT
100
0
ALLOWABLE OUTPUT CURRENT IN mA/BIT
6040
20
40
60
10080
V
CE
=1V
V
CE
=2V
T
A
= +50ı°C
V
DD
=5V
R
ˇ
θJA
= 40ı°C/W
V
CE
=3V
V
CE
=4V
80
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
10
TERMINAL DESCRIPTION
Terminal No. Terminal Name Function
1 GND Reference terminal for control logic.
2 SERIAL DATA IN Serial-data input to the shift-register.
3 CLOCK Clock input terminal for data shift on rising edge.
4 LATCH ENABLE Data strobe input terminal; serial data is latched with high-level input.
5-20 OUT0-15 The 16 current-sinking output terminals.
21 OUTPUT ENABLE When (active) low, the output drivers are enabled; when high, all output
drivers are turned OFF (blanked).
22 SERIAL DATA OUT CMOS serial-data output to the following shift-register.
23 REXT An external resistor at this terminal establishes the output current for all sink
drivers.
24 SUPPLY (VDD) The logic supply voltage (typically 5 V).
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIV ER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
11
The load current per bit (IO) is set by the external re sis tor
(REXT) as shown in the figure below.
Package Power Dissipation (PD). The maximum al-
low able package power dissipation is determined as
PD(max) = (150 - TA)/RθJA.
The actual package power dissipation is
PD(act) = DC • (VCE • IO • 16) + (VDD • IDD) ,
where DC is the duty cycle.
When the load supply voltage is greater than 3 V to 5 V,
considering the package power dissipating limits of these
devices, or if PD(act) > PD(max), an external voltage re-
ducer (VDROP) should be used.
Load Supply Voltage (VLED). These devices are de-
signed to operate with driver voltage drops (VCE) of
0.4 V to 0.7 V with LED forward voltages (VF) of 1.2 V to
4.0 V. If higher voltages are dropped across the driver,
package power dissipation will be increased significantly.
To minimize package power dissipation, it is rec om -
mend ed to use the lowest possible load supply voltage or
to set any series dropping voltage (VDROP) as
VDROP = VLED - VF - VCE
with VDROP = Io • RDROP for a single driver, or a Zener
diode (VZ), or a series string of diodes (approximately
0.7 V per diode) for a group of drivers. If the available
voltage source will cause unacceptable dissipation and
series resistors or diode(s) are undesirable, a regulator
such as the Sanken Series SAI or Series SI can be used to
pro vide supply voltages as low as 3.3 V.
For reference, typical LED forward voltages are:
White 3.5 – 4.0 V
Blue 3.0 – 4.0 V
Green 1.8 – 2.2 V
Yellow 2.0 – 2.1 V
Amber 1.9 – 2.65 V
Red 1.6 – 2.25 V
Infrared 1.2 – 1.5 V
Pattern Layout. This device has a common logic-
ground and power-ground terminal. If ground pattern lay-
out con tains large common-mode resistance, and the volt-
age between the system ground and the LATCH ENABLE
or CLOCK terminals ex ceeds 2.5 V (because of switching
noise), these devices may not operate correctly.
Applications Information
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
www.allegromicro.com
12
A6276EA
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 15 devices.
0.014
0.008
0.300
BSC
Dwg. MA-001-24 in
0.430
MAX
24
112
0.280
0.240
0.210
MAX
0.070
0.045
0.015
MIN
0.022
0.014
0.100
BSC
0.005
MIN
0.150
0.115
13
1.280
1.230
0.355
0.204
7.62
BSC
Dwg. MA-001-24 mm
10.92
MAX
24
112
7.11
6.10
5.33
MAX
1.77
1.15
0.39
MIN
0.558
0.356
2.54
BSC
0.13
MIN
3.81
2.93
13
32.51
31.24
67
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
13
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 31 devices or add “TR” to part number for tape and reel.
0°
TO
8°
1 2 3
0.020
0.013
0.0040
MIN.
0.0125
0.0091
0.050
0.016
Dwg. MA-008-24A in
0.050
BSC
24 13
0.2992
0.2914 0.419
0.394
0.6141
0.5985
0.0926
0.1043
0° TO 8°
1
24
23
0.51
0.33
0.10 MIN.
0.32
0.23
1.27
0.40
Dwg. MA-008-24A mm
1.27
BSC
13
7.60
7.40 10.65
10.00
15.60
15.20
2.65
2.35
A6276ELW
Dimensions in Inches
(for reference only)
Dimensions in Millimeters
(controlling dimensions)
6276
16-BIT SERIAL-INPUT,
CONSTANT-CURRENT
LATCHED LED DRIV ER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
14
A6276ELP
1.20
MAX
.047
0.15
0.00
.006
.000
0.30
0.19
.012
.007
4.5
4.3
.177
.169
6.6
6.2
.260
.244
0.20
0.09
.008
.004
8º
0º
0.75
0.45
.030
.018
1
REF
.039
7.9
7.7
.311
.303
C
SEATING
PLANE
A
B
24X
0.10 [.004] M C A B
C0.10 [.004]
24X
0.65 .026
0.25 .010
5.8
NOM
.228
0.45
NOM
.018
0.65
NOM
.026
2
NOM
.079
4.32
NOM
.170
0.40
REF
.016 3
NOM
.118
4.32
NOM
.170
3
NOM
.118
21
24
GAUGE PLANE
SEATING PLANE
B
A
ATerminal #1 mark area
BExposed thermal pad (bottom surface) U.S. Customary dimensions controlling
Preliminary dimensions, for reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference IPC7351
TSOP65P640-24M); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
24
21
C
