TSL2572 Light-to-Digital Converter General Description The TSL2572 device family provides ambient light sensing (ALS) that approximates human eye response to light intensity under a variety of lighting conditions and through a variety of attenuation materials. Accurate ALS measurements are the result of ams' patented dual-diode technology and the UV rejection filter incorporated in the package. In addition, the operating range is extended to 60,000 lux in sunlight when the low-gain mode is used. While useful for general purpose light sensing, the TSL2572 device is particularly useful for display management to provide optimum viewing in diverse lighting conditions while extending battery life. The TSL2572 device family is ideally suited for use in mobile handsets, TVs, tablets, monitors, and portable media players where the display backlight may account for 50% to 70% of the system power consumption. Ordering Information and Content Guide appear at end of datasheet. Key Benefits & Features The benefits and features of TSL2572, Light-to-Digital Converter are listed below: Figure 1: Added Value Of Using TSL2572 Benefits Features * Enables Operation in IR Light Environments * Patented Dual-Diode Architecture * Enables Dark Room to 60K Lux Sunlight Operation * 8M:1 Dynamic Range * Reduces Micro-Processor Interrupt Overhead * Programmable Interrupt Function * Improves Lux Accuracy Across Various Light Sources * UV-Rejection Package * Reduces Board Space Requirements While Simplifying Designs * Area Efficient 2mm x 2mm Dual Flat No-Lead (FN) Package * Ambient Light Sensing (ALS) * Approximates Human Eye Response * Programmable Analog Gain and Integration Time * 45,000,000:1 Dynamic Range * Operation to 60,000 lux in Sunlight * Very High Sensitivity -- Ideally Suited for Operation Behind Dark Glass * Package UV Rejection Filter ams Datasheet [v1-01] 2018-Mar-27 Page 1 Document Feedback TSL2572 - General Description * Maskable Interrupt * Programmable Upper and Lower Thresholds with Persistence Filter * Wait Timer and Power Management * Low Power 2.2 mA Sleep State with User- Selectable Sleep-After-Interrupt Mode * 90 mA Wait State with Programmable Wait Time from 2.7 ms to > 8 seconds * IC Fast Mode Compatible Interface * Data Rates up to 400 kbit/s * Input Voltage Levels Compatible with VDD or 1.8-V Bus * Register Set- and Pin-Compatible with the TSL2x71 Series Applications TSL2572, Light-to-Digital Converter is ideal for: * Display Backlight Control * Keyboard Illumination Control * Solid State Lighting Control for Daylight Harvesting * Printer Paper Detection End Products and Market Segments * Mobile Handsets, Tablets, Laptops, Monitors and TVs, Portable Media Players * Medical and Industrial Instrumentation * White Goods * Toys * Industrial/Commercial Lighting * Digital Signage * Printers Page 2 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - General Description Block Diagram The functional blocks of this device are shown below: Figure 2: TSL2572 Block Diagram Interrupt INT Wait Control CH0 Data ALS Control CH0 CH1 ADC CH1 Data Lower Limit I2C Interface Upper Limit CH0 ADC VDD SCL SDA GND CH1 ams Datasheet [v1-01] 2018-Mar-27 Page 3 Document Feedback TSL2572 - Pin Assignments Pin Assignments Figure 3: Package FN Dual Flat No-Lead (Top View) VDD 1 6 SDA SCL 2 5 INT GND 3 4 NC Not Actual Size Figure 4: Terminal Functions Terminal Type Description Name No VDD 1 SCL 2 GND 3 Power supply ground. All voltages are referenced to GND NC 4 Do not connect INT 5 O Interrupt -- open drain (active low) SDA 6 I/O IC serial data I/O terminal -- serial data I/O for IC Page 4 Document Feedback Supply voltage I IC serial clock input terminal -- clock signal for IC serial data ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Detailed Description Detailed Description The TSL2572 light-to-digital device provides on-chip photodiodes, integrating amplifiers, ADCs, accumulators, clocks, buffers, comparators, a state machine, and an IC interface. Each device combines a Channel 0 photodiode (CH0), which is responsive to both visible and infrared light, and a channel 1 photodiode (CH1), which is responsive primarily to infrared light. Two integrating ADCs simultaneously convert the amplified photodiode currents into a digital value providing up to 16 bits of resolution. Upon completion of the conversion cycle, the conversion result is transferred to the data registers. This digital output can be read by a microprocessor through which the illuminance (ambient light level) in lux is derived using an empirical formula to approximate the human eye response. Communication to the device is accomplished through a fast (up to 400 kHz), two-wire IC serial bus for easy connection to a microcontroller or embedded controller. The digital output of the device is inherently more immune to noise when compared to an analog interface. The device provides a separate pin for level-style interrupts. When interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. An interrupt is generated when the value of an ALS conversion exceeds either an upper or lower threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt. ams Datasheet [v1-01] 2018-Mar-27 Page 5 Document Feedback TSL2572 - Absolute Maximum Ratings Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Figure 5: Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted) Symbol VDD(1) Tstrg ESDHBM Parameter Min Supply voltage Max Units 3.8 V Input terminal voltage -0.5 3.8 V Output terminal voltage -0.5 3.8 V Output terminal current -1 +20 mA Storage temperature range -40 85 C ESD tolerance, human body model 2000 V Note(s): 1. All voltages are with respect to GND. Page 6 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Electrical Characteristics Electrical Characteristics Figure 6: Recommended Operating Conditions Symbol Parameter VDD Supply voltage TA Conditions Min Nom Max Units TSL25721, IC Vbus = VDD 2.4 3 3.6 V TSL25723 , IC Vbus = 1.8V 2.7 3 3.6 V 70 C Typ Max Unit Active 200 250 Wait mode 90 Sleep mode -- no IC activity 2.2 Operating free-air temperature -30 Figure 7: Operating Characteristics; VDD = 3 V, TA = 25C (unless otherwise noted) Symbol Parameter IDD VOL Supply current Min A 4 3 mA sink current 0 0.4 6 mA sink current 0 0.6 -5 5 INT, SDA output low voltage ILEAK Leakage current, SDA, SCL, INT pins VIH SCL, SDA input high voltage VIL Test Conditions V TSL25721 0.7 VDD TSL25723 1.25 V TSL25721 0.3 VDD TSL25723 0.54 SCL, SDA input low voltage ams Datasheet [v1-01] 2018-Mar-27 A V Page 7 Document Feedback TSL2572 - Electrical Characteristics Figure 8: ALS Characteristics; VDD = 3 V, TA = 25C, AGAIN = 16x; AEN = 1 (unless otherwise noted) (1) (2) (3) Parameter Dark ADC count value ADC integration time step size Test Conditions Ee = 0, AGAIN = 120x ATIME = 0xDB (100 ms) Channel Min Typ Max Unit CH0 0 1 5 CH1 0 1 5 2.58 2.73 2.9 ms 1 256 steps counts ATIME = 0xFF ADC Number of integration steps (4) ADC counts per step (4) ATIME = 0xFF 0 1024 counts ADC count value (4) ATIME = 0xC0 0 65535 counts White light, Ee = 263.9 CH0 4000 5000 6000 2 ADC count value ADC count value ratio: CH1/CH0 Re Irradiance responsivity Gain scaling, relative to 1x gain setting W/cm ATIME = 0xF6 (27 ms) (2) CH1 p = 850 nm, Ee = 263.4 CH0 W/cm2 ATIME = 0xF6 (27 ms) (3) CH1 680 counts 4000 5000 6000 2850 White light, ATIME 0xF6 (27 ms) (2) 0.086 0.136 0.186 p = 850 nm ATIME 0xF6 (27 ms) (3) 0.456 0.570 0.684 White light, ATIME = 0xF6 (27 ms) (2) CH0 18.9 CH1 2.58 p = 850 nm, ATIME = 0xF6 CH0 19.0 (27 ms) (3) CH1 10.8 counts/ (W/ cm2) AGAIN = 1x and AGL = 1 0.128 0.16 0.192 AGAIN = 8x and AGL = 0 7.2 8.0 8.8 AGAIN 16x and AGL = 0 14.4 16.0 17.6 AGAIN = 120x and AGL = 0 108 120 132 x Note(s): 1. Optical measurements are made using small-angle incident radiation from light-emitting diode optical sources. Visible white LEDs and infrared 850 nm LEDs are used for final product testing for compatibility with high-volume production. 2. The white LED irradiance is supplied by a white light-emitting diode with a nominal color temperature of 4000 K. 3. The 850 nm irradiance Ee is supplied by a GaAs light-emitting diode with the following typical characteristics: peak wavelength p = 850 nm and spectral halfwidth 1/2 = 42 nm. 4. Parameter ensured by design and is not tested. Page 8 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Electrical Characteristics Figure 9: Wait Characteristics; VDD = 3 V, TA = 25C, WEN = 1 (unless otherwise noted) Test Conditions Parameter Wait step size Channel WTIME = 0xFF Wait number of integration steps (1) Min Typ Max Unit 2.58 2.73 2.9 ms 256 steps Max Unit 400 kHz 1 Note(s): 1. Parameter ensured by design and is not tested. Figure 10: AC Electrical Characteristics; VDD = 3 V, TA = 25C, (unless otherwise noted) Parameter(1) Symbol Test Conditions Min Typ f(SCL) Clock frequency (IC only) t(BUF) Bus free time between start and stop condition 1.3 s t(HDSTA) Hold time after (repeated) start condition. After this period, the first clock is generated. 0.6 s t(SUSTA) Repeated start condition setup time 0.6 s t(SUSTO) Stop condition setup time 0.6 s t(HDDAT) Data hold time 0 s t(SUDAT) Data setup time 100 ns t(LOW) SCL clock low period 1.3 s t(HIGH) SCL clock high period 0.6 s tF Clock/data fall time 300 ns tR Clock/data rise time 300 ns Ci Input pin capacitance 10 pF 0 Note(s): 1. Specified by design and characterization; not production tested. ams Datasheet [v1-01] 2018-Mar-27 Page 9 Document Feedback TSL2572 - Parameter Measurement Information Parameter Measurement Information Figure 11: Timing Diagrams t(LOW) t(R) t(F) VIH SCL VIL t(HDSTA) t(BUF) t(HDDAT) t(HIGH) t(SUSTA) t(SUSTO) t(SUDAT) VIH SDA VIL P Stop Condition Page 10 Document Feedback S S P Start Condition ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Typical Characteristics Typical Characteristics Figure 12: Spectral Responsivity 1 Ch 0 Normalized Responsivity 0.8 0.6 0.4 Ch 1 0.2 0 300 400 500 600 700 800 900 1000 1100 - Wavelength - nm Figure 13: Normalized Responsivity vs. Angular Displacement 1.0 Both Axes Optical Axis Normalized Responsivity 0.8 0.6 0.4 0.2 0 -90 ams Datasheet [v1-01] 2018-Mar-27 -Q +Q -60 -30 0 30 60 Q - Angular Displacement - 90 Page 11 Document Feedback TSL2572 - Typical Characteristics Figure 14: Normalized IDD vs.VDD and Temperature DD IDD -- Active Current Normalized @ 3 V, 25C 110% a d U 108% 106% 104% 0C 102% 100% 50C 25C 75C 98% 96% 94% 92% 2.7 2.8 2.9 3 3.1 3.2 3.3 VDD -- V Figure 15: Response to White LED vs.Temperature Response -- Normalized to 25 C 115% 110% 105% Ch 0 100% 95% Ch 1 90% 0 Page 12 Document Feedback 10 20 30 40 50 Temperature - C 60 70 ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Principles Of Operation Principles Of Operation System State Machine An internal state machine provides system control of the ALS and wait timer features of the device. At power up, an internal power-on-reset initializes the device and puts it in a low-power Sleep state. When a start condition is detected on the IC bus, the device transitions to the Idle state where it checks the Enable register (0x00) PON bit. If PON is disabled, the device will return to the Sleep state to save power. Otherwise, the device will remain in the Idle state until the ALS function is enabled. Once enabled, the device will execute the Wait and ALS states in sequence as indicated in Figure 16. Upon completion and return to Idle, the device will automatically begin a new Wait-ALS cycle as long as PON and AEN remain enabled. If the ALS function generates an interrupt and the Sleep-After-Interrupt (SAI) feature is enabled, the device will transition to the Sleep state and remain in a low-power mode until an IC command is received. See the Interrupts section for additional information. Figure 16: Simplified State Diagram Sleep I2C Start !PON Idle WEN & AEN Wait ams Datasheet [v1-01] 2018-Mar-27 !WEN & AEN INT & SAI ALS Page 13 Document Feedback TSL2572 - Principles Of Operation Photodiodes Conventional ALS detectors respond strongly to infrared light, which the human eye does not see. This can lead to significant error when the infrared content of the ambient light is high (such as with incandescent lighting). This problem is overcome through the use of two photodiodes. The Channel 0 photodiode, referred to as the CH0 channel, is sensitive to both visible and infrared light, while the Channel 1 photodiode, referred to as CH1, is sensitive primarily to infrared light. Two integrating ADCs convert the photodiode currents to digital outputs.The ADC digital outputs from the two channels are used in a formula to obtain a value that approximates the human eye response in units of lux. ALS Operation The ALS engine contains ALS gain control (AGAIN) and two integrating analog-to-digital converters (ADC), one for the CH0 and one for the CH1 photodiodes. The ALS integration time (ATIME) impacts both the resolution and the sensitivity of the ALS reading. Integration of both channels occurs simultaneously and upon completion of the conversion cycle, the results are transferred to the data registers (C0DATA and C1DATA). This data is also referred to as channel count. The transfers are double-buffered to ensure data integrity. Figure 17: ALS Operation ATIME(r 1) 2.73 ms to 699 ms CH0 ALS CH0 Data ALS Control C0DATAH(r0x15), C0DATA(r0x14) AGL(r0x0D, b2) CH0 CH1 ADC CH1 Data C1DATAH(r0x17), C1DATA(r0x16) CH1 AGAIN(r0x0F, b1:0) 1, 8, 16, 120 Gain Page 14 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Principles Of Operation The registers for programming the integration and wait times are a 2's compliment values. The actual time can be calculated as follows: ATIME = 256 - Integration Time / 2.73 ms Inversely, the time can be calculated from the register value as follows: Integration Time = 2.73 ms x (256 - ATIME) In order to reject the 50/60-Hz ripple present in fluorescent lighting, the integration time needs to be programmed in multiples of 10 / 8.3 ms or the half cycle time. Both frequencies can be rejected with a programmed value of 50 ms (ATIME = 0xED) or multiples of 50 ms (i.e. 100, 150, 200, 400, 600). AGAIN can be programmed to 1x, 8x, 16x, or 120x with the 2-bit AGAIN field in the Control register (0x0F). The gain, in terms of amount of gain, will be represented by the value AGAINx, i.e. AGAINx = 1, 8, 16, or 120. With the AGL bit set, the 1x and 8x gains are lowered to 1/6x and 8/6x, respectively, to allow for operation up to 60k lux. Do not enable AGL when AGAIN is 16x or 120x. Lux Equation The lux calculation is a function of CH0 channel count (C0DATA), CH1 channel count (C1DATA), ALS gain (AGAINx), and ALS integration time in milliseconds (ATIME_ms). If an aperture, glass/plastic, or a light pipe attenuates the light equally across the spectrum (300 nm to 1100 nm), then a scaling factor referred to as glass attenuation (GA) can be used to compensate for attenuation. For a device in open air with no aperture or glass/plastic above the device, GA = 1. If it is not spectrally flat, then a custom lux equation with new coefficients should be generated. (See ams application note). Counts per Lux (CPL) needs to be calculated only when ATIME or AGAIN is changed, otherwise it remains a constant. The first segment of the equation (Lux1) covers fluorescent and incandescent light. The second segment (Lux2) covers dimmed incandescent light. The final lux is the maximum of Lux1, Lux2, or 0. CPL = (ATIME_ms x AGAINx) / (GA x 60) Lux1 = (1 x C0DATA - 1.87 x C1DATA) / CPL Lux2 = (0.63 x C0DATA - 1 x C1DATA) / CPL Lux = MAX(Lux1, Lux2, 0) ams Datasheet [v1-01] 2018-Mar-27 Page 15 Document Feedback TSL2572 - Principles Of Operation Interrupts The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defined range. While the interrupt function is always enabled and it's status is available in the status register (0x13), the output of the interrupt state can be enabled using the ALS interrupt enable (AIEN) fields in the enable register (0x00). Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level. An interrupt can be generated when the ALS CH0 data (C0DATA) falls outside of the desired light level range, as determined by the values in the ALS interrupt low threshold registers (AILTx) and ALS interrupt high threshold registers (AIHTx). It is important to note that the thresholds are evaluated in sequence, first the low threshold, then the high threshold. As a result, if the low threshold is set above the high threshold, the high threshold is ignored and only the low threshold is evaluated. To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows the user to specify the number of consecutive out-of-range ALS occurrences before an interrupt is generated. The persistence filter register (0x0C) allows the user to set the ALS persistence filter (APERS) value. See the persistence filter register for details on the persistence filter values. Once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see Command Register). Figure 18: Programmable Interrupt AIHTH(r07), AIHTL(r06) Upper Limit CH0 ADC APERS(r0x0C, b3:0) ALS Persistence CH0 Data Lower Limit CH0 AILTH(r05), AILTL(r04) Page 16 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Principles Of Operation System State Machine Timing The system state machine shown in Figure 16 provides an overview of the states and state transitions that provide system control of the device. This section highlights the programmable features, which affect the state machine cycle time, and provides details to determine system level timing. When the power management feature is enabled (WEN), the state machine will transition in turn to the Wait state. The wait time is determined by WLONG, which extends normal operation by 12x when asserted, and WTIME. The formula to determine the wait time is given in the box associated with the Wait state in Figure 19. When the ALS feature is enabled (AEN), the state machine will transition through the ALS Init and ALS ADC states. The ALS Init state takes 2.73 ms, while the ALS ADC time is dependent on the integration time (ATIME). The formula to determine ALS ADC time is given in the associated box in Figure 19. If an interrupt is generated as a result of the ALS cycle, it will be asserted at the end of the ALS ADC state and transition to the Sleep state if SAI is enabled. Figure 19: Detailed State Diagram Sleep I2C Start !PON WEN & AEN Idle INT & SAI !WEN & AEN ALS ADC Wait ATIME: 1 ~ 256 steps Time: 2.73 ms/step Range: 2.73 ms ~ 699 ms ALS Init Time: Range: WTIME: 1 ~ 256 steps WLONG = 0 WLONG = 1 2.73 ms/step 32.8 ms/step 2.73 ms ~ 699 ms 32.8 ms ~ 8.39s Time: 2.73 ms Note(s): 1. PON, WEN, AEN, and SAI are fields in the Enable register (0x00). ams Datasheet [v1-01] 2018-Mar-27 Page 17 Document Feedback TSL2572 - Principles Of Operation IC Protocol Interface and control are accomplished through an IC serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data. The devices support the 7-bit IC addressing protocol. The IC standard provides for three types of bus transaction: read, write, and a combined protocol (see Figure 20). During a write operation, the first byte written is a command byte followed by data. In a combined protocol, the first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the register address from the previous command will be used for data access. Likewise, if the MSB of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. The command byte contains either control information or a 5-bit register address. The control commands can also be used to clear interrupts. The IC bus protocol was developed by Philips (now NXP). For a complete description of the IC protocol, please review the NXP IC design specification at http://www.i2c-bus.org/references/. Figure 20: IC Protocols 1 7 S Slave Address 1 1 8 1 8 1 1 W A Command Code A Data Byte A P I2C Write Protocol 1 7 S Slave Address 1 1 8 1 8 1 1 R A Data A Data A P I2C Read Protocol 1 S 7 Slave Address 1 1 W A 8 1 1 Command Code A Sr Slave Address 7 1 1 R A 8 1 8 1 1 Data A Data A P I2C Read Protocol - Combined Format A N P R S Page 18 Document Feedback Acknowledge (0) Not Acknowledged (1) Stop Condition Read (1) Start Condition Sr W ... Repeated Start Condition Write (0) Communication of Protocol Master-to-Slave Slave-to-Master ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Register Overview Register Overview Register Set The device is controlled and monitored by data registers and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The register set is summarized in Figure 21. Figure 21: Register Address Address Register Name R/W -- COMMAND W 0x00 ENABLE 0x01 Register Function Reset Value Specifies register address 0x00 R/W Enables states and interrupts 0x00 ATIME R/W ALS time 0xFF 0x03 WTIME R/W Wait time 0xFF 0x04 AILTL R/W ALS interrupt low threshold low byte 0x00 0x05 AILTH R/W ALS interrupt low threshold high byte 0x00 0x06 AIHTL R/W ALS interrupt high threshold low byte 0x00 0x07 AIHTH R/W ALS interrupt high threshold high byte 0x00 0x0C PERS R/W Interrupt persistence filters 0x00 0x0D CONFIG R/W Configuration 0x00 0x0F CONTROL R/W Control register 0x00 0x12 ID R Device ID 0x13 STATUS R Device status 0x00 0x14 C0DATA R CH0 ADC low data register 0x00 0x15 C0DATAH R CH0 ADC high data register 0x00 0x16 C1DATA R CH1 ADC low data register 0x00 0x17 C1DATAH R CH1 ADC high data register 0x00 ID The mechanics of accessing a specific register depends on the specific protocol used. See the section on IC protocols on the previous pages. In general, the COMMAND register is written first to specify the specific control/status register for following read/write operations. ams Datasheet [v1-01] 2018-Mar-27 Page 19 Document Feedback TSL2572 - Register Over view Command Register The command registers specifies the address of the target register for future write and read operations. Figure 22: Command Register 7 COMMAND COMMAND Field Bits COMMAND 7 6 5 TYPE 4 3 2 1 0 Reset 0x00 ADD Description Select Command Register. Must write as 1 when addressing COMMAND register. Selects type of transaction to follow in subsequent data transfers: TYPE FIELD VALUE DESCRIPTION 00 Repeated byte protocol transaction 01 Auto-increment protocol transaction 10 Reserved -- Do not use 11 Special function -- See description below 6:5 Transaction type 00 will repeatedly read the same register with each data access. Transaction type 01 will provide an auto-increment function to read successive register bytes. Address field/special function field. Depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. The field values listed below apply only to special function commands: ADD 4:0 FIELD VALUE DESCRIPTION 00000 Normal -- no action 00110 ALS interrupt clear other Reserved -- do not write The ALS interrupt clear special function clears any pending ALS interrupt and is self clearing. Page 20 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Register Overview Enable Register (0x00) The ENABLE register is used to power the device ON/OFF, enable functions, and interrupts. Figure 23: Enable Register ENABLE 7 6 5 4 3 2 1 0 Reserved SAI Reserved Resv AIEN WEN Reserved AEN PON Reset 0x00 Field Bits Reserved 7 Reserved. Write as 0. SAI 6 Sleep after interrupt. When asserted, the device will power down at the end of an ALS cycle if an interrupt has been generated Reserved 5 Reserved. Write as 0. AIEN 4 ALS interrupt mask. When asserted, permits ALS interrupts to be generated. WEN 3 Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the wait timer. Reserved 2 Reserved. Write as 0. AEN 1 ALS Enable. This bit actives the two channel ADC. Writing a 1 activates the ALS. Writing a 0 disables the ALS. PON 0 Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator. ams Datasheet [v1-01] 2018-Mar-27 Description Page 21 Document Feedback TSL2572 - Register Over view ALS Timing Register (0x01) The ALS timing register controls the internal integration time of the ALS ADCs in 2.73-ms increments. Upon power up, the ALS time register is set to 0xFF. Figure 24: ALS Timing Register Field ATIME Bits 7:0 Description Value INTEG_CYCLES Time Max Count 0xFF 1 2.73 ms 1024 0xF6 10 27.3 ms 10240 0xDB 37 101 ms 37888 0xC0 64 175 ms 65535 0x00 256 699 ms 65535 Wait Time Register (0x03) Wait time is set 2.73 ms increments unless the WLONG bit is asserted in which case the wait times are 12x longer. WTIME is programmed as a 2's complement number. Upon power up, the wait time register is set to 0xFF. Figure 25: Wait Time Register Field WTIME Bits 7:0 Description Register Value Wait Time Time (WLONG = 0) Time (WLONG = 1) 0xFF 1 2.73 ms 0.033 s 0xB6 74 202 ms 2.4 s 0x00 256 699 ms 8.4 s Note(s): 1. The Wait Time Register should be configured before AEN is asserted. Page 22 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Register Overview ALS Interrupt Threshold Registers (0x04 - 0x07) The ALS interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation. If C0DATA crosses below the low threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. Figure 26: ALS Interrupt Threshold Registers Register Address Bits AILTL 0x04 7:0 ALS low threshold lower byte AILTH 0x05 7:0 ALS low threshold upper byte AIHTL 0x06 7:0 ALS high threshold lower byte AIHTH 0x07 7:0 ALS high threshold upper byte ams Datasheet [v1-01] 2018-Mar-27 Description Page 23 Document Feedback TSL2572 - Register Over view Persistence Register (0x0C) The persistence register controls the filter interrupt capabilities of the device. Configurable filtering is provided to allow interrupts to be generated after every ADC cycle or if the ADC cycle has produced a result that is outside of the values specified by threshold register for some specified amount of time. ALS interrupts are generated using C0DATA. Figure 27: Persistence Filter Register 7 PERS 6 5 4 3 Reserved Field Bits Reserved 7:4 2 1 APERS 0 Reset 0x00 Description Reserved. Write as 0. ALS Interrupt persistence filter. Controls rate of ALS interrupt to the host processor APERS Page 24 Document Feedback 3:0 FIELD VALUE MEANING INTERRUPT PERSISTENCE FUNCTION 0000 Every Every ALS cycle generates an interrupt 0001 1 1 value outside of threshold range 0010 2 2 consecutive values out of range 0011 3 3 consecutive values out of range 0100 5 5 consecutive values out of range 0101 10 10 consecutive values out of range 0110 15 15 consecutive values out of range 0111 20 20 consecutive values out of range 1000 25 25 consecutive values out of range 1001 30 30 consecutive values out of range 1010 35 35 consecutive values out of range 1011 40 40 consecutive values out of range 1100 45 45 consecutive values out of range 1101 50 50 consecutive values out of range 1110 55 55 consecutive values out of range 1111 60 60 consecutive values out of range ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Register Overview Configuration Register (0x0D) The configuration register sets the wait long time and ALS gain level. Figure 28: Configuration Register 7 CONFIG 6 5 Reserved 4 3 2 1 0 AGL WLONG Reserved Reset 0x00 Field Bits Reserved 7:3 AGL 2 ALS gain level. When asserted, the 1x and 8x ALS gain (AGAIN) modes are scaled by 0.16. Otherwise, AGAIN is scaled by 1. Do not use with AGAIN greater than 8x. WLONG 1 Wait Long. When asserted, the wait cycles are increased by a factor 12x from that programmed in the WTIME register. Reserved 0 Reserved. Write as 0. ams Datasheet [v1-01] 2018-Mar-27 Description Reserved. Write as 0. Page 25 Document Feedback TSL2572 - Register Over view Control Register (0x0F) The Control register provides ALS gain control to the analog block. Figure 29: Control Register 7 6 CONTROL 5 4 3 2 1 Bits Reserved 7:2 Reset 0x00 AGAIN Reserved Field 0 Description Reserved. Write as 0. ALS Gain. AGAIN FIELD VALUE ALS GAIN VALUE 00 1x gain 01 8x gain 10 16x gain 11 120x gain 1:0 ID Register (0x12) The ID Register provides the value for the part number. The ID register is a read-only register. Figure 30: ID Register 7 6 5 4 ID 3 2 Bits ID 7:0 0 Reset ID ID Field 1 Description 0x34 = TSL25721 Part number identification 0x3D = TSL25723 Page 26 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Register Overview Status Register (0x13) The Status Register provides the internal status of the device. This register is read only. Figure 31: Status Register 7 6 STATUS 5 Reserved Field Bit Reserved 7:5 AINT 4 Reserved 3:1 AVALID 0 4 3 2 AINT 1 Reserved 0 AVALID Reset 0x00 Description Reserved. Bits read as 0. ALS Interrupt. Indicates that the device is asserting an ALS interrupt. Reserved. Bits read as 0. ALS Valid. Indicates that the ALS channels have completed an integration cycle after AEN has been asserted. ADC Channel Data Registers (0x14 - 0x17) ALS data is stored as two 16-bit values. To ensure the data is read correctly, a two-byte read IC transaction should be used with auto increment protocol bits set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored in a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. Figure 32: ADC Channel Data Registers Register Address Bits C0DATA 0x14 7:0 ALS CH0 data low byte C0DATAH 0x15 7:0 ALS CH0 data high byte C1DATA 0x16 7:0 ALS CH1 data low byte C1DATAH 0x17 7:0 ALS CH1 data high byte ams Datasheet [v1-01] 2018-Mar-27 Description Page 27 Document Feedback TSL2572 - Application Information: Hardware Application Information: Hardware Typical Hardware Application A typical hardware application circuit is shown in Figure 33. A 1-F low-ESR decoupling capacitor should be placed as close as possible to the V DD pin. Figure 33: Typical Application Hardware Circuit VDD VBUS VDD RP 1 mF TSL2572 RP RPI INT SCL GND SDA V BUS in Figure 33 refers to the IC bus voltage, which is either V DD or 1.8 V. Be sure to apply the specified IC bus voltage shown in the Available Options table for the specific device being used. The IC signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R P) value is a function of the IC bus speed, the IC bus voltage, and the capacitive load. The ams EVM running at 400 kbps, uses 1.5-k resistors. A 10-k pull-up resistor (RPI) can be used for the interrupt line. Page 28 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Application Information: Hardware PCB Pad Layout Suggested land pattern based on the IPC-7351B Generic Requirements for Surface Mount Design and Land Pattern Standard (2010) for the small outline no-lead (SON) package is shown in Figure 34. Figure 34: Suggested FN Package PCB Layout 2.70 1.20 1.20 0.35 6 0.65 0.65 TOP VIEW Note(s): 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. ams Datasheet [v1-01] 2018-Mar-27 Page 29 Document Feedback TSL2572 - Package Information Package Information Figure 35: Package FN -- Dual Flat No-Lead Packaging Configuration PACKAGE FN Dual Flat No-Lead TOP VIEW 398 10 PIN OUT TOP VIEW PIN 1 355 10 2000 100 2000 100 VDD 1 6 SDA SCL 2 5 INT GND 3 4 NC Photodiode Array Area END VIEW SIDE VIEW 295 Nominal 650 50 203 8 650 BSC BOTTOM VIEW CL of Photodiode Array Area (Note 2) CL of Solder Contacts 300 50 1 Nominal RoHS 144 Nominal CL of Solder Contacts Green CL of Photodiode Array Area (Note 2) PIN 1 Pb 750 150 Lead Free Note(s): 1. All linear dimensions are in micrometers. 2. The die is centered within the package within a tolerance of 75 m. 3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55. 4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish. 5. This package contains no lead (Pb). 6. This drawing is subject to change without notice. Page 30 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Carrier Tape & Reel Information Carrier Tape & Reel Information Figure 36: Package FN Carrier Tape TOP VIEW 2.00 0.05 1.75 4.00 1.50 4.00 B + 0.30 8.00 - 0.10 3.50 0.05 1.00 0.25 A B A DETAIL A DETAIL B 5 Max 5 Max 2.18 0.05 0.254 0.02 Ao 0.83 0.05 Ko 2.18 0.05 Bo Note(s): 1. All linear dimensions are in millimeters. Dimension tolerance is 0.10 mm unless otherwise noted. 2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly. 3. Symbols on drawing Ao, Bo, and Ko are defined in ANSI EIA Standard 481-B 2001. 4. Each reel is 178 millimeters in diameter and contains 3500 parts. 5. ams packaging tape and reel conform to the requirements of EIA Standard 481-B. 6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape. 7. This drawing is subject to change without notice. ams Datasheet [v1-01] 2018-Mar-27 Page 31 Document Feedback TSL2572 - Soldering Information The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate. Soldering Information The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile. Figure 37: Soldier Reflow Profile Parameter Reference Device Average temperature gradient in preheating 2.5C/s tsoak 2 to 3 minutes Time above 217C (T1) t1 Max 60 s Time above 230C (T2) t2 Max 50 s Time above Tpeak -10C (T3) t3 Max 10 s Peak temperature in reflow Tpeak 260C Soak time Temperature gradient in cooling Max -5C/s Figure 38: Solder Reflow Profile Graph Tpeak Not to scale -- for reference only T3 T2 Temperature (C) T1 Time (s) t3 t2 tsoak Page 32 Document Feedback t1 ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Storage Information Storage Information Moisture Sensitivity Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package. To ensure the package contains the smallest amount of absorbed moisture possible, each device is baked prior to being dry packed for shipping. Devices are dry packed in a sealed aluminized envelope called a moisture-barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. Shelf Life The calculated shelf life of the device in an unopened moisture barrier bag is 12 months from the date code on the bag when stored under the following conditions: * Shelf Life: 12 months * Ambient Temperature: < 40C * Relative Humidity: < 90% Rebaking of the devices will be required if the devices exceed the 12 month shelf life or the Humidity Indicator Card shows that the devices were exposed to conditions beyond the allowable moisture region. Floor Life The FN package has been assigned a moisture sensitivity level of MSL 3. As a result, the floor life of devices removed from the moisture barrier bag is 168 hours from the time the bag was opened, provided that the devices are stored under the following conditions: * Floor Life: 168 hours * Ambient Temperature: < 30C * Relative Humidity: < 60% If the floor life or the temperature/humidity conditions have been exceeded, the devices must be rebaked prior to solder reflow or dry packing. Rebaking Instructions When the shelf life or floor life limits have been exceeded, rebake at 50C for 12 hours. ams Datasheet [v1-01] 2018-Mar-27 Page 33 Document Feedback TSL2572 - Ordering & Contact Information Ordering & Contact Information Figure 39: Ordering Information Ordering Code Device Address Package Leads Interface Description TSL25721FN TSL25721 0x39 FN-6 IC Vbus = VDD Interface TSL25723FN TSL25723 0x39 FN-6 IC Vbus = 1.8 V Interface Buy our products or get free samples online at: www.ams.com/ICdirect Technical Support is available at: www.ams.com/Technical-Support Provide feedback about this document at: www.ams.com/Document-Feedback For further information and requests, e-mail us at: ams_sales@ams.com For sales offices, distributors and representatives, please visit: www.ams.com/contact Headquarters ams AG Tobelbader Strasse 30 8141 Premstaetten Austria, Europe Tel: +43 (0) 3136 500 0 Website: www.ams.com Page 34 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - RoHS Compliant & ams Green Statement RoHS Compliant & ams Green Statement RoHS: The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes. ams Green (RoHS compliant and no Sb/Br): ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material). Important Information: The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. ams Datasheet [v1-01] 2018-Mar-27 Page 35 Document Feedback TSL2572 - Copyrights & Disclaimer Copyrights & Disclaimer Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten, Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG "AS IS" and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services. Page 36 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Document Status Document Status Document Status Product Preview Preliminary Datasheet Datasheet Datasheet (discontinued) ams Datasheet [v1-01] 2018-Mar-27 Product Status Definition Pre-Development Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice Pre-Production Information in this datasheet is based on products in the design, validation or qualification phase of development. The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice Production Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade Discontinued Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of Trade, but these products have been superseded and should not be used for new designs Page 37 Document Feedback TSL2572 - Revision Information Revision Information Changes from 1-00 (2016-Apr-01) to current revision 1-01 (2018-Mar-27) Page Updated Figure 6 7 Updated Figure 7 7 Updated Figure 30 26 Updated Figure 39 34 Note(s): 1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision. 2. Correction of typographical errors is not explicitly mentioned. Page 38 Document Feedback ams Datasheet [v1-01] 2018-Mar-27 TSL2572 - Content Guide Content Guide ams Datasheet [v1-01] 2018-Mar-27 1 1 2 2 3 General Description Key Benefits & Features Applications End Products and Market Segments Block Diagram 4 5 6 7 10 11 Pin Assignments Detailed Description Absolute Maximum Ratings Electrical Characteristics Parameter Measurement Information Typical Characteristics 13 13 14 14 15 16 17 18 Principles Of Operation System State Machine Photodiodes ALS Operation Lux Equation Interrupts System State Machine Timing IC Protocol 19 19 20 21 22 22 23 24 25 26 26 27 27 Register Overview Register Set Command Register Enable Register (0x00) ALS Timing Register (0x01) Wait Time Register (0x03) ALS Interrupt Threshold Registers (0x04 - 0x07) Persistence Register (0x0C) Configuration Register (0x0D) Control Register (0x0F) ID Register (0x12) Status Register (0x13) ADC Channel Data Registers (0x14 - 0x17) 28 28 29 Application Information: Hardware Typical Hardware Application PCB Pad Layout 30 31 32 Package Information Carrier Tape & Reel Information Soldering Information 33 33 33 33 33 Storage Information Moisture Sensitivity Shelf Life Floor Life Rebaking Instructions Page 39 Document Feedback TSL2572 - Content Guide 34 35 36 37 38 Page 40 Document Feedback Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information ams Datasheet [v1-01] 2018-Mar-27