© Semiconductor Components Industries, LLC, 2008
February, 2008 - Rev. 7
1Publication Order Number:
MC10EP89/D
MC10EP89
3.3V / 5V ECL Coaxial
Cable Driver
Description
The MC10EP89 is a differential fanout gate specifically designed to
drive coaxial cables. The device is especially useful in digital video
broadcasting applications; for this application, since the system is
polarity free, each output can be used as an independent driver. The
driver produces swings 70% larger than a standard ECL output. When
driving a coaxial cable, proper termination is required at both ends of
the line to minimize signal loss. The 1.6 V (5 V) and 1.4 V (3.3 V)
swing allow for termination at both ends of the cable, while
maintaining a 800 mV (5 V) and 700 mV (3.3 V) swing at the
receiving end of the cable. Because of the larger output swings, the
device cannot be terminated into the standard VCC-2.0 V. All of the
DC parameters are tested with a 50 W to VCC-3.0 V load. The driver
accepts a standard differential ECL input and can run off of the digital
video broadcast standard -5.0 V supply.
Features
•310 ps Typical Propagation Delay
•Maximum Frequency > 2 GHz Typical
•1.6 V (5 V) and 1.4 V (3.3 V) VOUTpp Swing
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
•Open Input Default State
•Safety Clamp on Inputs
•Q Output Will Default LOW with Inputs Open or at VEE
•Pb-Free Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
D = Date Code
G= Pb-Free Package
(Note: Microdot may be in either location)
ALYWG
G
HP89
MARKING
DIAGRAMS*
SOIC-8
D SUFFIX
CASE 751
TSSOP-8
DT SUFFIX
CASE 948R
1
8
1
8
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
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1
8HEP89
ALYWG
G
1
8
DFN8
MN SUFFIX
CASE 506AA
5V DG
G
14
MC10EP89
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2
1
2
3
45
6
7
8
D
VEE
VCC
Q0
D
Q1
Q0
Q1
Table 1. PIN DESCRIPTION
PIN
D*, D*
Q0, Q1, Q0, Q1 ECL Data Outputs
FUNCTION
ECL Data Inputs
VCC
VEE Negative Supply
Positive Supply
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
* Pins will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 kW
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg Pb-Free Pkg
SOIC-8
TSSOP-8
DFN8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
Flammability Rating Oxygen Index: 28 to 34 UL-94 V-0 @ 0.125 in
Transistor Count 152 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V -6 V
VIPECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
-6
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
TAOperating Temperature Range -40 to +85 °C
Tstg Storage Temperature Range -65 to +150 °C
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board 8 SOIC 41 to 44 °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) Standard Board 8 TSSOP 41 to 44 °C/W
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol Wave Solder Pb
Pb-Free
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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Table 4. DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 2)
-40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 30 36 26 34 40 30 36 42 mA
VOH Output HIGH Voltage (Note 3) 2130 2255 2405 2180 2336 2455 2200 2400 2475 mV
VOL Output LOW Voltage (Note 3) 500 784 1100 480 786 1100 440 882 1060 mV
VIH Input HIGH Voltage (Single-Ended) 2070 2410 2170 2490 2240 2580 mV
VIL Input LOW Voltage (Single-Ended) 1350 1800 1350 1820 1350 1855 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 4)
2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
3. All loading with 50 W to VCC - 3.0 V.
4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
Table 5. DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 5)
-40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 27 34 41 30 37 44 33 40 47 mA
VOH Output HIGH Voltage (Note 6) 3830 3955 4105 3880 4037 4155 3900 4102 4175 mV
VOL Output LOW Voltage (Note 6) 1900 2205 2500 1850 2265 2450 1850 2177 2450 mV
VIH Input HIGH Voltage (Single-Ended) 3770 4110 3870 4190 3940 4280 mV
VIL Input LOW Voltage (Single-Ended) 3050 3500 3050 3520 3050 3555 mV
VIHCMR Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 7)
2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.5 V to -0.5 V.
6. All loading with 50 W to VCC - 3.0 V.
7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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Table 6. DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V (Note 8)
-40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 24 30 36 26 34 40 30 36 42 mA
VOH Output HIGH Voltage (Note 9) -1170 -1145 -895 -1120 -964 -845 -1100 -900 -825 mV
VOL Output LOW Voltage (Note 9) -2800 -2516 -2200 -2820 -2514 -2220 -2860 -2478 -2240 mV
VIH Input HIGH Voltage (Single-Ended) -1230 -890 -1130 -810 -1060 -720 mV
VIL Input LOW Voltage (Single-Ended) -1950 -1500 -1950 -1480 -1950 -1445 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
-1.3 0.0 -1.3 0.0 -1.3 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V.
9. All loading with 50 W to VCC - 3.0 V.
10.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
Table 7. DC CHARACTERISTICS, NECL VCC = 0V, VEE = -5.2 (Note 11)
-40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 27 34 41 30 37 44 33 40 47 mA
VOH Output HIGH Voltage (Note 12) -1170 -1045 -895 -1120 -964 -845 -1100 -900 -825 mV
VOL Output LOW Voltage (Note 12) -3100 -2795 -2500 -3150 -2835 -2550 -3150 -2824 -2550 mV
VIH Input HIGH Voltage (Single-Ended) -1230 -890 -1130 -810 -1060 -720 mV
VIL Input LOW Voltage (Single-Ended) -1950 -1500 -1950 -1480 -1950 -1445 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
-3.2 0.0 -3.2 0.0 -3.2 0.0 V
IIH Input HIGH Current 150 150 150 mA
IIL Input LOW Current 0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.7 V to -0.3 V.
12.All loading with 50 W to VCC - 3.0 V.
13.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input
signal.
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Table 8. AC CHARACTERISTICS VCC = 0V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 14)
-40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fmax Maximum Toggle
(See Figure 2 Fmax/JITTER)
> 2 > 2 > 2 GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
220 280 340 250 310 370 270 330 390 ps
tSKEW Within Device Skew Q, Q
Device to Device Skew (Note 15)
5.0 20
120
5.0 20
120
5.0 20
120
ps
tJITTER Cycle-to-Cycle Jitter
(See Figure 2 Fmax/JITTER)
.5 < 1 .5 < 1 .5 < 1 ps
VPP Input Voltage Swing
(Differential Configuration)
150 800 1200 150 800 1200 150 800 1200 mV
tr
tf
Output Rise/Fall Times Q, Q
(20% - 80%)
175 250 325 200 275 350 225 295 375 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-3.0 V.
15.Skew is measured between outputs under identical transitions.
0
200
400
600
800
1000
1200
1400
1600
1800
0 1000 2000 3000 4000 5000
1
2
3
4
5
6
7
8
9
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
(JITTER)
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
3.3 V
5 V
VOUTpp (mV)
JITTEROUT ps (RMS)
ÉÉ
ÉÉ
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150 W150 W
VEE
0.1 mF
75 W
75 W
75 WWCOAX
0.1 mF
75 W
75W
75 W COAX
EP89
DC BLOCKING CAPACITORS
Figure 3. Cable Driver Termination Configuration
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q D
Zo = 50 W
Zo = 50 W
50 W50 W
VTT
VTT = VCC - 3.0 V
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8
ORDERING INFORMATION
Device Package Shipping†
MC10EP89D SOIC-8 98 Units / Rail
MC10EP89DG SOIC-8
(Pb-Free)
98 Units / Rail
MC10EP89DR2 SOIC-8 2500 / Tape & Reel
MC10EP89DR2G SOIC-8
(Pb-Free)
2500 / Tape & Reel
MC10EP89DT TSSOP-8 100 Units / Rail
MC10EP89DTG TSSOP-8
(Pb-Free)
100 Units / Rail
MC10EP89DTR2 TSSOP-8 2500 / Tape & Reel
MC10EP89DTR2G TSSOP-8
(Pb-Free)
2500 / Tape & Reel
MC10EP89MNR4 DFN8 1000 / Tape & Reel
MC10EP89MNR4G DFN8
(Pb-Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D - ECL Clock Distribution Techniques
AN1406/D - Designing with PECL (ECL at +5.0 V)
AN1503/D -ECLinPSt I/O SPiCE Modeling Kit
AN1504/D - Metastability and the ECLinPS Family
AN1568/D - Interfacing Between LVDS and ECL
AN1642/D - The ECL Translator Guide
AND8001/D - Odd Number Counters Design
AND8002/D - Marking and Date Codes
AND8020/D - Termination of ECL Logic Devices
AND8066/D - Interfacing with ECLinPS
AND8090/D - AC Characteristics of ECL Devices
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PACKAGE DIMENSIONS
SOIC-8 NB
CASE 751-07
ISSUE AJ
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDARD IS 751-07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
-X-
-Y-
G
M
Y
M
0.25 (0.010)
-Z-
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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PACKAGE DIMENSIONS
TSSOP-8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R-02
ISSUE A
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A2.90 3.10 0.114 0.122
B2.90 3.10 0.114 0.122
C0.80 1.10 0.031 0.043
D0.05 0.15 0.002 0.006
F0.40 0.70 0.016 0.028
G0.65 BSC 0.026 BSC
L4.90 BSC 0.193 BSC
M0 6 0 6
____
SEATING
PLANE
PIN 1
14
85
DETAIL E
B
C
D
A
G
DETAIL E
F
M
L
2X L/2
-U-
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
-T-
-V-
-W-
0.25 (0.010)
8x REFK
IDENT
K0.25 0.40 0.010 0.016
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
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PACKAGE DIMENSIONS
DFN8
CASE 506AA-01
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
A
D
E
B
C0.10
PIN ONE
2 X
REFERENCE
2 X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
8 X
A1
SEATING
PLANE
e/2 e
8 X
K
NOTE 3
b
8 X 0.10 C
0.05 C
A BB
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.20 0.30
D2.00 BSC
D2 1.10 1.30
E2.00 BSC
E2 0.70 0.90
e0.50 BSC
K0.20 ---
L0.25 0.35
14
85
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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PUBLICATION ORDERING INFORMATION
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Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
MC10EP89/D
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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