LTC2753BCUK-16#PBF - Linear Technology

LTC2753

2753f

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Dual Current Output

12-/14-/16-Bit SoftSpan

DACs with Parallel I/O

The LTC

2753 is a family of dual 12-, 14-, and 16-bit

multiplying parallel-input, current-output DACs. These

DACs operate from a single 2.7V to 5.5V supply and are all

guaranteed monotonic over temperature. The LTC2753A-16

provides 16-bit performance (±1LSB INL and DNL) over

temperature without any adjustments. These SoftSpan™

DACs offer six output ranges—two unipolar and four

bipolar—that can be programmed through the parallel

interface, or pinstrapped for operation in a single range.

The LTC2753 DACs use a bidirectional input/output parallel

interface that allows readback of any on-chip register. A

power-on reset circuit resets the DAC outputs to 0V when

power is initially applied. A logic low on the CLR pin asyn-

chronously clears the DACs to 0V in any output range.

The parts are speciﬁ ed over commercial and industrial

temperature ranges.

Dual 16-Bit VOUT DAC with Software-Selectable Ranges

■ Six Programmable Output Ranges

Unipolar: 0V to 5V, 0V to 10V

Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V

■ Maximum 16-Bit INL Error: ±1 LSB over Temperature

■ Low 1μA (Maximum) Supply Current

■ Guaranteed Monotonic over Temperature

■ Low Glitch Impulse 1nV•s

■ 2.7V to 5.5V Single Supply Operation

■ 2µs Settling Time to ±1 LSB

■ Parallel Interface with Readback of All Registers

■ Asynchronous CLR Pin Clears DAC Outputs to 0V in

Any Output Range

■ Power-On Reset to 0V

■ 48-Pin 7mm × 7mm QFN Package

■ High Resolution Offset and Gain Adjustment

■ Process Control and Industrial Automation

■ Automatic Test Equipment

■ Data Acquisition Systems

LTC2753-16 Integral Nonlinearity (INL)

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

16384 32768

–0.6

0.6

0.8

0.2

49152 65535

2753 TA01b

25°C

90°C

–45°C

VDD = 5V

VREF = 5V

±10V RANGE

–

SPAN I/O

DATA I/O

DAC A

LTC2753-16

RFBA

IOUT1A

VOUTA

VOUTB

IOUT2A

RVOSA

RVOSB

IOUT2B

IOUT1B

RFBB

ROFSB

REFB

REFA

150pF

15pF

1/2 LT1469

RCOM

RIN

ROFSA

VREF

DAC B

2753 TA01

3I/O PORT

I/O PORT

LTC2753

2753f

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

RCOM

RIN

IOUT2A

GND

D11

D10

UPD

READ

D/S

IOUT2B

GND

VDD

GND

CLR

MSPAN

REFA

ROFSA

RFBA

IOUT1A

RVOSA

RVOSB

IOUT1B

RFBB

ROFSB

REFB

LTC2753-12 UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

TJMAX = 125°C, θJA = 29°C/W

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

RCOM

RIN

IOUT2A

GND

D13

D12

D11

D10

UPD

READ

D/S

IOUT2B

GND

VDD

GND

CLR

MSPAN

REFA

ROFSA

RFBA

IOUT1A

RVOSA

RVOSB

IOUT1B

RFBB

ROFSB

REFB

LTC2753-14 UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

TJMAX = 125°C, θJA = 29°C/W

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

RCOM

RIN

IOUT2A

GND

D15

D14

D13

D12

D11

D10

UPD

READ

D/S

IOUT2B

GND

VDD

GND

CLR

MSPAN

REFA

ROFSA

RFBA

IOUT1A

RVOSA

RVOSB

IOUT1B

RFBB

ROFSB

REFB

LTC2753-16 UK PACKAGE

48-LEAD (7mm × 7mm) PLASTIC QFN

48 47 46 45 44 43 42 41 40 39 38 37

13 14 15 16 17 18 19 20 21 22 23 24

TJMAX = 125°C, θJA = 29°C/W

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

ABSOLUTE MAXIMUM RATINGS

IOUT1X, IOUT2X, RCOM to GND .................................±0.3V

RVOSX, RFBX, ROFSX, RIN, REFX to GND ...................±15V

VDD to GND .................................................. –0.3V to 7V

Digital Inputs and Digital I/O

to GND ..........................–0.3V to VDD+0.3V (max 7V)

(Notes 1, 2)

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2753CUK-12#PBF LTC2753CUK-12#TRPBF LTC2753UK-12 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2753IUK-12#PBF LTC2753IUK-12#TRPBF LTC2753UK-12 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LTC2753CUK-14#PBF LTC2753CUK-14#TRPBF LTC2753UK-14 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2753IUK-14#PBF LTC2753IUK-14#TRPBF LTC2753UK-14 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LTC2753BCUK-16#PBF LTC2753BCUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2753BIUK-16#PBF LTC2753BIUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

LTC2753ACUK-16#PBF LTC2753ACUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN 0°C to 70°C

LTC2753AIUK-16#PBF LTC2753AIUK-16#TRPBF LTC2753UK-16 48-Lead (7mm × 7mm) Plastic QFN –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

Operating Temperature Range

LTC2753C ..................................................... 0°C to 70°C

LTC2753I .................................................. –40°C to 85°C

Maximum Junction Temperature........................... 125°C

Storage Temperature Range ................... –65°C to 150°C

LTC2753

2753f

ELECTRICAL CHARACTERISTICS

DD = 5V, VREF = 5V unless otherwise speciﬁ ed. The ● denotes the

speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS

LTC2753-12 LTC2753-14 LTC2753B-16 LTC2753A-16

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

Static Performance

Resolution ●12 14 16 16 Bits

Monotonicity ●12 14 16 16 Bits

DNL Differential

Nonlinearity

●±1 ±1 ±1 ±0.2 ±1 LSB

INL Integral

Nonlinearity

●±1 ±1 ±2 ±0.4 ±1 LSB

GE Gain Error All Output

Ranges

●±0.5 ±2 ±1.5 ±5 ±20 ±4 ±14 LSB

GETC Gain Error Temp-

erature Coefﬁ cient

ΔGain/ΔTemp ±0.6 ±0.6 ±0.6 ±0.6 ppm/°C

BZE Bipolar Zero Error All Bipolar

Ranges

●±0.2 ±1 ±0.6 ±3 ±12 ±2 ±8 LSB

BZSTC Bipolar Zero Temp-

erature Coefﬁ cient

±0.5 ±0.5 ±0.5 ±0.5 ppm/°C

PSR Power Supply

Rejection

VDD = 5V, ±10%

VDD = 3V, ±10%

●

±0.025

±0.06

±0.1

±0.25

±0.4

±1

±0.03

±0.1

±0.2

±0.5

LSB/V

ILKG IOUT1 Leakage

Current

TA = 25°C

TMIN to TMAX ●

±0.05 ±2

±5

±0.05 ±2

±5

±0.05 ±2

±5

±0.05 ±2

±5

CIOUT1 Output

Capacitance

Full-Scale

Zero Scale

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resistances (Note 3)

R1, R2 Reference Inverting Resistors (Note 4) ●16 20 k

RREF DAC Input Resistance ●810 k

RFB Feedback Resistor (Note 3) ●810 k

ROFS Bipolar Offset Resistor (Note 3) ●16 20 k

RVOS Offset Adjust Resistor ●800 1000 k

Dynamic Performance

Output Settling Time 0V to 10V Range, 10V Step. To ±0.0015% FS

(Note 5)

2s

Glitch Impulse (Note 6) 1 nV•s

Digital-to-Analog Glitch Impulse (Note 7) 1 nV•s

Multiplying Feedthrough Error 0V to 10V Range, VREF = ±10V, 10kHz

Sine Wave

0.5 mV

THD Total Harmonic Distortion (Note 8) Multiplying –110 dB

Output Noise Voltage Density (Note 9) at IOUT1 13 nV/√

⎯

VDD = 5V, VREF = 5V unless otherwise speciﬁ ed. The ● denotes speciﬁ cations that apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C.

LTC2753

2753f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply

VDD Supply Voltage ●2.7 5.5 V

IDD Supply Current, VDD Digital Inputs = 0V or VDD ●0.5 1 A

Digital Inputs

VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V

2.7V ≤ VDD < 3.3V

●

2.4

VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V

2.7V ≤ VDD ≤ 4.5V

●

0.8

0.6

IIN Digital Input Current VIN = GND to VDD ●±1 µA

CIN Digital Input Capacitance VIN = 0V (Note 10) ●6pF

Digital Outputs

VOH IOH = 200µA ●VDD – 0.4 V

VOL IOL = 200µA ●0.4 V

TIMING CHARACTERISTICS

The ● denotes speciﬁ cations that apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD = 4.5V to 5.5V

Write and Update Timing

t1I/O Valid to WR Rising Edge Set-Up ●7ns

t2I/O Valid to WR Rising Edge Hold ●7ns

t3WR Pulse Width Low ●15 ns

t4UPD Pulse Width High ●15 ns

t5UPD Falling Edge to WR Falling Edge No Data Shoot-Through ●0ns

t6WR Rising Edge to UPD Rising Edge (Note 10) ●0ns

t7D/S Valid to WR Falling Edge Set-Up Time ●7ns

t8WR Rising Edge to D/S Valid Hold Time ●7ns

t9A1-A0 Valid to WR Falling Edge Setup Time ●5ns

t10 WR Rising Edge to A1-A0 Valid Hold Time ●0ns

t11 A1-A0 Valid to UPD Rising Edge Setup Time ●9ns

t12 UPD Falling Edge to A1-A0 Valid Hold Time ●7ns

Readback Timing

t13 WR Rising Edge to READ Rising Edge ●7ns

t14 READ Falling Edge to WR Falling Edge (Note 10) ●20 ns

t15 READ Rising Edge to I/O Propagation Delay CL = 10pF ●40 ns

t26 A1-A0 Valid to READ Rising Edge Setup Time ●20 ns

t27 READ Falling to A1-A0 Valid Hold Time (Note 10) ●0ns

ELECTRICAL CHARACTERISTICS

DD = 5V, VREF = 5V unless otherwise speciﬁ ed. The ● denotes the

speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

LTC2753

2753f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t17 UPD Valid to I/O Propagation Delay CL = 10pF ●26 ns

t18 D/S Valid to READ Rising Edge (Note 10) ●7ns

t19 READ Rising Edge to UPD Rising Edge No Update ●0ns

t20 UPD Falling Edge to READ Falling Edge No Update ●0ns

t22 READ Falling Edge to UPD Rising Edge (Note 10) ●7ns

t23 I/O Bus Hi-Z to READ Rising Edge (Note 10) ●0ns

t24 READ Falling Edge to I/O Bus Active (Note 10) ●20 ns

CLR Timing

t25 CLR Pulse Width Low ●15 ns

VDD = 2.7V to 3.3V

Write and Update Timing

t1I/O Valid to WR Rising Edge Set-Up ●15 ns

t2I/O Valid to WR Rising Edge Hold ●15 ns

t3WR Pulse Width Low ●30 ns

t4UPD Pulse Width High ●30 ns

t5UPD Falling Edge to WR Falling Edge No Data Shoot-Through ●0ns

t6WR Rising Edge to UPD Rising Edge (Note 10) ●0ns

t7D/S Valid to WR Falling Edge Set-Up Time ●7ns

t8WR Rising Edge to D/S Valid Hold Time ●7ns

t9A1-A0 Valid to WR Falling Edge Setup Time ●7ns

t10 WR Rising Edge to A1-A0 Valid Hold Time ●0ns

t11 A1-A0 Valid to UPD Rising Edge Setup Time ●15 ns

t12 UPD Falling Edge to A1-A0 Valid Hold Time ●15 ns

Readback Timing

t13 WR Rising Edge to Read Rising Edge ●10 ns

t14 Read Falling Edge to WR Falling Edge (Note 10) ●35 ns

t15 Read Rising Edge to I/O Propagation Delay CL = 10pF ●53 ns

t26 A1-A0 Valid to READ Rising Edge Setup Time ●35 ns

t27 READ Falling to A1-A0 Valid Hold Time (Note 10) ●0ns

t17 UPD Valid to I/O Propagation Delay CL = 10pF ●43 ns

t18 D/S Valid to Read Rising Edge (Note 10) ●12 ns

t19 Read Rising Edge to UPD Rising Edge No Update ●0ns

t20 UPD Falling Edge to Read Falling Edge No Update ●0ns

TIMING CHARACTERISTICS

The ● denotes speciﬁ cations that apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C.

LTC2753

2753f

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD = 2.7V to 3.3V

t22 READ Falling Edge to UPD Rising Edge (Note 10) ●10 ns

t23 I/O Bus Hi-Z to Read Rising Edge (Note 10) ●0ns

t24 Read Falling Edge to I/O Bus Active (Note 10) ●35 ns

CLR Timing

t25 CLR Pulse Width Low ●20 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Continuous operation above the speciﬁ ed maximum operating

junction temperature may impair device reliability.

Note 3: Because of the proprietary SoftSpan switching architecture, the

measured resistance looking into each of the speciﬁ ed pins is constant for

all output ranges if the IOUT1X and IOUT2X pins are held at ground.

Note 4: R1 is measured from RIN to RCOM; R2 is measured from REFA to

RCOM.

Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time

of 1.7s can be achieved by optimizing the time constant on an individual

basis. See Application Note 74, Component and Measurement Advances

Ensure 16-Bit DAC Settling Time.

Note 6: Measured at the major carry transition, 0V to 5V range. Output

ampliﬁ er: LT1469; CFB = 27pF.

Note 7. Full-scale transition; REF = 0V.

Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output

ampliﬁ er = LT1469.

Note 9. Calculation from Vn = √

⎯

⎯⎯⎯

B, where k = 1.38E-23 J/°K

(Boltzmann constant), R = resistance (), T = temperature (°K), and B =

bandwidth (Hz).

Note 10. Guaranteed by design. Not production tested.

TIMING CHARACTERISTICS

The ● denotes speciﬁ cations that apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C.

LTC2753

2753f

VREF (V)

–10 –8 0

–6 2

26810

2751 G09

VDD = 5V

±5V RANGE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

–0.6

0.6

0.8

0.2 +DNL

–DNL

+DNL

–DNL

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

16384 32768

–0.6

0.6

0.8

0.2

49152 65535

2753 G01

VDD = 5V

VREF = 5V

±10V RANGE

CODE

–1.0

DNL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

16384 32768

–0.6

0.6

0.8

0.2

49152 65535

2753 G02

VDD = 5V

VREF = 5V

±10V RANGE

TEMPERATURE (°C)

–40

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

–20 20

040

–0.6

0.6

0.8

0.2

60 80

2753 G04

VDD = 5V

VREF = 5V

±10V RANGE

+INL

–INL

TEMPERATURE (°C)

–40

–1.0

DNL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

–20 20

040

–0.6

0.6

0.8

0.2

60 80

2753 G05

VDD = 5V

VREF = 5V

±10V RANGE

+DNL

–DNL

TEMPERATURE (°C)

–40

BZE (LSB)

–20 20

040

60 80

2753 G06

VDD = 5V

VREF = 5V

±10V RANGE

0.5ppm/°C (TYP)

TEMPERATURE (°C)

–40

GE (LSB)

–16

–8

–4

–20 20

040

–12

60 80

2753 G07

VDD = 5V

VREF = 5V

±10V RANGE

0.6ppm/°C (TYP)

VREF (V)

–10 –8 0

–6 2

26810

2753 G08

VDD = 5V

±5V RANGE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

–0.6

0.6

0.8

0.2 +INL

–INL

+INL

–INL

INL vs Temperature

DNL vs Temperature Bipolar Zero vs Temperature Gain Error vs Temperature

INL vs VREF DNL vs VREF

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

LTC2753-16

TA = 25°C, unless otherwise noted.

LTC2753

2753f

500ns/DIV

UPD

5V/DIV

GATED

SETTLING

WAVEFORM

250µV/DIV

2753 G10

USING LT1469 AMP

CFEEDBACK = 12pF

0V TO 10V STEP

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

4096 8192

–0.6

0.6

0.8

0.2

12288 16383

2753 G11

VDD = 5V

VREF = 5V

±10V RANGE

CODE

–1.0

DNL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

4096 8192

–0.6

0.6

0.8

0.2

12288 16383

2753 G12

VDD = 5V

VREF = 5V

±10V RANGE

CODE

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

1024 2048

–0.6

0.6

0.8

0.2

3072 4095

2753 G13

VDD = 5V

VREF = 5V

±10V RANGE

CODE

DNL (LSB)

1024 2048 3072 4095

2753 G14

VDD = 5V

VREF = 5V

±10V RANGE

–1.0

–0.8

–0.4

–0.2

0.0

1.0

0.4

–0.6

0.6

0.8

0.2

TYPICAL PERFORMANCE CHARACTERISTICS

Settling 0V to 10V

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

LTC2753-12

LTC2753-16

Integral Nonlinearity (INL) Differential Nonlinearity (DNL)

LTC2753-14

VDD (V)

2.5

–1.0

INL (LSB)

–0.8

–0.4

–0.2

0.0

1.0

0.4

3.5 4.5

–0.6

0.6

0.8

0.2

55.5

2751 G09b

+INL

–INL

INL vs VDD

TA = 25°C, unless otherwise noted.

Multiplying Frequency Response

vs Digital Code

FREQUENCY (Hz)

100

–120

ATTENUATION (dB)

–100

–80

–60

–40

–20

1k 10k 100k 1M

2753 G10a

10M

ALL BITS OFF

D15

D14

D12

D10

D13

D11

ALL BITS ON

UNIPOLAR 5V OUTPUT RANGE

LT1469 OUTPUT AMPLIFIER

CFEEDBACK = 15pF

LTC2753

2753f

500ns/DIV

UPD

5V/DIV

VOUT

2mV/DIV

2753 G15

USING AN LT1469

CFEEDBACK = 27pF

VDD = 5V

VREF = 5V

0V TO 5V RANGE

1nV•S (TYP)

DIGITAL INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

2345

2753 G16

VDD = 5V

VDD = 3V

VDD (V)

2.5

0.5

LOGIC THRESHOLD (V)

0.75

1.25

1.5

33.5 4 4.5 5 5.5

1.75

2753 G17

RISING

FALLING

UPDATE FREQUENCY (Hz)

SUPPLY CURRENT (mA)

0.1

0.01

100k

0.001

0.0001 100 1k 10k 1M

2753 G18

VDD = 5V

VDD = 3V

Midscale Glitch

Logic Threshold

vs Supply Voltage

Supply Current vs

Logic Input Voltage

Supply Current

vs Update Frequency

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2753-12, LTC2753-14, LTC2753-16

TA = 25°C, unless otherwise noted.

LTC2753

2753f

PIN FUNCTIONS

RCOM (Pin 1): Center Tap Point for the Reference Inverting

Resistors. The 20k reference inverting resistors R1 and R2

are connected internally from RIN to RCOM and from RCOM

to REFA, respectively (see Block Diagram). For normal

operation tie RCOM to the negative input of the external

reference inverting ampliﬁ er (see Typical Applications).

RIN (Pin 2): Input Resistor R1 of the Reference Inverting

Resistors. The 20k resistor R1 is connected internally from

RIN to RCOM. For normal operation tie RIN to the external

reference voltage VREF. Typically 5V; accepts up to ±15V.

S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used

to program and to read back the output ranges of the

DACs.

IOUT2A (Pin 4): DAC A Current Output Complement. Tie

IOUT2A to ground.

GND (Pin 5): Shield Ground, provides necessary shielding

for IOUT2A. Tie to ground.

D3-D11 (Pins 6-14): LTC2753-12 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D11 is the MSB.

D5-D13 (Pins 6-14): LTC2753-14 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D13 is the MSB.

D7-D15 (Pins 6-14): LTC2753-16 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D15 is the MSB.

VDD (Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.

Requires a 0.1µF bypass capacitor to GND.

NC (Pin 16): No Internal Connection.

A1 (Pin 17): DAC Address Bit 1. See Table 3.

A0 (Pin 18): DAC Address Bit 0. See Table 3.

GND (Pin 19): Ground. Tie to ground.

CLR (Pin 20): Asynchronous Clear. When CLR is taken

to a logic low, the data registers are reset to the zero-volt

code for the present output range (VOUT = 0V).

MSPAN (Pin 21): Manual Span Control Pin. MSPAN is used

to conﬁ gure the LTC2753 for operation in a single, ﬁ xed

output range. When conﬁ gured for single-span operation,

the output range is set via hardware pin strapping. The

input and DAC registers of the span I/O port are transparent

and do not respond to write or update commands.

To conﬁ gure the part for single-span use, tie MSPAN directly

to VDD. If MSPAN is instead connected to GND (SoftSpan

conﬁ guration), the output ranges are set and veriﬁ ed by

using write, update and read operations. See Manual Span

Conﬁ guration in the Operation section. MSPAN must be

connected either directly to GND (SoftSpan conﬁ guration)

or VDD (single-span conﬁ guration).

D0-D2 (Pins 22-24): LTC2753-12 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

D0-D4 (Pins 22-26): LTC2753-14 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

D0-D6 (Pins 22-28): LTC2753-16 Only. DAC Input/Output

Data Bits. These I/O pins set and read back the DAC code.

D0 is the LSB.

NC (Pins 25-30): LTC2753-12 Only. No Internal Connection.

NC (Pins 27-30): LTC2753-14 Only. No Internal Connection.

NC (Pins 29, 30): LTC2753-16 Only. No Internal Con-

nection.

GND (Pin 31): Shield Ground, provides necessary shielding

for IOUT2B. Tie to ground.

IOUT2B (Pin 32): DAC B Current Output Complement. Tie

IOUT2B to ground.

S0 (Pin 33): Span I/O Bit 0. Pins S0, S1 and S2 are used to

program and to read back the output range of the DACs.

D/S (Pin 34): Data/Span Select. This pin is used to select

the data I/O pins or the span I/O pins (D0 to D15 or S0

to S2, respectively), along with their respective dedicated

registers, for write or read operations. Update operations

ignore D/S, since all updates affect both data and span

registers. For single-span operation, tie D/S to ground.

READ (Pin 35): Read Pin. When READ is asserted high,

the data I/O pins (D0-D15) or span I/O pins (S0-S2)

LTC2753

2753f

PIN FUNCTIONS

output the contents of the selected register (see Table

1). For single-span operation, readback of the span I/O

pins is disabled.

UPD (Pin 36): Update and Buffer Select Pin. When READ

is held low and UPD is asserted high, the contents of the

addressed DAC’s input registers (both data and span) are

copied into their respective DAC registers. The output of the

DAC is updated, reﬂ ecting the new DAC register values.

When READ is held high, the update function is disabled

and the UPD pin functions as a buffer selector—logic low

to select the input register, high to select the DAC register.

See Readback in the Operation section.

WR (Pin 37): Active Low Write Pin. A Write operation cop-

ies the data present on the data or span I/O pins (D0-D15

or S0-S2, respectively) into the associated input register.

When READ is high, the Write function is disabled.

S1 (Pin 38): Span I/O Bit 1. Pins S0, S1 and S2 are used

to program and to read back the output ranges of the

DACs.

REFB (Pin 39): Reference Input for DAC B. The impedance

looking into this pin is 10k to ground. For normal opera-

tion tie to the output of the reference inverting ampliﬁ er.

Typically –5V; accepts up to ±15V.

ROFSB (Pin 40): Bipolar Offset Network for DAC B. This

pin provides the translation of the output voltage range for

bipolar spans. Accepts up to ±15V; for normal operation

tie to the positive reference voltage at RIN (Pin 2). The

impedance looking into this pin is 20k to ground.

RFBB (Pin 41): DAC B Feedback Resistor. For normal

operation tie to the output of the I/V converter ampliﬁ er

for DAC B (see Typical Applications). The DAC output

current from IOUT1B ﬂ ows through the feedback resistor

to the RFBB pin. The impedance looking into this pin is

10k to ground.

IOUT1B (Pin 42): DAC B Current Output. This pin is a virtual

ground when the DAC is operating and should reside at

0V. For normal operation tie to the negative input of the I/V

converter ampliﬁ er for DAC B (see Typical Applications).

RVOSB (Pin 43): DAC B Offset Adjust. Nominal input range

is ±5V. The impedance looking into this pin is 1M to ground.

If not used, tie RVOSB to ground.

RVOSA (Pin 44): DAC A Offset Adjust. Nominal input range

is ±5V. The impedance looking into this pin is 1M to ground.

If not used, tie RVOSA to ground.

IOUT1A (Pin 45): DAC A Current Output. This pin is a virtual

ground when the DAC is operating and should reside at

0V. For normal operation tie to the negative input of the I/V

converter ampliﬁ er for DAC A (see Typical Applications).

RFBA (Pin 46): DAC A Feedback Resistor. For normal

operation tie to the output of the I/V converter ampliﬁ er

for DAC A (see Typical Applications). The DAC output

current from IOUT1A ﬂ ows through the feedback resistor

to the RFBA pin. The impedance looking into this pin is

10k to ground.

ROFSA (Pin 47): Bipolar Offset Network for DAC A. This

pin provides the translation of the output voltage range for

bipolar spans. Accepts up to ±15V; for normal operation

tie to the positive reference voltage at RIN (Pin 2). The

impedance looking into this pin is 20k to ground.

REFA (Pin 48): Reference Input for DAC A, and connec-

tion for internal reference inverting resistor R2. The 20k

resistor R2 is connected internally from RCOM to REFA. For

normal operation tie this pin to the output of the reference

inverting ampliﬁ er (see Typical Applications). Typically –5V;

accepts up to ±15V. The impedance looking into this pin

is 10k to ground (RIN and RCOM ﬂ oating).

Exposed Pad (Pin 49): Ground. The Exposed Pad must

be soldered to the PCB.

LTC2753

2753f

BLOCK DIAGRAM

DAC A

16-BIT WITH

SPAN SELECT

DAC B

16-BIT WITH

SPAN SELECT

2753 BD

16 45 IOUT1A

IOUT2A

IOUT1B

IOUT2B

RVOSA

RIN

R1 R2

2 1 48 47 46

RCOM REFA ROFSA RFBA

RVOSB

RFBB

ROFSB

REFBMSPANREAD WR UPD D/S CLR

3935 37 36 34 20 21 40 41

DATA DAC

SPAN INPUT

DATA INPUT

SPAN INPUT

CONTROL LOGIC

DATA INPUT

I/O

PORT

DATA I /O

6-14, 22-28

SPAN I /O

3, 38, 33

DAC

ADDRESS

I/O

PORT

SPAN DAC

DATA DAC

SPAN DAC

LTC2753

2753f

TIMING DIAGRAMS

Write, Update and Clear Timing

Readback Timing

CLR

2753 TD01

t10 t11 t12

DATA/SPAN I/O

INPUT

UPD

ADDRESS

A1 - A0 VALID

VALID

D/S

t25

t26 t17

D/S

2753 TD02

t15

t18

t27

t22

t20

t19

t13

t23

t14

t24

DATA/SPAN I/O

INPUT

DATA/SPAN I/O

OUTPUT

UPD

VALID

ADDRESS

A1-A0

READ

LTC2753

2753f

Output Ranges

The LTC2753 is a dual current-output, parallel-input preci-

sion multiplying DAC with software-programmable output

ranges. SoftSpan provides two unipolar output ranges

(0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V,

±5V, ±10V and –2.5V to 7.5V). These ranges are obtained

when an external precision 5V reference is used. When

a reference voltage of 2V is used, the SoftSpan ranges

become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to 3V.

The output ranges are linearly scaled for references other

than 2V and 5V.

Digital Section

The LTC2753 has 4 internal registers for each DAC, a total

of 8 registers (see Block Diagram). Each DAC channel has

two sets of double-buffered registers—one set for the data,

and one set for the span (output range) of the DAC. The

double-buffered feature provides the capability to simulta-

neously update the span and code, which allows smooth

voltage transitions when changing output ranges. It also

permits the simultaneous updating of multiple DACs.

Each set of double-buffered registers comprises an input

buffers—when data is loaded into an input register via a

write operation, the DAC outputs are not affected.

The contents of a DAC register, on the other hand, di-

rectly control the DAC output voltage or output range.

The contents of the DAC registers are changed by copying

the contents of an input register into its associated DAC

Write and Update Operations

The data input register of the addressed DAC is loaded

directly from a 16-bit microprocessor bus by holding the

D/S pin low and pulsing the WR pin low (write operation).

The DAC register is loaded by pulsing the UPD pin high

(update operation), which copies the data held in the input

include both data and span; but the DAC register values

will not change unless the input register values have previ-

ously been changed via a write operation.

Loading the span input register is accomplished similarly,

holding the D/S pin high and bringing the WR pin low. The

span and data register structures are the same except for

the number of parallel bits—the span registers have 3 bits,

while the data registers have 12, 14, or 16.

To make both registers transparent for ﬂ owthrough

mode, tie WR low and UPD high. However, this defeats

the deglitcher operation and output glitch impulse may

increase. The deglitcher is activated on the rising edge

of the UPD pin.

The interface also allows the use of the input and DAC

registers in a master-slave, or edge-triggered, conﬁ gura-

tion. This mode of operation occurs when WR and UPD

are tied together and driven by a single clock signal. The

data bits are loaded into the input register on the falling

edge of the clock and then loaded into the DAC register

on the rising edge.

It is possible to control both data and span on one 16-bit

wide data bus by allowing span pins S2 to S0 to share

bus lines with the data LSBs (D2 to D0). No write or read

operation includes both span and data, so there cannot

be a conﬂ ict.

The asynchronous clear pin resets both DACs to 0V in any

output range. CLR resets all data registers, while leaving

the span registers undisturbed.

OPERATION

Figure 1. Using MSPAN to Conﬁ gure the LTC2753 for Single-Span

Operation (±10V Range).

LTC2753-16

MSPAN

D/S

DAC B

DAC A

2753 F01

WR UPD READ A1 A0

DATA I/O

VDD

LTC2753

2753f

OPERATION

the D/S pin. The selected I/O port’s pins become logic

outputs during readback, while the unselected I/O port’s

pins remain high-impedance inputs.

With the DAC channel and I/O port selected, assert READ

high and select the desired input or DAC register using the

UPD pin. Note that UPD is a two function pin—the update

function is only available when READ is low. When READ

is high, the update function is disabled and the UPD pin

instead selects the input or DAC register for readback.

Table 1 shows the readback functions for the LTC2753.

Table 1. Write, Update and Read Functions

READ D/S WR UPD SPAN I/O DATA I/O

0 0 0 0 - Write to Input Register

0 0 0 1 - Write/Update

(Transparent)

00 10 - -

0 0 1 1 Update DAC Register Update DAC Register

0 1 0 0 Write to Input Register -

0 1 0 1 Write/Update

(Transparent)

01 10 - -

0 1 1 1 Update DAC register Update DAC Register

1 0 X 0 - Read Input Register

1 0 X 1 - Read DAC Register

1 1 X 0 Read Input Register -

1 1 X 1 Read DAC Register -

X = Don’t Care

The most common readback task is to check the contents

of an input register after writing to it, before updating the

new data to the DAC register. To do this, hold UPD low

and assert READ high. The contents of the selected port’s

input register are output to its I/O pins.

To read back the contents of a DAC register, hold UPD low

and assert READ high, then bring UPD high to select the

DAC register. The contents of the selected DAC register are

output by the selected port’s I/O pins. Note: if no update is

desired after the readback operation, UPD must be returned

low before bringing READ low; otherwise the UPD pin will

revert to its primary function and update the DAC.

These devices also have a power-on reset that initializes

both DACs to VOUT = 0V in any output range. The DACs

power up in the 0V-5V range if the part is in SoftSpan

conﬁ guration; for manual span (see Manual Span Conﬁ gu-

ration below), both DACs power up in the manually-chosen

range at the appropriate code.

Manual Span Conﬁ guration

Multiple output ranges are not needed in some applications.

To conﬁ gure the LTC2753 for single-span operation, tie the

MSPAN pin to VDD and the D/S pin to GND. The desired

output range is then speciﬁ ed by the span I/O pins (S0,

S1 and S2) as usual, but the pins are programmed by ty-

ing directly to GND or VDD (see Figure 1 and Table 2). In

this conﬁ guration, both DAC channels will initialize to the

chosen output range at power-up, with VOUT = 0V.

When conﬁ gured for manual span operation, span pin

readback is disabled.

Readback

The contents of any one of the 8 interface registers can

be read back from the I/O ports.

The I/O pins are grouped into two ports: data and span. The

data I/O port comprises pins D0-D11, D0-D13 or D0-D15

(LTC2753-12, LTC2753-14 or LTC2753-16, respectively).

The span I/O port comprises pins S0, S1 and S2 for all

parts.

Each DAC channel has a set of data registers that are

controlled and read back from the data I/O port; and a set

of span registers that are controlled and read back from

the span I/O port. The register structure is shown in the

Block Diagram.

A readback operation is initiated by asserting READ to

logic high after selecting the desired DAC channel and I/O

port. The I/O pins, which are high-impedance digital inputs

when READ is low, selectively change to low-impedance

logic outputs during readback.

Select the DAC channel with address pins A1 and A0, and

select the I/O port (data or span) to be read back with

LTC2753

2753f

System Offset Adjustment

Many systems require compensation for overall system

offset. The RVOSA and RVOSB offset adjustment pins are

provided for this purpose. For noise immunity and ease

of adjustment, the control voltage is attenuated to the

DAC output:

VOS = –0.01 • V(RVOSX) [0V to 5V, ±2.5V spans]

VOS = –0.02 • V(RVOSX) [0V to 10V, ±5V, –2.5V to 7.5V

spans]

VOS = –0.04 • V(RVOSX) [±10V span]

The nominal input range of this pin is ±5V; other reference

voltages of up to 15V may be used if needed. The RVOSX

pins have an input impedance of 1M. To preserve the

settling performance of the LTC2753, drive this pin with a

Thevenin-equivalent impedance of 10k or less. Short any

unused system offset adjustment pins to IOUT2.

Table 2. Span Codes

S2 S1 S0 SPAN

0 0 0 Unipolar 0V to 5V

0 0 1 Unipolar 0V to 10V

0 1 0 Bipolar –5V to 5V

0 1 1 Bipolar –10V to 10V

1 0 0 Bipolar –2.5V to 2.5V

1 0 1 Bipolar –2.5V to 7.5V

Codes not shown are reserved and should not be used.

Table 3. Address Codes

DAC CHANNEL A1 A0

A00

B01

ALL* 1 1

Codes not shown are reserved and should not be used.

*If readback is taken using the All DACs address, the LTC2753 defaults to

DAC A.

OPERATION

LTC2753

2753f

OPERATION— EXAMPLES

2753 TD03

SPAN I/O

INPUT

DATA I/O

INPUT

UPD

D/S

8000H

010

READ = LOW

UPDATE

(±5V RANGE, VOUT = 0V)

2753 TD04

SPAN I/O

INPUT

DATA I/O

INPUT

READ = LOW

UPD

D/S

C000H4000H

011

UPDATE (5V) UPDATE (–5V)

2753 TD05

DATA I/O

OUTPUT

DATA I/O

INPUT

READ

UPD

D/S

8000H

8000H0000H

HI-Z

INPUT REGISTER DAC REGISTER

HI-Z

UPDATE (2.5V)

1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at

0V, will stay there. The 16-Bit DAC code is shown in hex for compactness.

2. Load ±10V range with the output at 5V, changing to –5V.

3. Write and update midscale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input

and DAC registers before updating.

LTC2753

2753f

Op Amp Selection

Because of the extremely high accuracy of the 16-bit

LTC2753-16, careful thought should be given to op amp

selection in order to achieve the exceptional performance

of which the part is capable. Fortunately, the sensitivity of

INL and DNL to op amp offset has been greatly reduced

compared to previous generations of multiplying DACs.

Tables 4 and 5 contain equations for evaluating the effects

of op amp parameters on the LTC2753’s accuracy when

APPLICATIONS INFORMATION

programmed in a unipolar or bipolar output range. These

are the changes the op amp can cause to the INL, DNL,

unipolar offset, unipolar gain error, bipolar zero and bipolar

gain error. Tables 4 and 5 can also be used to determine

the effects of op amp parameters on the LTC2753-14

and the LTC2753-12. However, the results obtained from

Tables 4 and 5 are in 16-bit LSBs. Divide these results

by 4 (LTC2753-14) and 16 (LTC2753-12) to obtain the

correct LSB sizing.

Table 6 contains a partial list of LTC precision op amps

recommended for use with the LTC2753. The easy-to-use

design equations simplify the selection of op amps to meet

the system’s speciﬁ ed error budget. Select the ampliﬁ er

from Table 6 and insert the speciﬁ ed op amp parameters

in Table 5. Add up all the errors for each category to de-

termine the effect the op amp has on the accuracy of the

part. Arithmetic summation gives an (unlikely) worst-case

effect. A root-sum-square (RMS) summation produces a

more realistic estimate.

()

VREF

()

VREF

()

16.5k

AVOL1

OP AMP

VOS1 (mV)

IB1 (nA)

AVOL1 (V/V)

VOS2 (mV)

IB2 (mV)

AVOL2 (V/V)

VOS1 • 3.2 •

IB1 • 0.0003 •

A1 •

INL (LSB)

()

VREF

()

VREF

()

1.5k

AVOL1

()

66k

AVOL2

()

131k

AVOL1

()

131k

AVOL1

()

131k

AVOL2

()

131k

AVOL2

VOS1 • 0.82 •

IB1 • 0.00008 •

A2 •

DNL (LSB)

()

VREF

()

VREF

A3 • VOS1 • 13.2 •

IB1 • 0.13 •

UNIPOLAR

OFFSET (LSB)

()

VREF

()

VREF

()

VREF

VOS1 • 13.2 •

IB1 • 0.0018 •

A5 •

VOS2 • 26.2 •

IB2 • 0.26 •

BIPOLAR GAIN

ERROR (LSB)

()

VREF

()

VREF

()

VREF

()

VREF

A3 • VOS1 • 19.8 •

IB1 • 0.13 •

A4 • VOS2 • 13.1 •

A4 • IB2 • 0.13 •

A4 •

BIPOLAR ZERO

ERROR (LSB)

UNIPOLAR GAIN

ERROR (LSB)

()

VREF

()

VREF

()

VREF

()

VREF

()

VREF

VOS1 • 13.2 •

IB1 • 0.0018 •

A5 •

VOS2 • 26.2 •

IB2 • 0.26 •

Table 4. Variables for Each Output Range That Adjust the

Equations in Table 5

OUTPUT RANGE A1 A2 A3 A4 A5

5V 1.1 2 1 1

10V 2.2 3 0.5 1.5

±5V 22111.5

±10V 4 4 0.83 1 2.5

±2.5V 1 1 1.4 1 1

–2.5V to 7.5V 1.9 3 0.7 0.5 1.5

Table 6. Partial List of LTC Precision Ampliﬁ ers Recommended for Use with the LTC2753 with Relevant Speciﬁ cations

AMPLIFIER

AMPLIFIER SPECIFICATIONS

VOS

μV

AVOL

V/mV

VOLTAGE

NOISE

nV/√

⎯

CURRENT

NOISE

pA/√

⎯

SLEW

RATE

V/μs

GAIN BANDWIDTH

PRODUCT

MHz

tSETTLING

with LTC2753

μs

POWER

DISSIPATION

LT1001 25 2 800 10 0.12 0.25 0.8 120 46

LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11

LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp

LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp

LT1468 75 10 5000 5 0.6 22 90 2 117

LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp

Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1

Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.

LTC2753

2753f

APPLICATIONS INFORMATION

Op amp offset will contribute mostly to output offset and

gain error, and has minimal effect on INL and DNL. For

example, for the LTC2753-16 with a 5V reference in 5V

unipolar mode, a 250µV op amp offset will cause a 3.3LSB

zero-scale error and a 3.3LSB gain error; but only 0.8LSB

of INL degradation and 0.2LSB of DNL degradation.

While not directly addressed by the simple equations in

Tables 4 and 5, temperature effects can be handled just as

easily for unipolar and bipolar applications. First, consult

an op amp’s data sheet to ﬁ nd the worst-case VOS and IB

over temperature. Then, plug these numbers in the VOS

and IB equations from Table 5 and calculate the tempera-

ture-induced effects.

For applications where fast settling time is important, Ap-

plication Note 74, Component and Measurement Advances

Ensure 16-Bit DAC Settling Time, offers a thorough discus-

sion of 16-bit DAC settling time and op amp selection.

Precision Voltage Reference Considerations

Much in the same way selecting an operational ampliﬁ er

for use with the LTC2753 is critical to the performance of

the system, selecting a precision voltage reference also

requires due diligence. The output voltage of the LTC2753

is directly affected by the voltage reference; thus, any

voltage reference error will appear as a DAC output volt-

age error.

There are three primary error sources to consider when

selecting a precision voltage reference for 16-bit appli-

cations: output voltage initial tolerance, output voltage

temperature coefﬁ cient and output voltage noise.

Initial reference output voltage tolerance, if uncorrected,

generates a full-scale error term. Choosing a reference

with low output voltage initial tolerance, like the LT1236

(±0.05%), minimizes the gain error caused by the reference;

however, a calibration sequence that corrects for system

zero- and full-scale error is always recommended.

A reference’s output voltage temperature coefﬁ cient af-

fects not only the full-scale error, but can also affect the

circuit’s apparent INL and DNL performance. If a refer-

ence is chosen with a loose output voltage temperature

coefﬁ cient, then the DAC output voltage along its transfer

characteristic will be very dependent on ambient conditions.

Minimizing the error due to reference temperature coef-

ﬁ cient can be achieved by choosing a precision reference

with a low output voltage temperature coefﬁ cient and/or

tightly controlling the ambient temperature of the circuit

to minimize temperature gradients.

As precision DAC applications move to 16-bit and higher

performance, reference output voltage noise may con-

tribute a dominant share of the system’s noise ﬂ oor. This

in turn can degrade system dynamic range and signal-to-

noise ratio. Care should be exercised in selecting a voltage

reference with as low an output noise voltage as practi-

cal for the system resolution desired. Precision voltage

references, like the LT1236, produce low output noise in

the 0.1Hz to 10Hz region, well below the 16-bit LSB level

in 5V or 10V full-scale systems. However, as the circuit

bandwidths increase, ﬁ ltering the output of the reference

may be required to minimize output noise.

Table 7. Partial List of LTC Precision References Recommended

for Use with the LTC2753 with Relevant Speciﬁ cations

REFERENCE

INITIAL

TOLERANCE

TEMPERATURE

DRIFT

0.1Hz to 10Hz

NOISE

LT1019A-5,

LT1019A-10

±0.05% 5ppm/°C 12µVP-P

LT1236A-5,

LT1236A-10

±0.05% 5ppm/°C 3µVP-P

LT1460A-5,

LT1460A-10

±0.075% 10ppm/°C 20µVP-P

LT1790A-2.5 ±0.05% 10ppm/°C 12µVP-P

LTC2753

2753f

Grounding

As with any high resolution converter, clean grounding is

important. A low impedance analog ground plane and star

grounding techniques should be used. IOUT2 must be tied

to the star ground with as low a resistance as possible.

When it is not possible to locate star ground close to

IOUT2, a low resistance trace should be used to route this

APPLICATIONS INFORMATION

pin to star ground. This minimizes the voltage drop from

this pin to ground caused by the code dependent current

ﬂ owing to ground. When the resistance of this circuit

board trace becomes greater than 1, a force/sense am-

pliﬁ er conﬁ guration should be used to drive this pin (see

Figure 2). This preserves the excellent accuracy (1LSB

INL and DNL) of the LTC2753-16.

LTC2753

2753f

APPLICATIONS INFORMATION

–

1/2 LT1469

DAC A

LTC2753-16

VREF

IOUT1A

15pF

IOUT2A

RFBA

RVOSA

REFA

RCOM

RIN

ROFSA

VOUTA

–

IOUT2

*SCHOTTKY BARRIER DIODE

ZETEX*

BAT54S

LT1001

2753 F02

1000pF

ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE

4,32

–

LT1468

ZETEX

BAT54S

200

200Ω

IOUT2

150pF

Figure 2. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Ampliﬁ er.

LTC2753

2753f

–

1/2 LT1469

DAC A

DAC B

LTC2753-16

VREF

1R1

IOUT1A

IOUT2B

IOUT1B

15pF

IOUT2A

RFBA

RVOSA

RVOSB

RFBB

REFA

WR UPD READ D/S CLR

MSPAN

ADDRESS

*FOR MULTIPLYING APPLICATIONS C1 = 15pF

A1, A0

REFB

37 36 35 34 20 21 17, 18

ROFSB

RCOM

RIN

ROFSA

VOUTA

2753 F03

150pF

C1*

DATA I/O

D15 - D0

SPAN I/O

S2 - S0

–

1/2 LT1469

VOUTB

I/O PORT

Dual 16-Bit VOUT DAC with Software-Selectable Ranges

TYPICAL APPLICATIONS

LTC2753

2753f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

UK Package

48-Lead Plastic QFN (7mm × 7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

7.00 ± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1

CHAMFER

C = 0.35

0.40 ± 0.10

4847

BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES)

0.75 ± 0.05 R = 0.115

TYP

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UK48) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

5.15 ± 0.10

5.15 ± 0.05

R = 0.10

TYP

LTC2753

2753f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 1007 • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LT1027 Precision Reference 1ppm/°C Maximum Drift

LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise

LT1468 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate

LT1469 Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate

LTC1588/LTC1589/

LTC1592

Serial 12-/14-/16-Bit IOUT Single DAC Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package

LTC1591/LTC1597 Parallel 14-/16-Bit IOUT Single DAC Integrated 4-Quadrant Resistors

LTC1821 Parallel 16-Bit VOUT Single DAC ±1LSB INL, DNL, 0V to 10V, 0V to –10V, ±10V Output Ranges

LTC2601/LTC2611/

LTC2621

Serial 12-/14-/16-Bit VOUT Single DACs Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

DFN-10 Package

LTC2606/LTC2616/

LTC2626

Serial 12-/14-/16-Bit VOUT Single DACs Single DACs, I2C-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm

DFN-10 Package

LTC2641/LTC2642 Serial 12-/14-/16-Bit Unbuffered VOUT Single

DACs

±2LSB INL, ±1LSB DNL, 1µs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10

Packages

LTC2704 Serial 12-/14-/16-Bit VOUT Quad DACs Software-Selectable (SoftSpan) Ranges, Integrated Ampliﬁ ers, ±2LSB INL

LTC2751 Parallel 12-/14-/16-Bit IOUT SoftSpan

Single DACs

±1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 5mm × 7mm

QFN-38 Package

–

U2A

LT®1469

–

U4B

LT1469

LTC2753-16

LT1027

RVOSA

RVOSB

RCOM

RIN

ROFSB

ROFSA

IN OUT

TRIM

GND

V+

V–

REFA REFB RFBA

RFBB

IOUT1A

IOUT2B

IOUT1B

VOUTA

IOUT2A

DATA I/O

SPAN I/O

D15

D14

D13

D12

D11

D10

C22

0.001µF

30pF

VDD

2753 TA03

10k

OFFSET

TRIM A

OFFSET

TRIM B

10k

30pF

WRUPDREADD/S CLR MSPAN

34 35 36 37 20 21

WRUPDREADD/S CLR

GNDGNDGNDGND

51931 49 41

15 47 40 2 1 48 39

C23

0.1µF

C20

10µF

C13

10µF

GAIN

TRIM

10k

–

U4A

LT1469

VOUTB

V+

V–

Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply