Intel® LXT908 Universal 3.3 V 10BASE-T
and AUI Transceiver
Dat ash e et
The LXT908 Univers al 10BASE-T and AUI Transceiver (call hereafter LXT908 Transc eiver) is
desi gned for IEEE 802.3 physical layer ap plications. It provides all the active circuitry to
interface most standard 802.3 controllers to eit her the 10BASE-T media or Attachment Unit
Interfa ce (AUI). In addition to standard 10 Mbps E thernet, the LXT908 Transce iver also
supports full- duplex operation at 20 Mbps.
LXT908 Transceiver functions include Manchester encoding/decoding, re ceiver squelch and
trans mit pulse shaping, jabb er, link testing and reverse d polarity detection/correction. T he
LXT908 Transceiver can be used to dri ve e ither the AUI drop cab le or the 10BASE-T twisted-
pair ca ble with only a simple isolation t r ansformer. Integra ted fi lters simp lify the design work
required for FCC-c omplia nt EMI perfo rmance.
The LXT908 Transce iver i s fabricated with an advan ced CMOS process and re quires only a
singl e 3. 3V power supply.
Applications
Product Fe a tures
■Access devices (DSL, Cable Modems, and
Set-to p Boxes)
■Routers/Bridges/Switches/Hubs
■Tele co m Bac kplane
■USB to Ethernet Converters
Fu nctional Features
■Improve d Filters - Simplifies FCC
Compliance
■Integra ted Manchester Encoder/Decoder
■10BASE- T c ompliant Trans ceiver
■AUI Transceiver
■Supports Standard and Full-Duplex
Ethernet
Diagnostic Features
■Four LED Drivers
■AUI/RJ-45 Loopback
Con ve ni en ce Feat ures
■Aut o m a tic/Man u a l A U I /R J - 4 5 Se lection
■Automatic Polarity Correction
■SQE Disable/Enable function
■Power Down Mode wit h tri-stated outputs
■Four loopback modes
■Si ngle 3.3V opera tion
■Avai l abl e in 64 -pin LQ F P and 44-pin
PL CC package
■Commercial (0 to +70°C) and
Extended (-40 to +85°C ) temperature range
Order Number: 249049-003
29-Oct-2005
2 D atashee t
Document #: 249049
Revis ion #: 003
Rev. Date: 29-Oct-2005
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estoppel or otherwis e, to any such patents, trademarks, copyrights, or other intellectual property rights.
The Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver may contai n design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are availabl e on request.
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Copyright © 2005, Intel Corporation. All Rights Reserved.
Datasheet 3
Document #: 249049
Re vision #: 0 03
Rev. Date: 29-Oct-2005
Contents
Contents
1.0 Pin Assignments and Signal Descriptions ....................................................................8
2.0 Functional Description ..................................................................................................12
2.1 Introduction..........................................................................................................12
2.1.1 Controller Compatibilit y Modes ........... ............................... ....................12
2.1.2 Tra ns mit Functio n... ................... ........................ ....................... ..............12
2.1.3 Jabber Control Function...................... ............................... ....................13
2.1.4 Receive Function....................................................................................14
2.1.5 SQE Function....... ............................ ........................ ....................... .......14
2.1.6 Pola r ity Reverse Funct ion..................... ................................. ................15
2.1.7 Loopback Function... ................. ......... ................... .............. ...................15
2.1.8 Collision Detection Function...................................................................16
2.1.9 Lin k Pulse Transmission ........................................................................17
2.1.10 Lin k In tegrity Test Function....................................................................17
3.0 Application Information.................................................................................................19
3.1 External Components..... ....... ..... ....... ....... ....... ..... ....... ....... ..... ....... ....... ....... ..... ..19
3.1.1 Cryst a l In formati o n.................................. ............................ ...................19
3.1.2 Magnetic Information............................... ....... ....... ............ ....... ....... .......19
3.2 Layout Requirement s . ............................... ................................. .........................19
3.2.1 Auto Port Select wit h External Loopback Control....... ....... ....... ....... .......19
3.2.2 Full Duplex Support.... .................. ............................... ...........................21
3.2.3 Dual Network Support-10Bas e T and Toke n Ring . . ............. ..................22
3.2.4 Manual Port Select & Link Test Function . ............................ ..................23
3.2.5 Thr ee Med ia Ap p li c a tion.. ........................ ............................ ...................25
3.2.6 AUI Encoder/Dec oder Only... .......................... ..................... ..................26
4.0 Test Specificati ons.........................................................................................................27
4.1 Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figures 16 - 21.......31
4.2 Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figures 22 - 27......33
4.3 Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figures 28 - 33......35
4.4 Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figures 34 - 39 .....37
4.5 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figures 40 - 45 .....39
5.0 Packag e Speci fications .................................................................................................41
5.1 Top-Label Mark ing ................. ................... ........................ ..................... .............43
6.0 Product Orderi ng I nformation.......................................................................................45
Contents
4 D atashee t
Document #: 249049
Revis ion #: 003
Rev. Date: 29-Oct-2005
Figures 1 Block Diagram.......................................................................................................7
2 Pin Assi g n me n ts ............... ............................. ............................ ...........................8
3 TPO Output W avefo rm .......................................................................................13
4 Jabber Control Function. ................ ..................... ........................... .....................14
5 SQE Function ..... ..... ....................... ............................. ....................... ................15
6 Collision Detection Function ...............................................................................17
7 Transmitted Link Integ rity Pulse Timing .............................................................17
8 Link Integrity Test Fun ction ................................................................................18
9 LA N Adapter Board - Auto Port S elect with External Loopback Control ............20
10 Full-Duplex Operation ........................................................................................21
11 Intel® LXT90 8 Transc eiver/380C26 Interface for Dual Network
Support of 10BASE-T and Token Ring 22
12 LA N Adapter Board - Manual Port Select wit h Link Test Function ................... ..23
13 Man ual Port Select with Seeq 8005 Controller .............. ...................... ........... ...24
14 Three Media Application ....................................................................................25
15 AU I Enc oder /Decoder Onl y Ap pl i c a ti o n ... ..... ....................... ............................. .26
16 Mo de 1 RCLK/St a r t-o f-Fr ame Timin g . .............. ............................. ....................31
17 Mo de 1 RCLK/End -o f-Fram e Timin g ........................ .................................. ........31
18 Mo de 1 Transm it T iming .......................................... ............................. .............32
19 Mo de 1 Colli sion Detect Timin g ... ...................................... ................................32
20 Mo de 1 COL/SQ E Outp u t Timing/CI Out p ut Ti mi ng ... ....................... ................32
21 Mo de 1 Loopba ck Ti mi n g .... ............................ ............................ .......................32
22 Mo de 2 RCLK/St a r t-o f-Fr ame Timin g . .............. ............................. ....................33
23 Mo de 2 RCLK/End -o f-Fram e Timin g ........................ .................................. ........33
24 Mo de 2 Transm it T iming .......................................... ............................. .............34
25 Mo de 2 Colli sion Detect Timin g ... ...................................... ................................34
26 Mo de 2 COL/SQ E Outp u t Ti mi n g .................................. ............................. ........34
27 Mo de 2 Loopba ck Ti mi n g .... ............................ ............................ .......................34
28 Mo de 3 RCLK/St a r t-o f-Fr ame Timin g . .............. ............................. ....................35
29 Mo de 3 RCLK/End -o f-Fram e Timin g ........................ .................................. ........35
30 Mo de 3 Transm it T iming .......................................... ............................. .............36
31 Mo de 3 Colli sion Detect Timin g ... ...................................... ................................36
32 Mo de 3 COL/SQ E Outp u t Ti mi n g .................................. ............................. ........36
33 Mo de 3 Loopba ck Ti mi n g .... ............................ ............................ .......................36
34 Mo de 4 RCLK/St a r t-o f-Fr ame Timin g . .............. ............................. ....................37
35 Mo de 4 RCLK/End -o f-Fram e Timin g ........................ .................................. ........37
36 Mo de 4 Transm it T iming .......................................... ............................. .............38
37 Mo de 4 Colli sion Detect Timin g ... ...................................... ................................38
38 Mo de 4 COL/SQ E Outp u t Ti mi n g .................................. ............................. ........38
39 Mo de 4 Loopba ck Ti mi n g .... ............................ ............................ .......................38
40 Mo de 5 RCLK/St a r t-o f-Fr ame Timin g . .............. ............................. ....................39
41 Mo de 5 RCLK/End -o f-Fram e Timin g ........................ .................................. ........39
42 Mo de 5 Transm it T iming .......................................... ............................. .............40
43 Mo de 5 Colli sion Detect Timin g ... ...................................... ................................40
44 Mode 5 COL/S QE Out put Timing . ............................................... ......................40
45 Mo de 5 Loopba ck Ti mi n g .... ................................. ............................ ..................40
46 44-P in PLCC Package Spec ifications ......... ...................................... .................41
47 64-Pin LQF P Package Specification s ................................................................42
48 Sam ple LQFP Package - Intel® LXT908 Tra n sce i v e r.... ................... ..................43
Datasheet 5
Document #: 249049
Re vision #: 0 03
Rev. Date: 29-Oct-2005
Contents
49 S ample Pb-Free (RoHS-Comp liant) LQFP Package -
Intel® LXT908 Transceiver.......................................... .............. ................... .......43
50 S ample PLCC Package - Intel® LXT908 Transceiver.........................................44
51 S ample Pb-Free (RoHS-Comp liant) PLCC Package -
Intel® LXT908 Transceiver.......................................... .............. ................... .......44
52 Orde ring Inform ation - Sample............................................................................46
Tables 1 Signal Descriptions.............. ....... ....... ....... ....... ....... ............ ....... ....... .......... ....... ....9
2 Cont rolle r Compatibility Mode Options......................... . .................... ..................13
3 Suitable Crystals ................................................................................................19
4 Absolute Maximum Values..................................................................................27
5 Rec om m ended Operating Conditions. .................... ...................................... ......27
6 I/O Electrical Characteristics..............................................................................27
7 AUI Electri cal C haracteristics..............................................................................28
8 Twisted-Pair Electrical Characteristics................................................................28
9 Switch ing Characteristics....................................................................................29
10 RCLK/Start-o f-Frame Timi ng...............................................................................29
11 RCLK/En d-of-Frame Timing................................................................................30
12 Tra ns mit Timing.. ................... ............................. ....................... ..........................30
13 Coll ision, COL/CI Output and Loopback Timing.................. ............................... .30
14 P roduct Information..... .................. .......................... .......................... ..................45
Contents
6 D atashee t
Document #: 249049
Revis ion #: 003
Rev. Date: 29-Oct-2005
Revision History
Date Revision Page Description
29-Oct-2005 003
43
Added Section 5.1, “Top-Label Marking”:
Table 48 “Sample LQFP Packag e - Inte l® LXT908 T ransceiver ”
and Table 49 “Sample Pb-Free (RoHS-Compliant) LQFP
Package - Intel® LXT908 Transceiver” unde r
45 Modified Table 14 “Product Information” for RoHS information.
46 Modified Figure 52 “Ordering I nformation - Sampl e” .
J une 20 01 2001
1 Added new set of applications
19 Added 01. μF label to capacitor at bottom of Figure 9
20 Added 01. μF label to capacitor at bottom of Figure 10
21 Added 01. μF label to capacitor at bottom of Figure 11
22 Added 01. μF label to capacitor at bottom of Figure 12
23 Added 01. μF label to capacitor at bottom of Figure 13
26 Added second para. under “Test Specifications” regarding
Quality and Reliability issues
26 Removed “Ambient ope rating temp erature” from Absolute
Max imum Ratings table.
43 Added Appendix: Product Ordering Information
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 7
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
Figure 1. Bl ock Diagra m
MODE SELECT LOGIC Cont r olle r
Compatibility/
Port Select /
Loopback /
Link test
SQUELCH / LI NK
DETECT
MANCHESTER
DECODER
COLLISION LOGIC
WATCHDOG
TIMER
XTAL
OSC MANCHESTER
ENCODER
Select:
PL S Only
or
PLS / M AU
DO
A
UTOSEL
PAUI
LBK
LI
TCLK
CLKO
CLKI
TEN
TXD
CD
LEDL
MD0
TPOP
A
TPON
A
TPON
B
TPIP
TPIN
PULSE SHAPER
AND FILTER
TWISTED PAIR
INTERFACE
COLLISION/
POLARITY
DETECT
CORRECT
RC
RC
DI
LPBK
COLLISION
RECEIVER
RXD
RCLK
COL
CI
MD1
TPOP
B
DOP
DON
DIP
DIN
CIP
CIN
LEDR LEDT/PDN LEDC/FDE NTH JAB PLR
+
-
DROP CABLE
INTERFACE
ECL
TX
AMP
RX SLICER
RX
SLICER
CMOS
TX
AMP
DSQE
MD2
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
8Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
1.0 Pin Assignments an d Signal Descriptions
Figu re 2. Pin Ass i gn m e nts
7
8
9
10
11
12
13
14
15
16
17
n/c
LI
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
TPIN
TPIP
DSQE
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
n/c
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
LEDR
LEDT/PDN
LEDL
LEDC/FDE
LBK
GND1
RBIAS
MD2
RXD
CD
RCLK
MD1
MD0
NTH
CIN
CIP
VCC1
DON
DOP
DIN
DIP
PAUI
6
5
4
3
2
1
44
43
42
41
40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
CIN
NTH
MD0
MD1
n/c
n/c
n/c
TPIN
TPIP
n/c
DSQE
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
n/c
n/c
n/c
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
n/c
n/c
LI
n/c
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
n/c
n/c
n/c
n/c
RCLK
CD
RXD
MD2
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
LXT908PC/PE XX
XXXXXXXX
Part #
FPO #
Rev #
LXT908LC /LE XX
XXXXXXXX
Part #
FPO #
Rev #
BSMC
BSMC
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 9
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
Table 1. Signal Descriptions (Sheet 1 of 3)
Pin# Symbol I/O Description
PLCC LQFP
1
34 10
56 VCC1
VCC2 –
–Power 1 and 2. Connect to p ositive power supply terminal ( +3.3V
DC).
– 9 VCCA – Analog Supply. (+3.3V)
2
311
12 CIP
CIN I
IAUI Colli sion Pair. Differential input pair connected to the AUI
transceiver CI circuit. The input is collision signaling or SQE.
413NTHI
Normal Threshold. When NTH is High, the normal TP squelch
threshold is in effect. When NTH is Low, the normal TP squelch
threshold is r educed by 4.5 dB.
5
6
25
14
15
44
MD0
MD1
MD2
I
I
I
Mode Select 0 (MD0), Mode Select 1 (MD1) and Mode Select 2
(MD2). Mode s elect pins determine the controller comp atibility
mode as specified in Table 2 on page 13 .
7, 29
1, 2, 6,
16, 17 ,
18, 20 ,
30, 31 ,
32, 33 ,
41, 43,
48, 49,
50, 51,
60, 63,
64
N/C – No Connect. These pins may be left unconnected or tied to ground.
819 LI I
Link Tes t Enabl e. Controls Link Integrity Test; enabled when High,
disabled when Low.
921JABOJabber Indicator. Output goes High to indicate Jabber st ate.
10 22 TEST I Test. This pin must be tied High.
11 23 TCLK O
Transmit Clock. A 10 MHz clock output. This clock signal should
be directly connected to the transmit clock input of the controller.
TCLK goes to high impedance (tr i-state) when LEDT/PDN is pulled
Low externally.
12 24 TXD I Transmit Dat a. Input signal containing NRZ data to be transmitted
on the network. TXD is connected directly to the transmit data
output of the controller.
13 25 TEN I Transmit Enabl e. Enables data transmission and starts the Watch-
Dog T imer. Synchronous to TCLK (see Test S pecifications for
details).
14
15 26
27 CLKO
CLKI O
ICrystal Oscillator. A 20 MH z crystal must be connected acr oss
these pins, or a 20 MHz clock applied at CLKI, with CLKO left open.
16 28 COL O Collision Detect. Output driving the collision detect input of the
controller. C OL goes to high impedance (tri-state) when LEDT/PDN
is pulled Lo w exter nal ly.
17 29 AUTOSEL I
Automatic Port Select . When High, automatic port selection is
enabled (the Intel® LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver defaults to the AUI port only if TP link
integrity = Fail). When Low, manual port selection is enabled (the
PAUI pin deter mine s the active port) .
18 34 LEDR O
Receive LED. Ope n drain dri v er for the receive indicator LED .
Output is pulled Low during receive, except when data is being
looped back to DIN/DIP from a remote transceiver (external MAU).
LED “On” time (Low output) is extended by approximately 100 ms.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
10 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
19 35 LEDT/
PDN O
I
Transm it LED ( LEDT )/Po w er Dow n (P DN). Ope n drain driver f or
the transmit indicator LED. Output is pulled Low during transmit. Do
not allow this pin to float. If unused, tie High. LED “On” time
(L ow ou tp ut ) is ex t end ed by appr o xi matel y 10 0 ms. If ex te rna ll y ti ed
Low, the Intel® LXT90 8 Univer sal 3.3 V 10BASE-T and AUI
Transceiver goes to power-down state. In power-down state, TCLK,
COL, RXD, CD, and RC LK (pins 11, 16, 26, 27, and 28,
respect ively) are tri-stat ed.
20 36 LEDL O
I
Link LED. Ope n drain driver for link integri ty indicator LE D. Output
is pulled Low during link test pass. If externally tied Intel® LXT908
Universal 3.3 V 10BASE-T and AUI T ransceiv er Low, internal
circuitry is forced to “Link Pass” state and the Intel® LXT908
Universal 3.3 V 10BASE-T and AUI Transceiver will continue to
tran s mi t link test pu ls es .
21 37 LEDC/
FDE O
I
Collision LED (LEDC)/F u ll Duplex Enable (FDE). Open drain
driver for the collision indicator LED pulls Low during collision. LED
“On” time (Low output) is extended by approximately 100 ms. If
externally tied Low, the Intel® LXT908 Universal 3.3 V 10BASE-T
and AUI Transceiver disables the internal TP loopback and collision
detection circuits to allow full-duplex operation or external twisted-
pair loopback.
22 38 LBK I Loopback. Enables internal loopback mode. Refer to Functional
Description and Test Specifications for details.
23
33 39
55 GND1
GND2 –
–Ground Returns 1 an d 2. Connect to negative power supply
terminal (ground).
– 40 GN DA – Ana lo g Gr ound . Gro un d for an al og plane.
24 42 RBIAS I Bia s Control. A 12.4 kΩ 1% resistor to ground at this pin controls
oper a ting ci rc uit bias .
26 45 RXD O Receive Data. Output signal connected directly to the receive data
input of the controller. RXD goes to high impedance (tri-state) when
LEDT/PDN is pulled Low externally.
27 46 CD O Carrier Dete ct. An output to notify the controller of activity on the
network. CD goes to high impedance (tri-state) when LEDT/PDN is
pulled Lo w ext er n al ly.
28 47 RCLK O
Receive Clock. A recovered 10 MHz clock that i s synchronous to
the received data and connected to the controller receive clock
input. RCLK goes to high impedance (tri -state) when LE DT/PD N is
pulled Lo w ext er n al ly.
30 52 PLR O Polarity Reverse. Outp ut goes High to ind icate reversed polarity at
the TP input.
32
35
31
36
54
57
53
58
TPOPA
TPONA
TPOPB
TPONB
O
O
O
O
Twisted-Pair Trans mit Pairs A & B. T wo differential driver pair
outputs (A and B) to the tw isted-pair cable. The outputs are pre-
equalized. Each pair must be shorted together with an 11.5 Ω 1%
resistor to match an impedance of 100Ω.
37 59 DSQE I Disable SQE. When DSQE is High, the SQE function is disabled.
When DSQ E is Low, the SQE function is enabled. SQE must be
disabled for normal oper ation in Hub/S witch applications.
3839 61
62 TPIP
TPIN I
I
Twisted-Pair Receive Pair. A differential input pair from the TP
cable. Receive filter is integrated on chip. No external filters are
required.
Table 1. Signal Descriptions (Sheet 2 of 3)
Pin# Symbol I/O Description
PLCC LQFP
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 11
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
40 3 PAUI I
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low),
PAUI selects the active port. When PAUI is High, the AUI port is
selected. When PAUI is Low , the TP port is selected. In Auto Port
Select mode, PAUI must be tied to ground.
41
42 4
5DIP
DIN I
IAUI Receive Pair. Differential input pair from the AUI transceiver DI
circuit. The input is Manchester encoded .
43
44 7
8DOP
DON O
OAUI Transmit Pair. A differ ential output driver pair for the AUI
transceiver cable. The outpu t is Manchester en coded.
Table 1. Signal Descriptions (Sheet 3 of 3)
Pin# Symbol I/O Description
PLCC LQFP
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
12 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
2.0 Functional Description
2.1 Introduction
The LXT90 8 Universal 10BASE-T and AUI T r ansceiv er performs the physical layer signa ling
( PLS) and Media Attachment Unit (MAU) functions as defined b y the IEEE 80 2.3 specification. It
f unctions as an AUI (PLS-Only device ) for use with 10BASE-2 or 10BASE-5 coa xial cable
networks, or as an Integrate d P LS/MAU for use with 1 0BAS E-T twisted-p air (TP ) networks. In
addition to standard 10 Mbps operation, the Intel® LXT908 Universal 3. 3 V 10BASE-T an d AUI
Transceiver also supports full-duplex 20 Mbps operation.
The I nte l® LXT908 Universa l 3.3 V 10BASE-T and AUI Transceiver interfaces a back-end
controller to either an AUI drop cable or a twist ed-pair cable. The controller i nterface incl udes
t r ansm it and receiv e cloc k an d NRZ d ata cha n n els, as well as mode control l o g ic and s ignaling.
The AUI interf ac e comprises t hree circu its: Data Output (DO), Data Input (DI), a nd Collisi on (CI).
The twisted-pair interfac e comprises two circuits: Twisted-Pair Input (T P I) and Twi s ted-Pair
Output (TPO). In ad dition to the three basic interfaces, the Intel® LXT908 Universal 3.3 V
10BAS E-T and AUI Trans ceiver contains an internal crystal oscillator and four LED drivers for
visua l status reporting.
Fun ctions are defined fro m the back end controller si de of the interface. The Intel® LXT908
Universal 3.3 V 10BASE-T and AUI Transceiver Tra nsmit function refers to data transm itted by
the ba ck e nd to the AUI cable (PLS-Only mode) or to the twisted-pair network (Integrated PLS/
MAU mode). The Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Tr ansceiver Receive
f unction refers to data received by the bac k end from the AUI cable (PLS-Only) or from the
twisted-pair network (Inte grated PLS/MAU mode). In the integrated PLS/MAU mode, the Intel®
LXT908 Universal 3.3 V 10BASE-T and AUI Transceive r performs all required MAU functions
defined by the IEEE 802.3 10BASE –T specific ation, such as col lision detection, link integrity
tes ting, signal qualit y error mes saging, jabber contro l, a nd loopback. In the PLS-Only mode, the
Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceive r rec eives incoming signals from
the AUI DI circuit w ith
±18 ns of jitter an d dr ives the AUI DO ci rcuit.
2.1.1 Controller Compatibility Modes
The I nte l® LXT908 Universal 3.3 V 10BASE-T and AUI Tr ansceive r is compatible with most
industry-standard controllers including devices produced by Advanced Micro Devices (AMD),
Motorola, Inte l, Fujitsu, National Semic onductor, Seeq, and Texas Ins trum ents, as well as custom
controllers. Five different control signa l tim ing and polarity schemes (Modes 1 through 5) are
re quired to achieve this compatibility. Mode select pins (MD2:0) determ ine Controller
compatibility modes as listed in Table 2 on page 13. Refer to Test Specifications for a complete set
of timing diagrams for each mode.
2.1 .2 Transmi t Fu nction
The I nte l® LXT908 Universal 3.3 V 10BASE-T and AUI Transceive r receives NRZ data from the
controller at the TXD input as shown in Fi gure 1, “Blo c k Dia g r a m” on page 7 , an d p as s es it
through a M anchester encoder. The encoded data is then transferred to either the AUI cable (the
DO circuit) or the twis ted-pair netw ork (the TPO circuit). The advanc ed integrated pulse shaping
and fil ter ing network produc es the output si gnal on TPON and TPOP, shown in Figure 3. T h e TPO
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 13
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
output is pre-dist orted and pre-filtered to meet the 10BASE -T jitter template. An internal
continuous resistor-c apacitor filter is used to remov e any high-frequency cloc king noise from the
pulse shaping circu itry. Integrated filters simplify the design work required for FCC-compliant
EMI perfor mance . During idle periods , the Intel® LXT908 Unive r s al 3.3 V 10BAS E-T and AUI
Transce iver transmi ts link integrit y test pulses on the TPO circ uit (if LI is enabl ed a nd integrated
PLS/ MAU mode is selected) . External resis t ors control the termination impe dance.
2.1.3 Jabber Control Function
Fig ure 4 on page 14 is a state diagram of the I ntel® LXT908 Universal 3. 3 V 10BASE-T and AUI
Transceiver Jabber control function. The Intel® LXT908 Univers al 3.3 V 10BASE-T and AUI
Transce iver on-chip Watch-Dog T im er pre vents the DTE from locking into a continuous trans mi t
mode. When a transmission exceeds the time limit, the Watch-Dog Time r dis ables the t r ansmit and
loopback functions, and activates the JAB pin. Once the I ntel® LXT908 Universal 3.3 V 10BASE-
T and AUI Transcei ver is in the jabber stat e, the TXD circuit mu st remain idle for a period o f 0.25
to 0.75 seconds before it will exit the jabber state.
Figure 3. TPO Output Waveform
Ta ble 2. Controller Compatibility Mode Options
Controller Mode MD2 MD1 MD0
Mode 1 - For AMD AM7990, Motorola 68EN360, MPC860 or compatible
controllers Low Low Low
Mode 2 - For Intel 82596 or compatible controllers Low Low High
M ode 3 - For Fujitsu MB869 50, MB86960 or compat ible controllers (S eeq
8005)1Low High Low
Mode 4 - For National Semiconductor 8390 or compatible controllers (TI
TMS380C26) Low High High
Mode 5 - For custom controllers (Mode 3 with TCLK, RCLK and COL
inverted) High High Low
1. SEEQ controllers require inverters on CLKI, LBK, RCLK, and COL in Mode 3; or on CLKI, LBK, and TCLK
in Mode 5.
4V
2V
0V
-2V
-4V
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
14 Datasheet
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Revision #: 003
Rev. Date: 29-Oct- 2005
2. 1.4 Re ceive Fu nct ion
The I nte l® LXT908 Universal 3.3 V 10BASE-T and AUI Transceive r receive functi on acquires
tim ing a nd data from the twiste d-pair network (TPI circ uit) or from the AUI (DI circuit). Valid
re ceive d signals a re passed through the on-chip filters and Manc hester decode r then output as
decoded NRZ data and recovered clock on the RXD and RCLK pins , re spectively.
An internal RC filt er and an intelligent squ elch function discrimina te noise from li nk tes t pulses
and valid data streams. The receive function is activated only by valid data streams a bove the
squelch level and with proper timing. If the differential si gnal at the TPI or the DI circuit inputs
f alls below 75 percent of the threshold level (unsquelched) for 8 bit times (typi ca l), the
Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver receive functi on enters the idle
state. If the p o larity of the TPI circuit is reve r sed, I n tel® LXT908 Universal 3.3 V 10BASE-T and
AUI Transceiver detects the polarity rev ers e and reports it via the PLR output. The Intel® LXT908
Universal 3.3 V 10BASE-T and AUI T r ansceiv er automatically corrects r eve rsed polarity.
2.1.5 SQE Function
I n the integr ated PLS/MAU mode, the Intel® LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver suppor ts t he signal quality error (SQE) functi on as shown i n Figure 5 on page 15,
although the SQE function can be disabled. Aft er e very s uccessful transmission on the 10B ASE-T
Figure 4. Jabber Control Function
No Output
Nonjabber Out put
Start_XMIT_MAX_Timer
Power On
DO=Active
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Active ∗
XMIT_Max_Timer_Done
DO=Idle
DO=Idle
Unjab_ Timer_Done DO=Active ∗
Unjab_Timer_Not_Done
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 15
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
network when SQE is enabled, the Intel® L XT908 Uni versal 3.3 V 10BASE-T and AUI
Transceiver trans mi ts t he SQE signal for 10BT ± 5BT over the internal CI circuit, wh ich is
indicated on th e COL pi n of the device. SQE must be dis abled for normal operation in hub and
switch applications . In twis ted-pair a pplicat ions, the SQE function is disabled when DSQE is set
High, and enabled when DSQE is Low. When using the 10BAS E-2 port of the Intel® LXT908
Univers al 3.3 V 10BASE-T and AUI T ransceive r, the SQE function is determined by the exte rnal
MA U at ta ch ed .
2.1.6 Polarity Reverse Function
The Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transcei ver polarity reverse function
use s both link pu lses an d end-of-fra me data t o deter mine polar ity of the rec eived signal. A reversed
polarity condition is detected when eight opposite receive link pulses are detected without receipt
of a link pulse of the expecte d polarity. Reversed pola r ity is also de tected if four frames are
received with a reversed start-of-idle. Whenever a correct polarity frame or a correct link pulse is
received, these two counters are reset to ze ro. If the Intel® LXT908 Universal 3.3 V 10BASE-T
and AUI T r ansce iver ent ers the l ink f ai l state and no val id dat a or link p ulse s are r eceived wi thi n 96
to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is
disabled, polarity detection is base d only on received data. Polarity correction is always e nabled.
2.1.7 Loopback Function
The Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transcei ver provides the normal
loopback functi on specified by the 10BASE-T standard for the twisted-pair port . Th e loopback
function operates in conjunction with the tr ans m it function. Data t r ansmitte d by the ba ck-end is
internally looped back within the
Figure 5. SQE Function
Output Idle
Output Det ected
Power On
DO=Active
SQE Wait Test
Start_SQE_Test__Wait_Timer
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test__Wait_Timer_Done ∗
XMIT=Enable
DO=Idle
SQE_Test_Timer_Done
XMIT=Disable
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
16 Datasheet
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Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver from the TXD pin through the
Manc hester e nco der/decode r to the RXD pi n and ret urned t o the back-end. This “norm al” l oopback
f unction is di sabled whe n a data col lisi on oc curs, c leari ng th e RXD circui t for the TPI data. Normal
loopback is also disabled during link fail and jabber states.
The I nte l® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver also provides three
additional loopback functions. An external loopba ck m ode, useful for system-level testing, is
controlled by pi n 21 (LED C). When LEDC is tied Low, the Intel® LXT908 Universal 3.3 V
10BASE-T and AUI Transceiver di sables the collisio n dete ction and int ernal loopba ck ci rcuits, to
allow external loo pback or full-duplex operation.
“Norma l” twisted-pair loopback is controlled by pin 22 (LBK). When the twisted-pair port is
se lected and LBK is High, t w isted-pair loopback is “forced”, o verriding collisions on the twisted-
pair circuit. When LBK is Low, normal loopback is in effe ct.
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-en d is internally l ooped back from the TXD pin through the
Manchester encoder/decoder to t he RXD pin. Whe n LBK is Low, no AUI loopback occurs.
2.1.8 Collision Detection Function
The c o llision detect ion function operates on the twisted-pair sid e of the interface. Fo r standard
(ha lf-duplex) 10BASE-T operation, a collision is defined as the simultaneous presenc e of valid
signals on both the TPI ci r cuit and the TPO circu it. The Intel® LXT908 Univers al 3.3 V 10BASE-
T and AUI Transcei ver reports coll isions to the back-end via the COL pin. If the TPI circuit
becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end
over the RXD circuit, disabl ing normal lo opba ck. Figure 6 is a state di agram of the Inte l ® LXT 908
Universal 3.3 V 10BASE-T and AUI T ransceiver collis ion detection function. Refer t o Test
Spe cifications for collis ion detection and COL/ CI output ti ming.
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 17
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
Note: For full-duplex op eration, the co llision detection circuitry must be disabled.
2.1.9 Link Pulse Transmission
The Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver transmits standard l ink
pulses which meet th e 10BASE-T specifi cations. Figure 7 shows the link integri ty pulse timi ng.
2.1.10 Link Integrity Test Function
Fig ure 8 on page 18 is a state diagram of the I ntel® LXT908 Universal 3. 3 V 10BASE-T and AUI
T ra nsceive r Link Inte grity te st func ti on. The link int eg rity tes t is use d to determin e the st atus o f the
rece ive side t wiste d-pair ca ble. Link inte grity te stin g is enab led when pi n 8 (LI) is ti ed High. When
enabled, the receiver recognizes link integrity puls es which are tra nsmitted in th e absence of
receive traffic.
Fig ure 6. C ol l isi on De te c tion Func ti on
Idle
Power On
Collision
TPO=DO
DI=TPI
CI=SQE
Output
TPO=DO
DI=DO
Input
DI=TPI
DO=Active ∗
TPI=Idle ∗
XMIT=Enable
DO=Active ∗
TPI=Active ∗
XMIT=Enable
DO=Active ∗
TPI=Active ∗
XMIT=Enable
DO=Active ∗
TPI=Idle
DO=Idle +
XMIT=Disable
DO=Idle
TPI=Idle
TPI=Active
AA
A
Figure 7. Tran smi tted Link Integrity Pu lse Timing
10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
18 Datasheet
Document #: 249049
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I f no ser ial data stream or link integrit y pulses are detec ted within 50 - 150 ms, th e chi p enters a
link fail state and disables the transmit and normal loopback functions. The Intel® LXT908
Universal 3.3 V 10BAS E-T and AUI Transceiver ignore s any li nk integrity pul se with interval less
than 2 - 7 ms. The Intel® LXT90 8 Universal 3.3 V 10BASE-T and AUI T ransceiver will remain in
the link fail sta te until it detects eithe r a serial data packet or two or more link integrity pulses.
Figu re 8. Link In t egri t y Te st Fu nc ti on
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Power On
Link Test Fail Reset
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Loss_Timer_Done
∗ TPI=Idle
∗ Link_Test_Rcvd=False
TP I= A c ti ve +
(Link_Test_Rcvd=True
∗ Link_Test_Min_Timer_Done)
Link Test Fail Wait
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Test_Rcvd=False
∗ TPI=Idle
TPI=Active
TPI=Active Link_Test_Rcvd=Idle
∗ TPI=Idle
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max Link_Test_Min_Timer_Done
∗ Link_Test_Rcvd=True
(TPI=Idle ∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
∗ Link_Test_Rcvd=True)
TPI=Idle ∗
DO=Idle
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 19
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
3.0 Applicati on Information
Fig ure 9 on page 20 through F igure 15 on page 26 sho w typical Inte l® LXT908 Universal 3.3 V
10BASE-T and AUI Transceiver applications.
3.1 Ex ternal Components
3.1.1 Crystal Information
Sui table c rysta ls a re avai lable from various manufact urers. Table 3 li sts su itabl e cr ystal s base d on a
limited evalua tion. Designers should test and vali date all cryst als before using them in production.
3.1. 2 Magn etic Inf ormat ion
The twisted-pair interface requi res a 1:1 ratio for the receive transformer, and a 1:2 ratio f or the
transm it transformer. The AUI interface requires a 1:1 rat io for data-in, data-out, and c ollision-pair
tra nsform ers. A cross-reference list of suitable magnetic s a nd part numbers is available in
Applic ation Note 73, Magnet ic Manu facture rs (24 8991-0 01), tha t can be found on t he I ntel we bsite
(www.inte l.com). Designe rs should test and validate all magnetics before committin g to a specific
component.
3.2 Layout Requirements
3.2.1 Auto Port Select with External Loopback Control
Fig ure 9 on page 20 is a typical Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver
application. The diagram groups similar pins together, but does not represent the actual Intel®
LXT908 Universal 3.3 V 10BASE-T and AUI T r ansceive r pin-out. The controller interface pi ns
(TXD, RXD, TEN, TCLK, RCLK, CD, COL, and L BK) are shown at the top left of the dia gram.
Programmable option pins are grouped at the center left of the diagram . T he PAUI pin is tied Low
and all other option pins are tied High. This s etup select s t he following opti ons:
•Automatic Port Selection
(PAUI Low and AUTOSEL High)
•Normal Receive Threshold (NTH High)
•Mode 4, co mpatible with Nat ional NS8390 controllers (MD2:0 = Low, High, Hi gh)
•SQE Disabled (DSQE Hi gh)
•Link Testing Enabled (LI High)
Tabl e 3. Su itable Crystals
Manufacturer Part Number
MTRON MP-1
MP-2
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
20 Datasheet
Document #: 249049
Revision #: 003
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S tatus outputs are grouped at the lowe r left of the diagram. L ine status outputs drive LED
i n d ica to r s and t h e Jabb er an d Polarity status ind ica to rs are available, as required .
Power and ground pins are sh own at the bottom of the diagram. A single-power suppl y is used for
both VCC1 and VCC2, with a decoupling capacitor installed betwee n the power and ground
busses.
An additional power and ground pin (VCCA and GNDA) is supported in designs using t he 64-pin
LQFP pac kage. A single- power suppl y is used for all three power and ground pins (VCC1, VCC2,
VCCA) and (GND1, GND2, GNDA). Please install a decoupling capacitor between each power
and ground buss.
The twisted-pair and AUI interfaces are shown at the upper and lower right of the diagram,
r espective ly. Impedance matching resist ors for 1 00 UTP are i nstalled in each I/O pa ir, but no
external filters are required.
Figure 9. LAN Adapter Boar d - Auto P o rt Select with External Loopb ack Control
LXT908
20 MHz
20 pF 20 pF
CLKI
TXD TPIN
100 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD2
MD1
DSQE
LI
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
NS8390 BACK-END
CONTROLLER
INTERFACE
LOOPBACK
ENABLE
PROGRAMMING
OPTIONS
MODE SE LE CT
LINE STATUS
1 %
+3.3V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330330
1 : 2
TEST
TPONA
TPONB
TPOPA
TPOPB
11.5 Ω 1%
11.5 Ω 1%
MD0
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
1
1
220pF
0.1 μF
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 21
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
3.2.2 Full Duplex Support
Figure 10 shows th e Intel® LXT908 Univ ersa l 3.3 V 10BAS E-T and AUI T rans ceiver wit h a Texas
Instruments 380C24 CommPr ocessor. Th e 380C24 is compatible with Mode 4 (MD2:0 = Low,
High, High). When used with the 380C24 or other full- duplex-capable controllers, the Intel®
LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver supports full-duplex Ethernet,
effectively doubli ng the available bandwidth of the ne twork. In this application, the SQE function
is enabled (DSQE tied Low), and the In tel® LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver AUI port is no t us ed.
Figure 10. F ull-Duplex Operation
3
LXT908
CLKI
TXD TPIN
100 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
RJ45
3
6
8
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
12.4 k Ω
TCLK
RCLK
RXD
CD
COL
LBK
LEDC/FDE
TXD
TXEN
TXC
RXC
RXD
CSN
COLL
LPBK
1 %
+3.3 V VCC1
VCC2
CLKO
TMS380C24
1 : 2
To 10 BASE-T TWISTED-
PA IR NE TWORK
20 M Hz 20 pF20 pF
*TEST0 1N914
10 KΩ
AUTOSEL
NTH
LI
MD2
MD1
MD0
JAB
PLR
Green Red Red
PROGRAMMING
OPTIONS
MODE
SELECT
LI NE STATUS
LEDR
LEDT/PDN
LEDL
330 330
OUTSEL0
PAUI
330
1
4.7 KΩ
TEST
DSQE
*Open Coll ect or
Driver
TPONA
TPONB
TPOPA
TPOPB
11.5 Ω 1%
11.5 Ω 1%
PAUI
1Half/Full Duplex Sel ectio n controlled by TMS380C24 Pin
s
Test0 and OUTSEL0.
Bias resi stor RBIAS should be locate d close to the pin
and isolated fr om other signals.
2
3The TMS380C26 m ay be substituted for dual network
support of 10B ASE -T and Token Ring.
2
220pF
0.1 μF
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
22 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
3.2.3 Dual Network Support-10Base T and Token Ring
Fi gure 11 shows the Intel® L XT908 Univer sal 3.3 V 10BAS E-T and AUI T rans ceiver with a Texas
I nstruments 380C26 CommProcessor. The 380 C26 is compatible with Mode 4 (MD2:0 = Low,
High, High).
When us ed with the 380C26, both the Intel® LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver a nd a TMS38054 Token Ring transceive r can be tied to a single RJ-45, allowing dual
net work support from a s ingle connec tor. The Intel® LXT 908 Univers al 3.3 V 10BASE -T and AUI
Transceiver AUI port is not used.
Figu re 11. Inte l ® LXT908 Transceiver/380C26 Interface for Dual Network Support of 10BASE-T
and Token Ring
LXT908
20 M Hz
20 pF 20 pF
CLKI
TXD TPIN
100 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
18 pF
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
From TI TMS380 54 Token
Ri ng Transceiver
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
1
12.4 k Ω
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
DSQE
LI
MD2
MD1
MD0
JAB
PLR
TXD
TXE
TXC
RXC
RXD
CRS
COL
LBK
Green Red Red Red
PROGRAMMING
OPTIONS
MO DE SELEC T
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330330
380C26 2
To TI TMS38054 Token Ring
Transceiver
1 : 2
To 10 BASE-T TWISTED-
PA IR NE TWORK
Bias resistor RBIAS should be locat ed close to the pin
and isolated fr om oth er signals.
1
2Additional magneti cs and swit ching logic ( not shown)
is required to implement the dual network sol ution.
TEST
11.5 Ω 1%
11.5 Ω 1%
220pF
0.1 μF
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 23
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
3.2.4 Manual Port Select & Link Test Function
When MD2:0 = L ow, High, Low, the Intel® LXT908 Universal 3.3 V 10BASE-T and AUI
Transceiver logi c an d fr am ing are set to Mode 3 (compatible with F ujitsu MB86950 and
MB86960, and Seeq 8005 controllers) . Figure 12 shows the setup for Fujitsu controllers. Fi gure 13
on page 24 shows t he four inverters required to inte rfac e with the Seeq 8005 controller. As in
Fig ure 9 on page 20, both these Mode 3 applications show the LI pin tied High, enabling Link
Testing; and the NTH and DSQE pins are both tied High, sel ec ting the standa rd rec eiver threshold
and dis abling SQE. However, in these applic ations, AUT OSEL is tied L ow, allowing external port
selection thro ugh the PAUI pin.
Figure 12. L AN Adap ter Board - Manual Port Select with Link Test Function
LXT908
20 MHz
20 pF 20 pF
CLKI
TXD TPIN
100 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAIR NETWORK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
1
78 Ω
78 Ω
78 Ω
12.4 kΩ
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
MD2
DSQE
LI
JAB
PLR
TXD
TEN
TCKN
RCKN
RXD
XCD
LBC
Red Red Red
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
PROGRAMMING
OPTIONS
LI NE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
330 330 330
1 : 2
Green
330
Port Selection
TEST
11.5 Ω 1%
11.5 Ω 1%
XCOL
MD1
MD0
MODE
SELECT
Bias resist or RBIAS should be located close to the pin and isolated from other signals.
1
220pF
0.1 μF
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
24 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 13. Manual Port Select with Seeq 8005 Controller
LXT908
CLKI
LBK TPIN
100 Ω
TPIP
1 : 1116
14
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE-T TWISTED-
PAI R N E TW O RK
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
RBIAS
GND2
GND1
CD
D - CONNECTOR to
AUI DRO P CABL E
Chassis
Gnd
Fuse
1
78 Ω
78 Ω
78
12.4 kΩ
RXD
RCLK
COL
TEN
TCLK
TXD
PAUI
AUTOSEL
NTH
DSQE
LI
MD2
JAB
PLR
Red Red Red
PROGRAMMING
OPTIONS
LINE STATUS
1 %
+3.3V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
330 330 330
1 : 2
Green
330
Port Sel ection
CLKO
8005
CLKI
LPBK
CSN
RxD
RxC
COLL
TxEN
TxC
TxD
External
20 MHz
Source Left Open
TEST
11.5 Ω 1%
11.5 Ω 1%
MODE SELE CT MD1
MD0
Bias resistor RBIAS should be located close to t he pin and isolat ed from other signals.1
220pF
0.1 μF
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 25
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
3.2.5 Three Media Application
Figure 14 shows the Intel® LXT908 Universal 3.3 V 10BASE-T and AUI Transcei ver in Mode 2
(comp atible with Intel 82596 contro llers) with additional media options for th e AUI port.
Two trans formers are used t o couple the AUI port to either a D-connector or a BNC connector. (A
DP8392 coax transceive r with PM6044 power supply are required to drive the thin coax network
through the BNC.
Figure 14. T hr ee Med ia Application
LXT908
CLKI
TXD TPIN
100 Ω
TPIP
1 : 1116
14
11.5Ω 1%
11.5Ω 1%
6
5
4
3
2
1
11
9
TPONA
TPONB
TPOPB
TPOPA
RJ45
3
6
8
To 10 BASE -T
TWISTED-
PAIR
NETWORK
1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIP
RBIAS GND2
GND1
TEN
D - CONNECTOR to
AUI DROP CAB LE
(Thick Coax)
Chassis
Gnd
Fuse
1
78 Ω
78 Ω
TCLK
RCLK
RXD
CD
COL
LBK
PAUI
AUTOSEL
NTH
LI
MD2
MD1
MD0
JAB
PLR
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
82566 BACK-END/
CONTROLLER
INTERFACE
PROGRAMMING
OPTIONS
MODE SELECT
LINE STATUS
1 %
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKO
1 : 2
20 M Hz
System
Clock
CLK
LINK TEST
ENABLE
Power Down
Left Open
1
2
4
5
7
89
10
12
13
15
16
78 Ω
1
2
4
5
7
89
10
12
13
15
16
DIN
CD-
CD+
TX-
VEE
TX+
RX-
RX+
VEE
CDS
TXD
RXI
VEE
RR-
RR+
GND
HBE
1N916
0V
BHC to THIN
COAX
NETWORK
1 kΩ 1%
-9V
V+
N/C
V-
5V
5V
EN
GND
GND
12
13
9
1+5 V
2
3
23
1 MΩ
1/2 W
24
TEST
0.1 μF
1.5 kΩ
0.01 μF75μF / 1 kV
PM6044
DP8392
10 k Ω
DSQE
10 k Ω
12.4 kΩ
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
26 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
3.2.6 AUI Encoder/Decoder Only
I n the app lic at ion sh own in Figure 15, the DTE is c onn ected to a coaxia l ne twor k through th e AUI.
AUTOSEL is tied Low and PAUI is tied High, manually selecting the AUI port. The twi sted-pa ir
port i s not use d. W i th MD2: 0 all t ied L ow, th e Intel ® LXT90 8 Universal 3.3 V 10BAS E-T and AUI
T r ansceiv er logic and frami ng are set to Mode 1 (compatibl e with AMD and Motoro la cont roll ers).
The LI pin is tied Low, disabling the li nk test function. The DSQE pin is al so Low, enabling the
SQE function. The LBK input controls loopback. A 20 MHz system clock is supplied at CLKI,
with CLKO left open.
Figure 15. AUI Encoder/ Decod er On ly Application
LXT908
TXD
RBIAS
GND2
GND1
TEN
1
TCLK
RCLK
RXD
CD
COL
LBK
AUTOSEL
NTH
DSQE
LI
MD2
MD1
MD0
JAB
PLR
TX
TENA
TCLK
RCLK
RX
RENA
CLSN
LBK
Red Red Red
AM79 90 B ACK- E ND/
CONTROLLER
INTERFACE
LOOPBACK
CONTROL
PROGRAMMING
OPTIONS
MODE SELECT
LINE STA TUS
1 %
GREEN
+3.3 V
LEDC/FDE
LEDR
LEDT/PDN
LEDL
VCC1
VCC2
CLKI
330 330 330330
1
2
4
5
7
89
10
12
13
15
16 1
2
3
4
5
6
7
8
15
14
13
12
9
10
11
+ 12 V
CIN
CIP
DON
DOP
DIN
DIP
D - CONNECTOR to
AUI DROP CABLE
Chassis
Gnd
Fuse
78 Ω
78 Ω
78 Ω
12.4 k Ω
CLKO
PAUI
20 M Hz Left Open
SYSTEM
CLOCK
TEST
Bias resistor RBIAS should be located close to the pin and isol ated from the other signal s
1
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 27
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.0 Test Sp ecifications
Note: Table 4 through Table 13 on page 30 a nd Figure 16 on page 31 through Figure 45 on page 40
represent the performance specifi cations of the Int el® LXT908 Universal 3.3 V 10BAS E-T and
AUI Transcei ver. These specificati ons ar e guaranteed by test except where n oted “by design.”
Minimu m and maximu m val ues list ed in Table 6 through Table 13 on page 30 apply over the
recomm ended operating conditio ns specifie d in Tab le 5.
For all Quality and Reliability issues (for example, parts packaging and thermal specificati ons ),
please send your questions to Intel at the following e-mai l address: www.qr.requests@intel.com.
.
Table 4. Absolute Maximum V alues
Parameter Symbol Min Max Units
Supply voltage VCC -0.3 6 V
Storage temperature TSTG -65 +150 ºC
Caution: E xceeding these values may cause permanent damage. Functional ope ration
under these conditions is not implied. Exposure to maximum rating conditions
for extend ed pe riods ma y affect device re liabili ty.
Table 5. Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Recommended supply voltage1VCC 3.13 3.3 3.47 V
Recommended operating temperature (Commercial) TOP 0–+70ºC
Recommended operating temperature (Extended) TOP -40 – +85 ºC
1. V oltages with respect to ground unless otherwise specified.
Tabl e 6. I/ O Electrical Charac te ris tics
Parameter Sym Min Typ1Max Units Test Conditions
Input Low voltage2VIL ––0.8V
Input H igh v oltage2VIH 2.0 – – V
Output Low voltage VOL ––0.4VIOL = 1.6 mA
VOL ––10%VCC IOL < 10 µA
Output Low voltage
(Open drain LED driver) VOLL ––0.7VIOLL = 10 mA
Output High voltage VOH 2.4 – – V IOH = 40 µA
VOH 90 – – %VCC IOH < 10 µA
Output rise time
TCLK & RCLK
CMOS – – 3 12 ns CLOAD = 20 pF
TTL – – 2 8 ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
28 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Ou tp ut fall tim e
TCLK & RCL K
CMOS – – 3 12 ns CLOAD= 20 pF
TTL – – 2 8 ns
CL K I ris e t im e (ex t e rnall y dri ve n ) – – – 10 ns
CLKI duty cycle (externally driven) – – 40/60 %
Supply curre nt Normal Mode
ICC – 65 85 mA Idle Mode
ICC –95120mA
Tran sm ittin g on
TP
ICC –90120mA
Tran sm ittin g on
AUI
Power Down
Mode ICC –0.752mA
Table 7. AUI Elec trica l Characteristics
Parameter Symbol Min Typ1M ax Units Test Conditions
I np ut Lo w curr e nt IIL ––-700
µA–
Input High current IIH ––500
µA–
Differentia l output voltage VOD ±550 – ±1200 mV –
Differentia l squelch threshold VDS 150 260 350 mV 5 MHz squ a r e
wave input
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. Twisted-Pair E lectrical Chara cteris tics
Parameter Symbol Min Typ1M ax Units Test C ond itio ns
Transmit output impedance ZOUT –5– Ω
Transmit timing jitter addition2––±6.4±10ns
0 line length for
internal MAU
Transmit timing jit ter added by the
MA U and PLS se ct ions2, 3 – – ±3.5 ±5.5 ns
After line mo del
specified by IEEE
802.3 for 10B ASE-T
internal MAU
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is gu aranteed by design; not subj ect to producti on testing.
3. IEEE 802.3 specifies maximum jitter additions at 1 .5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5
ns from the MAU.
Table 6. I/O Electrical Characteristics (Continued)
Parameter Sym Min Typ1Max Units Test Conditions
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed
at levels of 0V and 3V.
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 29
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
Receive input impedance ZIN –20–kΩBet wee n T PIP/TP I N ,
CIP/CIN & DIP/DIN
Diff e rential Squelch
Threshold
Normal
Threshold
NTH = Hi gh VDS 300 395 585 mV 5 MHz square wave
input
Reduced
Threshold
NTH = L ow VDS 180 250 345 mV 5 MHz square wave
input
Table 9. Switching Characteristics
Parameter Symbol Minimum Typical1Maximum Units
Ja bb er Tim in g Maximum transmit time – 20 – 150 ms
Unjab time – 250 – 750 ms
Link Integrity
Timing
Time link loss receiv e – 50 – 150 ms
Link min r eceive – 2 – 7 ms
Link max receive – 50 – 150 ms
Link transmit period – 8 10/20 24 ms
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 10. RCLK/ Star t-o f-Frame Timing
Parameter Symbol Minimum Typical1Maximum Units
Decoder acquisition time AUI tDATA – 900 1100 ns
TP tDATA – 1200 1500 ns
CD turn-on del ay AUI tCD –25200ns
TP tCD –420550ns
Receive data setup from
RCLK Mode 1 tRDS 60 70 – ns
Modes 2 through 5 tRDS 30 45 – ns
Receive data hold from
RCLK Mode 1 tRDH 10 20 – ns
Modes 2 through 5 tRDH 30 45 – ns
RCLK shut off delay from CD assert (Mode 3
and Mode 5) tsws – ±100 – ns
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Table 8. Twisted-Pair Electrical Characteristics (Conti nued)
Parameter Symbol Min Typ1Max Units Test C onditions
1. Typical values are at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. Parameter is guaranteed by design; not subject to production testing.
3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder , and 3.5
ns from the MAU.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
30 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Tab le 11. RCLK/End-of-Frame Timing
Parameter Type Sym Mode
1Mode
2Mode
3Mode
4Mode
5Units
RCLK after CD off Min tRC 51–5–BT
RXD thro ughp ut delay Ma x tRD 400 375 375 375 375 ns
CD turn off delay 2Max tCDOFF 500 475 475 475 475 ns
Rece ive bl ock out af ter T EN off T yp1tIFG 550– – –BT
RCLK switching delay after CD
off (Mode 3 and 5) Typ1tSWE ––
120(±8
0) –120(±8
0) ns
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
2. CD turn -off delay me as ur ed fro m mid dle o f l ast bi t : tim in g sp ec ific at i on i s un af fe ct ed by the val ue of th e la st
bit.
Table 12. Transm it Ti mi ng
Parameter Symbol Minimum Typical1Maximum Units
TEN setup from TC LK tEHCH 22 – – ns
TXD setup from TC LK tDSCH 22 – – ns
TEN hold after TCLK tCHEL 5––ns
TXD hold after TCLK tCHDU 5––ns
Transmit start-up delay - A UI tSTUD – 220 450 ns
Transmit start-up delay - TP tSTUD – 430 450 ns
Transmit t hrough-put delay - AUI tTPD ––300ns
Transmit t hrough-put delay - TP tTPD – 305 350 ns
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Tab le 13 . Collis i on, C OL/CI Out p ut a nd Lo opbac k Timin g
Parameter Symbol Minimum Typical1Maximum Units
COL turn-on d elay tCOLD –40500ns
COL turn-off delay tCOLOFF – 420 500 ns
COL (SQE) Delay aft er TEN off tSQED 0.65 1.2 1.6 μs
COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns
LBK setup from TEN tKHEH 10 25 – ns
LBK ho ld after TEN tKHEL 10 0 – ns
1. Typi cal values a re at 25°C and are for design aid only, are not guaranteed, and are not subject to
production testing.
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 31
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.1 T iming Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low)
Figures 16 - 21
Figure 16. Mo de 1 RCLK/Sta rt-of-Frame Timin g
Figure 17. M o de 1 RCLK/ End-o f-Frame Timing
11010101011
101010111010 1
tCD
tDATA
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tRDS tRDH
010001010
Note: RXD changes 25 ns aft er the rising edge of RCLK.
101010100
1 01 0 1 0 1 00
tRD
tCDOFF
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
tRC
Note: RX D changes 25 n s after the rising edge of RCLK.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
32 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 18. Mode 1 Transmit Timing
Fi g ure 1 9 . Mod e 1 Coll ision D e t e c t Ti m ing
Figure 20. Mode 1 COL/SQE Output Timing/CI Output Timing
Figure 21. Mode 1 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tTPD
tDSCH
tSTUD
tCOLOFF
tCOLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 33
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.2 T iming Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High)
Figures 22 - 27
Figure 22. Mo de 2 RCLK/Sta rt-of-Frame Timin g
Figure 23. M o de 2 RCLK/ End-o f-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tRDS tRDH
CD
RCLK
RXD
tDATA
TPIP/TPIN
or DIP/DIN
11010101011 010001010
Note: RXD changes at the ri sing edge of RCLK. The controller should sample a t the f alling edge.
101010100
tRD
TPIP/TPIN
or DIP/DIN
CD
RCLK
RXD
1 01 0 1 0 1 00
tCDOFF
Note: RX D changes at the rising edge o f RCLK. The controll er should sam pl e at the fa ll ing edge.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
34 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 24. Mode 2 Transmit Timing
Fi g ure 2 5 . Mod e 2 Coll ision D e t e c t Ti m ing
Figure 26. Mode 2 COL/SQE Output Timing
Figure 27. Mode 2 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tTPDtSTUD
tCOLOFFtCOLD
CI
COL
tSQED
TEN
COL
tIFG
tSQEP
tKHEL
tKHEH
LBK
TEN
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 35
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.3 T iming Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low)
Figures 28 - 33
Figure 28. Mo de 3 RCLK/Sta rt-of-Frame Timin g
Figure 29. M o de 3 RCLK/ End-o f-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
11010101011 01000101
tCD
tSWS Recovered from Input Data Stream
Generated from TCLK
Note: RXD changes at th e r ising e dge of R C LK. Th e control ler sho ul d samp le a t the fal li ng edge.
tRD
tCDOFF
CD
RCLK
RXD
tSWE
Recovere d Clock Generated from TCLK
101010100
TPIP/TPIN
or DI P/DIN
1 01 0 1 0 1 00
Note: RXD changes at the rising edge of RCLK. Th e controller should sample at the f allin g edge.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
36 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 30. Mode 3 Transmit Timing
Fi g ure 3 1 . Mod e 3 Coll ision D e t e c t Ti m ing
Figure 32. Mode 3 COL/SQE Output Timing
Figure 33. Mode 3 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tSTUD
tDSCH
tTPD
tCOLOFF
tCOLD
CI
COL
tSQED
TEN
COL
tSQEP
tKHEL
tKHEH
LBK
TEN
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 37
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.4 Timing Diagrams fo r Mode 4 (MD2, 1, 0 = Low, High, High)
Figures 34 - 39
Figure 34. Mo de 4 RCLK/Sta rt-of-Frame Timin g
Figure 35. M o de 4 RCLK/ End-o f-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tCD
tDATA
CD
RCLK
RXD
TPIP/TPIN
or DIP/DIN
tRDS tRDH
11010101011 01000101
Note: RXD changes at th e r ising edge of RC LK. T he cont r oller should sampl e at the falling edge.
101010100
1 01 0 1 0 1 00
tRD
TPIP/TPIN
or DIP/DI N
CD
RCLK
RXD
tCDOFF
Note: RXD changes at the r ising edge of R C LK. Th e contr oller should sample at the f allin g edge.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
38 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 36. Mode 4 Transmit Timing
Fi g ure 3 7 . Mod e 4 Coll ision D e t e c t Ti m ing
Figure 38. Mode 4 COL/SQE Output Timing
Figure 39. Mode 4 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tDSCH
tSTUD tTPD
tCOLOFF
tCOLD
CI
COL
tSQEP
tSQED
TEN
COL
tKHEL
tKHEH
LBK
TEN
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 39
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
4.5 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low)
Figures 40 - 45
Figure 40. Mo de 5 RCLK/Sta rt-of-Frame Timin g
Figure 41. M o de 5 RCLK/ End-o f-Frame Timing
1 0 1 0 1 0 1 1 1 01 0 1
tRDS tRDH
tDATA
CD
RCLK
RXD
TPIP/
TPIN
11010101011 01000101
tCD
tSWS Recovered from Input Data Stream
Generated from TCLK
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
tRD
tCDOFF
CD
RCLK
RXD
tSWE
Recovered Clock Generated from TCLK
101010100
TPIP/
TPIN
1 01 0 1 0 1 00
Note: RXD changes at the rising edge of RCLK. The controller should sample at the falling edge.
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
40 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 42. Mode 5 Transmit Timing
Fi g ure 4 3 . Mod e 5 Coll ision D e t e c t Ti m ing
Figu re 44 . Mo de 5 C OL/SQE Output Timi ng
Figure 45. Mode 5 Loopback Timing
tCHEL
tEHCH
tCHDU
TEN
TCLK
TXD
TPO
tSTUD
tDSCH
tTPD
tCOLOFF
tCOLD
CI
COL
tSQED
TEN
COL
tSQEP
tKHEL
tKHEH
LBK
TEN
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 41
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
5.0 Package Sp ecificat ions
Figure 46. 44-Pin PLCC Package Specifications
A2A
D
F
A1
C
B
D1
D
C
L
44-Pin Plastic Leaded Chip Carrier
•Part Numb er LXT908PC - Commercia l tempera ture range (0°C to +70 °C)
•Part Number LXT 908PE - Extended tempe rature range (-40°C to +8 5 °C)
Dim Inches Millimeters
Min Max Min Max
A 0.165 0.180 4.191 4.572
A10.090 0.120 2.286 3.048
A20.062 0.083 1.575 2.108
B 0.050 – 1.270 –
C 0.026 0.032 0.660 0.813
D 0.685 0.695 17.399 17.653
D10.650 0.656 16.510 16.662
F 0.013 0.021 0.330 0.533
Figure 47. 64-Pin LQFP Pack age Specifications
D
D1
A1
A2
L
A
B
L1
θ3
θ3
θ
E
E1
e/2
e
Dim Inches Millimeters
Min Max Min Max
A – 0.063 – 1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B 0.007 .011 0.17 0.27
D 0.472 BSC 12.00 BSC
D1 0. 394 BSC 10. 00 BSC
E 0.472 BSC 12.00 BSC
E1 0. 39 4 BSC 1 0. 00 BSC
e 0.02 0 BSC 0.5 0 BSC
L 0.018 0.030 0.45 0.75
L1 0.039 REF 1.00 REF
θ311o13o11o13o
θ0o7o0o7o
64-Pin Low-Profile Quad Flat Package
•Part Number LXT908LC (Commerc ial Temperature R ange)
•Part Number LXT 908LE (Extende d Temper ature Range)
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 43
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
5.1 Top-Label Marking
Figure 48 shows a s ample LQFP package for the LXT908 Transcei ver.
Note: In contrast to the Pb -F ree (RoHS- compliant) LQFP packages, the non-RoHS -compliant pa cka ges
do not have t he “e3” s ymbol in the last line of the package label.
Figure 49 sho w s a sample Pb-F r ee (R oH S - co mp l ia n t) LQ FP p ac k ag e f or th e LX T9 0 8 Transceiv er .
Figure 48. S am p le LQFP P ackag e - Intel® LX T 908 Transcei ver
P
in 1
LXT908LE A4
XXXXXXXX
Pa rt Number
FPO Number
BSMC
Bottom Side Mark Cod
e
B5384-01
Figure 49. S amp le Pb-Free (RoHS-Comp lian t) LQFP Package - Intel® LXT908 Trans ceiv er
Pin 1
WJLXT908E A4
XXXXXXXX
Part Number
FPO Number
e3 Pb-Free Indication
BSMC
Bottom Side Mark Code
B5385-01
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
44 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Figure 50 s hows a sample PLCC package for the LXT908 Transcei ver.
Note: I n contrast to the Pb-Free (RoHS-compliant) PLCC packa ges , the non-RoHS-compliant packages
do not ha ve th e “ e 3” symb ol i n th e la s t li ne of th e pac k a g e lab el.
Figure 51 s hows a sample Pb-Free (RoHS - compliant) PL CC package for the LXT908 Transceiver.
Figure 50. Sample PLCC Package - Intel ® LXT908 Tran sceiver
P
in 1
LXT908PC A4
XXXXXXXX
Pa rt Number
FPO Number
BSMC
Bottom Side Mark Cod
e
B5386-01
Figure 51. Sample Pb-Free (RoHS-Compliant) PLCC Package - Intel® LX T9 08 Trans ceiver
Pin 1
EELXT908E A4
XXXXXXXX
Part Number
FPO Number
e3 Pb- Free Indication
BSMC
Bottom Side Mark Code
B5387-01
Inte l® LX T908 Universal 3.3 V 10BASE-T and AUI Tr ansc eiver
Datasheet 45
Docum ent #: 249049
Rev ision #: 003
Rev. Date: 29-Oct- 2005
6.0 Product Ordering Info r m a tion
Table 14 lis ts produc t ordering information for the Intel® LX T908 Univer sal 3.3 V 10BASE-T and
AUI Trans cei v er.
Table 14. Product I nformation
Number Rev isi on Package Type Pin Count RoHS Compliant
DJLXT908LC.A4 A4 LQFP 64 No
WJLXT908LC.A4 A4 LQFP 64 Yes
DJLXT908LE.A4 A4 LQFP 64 No
WJLXT908LE.A4 A4 LQFP 64 Yes
NLXT908PC.A4 A4 PLCC 44 No
EELXT908PC.A4 A4 PLCC 44 Yes
NLXT908PE.A4 A4 PLCC 44 No
EELXT908PE.A4 A4 PLCC 44 Yes
Intel® LXT908 Universal 3.3 V 10BASE -T and AUI Tran scei ver
46 Datasheet
Document #: 249049
Revision #: 003
Rev. Date: 29-Oct- 2005
Fi gure 52 sho ws an or der matrix wit h sample i nformation for o rdering an I ntel® LXT 908 Univer sal
3.3 V 10BASE-T and AUI Transcei ver.
Figu re 52. Or de ri ng In fo rma ti on - Sampl e
DJ C908 LLXT A4
Product Revision
xn = 2 Alphanumeric characters
Temperature Range
A = Ambient (0 – 550C)
C = Commercial (0 –700C)
E = Extended (-40 – 850C)
Internal Package Designator
L = LQFP
P = PLCC
N = DI P
Q = PQFP
H = QF P
T = TQFP
B = BGA
C = CB G A
E = TBGA
K = HSBGA (BGA with heat slug
Product Code
xxxxx = 3-5 Digit alphanumeric
IXA Product Prefix
LXT = PHY layer device
IXE = Switching engine
IXF = Formatting devic e (MAC/Framer)
IXP = Network processor
Intel Package Designator
B5383-01
