MIC4607 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection Features General Description * Gate Drive Supply Voltage up to 16V * Overcurrent Protection * Drives High-Side and Low-Side N-Channel MOSFETs with Independent Inputs or With a Single PWM Signal * TTL Input Thresholds * On-Chip Bootstrap Diodes * Fast 35 ns Propagation Times * Shoot-Through Protection * Drives 1000 pF Load with 20 ns Rise and Fall Times * Low Power Consumption * Supply Undervoltage Protection * -40C to +125C Junction Temperature Range The MIC4607 is an 85V, three-phase MOSFET driver. The MIC4607 features a fast (35 ns) propagation delay time and a 20 ns driver rise/fall time for a 1 nF capacitive load. TTL inputs can be separate high- and low-side signals or a single PWM input with high and low drive generated internally. High- and low-side outputs are guaranteed to not overlap in either mode. The MIC4607 includes overcurrent protection as well as a high-voltage internal diode that charges the high-side gate drive bootstrap capacitor. Applications * Three-Phase and BLDC Motor Drives * Three-Phase Inverters A robust, high-speed, and low-power level shifter provides clean level transitions to the high-side output. The robust operation of the MIC4607 ensures that the outputs are not affected by supply glitches, HS ringing below ground, or HS slewing with high-speed voltage transitions. Undervoltage protection is provided on both the low-side and high-side drivers. The MIC4607 is available in a both a 28-pin 4 mm x 5 mm QFN and 28-pin TSSOP package with an operating junction temperature range of -40C to +125C. Typical Application Circuit MIC4607 Three-Phase Motor Driver DS20005610D-page 1 2016-2019 Microchip Technology Inc. MIC4607 Package Type MIC4607-1 28-pin QFN MIC4607-2 28-pin QFN MIC4607-1 28-pin TSSOP MIC4607-2 28-pin TSSOP DS20005610D-page 2 2016-2019 Microchip Technology Inc. MIC4607 Functional Diagram MIC4607 xPhase Top-Level Functional Diagram Input Logic Block 2016-2019 Microchip Technology Inc. DS20005610D-page 3 MIC4607 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings , (Note 2) Supply Voltage (VDD, VxHB - VxHS)..................................................................................................................................... -0.3V to 18V Input Voltages (VxLI, VxHI, VxPWM, VEN)................................................................................................................... -0.3V to VDD + 0.3V FLT/ Pin.................................................................................................................................................................... -0.3V to VDD + 0.3V DLY Pin ............................................................................................................................................................................... -0.3V to 18V Voltage on xLO (VxLO).............................................................................................................................................. -0.3V to VDD + 0.3V Voltage on xHO (VxHO) ....................................................................................................................................VHS - 0.3V to VHB + 0.3V Voltage on xHS (Continuous).............................................................................................................................................. -0.3V to 90V Voltage on xHB ................................................................................................................................................................................ 108V ILIM+ ................................................................................................................................................................................... -0.3V to +5V ILIM- ................................................................................................................................................................................... -0.3V to +2V Average Current in VDD to HB Diode ........................................................................................................................................... 100 mA ESD Protection on All Pins (Note 1): HBM .................................................................................................................................................................................. 1 kV MM ................................................................................................................................................................................... 200V CDM................................................................................................................................................................................. 200V Operational Characteristics , (Note 2) Supply Voltage (VDD), [decreasing VDD] ............................................................................................................................. 5.25V to 16V Supply Voltage (VDD), [increasing VDD] ................................................................................................................................ 5.5V to 16V Voltage on xHS ................................................................................................................................................................... -0.3V to 85V Voltage on xHS (repetitive transient <100 ns)..................................................................................................................... -0.7V to 90V HS Slew Rate............................................................................................................................................................................... 50 V/ns Voltage on xHB ................................................................................................................................................ VHS + 5.5V to VHS + 16V and/or ............................................................................................................................................................ VDD -1V to VDD +85V Notice: Exceeding the absolute maximum ratings may damage the device. Notice: The device is not guaranteed to function outside its operating ratings. Note 1: 2: Devices are ESD sensitive. Handling precautions are recommended. Human body model, 1.5 k in series with 100 pF. An "x" in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI). DS20005610D-page 4 2016-2019 Microchip Technology Inc. MIC4607 DC CHARACTERISTICS (Note 1, 2) Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VHS = 0V; No load on xLO or xHO; TA = 25C; unless noted. Bold values indicate -40C< TJ < +125C. Parameters Symbol Min. Typ. Max. Units Conditions IDD -- 390 750 A xLI = xHI = 0V -- 2.2 10 A xLI = xHI = 0V; EN = 0V with HS = floating Supply Current VDD Quiescent Current VDD Shutdown Current IDDSH xLI = xHI = 0V; EN = 0V; HS = 0V -- 58 150 IDDO -- 0.6 1.5 mA f = 20 kHz Per Channel xHB Quiescent Current IHB -- 20 75 A xLI = xHI = 0V or xLI = 0V and xHI = 5V Per Channel xHB Operating Current IHBO -- 30 400 A f = 20 kHz xHB to VSS Current, Quiescent IHBS -- 0.05 5 A VxHS = VxHB = 90V xHB to VSS Current, Operating IHBSO -- 30 300 A f = 20 kHz VDD Operating Current Input (TTL: xLI, xHI, xPWM, EN) (Note 3) Low-Level Input Voltage VIL -- -- -- VIH 2.2 -- 0.8 -- V High-Level Input Voltage V -- Input Voltage Hysteresis VHYS 0.1 -- V -- k xLI and xHI Inputs (-1 Version) Input Pull-Down Resistance RI 100 300 500 50 130 250 3.8 -- 4.4 4.9 -- xPWM Input (-2 Version) Undervoltage Protection VDD Falling Threshold VDDF VDD Threshold Hysteresis VDDH xHB Falling Threshold VHBF xHB Threshold Hysteresis 0.25 V -- V -- V -- 0.25 4.9 -- V -- 175 200 225 mV (VILIM+ - VILIM-) tILIM_PROP -- 70 -- ns VILIM+ = 0.5V peak FLT/ Output Low Voltage VOLF -- 0.2 V Rising DLY Threshold 0.5 -- V VILIM = 1V; IFLT/ = 1 mA -- A VDLY = 0V s CDLY = 1 nF VHBH 4.0 -- VILIM+ 4.4 Overcurrent Protection Rising Overcurrent Threshold ILIM to Gate Propagation Delay Fault Circuit VDLY+ -- 1.5 DLY Current Source IDLY 0.44 Fault Clear Time tFCL 0.3 -- 670 0.6 -- Low-Current Forward Voltage VDL -- 0.4 0.70 V IVDD-xHB = 100 A High-Current Forward Voltage VDH -- 0.8 1 V IVDD-xHB = 50 mA Bootstrap Diode Note 1: 2: 3: 4: "x" in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI). Specification for packaged product only. VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. Guaranteed by design. Not production tested. 2016-2019 Microchip Technology Inc. DS20005610D-page 5 MIC4607 DC CHARACTERISTICS (Note 1, 2) (CONTINUED) Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VHS = 0V; No load on xLO or xHO; TA = 25C; unless noted. Bold values indicate -40C< TJ < +125C. Parameters Symbol Min. Typ. Max. Units RD -- 4 6 V -- Low-Level Output Voltage VOLL -- 0.3 0.6 V IxLO = 50 mA High-Level Output Voltage VOHL 0.5 1 V IxLO = 50 mA, VOHL = VDD - VxLO Peak Sink Current IOHL -- 1 -- A VxLO = 0V Peak Source Current IOLL -- 1 -- A VxLO = 12V xHO Gate Driver Low-Level Output Voltage VOLH -- 0.3 0.6 V IxHO = 50 mA High-Level Output Voltage VOHH -- 0.5 1 V IxHO = 50 mA, VOHH = VxHB - VxHO Peak Sink Current IOHH -- 1 -- A VxHO = 0V Peak Source Current IOLH -- 1 -- A VxHO = 12V Dynamic Resistance Conditions xLO Gate Driver -- Switching Specifications (LI/HI mode with inputs non-overlapping, assumes HS low before LI goes high and LO low before HI goes high). Lower Turn-Off Propagation Delay (LI Falling to LO Falling) tLPHL Upper Turn-Off Propagation Delay (HI Falling to HO Falling) tHPHL Lower Turn-On Propagation Delay (LI Rising to LO Rising) tLPLH Upper Turn-On Propagation Delay (HI Rising to HO Rising) tHPLH -- -- -- -- 35 75 ns -- 35 75 ns -- 35 75 ns -- 35 75 ns -- Output Rise/Fall Time tR/F -- 20 -- ns CL = 1000 pF Output Rise/Fall Time (3V to 9V) tR/F -- 0.8 -- s CL = 0.1 F Minimum Input Pulse Width that Changes the Output tPW -- 50 -- ns Note 4 Switching Specifications PWM Mode (MIC4607-2) or LI/HI mode (MIC4607-1) with Overlapping LI/HI Inputs Delay from PWM Going High / LI Low, to LO Going Low tLOOFF -- 35 75 ns -- LO Output Voltage Threshold for LO FET to be Considered Off VLOOFF -- 1.9 -- V -- Delay from LO Off to HO Going High tHOON -- 35 75 ns -- Delay from PWM or HI Going Low to HO Going Low tHOOFF -- 35 75 ns -- Note 1: 2: 3: 4: "x" in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI). Specification for packaged product only. VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. Guaranteed by design. Not production tested. DS20005610D-page 6 2016-2019 Microchip Technology Inc. MIC4607 DC CHARACTERISTICS (Note 1, 2) (CONTINUED) Electrical Characteristics: Unless otherwise indicated, VDD = VxHB = 12V; VEN = 5V; VSS = VHS = 0V; No load on xLO or xHO; TA = 25C; unless noted. Bold values indicate -40C< TJ < +125C. Parameters Symbol Min. Typ. Max. Units Conditions Switch Node Voltage Threshold Signaling HO is Off VSWTH 1 2.2 4 V -- Delay between HO FET Being Considered Off to LO Turning On tLOON -- 35 75 ns -- Forced xLO On if VSWTH is tSWTO 100 250 500 ns -- Not Detected Note 1: "x" in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI). 2: Specification for packaged product only. 3: VIL(MAX) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. VIH(MIN) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. 4: Guaranteed by design. Not production tested. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, TA = +25C, VIN = VEN = 12V, VBOOST - VSW = 3.3V, VOUT = 3.3V Parameters Sym. Min. Typ. Max. Units Conditions Operating Junction Temperature Range TJ -40 -- +125 C Operating Ambient Temperature Range TA -40 -- +125 C -- Lead Temperature -- -- 260 -- C Soldering, 10s Storage Temperature Range TS -60 -- +150 C -- Maximum Junction Temperature TJ -- -- +125 C -- Thermal Resistance, 4 mm x 5 mm QFN-28L JA -- 43 -- C/W -- Thermal Resistance, 4 mm x 5 mm QFN-28L JC -- 3.4 -- C/W -- TSSOP-28L JA -- 70 -- C/W -- TSSOP-28L JC -- 20 -- C/W -- Temperature Ranges -- Package Thermal Resistances 2016-2019 Microchip Technology Inc. DS20005610D-page 7 MIC4607 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. IVHB QUIESCENT CURRENT (A) IVDD QUIESCENT CURRENT (A) 100 490 VxHS = GND 125C VEN = 5V 460 430 400 25C 370 340 310 -40C VxHS = GND VEN = 5V 90 70 60 50 VHB = 12V 5 30 6 7 8 9 -50 10 11 12 13 14 15 16 -25 FIGURE 2-1: VDD Voltage. VDD Quiescent Current vs. VDD = 16V 460 VxHS = GND VEN = 5V 440 420 400 380 360 340 320 VDD = 5.5V 300 VDD = 12V 280 -50 -25 0 25 50 75 100 6 VxHS = GND VEN = 5V -40C 70 60 50 40 25C 30 100 125 125C 20 -40C VDD = VHB 5 4 125C 3 2 1 25C 0 5 6 7 8 9 10 11 12 13 14 15 16 VDD+HB (V) FIGURE 2-5: VDD+HB Shutdown Current (Floating Switch Node) vs. Voltage. IVDD+VHB SHUTDOWN CURRENT (uA) VDD Quiescent Current vs. 80 75 xHI = xLI = 0V VxHS = FLOATING VEN = 0V 7 125 100 90 50 8 TEMPERATURE (C) FIGURE 2-2: Temperature. 25 FIGURE 2-4: VHB Quiescent Current (All Channels) vs Temperature. IVDD+VHB SHUTDOWN CURRENT (A) 500 480 0 TEMPERATURE (C) VDD (V) IVDD QUIESCENT CURRENT (A) VHB = 5.5V 40 20 280 IVHB QUIESCENT CURRENT (A) VHB = 16V 80 8 7 VDD= 16V 6 xHI = xLI = 0V VxHS = FLOATING VEN = 0V VDD = VHB 5 VDD= 12V 4 3 VDD = 5.5V 2 1 0 5 6 7 8 9 10 11 12 13 14 15 16 VHB (V) FIGURE 2-3: VHB Quiescent Current (All Channels) vs. VHB Voltage. DS20005610D-page 8 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) FIGURE 2-6: VDD+HB Shutdown Current (Floating Switch Node) vs. Temperature. 2016-2019 Microchip Technology Inc. 120 IDD+VHB OPERATING CURRENT (mA) IVDD+VHB SHUTDOWN CURRENT (A) MIC4607 xHI = xL I= 0V VxHS = GND 110 VEN = 0V 100 VDD = VHB -40C 90 80 25C 70 60 50 40 125C 30 20 5 6 7 8 9 10 11 12 13 14 15 16 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 VDD = 16V VxHS = 0V CLOAD=0nF 125C 25C -40C 0 10 20 VDD+HB (V) FIGURE 2-7: VDD+HB Shutdown Current (Grounded Switch Node) vs. Voltage. 50 60 70 80 90 100 25 120 xHI = xLI = 0V VxHS = GND 110 VDD= 16V 100 VDD = VHB 80 70 60 VDD = 5.5V 50 40 VEN = VHB = VDD 20 25C 15 -40C 30 20 0 25 50 VxHS = GND 10 VDD= 12V -25 IHO/LO = -50mA 125C VEN = 0V 90 -50 75 100 5 125 5 6 7 8 TEMPERATURE (C) 9 10 11 12 13 14 15 16 VDD (V) FIGURE 2-8: VDD+HB Shutdown Current (Grounded Switch Node) vs. Temperature. FIGURE 2-11: vs. VDD. 1.5 HO/LO Sink On-Resistance 20 VDD = 12V VxHS = 0V CLOAD = 0nF 1.4 1.3 1.2 IHO/LO = 50mA VxHS = GND VEN = VHB = VDD 15 1.1 1 RON SINK () IDD+VHB OPERATING CURRENT (mA) 40 FIGURE 2-10: VDD+HB Operating Current vs. Switching Frequency. RON SOURCE () IVDD+VHB SHUTDOWN CURRENT (A) 30 FREQUENCY (kHz) 25C 0.9 -40C 0.8 0.7 VDD = 12V VDD = 5.5V 10 0.6 5 125C 0.5 0.4 VDD = 16V 0.3 0.2 0 0 10 20 30 40 50 60 70 80 90 100 -50 -25 FIGURE 2-9: VDD+HB Operating Current vs. Switching Frequency. 2016-2019 Microchip Technology Inc. 0 25 50 75 100 125 TEMPERATURE (C) FREQUENCY (kHz) FIGURE 2-12: vs. Temperature. HO/LO Sink On-Resistance DS20005610D-page 9 MIC4607 25 70 IHO/LO = -50mA 60 VEN = VHB = VDD 20 25C 15 VDD = 12V VxHS = 0V CL=1nF VxHS = GND DELAY (ns) RON SOURCE () 125C 10 50 tLPLH 40 30 tHPHL -40C 5 6 7 8 9 10 11 12 13 14 15 -50 16 -25 VDD (V) 0 25 50 75 100 125 TEMPERATURE (C) FIGURE 2-16: Propagation Delay (HI/LI Input) vs. Temperature. FIGURE 2-13: HO/LO Source On-Resistance vs. VDD. 25 50 IHO/LO = -50mA VEN = VHB = VDD VDD = 5.5V 40 tr (ns) 20 VxHS = 0V CL = 1nF 45 VxHS = GND RON SOURCE () tHPLH 20 5 VDD = 12V 15 35 30 125C 25 25C 20 10 VDD = 16V 15 -40C 10 5 -50 -25 0 25 50 75 100 5 125 6 7 8 9 10 11 12 13 14 15 16 VDD (V) TEMPERATURE (C) FIGURE 2-17: Voltage. FIGURE 2-14: HO/LO Source On-Resistance vs. Temperature. Output Rise Time vs. VDD 45 70 TAMB = 25C VxHS = 0V CL= 1nF tHPLH 60 VxHS = 0V CL = 1nF 40 35 25C tHPHL 30 50 tf (ns) DELAY (ns) tLPHL tLPLH 40 tLPHL 125C 25 20 15 30 -40C 10 5 20 5 6 7 8 9 10 11 12 13 14 15 16 5 FIGURE 2-15: Propagation Delay (HI/LI Input) vs. VDD Voltage. DS20005610D-page 10 6 7 8 9 10 11 12 13 14 15 16 VDD (V) VDD (V) FIGURE 2-18: Voltage. Output Fall Time vs. VDD 2016-2019 Microchip Technology Inc. MIC4607 4.9 55 45 UVLO THRESHOLD (V) 35 30 25 20 15 5 -50 -25 0 25 50 75 100 4.7 4.6 VHB FALLING 4.5 4.4 4.3 VDD RISING 4.2 VDD FALLING 4 125 -50 TEMPERATURE (C) FIGURE 2-19: Temperature. VxHS = 0V 4.1 FALL TIME RISE TIME VDD = 12V VDD = 12V 10 VHB RISING 4.8 FALL TIME VDD = 5.5V 40 tr/tf (ns) RISE TIME VDD = 5.5V VxHS = 0V CL=1nF 50 -25 0 25 50 75 100 125 TEMPERATURE (C) Rise/Fall Time vs. FIGURE 2-22: Temperature. VDD/VHB UVLO vs. FIGURE 2-23: VDD Voltage. Overcurrent Threshold vs. FIGURE 2-24: Temperature. Overcurrent Threshold vs. 130 VxHS = 0V CL=1nF TAMB = 25C 120 110 125C DEAD TIME (ns) 100 25C 90 -40C 80 70 60 50 40 30 20 10 5 6 7 8 9 10 11 12 13 14 15 16 VDD (V) Dead Time vs. VDD Voltage. FIGURE 2-20: 130 VDD= 12V VxHS = 0V CL=1nF 120 DEAD TIME (ns) 110 VDD = 5.5V 100 90 80 VDD = 16V 70 VDD = 12V 60 50 40 30 20 10 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) FIGURE 2-21: Dead Time vs. Temperature. 2016-2019 Microchip Technology Inc. DS20005610D-page 11 MIC4607 120 PROPAGATION DELAY (ns) VHS = 0V 125C 110 100 90 25C -40C 80 70 60 50 5 6 7 8 9 10 11 12 13 14 15 16 VDD (V) FIGURE 2-25: Overcurrent Propagation Delay vs. VDD Voltage. FIGURE 2-28: Characteristics. Bootstrap Diode I-V PROPAGATION DELAY (ns) 120 VxHS = 0V VDD = 16V 110 VDD = 5.5V 100 90 80 70 VDD = 12V 60 50 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) FIGURE 2-26: Overcurrent Propagation Delay vs. Temperature. FIGURE 2-27: Current. DS20005610D-page 12 Bootstrap Diode Reverse 2016-2019 Microchip Technology Inc. MIC4607 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1 and Table 3-2. TABLE 3-1: QFN PIN FUNCTION TABLE Pin Name Pin Number QFN MIC4607-1 MIC4607-2 1 BHI BPWM High-side input (-1) or PWM input (-2) for Phase B. 2 ALI NC Low-side input (-1) or no connect (-2) for Phase A. 3 AHI APWM Description High-side input (-1) or PWM input (-2) for Phase A. 4 EN EN Active-high enable input. High input enables all outputs and initiates normal operation. Low input shuts down device into a low LQ mode. 5 FLT/ FLT/ Open-Drain. FLT/ pin goes low when outputs are latched off due to an overcurrent event. Must be pulled-up to an external voltage with a resistor. 6 BHB BHB Phase B High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and BHS. An on-board bootstrap diode is connected from VDD to BHB. 7 BHO BHO Phase B High-Side Drive Output. Connect to the gate of the external high-side power MOSFET. 8 BHS BHS Phase B High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 9 BLO BLO Phase B Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. 10 NC NC No Connect. 11 ILIM- ILIM- Differential Current-Limit Input. Connect to most negative end of the external current-sense resistor. 12 VSS VSS Power Ground for Phase A and Phase B. 13 ILIM+ ILIM+ Differential Current-Limit Input. Connect to most positive end of the external current-sense resistor. 14 ALO ALO Phase A Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. 15 AHS AHS Phase A High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 16 AHO AHO Phase A High Side Drive Output. Connect to the gate of the external high-side power MOSFET. 17 AHB AHB Phase A High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and AHS. An on-board bootstrap diode is connected from VDD to AHB. 18 VDD VDD Input Supply for Gate Drivers and Internal Logic/Control Circuitry. Decouple this pin to VSS with a minimum 2.2 F ceramic capacitor. 19 DLY DLY Fault Delay. Connect an external capacitor from this pin to ground to increase the current-limit reset delay. Leave open for minimum delay. Do not externally drive this pin. 20 VSS VSS Phase C Power and Control Circuitry Ground. 21 CLO CLO Phase C Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. 22 CHS CHS Phase C High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 2016-2019 Microchip Technology Inc. DS20005610D-page 13 MIC4607 TABLE 3-1: QFN PIN FUNCTION TABLE (CONTINUED) Pin Name Pin Number QFN MIC4607-1 MIC4607-2 23 CHO CHO Phase C High-Side Drive Output. Connect to the gate of the external high-side power MOSFET. 24 CHB CHB Phase C High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and CHS. An on-board bootstrap diode is connected from VDD to CHB. 25 NC NC No Connect. 26 CLI NC Low-Side Input (-1) or No Connect (-2) for Phase C. 27 CHI CPWM High-Side Input (-1) or PWM Input (-2) for Phase C. 28 BLI NC Low-Side Input (-1) or No Connect (-2) for Phase B. EP ePad ePad TABLE 3-2: Pin Number TSSOP Description Exposed Heatsink Pad: Connect to GND for best thermal performance. TSSOP PIN FUNCTION TABLE Pin Name Description MIC4607-1 MIC4607-2 1 NC NC No Connect. 2 CLI NC Low-Side Input (-1) or No Connect (-2) for Phase C. 3 CHI CPWM High-Side Input (-1) or PWM Input (-2) for Phase C. 4 BLI NC Low-Side Input (-1) or No Connect (-2) for Phase B. 5 BHI BPWM High-side input (-1) or PWM input (-2) for Phase B. 6 ALI NC Low-side input (-1) or no connect (-2) for Phase A. 7 AHI APWM High-side input (-1) or PWM input (-2) for Phase A. 8 EN EN Active-high enable input. High input enables all outputs and initiates normal operation. Low input shuts down device into a low LQ mode. 9 FLT/ FLT/ Open-Drain. FLT/ pin goes low when outputs are latched off due to an overcurrent event. Must be pulled-up to an external voltage with a resistor. 10 BHB BHB Phase B High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and BHS. An on-board bootstrap diode is connected from VDD to BHB. 11 BHO BHO Phase B High-Side Drive Output. Connect to the gate of the external high-side power MOSFET. 12 BHS BHS Phase B High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 13 BLO BLO Phase B Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. 14 ILIM- ILIM- Differential Current-Limit Input. Connect to most negative end of the external current-sense resistor. 15 VSS VSS Power Ground for Phase A and Phase B. 16 ILIM+ ILIM+ Differential Current-Limit Input. Connect to most positive end of the external current-sense resistor. 17 ALO ALO Phase A Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. DS20005610D-page 14 2016-2019 Microchip Technology Inc. MIC4607 TABLE 3-2: TSSOP PIN FUNCTION TABLE (CONTINUED) Pin Name Pin Number TSSOP MIC4607-1 MIC4607-2 18 AHS AHS Phase A High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 19 AHO AHO Phase A High Side Drive Output. Connect to the gate of the external high-side power MOSFET. 20 AHB AHB Phase A High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and AHS. An on-board bootstrap diode is connected from VDD to AHB. 21 VDD VDD Input Supply for Gate Drivers and Internal Logic/Control Circuitry. Decouple this pin to VSS with a minimum 2.2 F ceramic capacitor. 22 DLY DLY Fault Delay. Connect an external capacitor from this pin to ground to increase the current-limit reset delay. Leave open for minimum delay. Do not externally drive this pin. 23 VSS VSS Phase C Power and Control Circuitry Ground. 24 CLO CLO Phase C Low-Side Drive Output. Connect to the gate of the low-side power MOSFET gate. 25 CHS CHS Phase C High-Side Driver Return. Connect to the bootstrap capacitor and to a resistor that connect to the source of the external MOSFET. See the Applications section for additional information on the resistor. 26 CHO CHO Phase C High-Side Drive Output. Connect to the gate of the external high-side power MOSFET. 27 CHB CHB Phase C High-Side Bootstrap Supply. An external bootstrap capacitor is required. Connect the bootstrap capacitor across this pin and CHS. An on-board bootstrap diode is connected from VDD to CHB. 28 NC NC 2016-2019 Microchip Technology Inc. Description No Connect. DS20005610D-page 15 MIC4607 4.0 TIMING DIAGRAMS 4.1 Non-Overlapping LI/HI Input Mode (MIC4607-1) In non-overlapping LI/HI input mode, enough delay is added between the xLI and xHI inputs to allow xHS to be low before xLI is pulled high and similarly xLO is low before xHI goes high. xHO goes high with a high signal on xHI after a typical delay of 35 ns (tHPLH). xHI going low drives xHO low also with typical delay of 35 ns (tHPHL). Likewise, xLI going high forces xLO high after typical delay of 35 ns (tLPLH) and xLO follows low transition of xLI after typical delay of 35 ns (tLPHL). xHO and xLO output rise and fall times (tR/tF) are typically 20 ns driving 1000 pF capacitive loads. xHS 0V tF tR xHO tHPLH tR tHPHL tF xLO tLPLH tLPHL xHI xLI FIGURE 4-1: Separate Non-Overlapping LI/HI Input Mode (MIC4607-1). Note 1: All propagation delays are measured from the 50% voltage level and rise/fall times are measured 10% to 90%. 2: "x" in front of a pin name refers to either A, B or C phase. (e.g. xHI can be either AHI, BHI or CHI). DS20005610D-page 16 2016-2019 Microchip Technology Inc. MIC4607 4.2 Overlapping LI/HI Input Mode (MIC4607-1) When xLI/xHI input high signals overlap, xLO/xHO output states are determined by the first output to be turned on. That is, if xLI goes high (ON), while xHO is high, xHO stays high until xHI goes low at which point, after a delay of tHOOFF and when xHS < 2.2V, xLO goes high with a delay of tLOON. Should xHS never trip the aforementioned internal comparator reference (2.2V), a falling xHI edge delayed by a typical 250 ns will set xHS 0V "HS latch" allowing xLO to go high. If xHS falls very fast, xLO will be held low by a 35 ns delay gated by HI going low. Conversely, xHI going high (ON) when xLO is high has no effect on outputs until xLI is pulled low (off) and xLO falls to < 1.9V. Delay from xLI going low to xLO falling is tLOOFF and delay from xLO < 1.9V to xHO being on is tHOON. 2.2V (typ) tLOON xHO tHOON tHOOFF 1.9V (typ) xLO tLOOFF xHI xLI FIGURE 4-2: Separate Overlapping LI/HI Input Mode (MIC4607-1). 2016-2019 Microchip Technology Inc. DS20005610D-page 17 MIC4607 4.3 PWM Input Mode (MIC4607-2) A low going xPWM signal applied to the MIC4607-2 causes xHO to go low, typically 35ns (tHOOFF) after the xPWM input goes low, at which point the switch node, xHS, falls (1-2). When xHS reaches 2.2V (VSWTH), the external high-side MOSFET is deemed off and xLO goes high, typically within 35 ns (tLOON) (3-4). xHS falling below 2.2V sets a latch that can only be reset by xPWM going high. This design prevents ringing on xHS from causing an indeterminate xLO state. Should xHS never trip the aforementioned internal comparator reference (2.2V), a falling xPWM edge delayed by 250 ns will set "HS latch" allowing xLO to go high. A 35 ns delay gated by xPWM going low can determine the time to xLO going high for fast falling HS designs. xPWM going high forces xLO low in typically 35ns (tLOOFF) (5-6). When xLO reaches 1.9V (VLOOFF), the low-side MOSFET is deemed off and xHO is allowed to go high. The delay between these two points is typically 35 ns (tHOON) (7-8). xHO and xLO output rise and fall times (tR/tF) are typically 20 ns driving 1000 pF capacitive loads. tF tR 2 xHO tHOON tR 4 6 xLO 7 (VLOOFF) tF tLOON tLOOFF 3 (VSWTH) xHS 0V 1 5 xPWM tHOOFF FIGURE 4-3: DS20005610D-page 18 PWM Mode (MIC4607-2). 2016-2019 Microchip Technology Inc. MIC4607 4.4 Overcurrent Timing Diagram The motor current is sensed in an external resistor that is connected between the low-side MOSFET's source pins and ground. If the sense resistor voltage exceeds the rising overcurrent threshold (typically 0.2V), all LO and HO outputs are latched off and the FLT/ pin is pulled low. Once the outputs are latched off, an internal current source (typically 0.44 A) begins to charge up the external CDLY capacitor. The outputs remain latched off and all xLI/xHI (or xPWM) input signals are ignored until the voltage on the CDLY capacitor rises FIGURE 4-4: above the VDLY+ threshold (typically 1.5V), which resets the latch on the first rising edge of any LI input of the MIC4607-1 (or falling edge on any PWM input for the MIC4607-2). Once this occurs, the CDLY capacitor is discharged, the FLT/ pin returns to a high impedance state and all outputs will respond to their respective input signals. On startup, the current limit latch is reset during a rising VDD or a rising EN pin voltage to assure normal operation. Overcurrent Timing Diagram. 2016-2019 Microchip Technology Inc. DS20005610D-page 19 MIC4607 5.0 FUNCTIONAL DESCRIPTION The MIC4607 is a non-inverting, 85V three-phase MOSFET driver designed to independently drive all six N-Channel MOSFETs in a three-phase bridge. The MIC4607 offers a wide 5.5V to 16V VDD operating supply range with either six independent TTL inputs (MIC4607-1) or three PWM inputs, one for each phase (MIC4607-2). Refer to the Functional Diagram section. A high level applied to the xLI pin causes VDD to be applied to the gate of the external MOSFET. A low level on the xLI pin grounds the gate of the external MOSFET. VDD SWITCH NODE The drivers contain input buffers with hysteresis, four independent UVLO circuits (three high-side and one low-side), and six output drivers. The high-side output drivers utilize a high-speed level-shifting circuit that is referenced to its HS pin. Each phase has an internal diode that is used by the bootstrap circuits to provide the drive voltages for each of the three high-side outputs. A programmable overcurrent protection circuit turns off all outputs during an overcurrent fault. 5.1 Startup and UVLO The UVLO circuits force the driver's outputs low until the supply voltage exceeds the UVLO threshold. The low-side UVLO circuit monitors the voltage between the VDD and VSS pins. The high-side UVLO circuits monitor the voltage between the xHB and xHS pins. Hysteresis in the UVLO circuits prevent system noise and finite circuit impedance from causing chatter during turn-on. 5.2 VSS FIGURE 5-1: Diagram. 5.5 Low-Side Driver Block High-Side Driver and Bootstrap Circuit Figure 5-2 illustrates a block diagram of the high-side driver and bootstrap circuit. This driver is designed to drive a floating N-channel MOSFET, whose source terminal is referenced to the HS pin. VDD HB VIN CB HO LEVEL SHIFT EXTERNAL FET Input Stage All input pins (xLI and xHI) are referenced to the VSS pin. The MIC4607 has a TTL-compatible input range and can be used with input signals with amplitude less than the supply voltage. The threshold level is independent of the VDD supply voltage and there is no dependence between IVDD and the input signal amplitude. This feature makes the MIC4607 an excellent level translator that will drive high level gate threshold MOSFETs from a low-voltage PWM IC. 5.4 MIC4607 Enable Inputs There is one external enable pin that controls all three phases. A logic high on the enable pin (EN) allows for startup of all phases and normal operation. Conversely, when a logic low is applied on the enable pin, all phases turn-off and the device enters a low current shutdown mode. All outputs (xHO and xLO) are pulled low when EN is low. Do not leave the EN pin floating. 5.3 EXTERNAL FET LO Low-Side Driver The low-side driver is designed to drive a ground (VSS pin) referenced N-channel MOSFET. Low driver impedances allow the external MOSFET to be turned on and off quickly. The rail-to-rail drive capability of the output ensures a low RDS(ON) from the external power device. Refer to Figure 5-1. DS20005610D-page 20 MIC4607 HS RHS SWITCH NODE FIGURE 5-2: High-Side Driver and Bootstrap-Circuit Block Diagram. A low-power, high-speed, level-shifting circuit isolates the low side (VSS pin) referenced circuitry from the high-side (xHS pin) referenced driver. Power to the high-side driver and UVLO circuit is supplied by the bootstrap capacitor (CB) while the voltage level of the xHS pin is shifted high. The bootstrap circuit consists of an internal diode and external capacitor, CB. In a typical application, such as the motor driver shown in Figure 5-3 (only Phase A illustrated), the AHS pin is at ground potential while the low-side MOSFET is on. The internal diode charges capacitor CB to VDD - VF during this time (where VF is 2016-2019 Microchip Technology Inc. MIC4607 the forward voltage drop of the internal diode). After the low-side MOSFET is turned off and the AHO pin turns on, the voltage across capacitor CB is applied to the gate of the high-side external MOSFET. As the high-side MOSFET turns on, voltage on the AHS pin rises with the source of the high-side MOSFET until it reaches VIN. As the AHS and AHB pins rise, the internal diode is reverse biased, preventing capacitor CB from discharging. During this time, the high-side MOSFET is kept ON by the voltage across capacitor CB. 5.7 Overcurrent Protection Circuitry The MIC4607 provides overcurrent protection for the motor driver circuitry. It consists of: * A comparator that senses the voltage across a current-sense resistor * A latch and timer that keep all gate drivers off during a fault * An open-drain pin that pulls low during the fault. If an overcurrent condition is detected, the FLT/ pin is pulled low and the gate drive outputs are latched off for a time that is determined by the DLY pin circuitry. After the delay circuitry times out, a high-going edge on any of the LI pins (for the MIC4607-1 version) or a low-going edge on any of the PWM pins (for the MIC4607-2 version) is required to reset the latch, de-assert the FLT/ pin and allow the gate drive outputs to switch. For additional information, refer to the Timing Diagrams section as well as the Functional Diagram section. 5.7.1 FIGURE 5-3: Example. 5.6 MIC4607 Motor Driver Programmable Gate Drive The MIC4607 offers programmable gate drive, meaning the MOSFET gate drive (gate-to-source voltage) equals the VDD voltage. This feature offers designers flexibility in selecting the proper MOSFETs for a given application. Different MOSFETs require different VGS characteristics for optimum RDS(ON) performance. Typically, the higher the gate voltage (up to 16V), the lower the RDS(ON) achieved. For example, as shown in Figure 5-4, a NTMSF4899NF MOSFET can be driven to the ON state with a gate voltage of 5.5V but RDS(ON) is 5.2 m. If driven to 10V, RDS(ON) is 4.1 m--a decrease of 20%. In low-current applications, the losses due to RDS(ON) are minimal, but in high-current motor drive applications such as power tools, the difference in RDS(ON) can lower the efficiency, reducing run time. ILIM The ILIM+ and ILIM- pins provide a Kelvin-sensed circuit that monitors the voltage across an external current sense resistor. This resistor is typically connected between the source pins of all three low-side MOSFETs and power ground. If the peak voltage across this resistor exceeds the VILIM+ threshold, it will cause all six outputs to latch off. Both pins should be shorted to VSS ground if the overcurrent features is not used. 5.7.2 DLY A capacitor connected to the DLY pin determines the amount of time the gate drive outputs are latched off before they can be restarted. During normal operation, the DLY pin is held low by an internal MOSFET. After an overcurrent condition is detected, the MOSFET turns off and the external capacitor is charged up by an internal current source. The outputs remain latched off until the DLY pin voltage reaches the VDLY+ threshold (typically 1.5V). The delay time can be approximately calculated using Equation 5-1. EQUATION 5-1: C DLY V DLY t DLY = -----------------------------------I DLY FIGURE 5-4: MOSFET RDS(ON) vs. VGS. 2016-2019 Microchip Technology Inc. DS20005610D-page 21 MIC4607 5.7.3 FLT/ This open-drain output is pulled low while the gate drive outputs are latched off after an over-current condition. It will de-assert once the DLY pin has reached the VDLY+ threshold and a rising edge occurs on any LI pin (for the MIC4607-1) or a falling edge on any PWM pin (MIC4607-2). During normal operation, the internal pull-down MOSFET is of the pin is high impedance. A pull-up resistor must be connected to this pin. DS20005610D-page 22 2016-2019 Microchip Technology Inc. MIC4607 6.0 APPLICATION INFORMATION 6.1 Adaptive Dead-Time The MIC4607 uses a combination of active sensing and passive delay to ensure that both MOSFETs are not on at the same time. Figure 6-2 illustrates how the adaptive dead-time circuitry works. For each phase, it is important that both MOSFETs of the same phase branch are not conducting at the same time or VIN will be shorted to ground and current will "shoot through" the MOSFETs. Excessive shoot-through causes higher power dissipation in the MOSFETs, voltage spikes and ringing. The high switching current and voltage ringing generate conducted and radiated EMI. Minimizing shoot-through can be done passively, actively or through a combination of both. Passive shoot-through protection can be achieved by implementing delays between the high and low gate drivers to prevent both MOSFETs from being on at the same time. These delays can be adjusted for different applications. Although simple, the disadvantage of this approach is that it requires long delays to account for process and temperature variations in the MOSFET and MOSFET driver. Adaptive Dead-Time monitors voltages on the gate drive outputs and switch node to determine when to switch the MOSFETs on and off. This active approach adjusts the delays to account for some of the variations, but it too has its disadvantages. High currents and fast switching voltages in the gate drive and return paths can cause parasitic ringing to turn the MOSFETs back on even while the gate driver output is low. Another disadvantage is that the driver cannot monitor the gate voltage inside the MOSFET. Figure 6-1 shows an equivalent circuit of the high-side gate drive. FIGURE 6-1: MIC4607 Driving an External MOSFET. The internal gate resistance (RG_FET) and any external damping resistor (RG) and HS pin resistor (RHS), isolate the MOSFET's gate from the driver output. There is a delay between when the driver output goes low and the MOSFET turns off. This turn-off delay is usually specified in the MOSFET data sheet. This delay increases when an external damping resistor is used. 2016-2019 Microchip Technology Inc. FIGURE 6-2: Diagram. Adaptive Dead-Time Logic For the MIC4607-2, a high level on the xPWM pin causes HI to go low and LI to go high. This causes the xLO pin to go low. The MIC4607 monitors the xLO pin voltage and prevents the xHO pin from turning on until the voltage on the xLO pin reaches the VLOOFF threshold. After a short delay, the MIC4607 drives the xHO pin high. Monitoring the xLO voltage eliminates any excessive delay due to the MOSFET driver's turn-off time and the short delay accounts for the MOSFET turn-off delay as well as letting the xLO pin voltage settle out. If an external resistor is used between the xLO output and the MOSFET gate, it must be made small enough to prevent excessive voltage drop across the resistor during turn-off. Figure 6-3 illustrates using a diode (DLS) and resistor (RLS2) in parallel with the gate resistor to prevent a large voltage drop between the xLO pin and MOSFET gate voltages during turn-off. FIGURE 6-3: Low-Side Drive Gate Resistor Configuration. A low on the xPWM pin causes HI to go high and LO to go low. This causes the xHO pin to go low after a short delay (tHOOFF). Before the xLO pin can go high, the voltage on the switching node (xHS pin) must have dropped to 2.2V. Monitoring the switch voltage instead of the xHO pin voltage eliminates timing variations and excessive delays due to the high-side MOSFET DS20005610D-page 23 MIC4607 turn-off. The xLO driver turns on after a short delay (tLOON). Once the xLO driver is turned on, it is latched on until the xPWM signal goes high. This prevents any ringing or oscillations on the switch node or xHS pin from turning off the xLO driver. If the xPWM pin goes low and the voltage on the xHS pin does not cross the VSWTH threshold, the xLO pin will be forced high after a short delay (tSWTO), ensuring proper operation. The internal logic circuits also ensure a "first on" priority at the inputs. If the xHO output is high, the xLI pin is inhibited. A high signal or noise glitch on the xLI pin has no effect on the xHO or xLO outputs until the xHI pin goes low. Similarly, xLO being high holds xHO low until xLI and xLO are low. Fast propagation delay between the input and output drive waveform is desirable. It improves overcurrent protection by decreasing the response time between the control signal and the MOSFET gate drive. Minimizing propagation delay also minimizes phase shift errors in power supplies with wide bandwidth control loops. Care must be taken to ensure that the input signal pulse width is greater than the minimum specified pulse width. An input signal that is less than the minimum pulse width can result in no output pulse or an output pulse whose width is significantly less than the input. The maximum duty cycle (ratio of high-side on-time to switching period) is determined by the time required for the CB capacitor to charge during the off-time. Adequate time must be allowed for the CB capacitor to charge up before the high-side driver is turned back on. Although the adaptive dead-time circuit in the MIC4607 prevents the driver from turning both MOSFETs on at the same time, other factors outside of the anti-shoot-through circuit's control can cause shoot-through. Other factors include ringing on the gate drive node and capacitive coupling of the switching node voltage on the gate of the low-side MOSFET. The scope photo in Figure 6-4 shows the dead time (<20 ns) between the high- and low-side MOSFET transitions as the low-side driver switches off while the high-side driver transitions from off to on. FIGURE 6-4: Adaptive Dead-Time LO (LOW) to HO (HIGH). DS20005610D-page 24 Table 6-1 contains truth tables for the MIC4607-1 (independent TTL inputs) and Table 6-2 is for the MIC4607-2 (PWM inputs) that details the "first on" priority as well as the failsafe delay (tSWTO). TABLE 6-1: MIC4607-1 TRUTH TABLE xLI xHI xLO xHO 0 0 0 0 Both outputs off. 0 1 0 1 xHO will not go HIGH until xLO falls below 1.9V. 1 0 1 0 xLO will be delayed an extra 250 ns if xHS never falls below 2.2V. 1 1 X X First ON stays on until input of same goes LOW. TABLE 6-2: Comments MIC4607-2 TRUTH TABLE xPWM xLO xHO Comments 0 1 0 xLO will be delayed an extra 250 ns if xHS never falls below 2.2V. 1 0 1 xHO will not go HIGH until xLO falls below 1.9V. 6.2 HS Pin Clamp A resistor/diode clamp between the switching node and the HS pin is necessary to clamp large negative glitches or pulses on the HS pin. Figure 6-5 shows the Phase A section high-side and low-side MOSFETs connected to one phase of the three phase motor. There is a brief period of time (dead time) between switching to prevent both MOSFETs from being on at the same time. When the high-side MOSFET is conducting during the on-time state, current flows into the motor. After the high-side MOSFET turns off, but before the low-side MOSFET turns on, current from the motor flows through the body diode in parallel with the low-side MOSFET. Depending upon the turn-on time of the body diode, the motor current, and circuit parasitics, the initial negative voltage on the switch node can be several volts or more. The forward voltage drop of the body diode can be several volts, depending on the body diode characteristics and motor current. Even though the HS pin is rated for negative voltage, it is good practice to clamp the negative voltage on the HS pin with a resistor and a diode to prevent excessive negative voltage from damaging the driver. Depending upon the application and amount of negative voltage on the switch node, a 3 resistor is recommended. If the HS pin voltage exceeds 0.7V, a diode between the xHS pin and ground is recommended. The diode reverse 2016-2019 Microchip Technology Inc. MIC4607 voltage rating must be greater than the high-voltage input supply (VIN). Larger values of resistance can be used if necessary. The average power dissipated by the forward voltage drop of the diode equals: Adding a series resistor in the switch node limits the peak high-side driver current during turn-off, which affects the switching speed of the high-side driver. The resistor in series with the HO pin may be reduced to help compensate for the extra HS pin resistance. EQUATION 6-2: AHB VDD DBST AHI Level Shift AHO RG AHS RHS VNEG DCLAMP Phase A M ALO ALI RG Phases B&C MIC4607 VSS FIGURE 6-5: 6.3 Negative HS Pin Voltage. Power Dissipation Considerations Power dissipation in the driver can be separated into three areas: * Internal diode dissipation in the bootstrap circuit * Internal driver dissipation * Quiescent current dissipation used to supply the internal logic and control functions. 6.4 Where: VF Diode forward voltage drop. There are three phases in the MIC4607. The power dissipation for each of the bootstrap diodes must be calculated and summed to obtain the total bootstrap diode power dissipation for the package. VIN CB CVDD Pdiode FWD = I F AVE V F Bootstrap Circuit Power Dissipation Power dissipation of the internal bootstrap diode primarily comes from the average charging current of the bootstrap capacitor (CB) multiplied by the forward voltage drop of the diode. Secondary sources of diode power dissipation are the reverse leakage current and reverse recovery effects of the diode. The average current drawn by repeated charging of the high-side MOSFET is calculated by Equation 6-1. EQUATION 6-1: I F AVE = Q GATE f S The value of VF should be taken at the peak current through the diode; however, this current is difficult to calculate because of differences in source impedances. The peak current can either be measured or the value of VF at the average current can be used, which will yield a good approximation of diode power dissipation. The reverse leakage current of the internal bootstrap diode is typically 3 A at a reverse voltage of 85V at 125C. Power dissipation due to reverse leakage is typically much less than 1 mW and can be ignored. An optional external bootstrap diode may be used instead of the internal diode (Figure 6-6). An external diode may be useful if high gate charge MOSFETs are being driven and the power dissipation of the internal diode is contributing to excessive die temperatures. The voltage drop of the external diode must be less than the internal diode for this option to work. The reverse voltage across the diode will be equal to the input voltage minus the VDD supply voltage. The above equations can be used to calculate power dissipation in the external diode; however, if the external diode has significant reverse leakage current, the power dissipated in that diode due to reverse leakage can be calculated with the formula in Equation 6-3: EQUATION 6-3: Pdiode REV = I R V REV 1 - D Where: IR VREV D Reverse current flow at VREV and TJ. Diode reverse voltage. Duty cycle (tON x fS). Where: QGATE Total gate charge at VHB - VHS. fS Gate drive switching frequency. 2016-2019 Microchip Technology Inc. The on-time is the time the high-side switch is conducting. In most topologies, the diode is reverse biased during the switching cycle off-time. DS20005610D-page 25 MIC4607 MOSFET's specifications. The ESR of capacitor CB and the resistance of the connecting etch can be ignored since they are much less than RON and RG_FET. The effective capacitances of CGD and CGS are difficult to calculate because they vary non-linearly with ID, VGS, and VDS. Fortunately, most power MOSFET specifications include a typical graph of total gate charge versus VGS. Figure 6-8 shows a typical gate charge curve for an arbitrary power MOSFET. This chart shows that for a gate voltage of 10V, the MOSFET requires about 23.5 nC of charge. The energy dissipated by the resistive components of the gate drive circuit during turn-on is calculated as: EQUATION 6-4: 2 1 E = --- C ISS V GS 2 Where: FIGURE 6-6: Diode. 6.5 Optional External Bootstrap Gate Driver Power Dissipation Power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source and gate to drain capacitance of the external MOSFET. Figure 6-7 shows a simplified equivalent circuit of the MIC4607 driving an external high-side MOSFET. CISS Total gate capacitance of the MOSFET. but EQUATION 6-5: Q = CV so, EQUATION 6-6: 1 E = --- Q G V GS 2 FIGURE 6-7: MIC4607 Driving an External High-Side MOSFET. 6.5.1 DISSIPATION DURING THE EXTERNAL MOSFET TURN-ON Energy from capacitor CB is used to charge up the input capacitance of the MOSFET (CGD and CGS). The energy delivered to the MOSFET is dissipated in the three resistive components, RON, RG and RG_FET. RON is the on resistance of the upper driver MOSFET in the MIC4607. RG is the series resistor (if any) between the driver and the MOSFET. RG_FET is the gate resistance of the MOSFET and is typically listed in the power DS20005610D-page 26 FIGURE 6-8: VGS. Typical Gate Charge vs. 2016-2019 Microchip Technology Inc. MIC4607 The same energy is dissipated by ROFF, RG, and RG_FET when the driver IC turns the MOSFET off. Assuming RON is approximately equal to ROFF, the total energy and power dissipated by the resistive drive elements is: EQUATION 6-7: E DRIVER = Q G V GS The power dissipated in the driver equals the ratio of RON and ROFF to the external resistive losses in RG and RG_FET. Letting RON = ROFF, the power dissipated in the driver due to driving the external MOSFET is: EQUATION 6-11: R ON Pdiss DRIVER = P DRIVER ------------------------------------------------R ON + R G + R G_FET Where: EDRIVER Energy dissipated per switching cycle and EQUATION 6-8: P DRIVER = Q G V GS f S Where: PDRIVER Power dissipated per switching cycle QG Total gate charge at VGS VGS Gate-to-source voltage on MOSFET fS Switching freq. of the gate drive circuit There are six MOSFETs driven by the MIC4607. The power dissipation for each of the drivers must be calculated and summed to obtain the total driver diode power dissipation for the package. In some cases, the high-side FET of one phase may be pulsed at a frequency, fS, while the low-side FET of the other phase is kept continuously on. Since the MOSFET gate is capacitive, there is no driver power if the FET is not switched. The operation of all driver outputs must be considered to accurately calculate power dissipation. The die temperature can be calculated after the total power dissipation is known. EQUATION 6-12: 6.6 Power is dissipated in the input and control sections of the MIC4607, even if there is no external load. Current is still drawn from the VDD and HB pins for the internal circuitry, the level shifting circuitry, and shoot-through current in the output drivers. The VDD and VHB currents are proportional to operating frequency and the VDD and VHB voltages. The Typical Performance Curves show how supply current varies with switching frequency and supply voltage. The power dissipated by the MIC4607 due to supply current is: EQUATION 6-9: Pdiss SUPPLY = V DD I DD + V HB I HB Values for IDD and IHB are found in the EC table and the typical characteristics graphs. 6.7 T J = T A + Pdiss TOTAL JA Supply Current Power Dissipation Total Power Dissipation and Thermal Considerations Total power dissipation in the MIC4607 is equal to the power dissipation caused by driving the external MOSFETs, the supply currents and the internal bootstrap diodes. EQUATION 6-10: Pdiss TOTAL = Pdiss SUPPLY + Pdiss DRIVE + P DIODE 2016-2019 Microchip Technology Inc. Where: TA Maximum ambient temperature TJ Junction temperature PdissTOTAL JA 6.8 Total power dissipation of MIC4607 Thermal resistance from junction to ambient air Other Timing Considerations Make sure the input signal pulse width is greater than the minimum specified pulse width. An input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is significantly less than the input. The maximum duty cycle (ratio of high-side on-time to switching period) is controlled by the minimum pulse width of the low side and by the time required for the CB capacitor to charge during the off-time. Adequate time must be allowed for the CB capacitor to charge up before the high-side driver is turned on. 6.9 Decoupling and Bootstrap Capacitor Selection Decoupling capacitors are required for both the low-side (VDD) and high-side (xHB) supply pins. These capacitors supply the charge necessary to drive the DS20005610D-page 27 MIC4607 external MOSFETs and also minimize the voltage ripple on these pins. The capacitor from xHB to xHS has two functions: it provides decoupling for the high-side circuitry and also provides current to the high-side circuit while the high-side external MOSFET is on. Ceramic capacitors are recommended because of their low impedance and small size. Z5U type ceramic capacitor dielectrics are not recommended because of the large change in capacitance over temperature and voltage. A minimum value of 0.1 F is required for CB (xHB to xHS capacitors) and 1 F for the VDD capacitor, regardless of the MOSFETs being driven. Larger MOSFETs may require larger capacitance values for proper operation. The voltage rating of the capacitors depends on the supply voltage, ambient temperature and the voltage derating used for reliability. 25V rated X5R or X7R ceramic capacitors are recommended for most applications. The minimum capacitance value should be increased if low voltage capacitors are used because even good quality dielectric capacitors, such as X5R, will lose 40% to 70% of their capacitance value at the rated voltage. Placement of the decoupling capacitors is critical. The bypass capacitor for VDD should be placed as close as possible between the VDD and VSS pins. The bypass capacitor (CB) for the xHB supply pin must be located as close as possible between the xHB and xHS pins. The etch connections must be short, wide, and direct. The use of a ground plane to minimize connection impedance is recommended. Refer to the "Grounding, Component Placement and Circuit Layout" sub-section for more information. The voltage on the bootstrap capacitor drops each time it delivers charge to turn on the MOSFET. The voltage drop depends on the gate charge required by the MOSFET. Most MOSFET specifications specify gate charge versus VGS voltage. Based on this information and a recommended VHB of less than 0.1V, the minimum value of bootstrap capacitance is calculated as: EQUATION 6-13: Q GATE C B ---------------V HB Where: QGATE Total gate charge at VHB. VHB Voltage drop at the HB pin. If the high-side MOSFET is not switched but held in an on state, the voltage in the bootstrap capacitor will drop due to leakage current that flows from the HB pin to ground. This current is specified in the Electrical Characteristics table. In this case, the value of CB is calculated as: DS20005610D-page 28 EQUATION 6-14: I HBS t ON C B --------------------------V HB Where: IHBS Maximum xHB pin leakage current. tON Maximum high-side FET on-time. The larger value of CB from Equation 6-13 or Equation 6-14 should be used. 6.10 Grounding, Component Placement and Circuit Layout Nanosecond switching speeds and ampere peak currents in and around the MIC4607 driver require proper placement and trace routing of all components. Improper placement may cause degraded noise immunity, false switching, excessive ringing, or circuit latch-up. Figure 6-9 shows the critical current paths of the highand low-side driver when their outputs go high and turn on the external MOSFETs. It also helps demonstrate the need for a low impedance ground plane. Charge needed to turn-on the MOSFET gates comes from the decoupling capacitors CVDD and CB. Current in the low-side gate driver flows from CVDD through the internal driver, into the MOSFET gate, and out the source. The return connection back to the decoupling capacitor is made through the ground plane. Any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the MOSFET. This voltage works against the gate drive voltage and can either slow down or turn off the MOSFET during the period when it should be turned on. Current in the high-side driver is sourced from capacitor CB and flows into the xHB pin and out the xHO pin, into the gate of the high side MOSFET. The return path for the current is from the source of the MOSFET and back to capacitor CB. The high-side circuit return path usually does not have a low-impedance ground plane so the etch connections in this critical path should be short and wide to minimize parasitic inductance. As with the low-side circuit, impedance between the MOSFET source and the decoupling capacitor causes negative voltage feedback that fights the turn-on of the MOSFET. It is important to note that capacitor CB must be placed close to the xHB and xHS pins. This capacitor not only provides all the energy for turn-on but it must also keep xHB pin noise and ripple low for proper operation of the high-side drive circuitry. 2016-2019 Microchip Technology Inc. MIC4607 FIGURE 6-9: Turn-On Current Paths. Figure 6-10 shows the critical current paths when the driver outputs go low and turn off the external MOSFETs. Short, low-impedance connections are important during turn-off for the same reasons given in the turn-on explanation. Current flowing through the internal diode replenishes charge in the bootstrap capacitor, CB. FIGURE 6-10: Turn-Off Current Paths. 2016-2019 Microchip Technology Inc. DS20005610D-page 29 MIC4607 7.0 MOTOR APPLICATIONS Figure 7-1 illustrates an automotive motor application. The 12V battery input voltage can see peaks as high as 60V during a load dump event. The 85V-rated MIC4607 drives six MOSFETs that provide power to the BLDC motor. A current-sense resistor senses the peak motor current. The voltage across this resistor is monitored by the OC circuit in the MIC4607, which provides overcurrent protection for the application. The 120V rating of the MIC5281 series of LDOs provide input surge voltage protection, while regulating the battery voltage down to 3.3V and 10V to 12V for the microcontroller and gate driver respectively. This circuit can also be used for power tool applications, where the battery voltage carries high-voltage peaks and surges. FIGURE 7-1: DS20005610D-page 30 Figure 7-2 is a block diagram for a 24V motor drive application. The regulated 24V bus allows the use of lower input voltage LDOs, such as the MIC5239-3.3 and MIC5234. This circuit configuration can be used in industrial applications. Figure 7-3 illustrates an off-line motor application. Adding an off-line power supply to the front end allow the MIC4607 to be used in applications such as blenders and other small white goods as well as ceiling fan applications. The circuit consists of an MIC38C44 based AC/DC power supply, that is used to generate 24 VDC to power a BLDC motor. The MIC4607 drives the six MOSFETs that provide power to the motor. The MIC4607 can also be used in low and mid-voltage inverter applications. Figure 7-4 shows how power generated by a spinning (or breaking) motor can be used to generate DC power to a load or provide power for battery-charging applications. Automotive or Power Tool Application. 2016-2019 Microchip Technology Inc. MIC4607 FIGURE 7-2: Industrial Motor Driver. FIGURE 7-3: Blender Motor Drive Application Diagram. 2016-2019 Microchip Technology Inc. DS20005610D-page 31 MIC4607 FIGURE 7-4: DS20005610D-page 32 Three-Phase Synchronous Rectification. 2016-2019 Microchip Technology Inc. MIC4607 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 24-lead VQFN* Example XXXX-X WNNN 4607-1 8943 28-lead TSSOP* XXXX -XXXX WNNN Legend: XX...X Y YY WW NNN e3 * Example 4607 -2YTS 1612 Product code or customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. , , Pin one index is identified by a dot, delta up, or delta down (triangle mark). Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Package may or may not include the corporate logo. Underbar (_) and/or Overbar () symbol may not be to scale. 2016-2019 Microchip Technology Inc. DS20005610D-page 33 MIC4607 28-Lead QFN Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS20005610D-page 34 2016-2019 Microchip Technology Inc. MIC4607 28-Lead TSSOP Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 2016-2019 Microchip Technology Inc. DS20005610D-page 35 MIC4607 NOTES: DS20005610D-page 36 2016-2019 Microchip Technology Inc. MIC4607 APPENDIX A: REVISION HISTORY Revision A (August 2016) * Converted Micrel document MIC4607 to Microchip data sheet template DS20005610A. * Minor text changes throughout. Revision B (January 2018) * Replaced Figure 6-5 with a corrected version. * Updated values in Absolute Maximum Ratings , (Note 2) and Operational Characteristics , (Note 2) sections. Revision C (August 2018) * AEC-Q100 qualification. Revision D (April 2019) * Removed statement 'Qualified According to AECQ100' from Features. * Remove statement 'Automotive BLDC Motor Applications' from Applications. 2016-2019 Microchip Technology Inc. DS20005610D-page 37 MIC4607 NOTES: DS20005610D-page 38 2016-2019 Microchip Technology Inc. MIC4607 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X X XX Device Input Option Junction Temperature Range Package Device: MIC4607: Input Option: 1 2 = Dual Inputs = Single PWM Input Temperature Range: Y = -40C to +125C Package: ML = 28-lead 4x5 QFN TS = 28-lead 5.0x4.4 TSSOP Media Type: T5 TR - XX Media Type Examples: a) MIC4607-1YML-T5: b) MIC4607-1YML-TR: c) MIC4607-1YTS: d) MIC4607-1YTS-T5: e) MIC4607-1YTS-TR: f) MIC4607-2YML-T5: g) MIC4607-2YML-TR: h) MIC4607-2YTS: 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection (RoHS Compliant) = 500/Reel = 5000/Reel QFN (ML) Package = 2500/Reel TSSOP (TS) Package <blank>=50/Tube TSSOP (TS) Package 2016-2019 Microchip Technology Inc. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temperature Range, 28-Pin QFN, 500/Reel. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temp. Range, 28-Pin QFN, 5000/Reel. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temp. Range, 28-Pin TSSOP, 50/Tube 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temp. Range, 28-Pin TSSOP, 500/Reel 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temp. Range, 28-Pin TSSOP, 2500/Reel. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Single PWM Input, -40C to +125C Temp. Range, 28-Pin TSSOP, 500/Reel. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Single PWM Input, -40C to +125C Temp. Range, 28-Pin TSSOP, 2500/Reel. 85V, Three-Phase MOSFET Driver with Adaptive Dead-Time, Anti-Shoot-Through and Overcurrent Protection, Dual Inputs, -40C to +125C Temp. Range, 28-Pin TSSOP, 50/Tube DS20005610D-page 39 MIC4607 NOTES: DS20005610D-page 40 2016-2019 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2016-2019, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-4444-2 2016-2019 Microchip Technology Inc. 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