Complete 10-Bit and 12-Bit, 25 MHz
CCD Signal Processors
Data Sheet AD9943/AD9944
FEATURES
25 MSPS correlated double sampler (CDS)
6 dB to 40 dB 10-bit variable gain amplifier (VGA)
Low noise optical black clamp circuit
Preblanking function
10-bit (AD9943), 12-bit (AD9944) 25 MSPS A/D converter
No missing codes guaranteed
3-wire serial digital interface
3 V single-supply operation
Space-saving 32-lead 5 mm × 5 mm LFCSP package
APPLICATIONS
Digital still cameras
Digital video camcorders
PC cameras
Portable CCD imaging devices
CCTV cameras
GENERAL DESCRIPTION
The AD9943/AD9944 are complete analog signal processors
for CCD applications. They feature a 25 MHz single-channel
architecture designed to sample and condition the outputs of
interlaced and progressive scan area CCD arrays. The signal
chain for the AD9943/AD9944 consists of a correlated double
sampler (CDS), a digitally controlled variable gain amplifier
(VGA), and a black level clamp. The AD9943 offers 10-bit
ADC resolution, while the AD9944 contains a true 12-bit ADC.
The internal registers are programmed through a 3-wire
serial digital interface. Programmable features include gain
adjustment, black level adjustment, input clock polarity, and
power-down modes. The AD9943/AD9944 operate from a
single 3 V power supply, typically dissipate 79 mW, and are
packaged in space-saving 32-lead LFCSP packages.
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
DATACLKSHDSHP
BAND GAP
REFERENCE
DOUT
CCDIN
PBLK
REFT REFB
INTERNAL
TIMING
6dB–40dB
AVDD
DVDD
DVSS
AVSS
DRVDD
DRVSS
10
DIGITAL
INTERFACE
SDATASCKSL
CLPOB
10/12
CDS VGA
CLP
AD9943/AD9944
CONTROL
REGISTERS
10-/12-BIT
ADC
02905-B-001
Rev. C Document Feedback
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AD9943/AD9944 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
AD9943 System Specifications ................................................... 3
AD9944 System Specifications ................................................... 4
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Ter mi nol o g y ...................................................................................... 9
Equivalent Input Circuits .............................................................. 10
Typical Performance Characteristics ........................................... 11
Internal Register Map .................................................................... 12
Serial Interface ................................................................................ 13
Circuit Description and Operation .............................................. 14
DC Restore .................................................................................. 14
Correlated Double Sampler ...................................................... 14
Optical Black Clamp .................................................................. 14
A/D Converter ............................................................................ 15
Variable Gain Amplifier ............................................................ 15
CCD Mode Timing ........................................................................ 16
Applications Information .............................................................. 17
Internal Power-On Reset Circuitry .......................................... 18
Grounding and Decoupling Recommendations .................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide ............................................................................... 19
REVISION HISTORY
3/14—Rev. B to Rev. C
Added Exposed Pad Notation, Figure 2 and Table 6 ................... 7
Added Exposed Pad Notation, Figure 3 and Table 7 ................... 8
Changes to Figure 17 ...................................................................... 17
Changes to Figure 18 ...................................................................... 18
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
5/04—Data Sheet Changed from Rev. A to Rev. B
Updated Format .................................................................. Universal
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
5/03—Data Sheet changed from Rev. 0 to Rev. A
Added AD9944 ................................................................... Universal
Changes to Features Section............................................................ 1
Updated Ordering Guide ................................................................. 5
Replaced TPC 3 ................................................................................. 9
Added Figure 12.............................................................................. 15
Updated Outline Dimensions ....................................................... 16
Rev. C | Page 2 of 20
Data Sheet AD9943/AD9944
SPECIFICATIONS
GENERAL SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
TEMPERATURE RANGE
Operating −20 +85 °C
Storage −65 +150 °C
POWER SUPPLY VOLTAGE
Analog, Digital, Digital Driver 2.7 3.6 V
POWER CONSUMPTION
Normal Operation 79 mW
Power-Down Mode 150 µW
MAXIMUM CLOCK RATE 25 MHz
DIGITAL SPECIFICATIONS
DRVDD = DVDD = 2.7 V, CL = 20 pF, unless otherwise noted.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage VIH 2.1 V
Low Level Input Voltage VIL 0.6 V
High Level Input Current IIH 10 µA
Low Level Input Current
I
IL
10
µA
Input Capacitance CIN 10 pF
LOGIC OUTPUTS
High Level Output Voltage, I
OH
= 2 mA
V
OH
2.2
V
Low Level Output Voltage, IOL = 2 mA VOL 0.5 V
AD9943 SYSTEM SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 2.
Parameter Min Typ Max Unit Conditions
CDS
Maximum Input Range before Saturation1 1.0 V p-p
Allowable CCD Reset Transient1 500 mV See input waveform in footnote.
Maximum CCD Black Pixel Amplitude1 100 mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain 5.3 dB See Figure 13 for VGA gain curve.
Maximum Gain 40 41.5 dB See Variable Gain Amplifier section for VGA
gain equation.
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
Minimum Clamp Level 0 LSB
Maximum Clamp Level
63.75
LSB
Rev. C | Page 3 of 20
AD9943/AD9944 Data Sheet
Parameter Min Typ Max Unit Conditions
A/D CONVERTER
Resolution 10 Bits
Differential Nonlinearity (DNL) ±0.3 LSB
No Missing Codes Guaranteed
Data Output Coding
Straight binary
Full-Scale Input Voltage 2.0 V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
Gain Accuracy ±1 dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.3 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1 Input signal characteristics defined as follows:
AD9944 SYSTEM SPECIFICATIONS
TMIN to TMAX, AVDD = DVDD = DRVDD = 3 V, fSAMP = 25 MHz, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Conditions
CDS
Maximum Input Range before Saturation1 1.0 V p-p
Allowable CCD Reset Transient1 500 mV See input waveform in footnote.
Maximum CCD Black Pixel Amplitude
1
100
mV
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution 1024 Steps
Gain Monotonicity Guaranteed
Gain Range
Minimum Gain 5.3 dB See Figure 13 for VGA gain curve.
Maximum Gain 40 41.5 dB See Variable Gain Amplifier section for VGA
gain equation.
BLACK LEVEL CLAMP
Clamp Level Resolution 256 Steps
Clamp Level Measured at ADC output.
Minimum Clamp Level
0
LSB
Maximum Clamp Level 255 LSB
A/D CONVERTER
Resolution
12
Bits
Differential Nonlinearity (DNL) ±0.4 LSB
No Missing Codes Guaranteed
Data Output Coding Straight binary
Full-Scale Input Voltage 2.0 V
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. C | Page 4 of 20
Data Sheet AD9943/AD9944
Parameter Min Typ Max Unit Conditions
VOLTAGE REFERENCE
Reference Top Voltage (REFT) 2.0 V
Reference Bottom Voltage (REFB) 1.0 V
SYSTEM PERFORMANCE Specifications include entire signal chain.
Gain Range
Low Gain (VGA Code = 0) 5.3 dB
Maximum Gain (VGA Code = 1023) 40 41.5 dB
Gain Accuracy
±1
dB
Peak Nonlinearity 500 mV Input Signal 0.1 % 12 dB gain applied.
Total Output Noise 0.9 LSB rms AC grounded input, 6 dB gain applied.
Power Supply Rejection (PSR) 50 dB Measured with step change on supply.
1 Input signal characteristics defined as follows:
TIMING SPECIFICATIONS
CL = 20 pF, fSAMP = 25 MHz. See CCD-mode timing in Figure 14 and Figure 15, and serial timing in Figure 10 and Figure 11.
Table 4.
Parameter Symbol Min Typ Max Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period tCONV 40 ns
DATACLK High/Low Pulse Width tADC 16 20 ns
SHP Pulse Width tSHP 10 ns
SHD Pulse Width tSHD 10 ns
CLPOB Pulse Width1 tCOB 2 20 Pixels
SHP Rising Edge to SHD Falling Edge tS1 10 ns
SHP Rising Edge to SHD Rising Edge tS2 16 20 ns
Internal Clock Delay
t
ID
3.0
ns
DATA OUTPUTS
Output Delay tOD 9.5 ns
Pipeline Delay
9
Cycles
SERIAL INTERFACE
Maximum SCK Frequency fSCLK 10 MHz
SL to SCK Setup Time
t
LS
10
ns
SCK to SL Hold Time tLH 10 ns
SDATA Valid to SCK Rising Edge Setup tDS 10 ns
SCK Falling Edge to SDATA Valid Hold tDH 10 ns
1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
100mV TYP
OPTICAL BLACK PIXEL
500mV TYP
RESET TRANSIENT
1V TYP
INPUT SIGNAL RANGE
02905-B-002
Rev. C | Page 5 of 20
AD9943/AD9944 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter (With Respect To) Min Max Unit
AVDD (AVSS) −0.3 +3.9 V
DVDD (DVSS) −0.3 +3.9 V
DRVDD (DRVSS) −0.3 +3.9 V
Digital Outputs (DRVSS) −0.3 DRVDD + 0.3 V
SHP, SHD, DATACLK (DVSS) −0.3 DVDD + 0.3 V
CLPOB, PBLK (DVSS) −0.3 DVDD + 0.3 V
SCK, SL, SDATA DVSS (AVSS) −0.3 DVDD + 0.3 V
REFT, REFB, CCDIN
−0.3
AVDD + 0.3
V
Junction Temperature 150 °C
Lead Temperature (10 sec) 300 °C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The thermal resistance of a 32-lead LFCSP package
(with the exposed bottom pad soldered to the board GND)
is θJA = 27.7°C / W.
ESD CAUTION
Rev. C | Page 6 of 20
Data Sheet AD9943/AD9944
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. AD9943 Pin Configuration
Table 6. AD9943 Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 to 10 D0 to D9 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14 DATACLK DI Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19 SHD DI CDS Sampling Clock for CCD Data Level.
20
AVDD
P
Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25 SL DI Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 to 32 NC NC Internally not connected.
EPAD Exposed Pad. Solder the exposed pad to the ground plane of the PCB.
1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
REFB
REFT
CCDIN
AVSS
D0
D1
D2
NC2
AVDD
SHD
SHP
CLPOB
D8
D9
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
D3
D4
D5
D6
D7
NC2
NC1
NC1
NC1
SCK
SDATA
SL
1NC = NO CONNECT. INTE RNALLY PULLED DOWN. FLOAT OR CONNECT TO GND.
2NC = NO CONNECT. INTE RNALLY NOT CO NNE CTED.
NOTES
1. SOLDER THE EXPOSED PAD TO THE G ROUND PLANE OF THE P CB.
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9943
TOP VIEW
(No t t o Scal e)
02905-003
Rev. C | Page 7 of 20
AD9943/AD9944 Data Sheet
Figure 3. AD9944 Pin Configuration
Table 7. AD9944 Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 to 10 D2 to D11 DO Digital Data Outputs.
11 DRVDD P Digital Output Driver Supply.
12 DRVSS P Digital Output Driver Ground.
13 DVDD P Digital Supply.
14
DATACLK
DI
Digital Data Output Latch Clock.
15 DVSS P Digital Supply Ground.
16 PBLK DI Preblanking Clock Input.
17 CLPOB DI Black Level Clamp Clock Input.
18 SHP DI CDS Sampling Clock for CCD Reference Level.
19
SHD
DI
CDS Sampling Clock for CCD Data Level.
20 AVDD P Analog Supply.
21 AVSS P Analog Ground.
22 CCDIN AI Analog Input for CCD Signal.
23 REFT AO A/D Converter Top Reference Voltage Decoupling.
24 REFB AO A/D Converter Bottom Reference Voltage Decoupling.
25
SL
DI
Serial Digital Interface Load Pulse.
26 SDATA DI Serial Digital Interface Data Input.
27 SCK DI Serial Digital Interface Clock Input.
28 to 30 NC NC Internally pulled down. Float or connect to GND.
31 D0 DO Digital Data Output.
32 D1 DO Digital Data Output.
EPAD Exposed Pad. Solder the exposed pad to the ground plane of the PCB.
1 Type: AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
REFB
REFT
CCDIN
AVSS
D2
D3
D4
D1
AVDD
SHD
SHP
CLPOB
D10
D11
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
D5
D6
D7
D8
D9
D0
NC
NC
NC
SCK
SDATA
SL
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AD9944
TOP VIEW
(No t t o Scal e)
NOTES
1. NC = NO CO NNE C T. I NTERNAL LY PULLED DOWN. FLOAT O R CONNECT TO GND.
2. SOLDER THE EXPOSED PAD TO THE G ROUND PLANE OF THE P CB.
02905-004
Rev. C | Page 8 of 20
Data Sheet AD9943/AD9944
TERMINOLOGY
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Therefore
every code must have a finite width. No missing codes
guaranteed to 10-bit resolution indicates that all 1024 codes,
respectively, must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full-signal chain specification, refers to the
peak deviation of the output of the AD9943/AD9944 from a
true straight line. The point used as zero scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular output code to the
true straight line. The error is then expressed as a percentage of
the 2 V ADC full-scale signal. The input signal is always
appropriately gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage, using the relationship
( )
codesScaleFullADC
N
2LSB1 =
where N is the bit resolution of the ADC. For example, 1 LSB of
the AD9943 is 1.95 mV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9943/AD9944’s power supply. The PSR specification is
calculated from the change in the data outputs for a given
step change in the supply voltage.
Internal Delay for SHP/SHD
The internal delay (also called aperture delay) is the time delay
that occurs from the time a sampling edge is applied to the
AD9943/AD9944 until the actual sample of the input signal is
held. Both SHP and SHD sample the input signal during the
transition from low to high, so the internal delay is measured
from each clock’s rising edge to the instant the actual internal
sample is taken.
Rev. C | Page 9 of 20
AD9943/AD9944 Data Sheet
EQUIVALENT INPUT CIRCUITS
Figure 4. Digital Inputs—SHP, SHD, DATACLK, CLOB, PBLK, SCK, SL
Figure 5. Data Outputs
Figure 6. CCDIN (Pin 22)
330Ω
DVDD
DVSS
INPUT
02905-B-005
DVDD
DVSS DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
02905-B-006
AVDD
AVSS AVSS
02095-B-007
60Ω
Rev. C | Page 10 of 20
Data Sheet AD9943/AD9944
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. AD9943/AD9944 Power vs. Sample Rate
Figure 8. AD9943 Typical DNL Performance
Figure 9. AD9944 Typical DNL Performance
SAMPLE RATE (MHz)
100
50
2515
POWER DISSIPATION (mV)
10
80
20
90
70
60
V
DD
= 3.3V
V
DD
= 3.0V
V
DD
= 2.7V
40
02905-B-008
01000
400
200 600 800
0
–0.50
0.50
0.25
–0.25
02905-B-009
0.50
0.25
0
–0.25
–0.50
0 800 1600 2400 3200 4000
02905-B-010
Rev. C | Page 11 of 20
AD9943/AD9944 Data Sheet
INTERNAL REGISTER MAP
All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and
AD9944 = 128 LSB clamp level).
Table 8.
Address Bits
Register Name A2 A1 A0 Data Bits Function
Operation 0 0 0 D0 Software Reset (0 = normal operation, 1 = reset all registers to default).
D2, D1 Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown).
D3 OB Clamp Disable (0 = clamp on, 1 = clamp off).
D5, D4 Test Mode. Should always be set to 00.
D6 PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level).
D8, D7 Test Mode 1. Should always be set to 00.
D11 to D9 Test Mode 2. Should always be set to 000.
Control 0 0 1 D0 SHP/SHD Input Polarity (0 = active low, 1 = active high).
D1 DATACLK Input Polarity (0 = active low, 1 = active high).
D2 CLPOB Input Polarity (0 = active low, 1 = active high).
D3 PBLK Input Polarity (0 = active low, 1 = active high).
D4 Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated).
D5
Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent).
D6 Data Output Coding (0 = binary output, 1 = gray code output).
D11 to D7 Test Mode. Should always be set to 00000.
Clamp Level
0
1
0
D7 to D0
OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB,
AD9944: 0 = 0 LSB, 255 = 255 LSB).
VGA Gain 0 1 1 D9 to D0 VGA Gain (0 = 6 dB, 1023 = 40 dB).
Rev. C | Page 12 of 20
Data Sheet AD9943/AD9944
SERIAL INTERFACE
Figure 10. Serial Write Operation
Figure 11. Continuous Serial Write Operation to All Registers
t
LS
t
LH
SDATA
SCK
SL
TEST BIT
A2 0
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED
FOR THE UNDEFINED BITS.
4.
TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW.
D11
02905-B-011
SDATA A0 A1 A2 D0 D1 D2 D3 D4 D5 D10 D11
SCK
SL
0
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.)
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
D0 D1 D10 D11 D0 ...
...
...
DATA FOR STARTING
REGISTER ADDRESS DATA FOR NEXT
REGISTER ADDRESS
D2D1
... ...
116
2 3 4 5 6 7 8 9 10 15 18
17 2827 30
29 31
TEST
BIT
02905-B-012
Rev. C | Page 13 of 20
AD9943/AD9944 Data Sheet
CIRCUIT DESCRIPTION AND OPERATION
Figure 12. CCD Mode Block Diagram
The AD9943/AD9944 signal processing chain is shown in
Figure 12. Each processing step is essential for achieving a high
quality image from the raw CCD pixel data.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V, which is compatible with the 3 V single
supply of the AD9943/AD9944.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract video
information and reject low frequency noise. The timing shown
in Figure 14 illustrates how the two CDS clocks, SHP and SHD,
are used, respectively, to sample the reference level and data
level of the CCD signal. The CCD signal is sampled on the
rising edges of SHP and SHD. Placement of these two clock
signals is critical for achieving the best performance from the
CCD. An internal SHP/SHD delay (tID) of 3 ns is caused by
internal propagation delays.
OPTICAL BLACK CLAMP
The optical black clamp loop is used to remove residual offsets
in the signal chain and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with the
fixed black level reference selected by the user in the clamp level
register. The resulting error signal is filtered to reduce noise,
and the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital
clamping is used during the post processing, the optical black
clamping for the AD9943/AD9944 may be disabled using
Bit D3 in the operation register. Refer to Table 8 and Figure 10
and Figure 11.
When the loop is disabled, the clamp level register may still be
used to provide programmable offset adjustment. Horizontal
timing is shown in Figure 15. The CLPOB pulse should be
placed during the CCD’s optical black pixels. It is recommended
that the CLPOB pulse be used during valid CCD dark pixels.
The CLPOB pulse should be a minimum of 20 pixels wide to
minimize clamp noise. Shorter pulse widths may be used, but
clamp noise may increase and the loop’s ability to track low
frequency variations in the black level is reduced.
6dB TO 40dB
CCDIN
DIGITAL
FILTERING
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
DOUT
10-/12-BIT
ADC
VGA
8-BIT
DAC
CLAMP LEVEL
REGISTER
8
VGA GAIN
REGISTER
10
CDS
INTERNAL
VREF
2V FULL SCALE
10/12
0.1µF
02905-B-013
Rev. C | Page 14 of 20
Data Sheet AD9943/AD9944
A/D CONVERTER
The ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range. The ADC uses
a pipelined architecture with a 2 V full-scale input for low noise
performance.
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 6 dB to 40 dB,
programmable with 10-bit resolution through the serial digital
interface. The minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V. A plot of the
VGA gain curve is shown in Figure 13.
( )
( )
dB3.5dB035.0dB +×= CodeVGAGainVGA
Figure 13. VGA Gain Curve
VGA GAIN REGISTER MODE
42
12
383127
VGA GAIN (dB)
0
30
255
36
34
18
6511 639 767 895 1023
02905-B-014
Rev. C | Page 15 of 20
AD9943/AD9944 Data Sheet
CCD MODE TIMING
Figure 14. CCD Mode Timing
Figure 15. Typical CCD Mode Line Clamp Timing
NN + 1 N + 2 N + 9 N + 10
t
OD
t
S1
t
ID
t
ID
N – 10 N – 9 N– 8 N – 1 N
NOTES
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
SHP
SHD
DATACLK
OUTPUT
DATA
CCD
SIGNAL
t
S2
t
CP
02905-B-015
CCD
SIGNAL
EFFECTIVE PIXELS
CLPOB
OPTICAL BLACK PIXELS HORIZONTAL
BLANKING DUMMY PIXELS EFFECTIVE PIXELS
PBLK
NOTES
1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.
OUTPUT
DATA EFFECTIVE PIXEL DATA OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA
02905-B-016
Rev. C | Page 16 of 20
Data Sheet AD9943/AD9944
APPLICATIONS INFORMATION
The AD9943/AD9944 are complete analog front end (AFE)
products for digital still camera and camcorder applications. As
shown in Figure 12, the CCD image (pixel) data is buffered and
sent to the AD9943/AD9944 analog input through a series
input capacitor. The AD9943/AD9944 perform the dc
restoration, CDS, gain adjustment, black level correction, and
analog-to-digital conversion. The AD9943/AD9944’s digital
output data is then processed by the image processing ASIC.
The internal registers of the AD9943/AD9944—used to control
gain, offset level, and other functions—are programmed by the
ASIC or microprocessor through a 3-wire serial digital
interface. A system timing generator provides the clock signals
for both the CCD and the AFE.
Figure 16. System Applications Diagram
Figure 17. AD9943 Recommended Circuit Configuration for CCD Mode
CCD
CCDIN
BUFFER
V
OUT
AD9943/AD9944
ADC
OUT
REGISTER
DATA
SERIAL
INTERFACE
DIGITAL
OUTPUTS DIGITAL IMAGE
PROCESSING
ASIC
TIMING
GENERATOR
V-DRIVE
CCD
TIMING
CDS/CLAMP
TIMING
0.1µF
02905-B-017
24 REF B
23 REF T
22 CCDIN
21 AVSS
D0 1
D1 2
D2 3
NC
20 AVDD
19 SHD
18 SHP
17 CLP O B
D3 4
D4 5
D5 6
D6 7
D7 8
DATA
OUTPUTS
10
D8
D9
910
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
12 13 14 15 16
5CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
1.0µF
1.0µF 0.1µF
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
32 31 30 29 28 27 26 25
NC
NC
NC
NC
SCK
SDTA
SL
11
02905-018
AD9943
TOP VIEW
(No t t o Scal e)
Rev. C | Page 17 of 20
AD9943/AD9944 Data Sheet
Figure 18. AD9944 Recommended Circuit Configuration for CCD Mode
INTERNAL POWER-ON RESET CIRCUITRY
After power-on, the AD9943/AD9944 automatically reset all
internal registers and perform internal calibration procedures.
This takes approximately 1 ms to complete. During this time,
normal clock signals and serial write operations may occur.
However, serial register writes are ignored until the internal
reset operation is completed.
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 17 and Figure 18, a single ground plane is
recommended for the AD9943/AD9944. This ground plane
should be as continuous as possible. This ensures that all analog
decoupling capacitors provide the lowest possible impedance
path between the power and bypass pins and their respective
ground pins. All decoupling capacitors should be located as
close as possible to the package pins. A single clean power
supply is recommended for the AD9943 and AD9944, but a
separate digital driver supply may be used for DRVDD (Pin 11).
DRVDD should always be decoupled to DRVSS (Pin 12), which
should be connected to the analog ground plane. Advantages of
using a separate digital driver supply include using a lower
voltage (2.7 V) to match levels with a 2.7 V ASIC, and reducing
digital power dissipation and potential noise coupling. If the
digital outputs must drive a load larger than 20 pF, buffering
is the recommended method to reduce digital code transition
noise. Alternatively, placing series resistors close to the digital
output pins may also help reduce noise.
Note: The exposed pad on the bottom of the AD9943/AD9944
should be soldered to the GND plane of the printed circuit board.
24 REF B
23 REF T
22 CCDIN
21 AVSS
D2 1
D3 2
D0
D1
D4 3
20 AVDD
19 SHD
18 SHP
17 CLP O B
D5 4
D6 5
D7 6
D8 7
D9 8
DATA
OUTPUTS
12
D10
D11
910
3V
DRIVER
SUPPLY
3V
ANALOG
SUPPLY
3V
ANALOG
SUPPLY
DRVDD
DRVSS
DVDD
DATACLK
DVSS
PBLK
12 13 14 15 16
5CLOCK
INPUTS
3
SERIAL
INTERFACE
CCDIN
1.0µF
1.0µF 0.1µF
0.1µF
0.1µF
0.1µF
NC = NO CONNECT
32 31 30 29 28 27 26 25
NC
NC
NC
SCK
SDTA
SL
11
02905-019
AD9944
TOP VIEW
(No t t o Scal e)
Rev. C | Page 18 of 20
Data Sheet AD9943/AD9944
OUTLINE DIMENSIONS
Figure 19. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9943KCPZ
−
20°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] CP-32-7
AD9943KCPZRL
−
20°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] CP-32-7
AD9944KCPZ
−
20°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] CP-32-7
AD9944KCPZRL
−
20°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] CP-32-7
1 Z = RoHS Compliant Part.
COM P LIANT T O JEDEC S TANDARDS M O-220- WHHD.
112408-A
1
0.50
BSC
BOTTOM VIEWTOP VIEW
PIN 1
INDICATOR
32
9
16
17
24
25
8
EXPOSED
PAD
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
SEATING
PLANE
0.05 M AX
0.02 NO M
0.20 REF
COPLANARITY
0.08
0.30
0.25
0.18
5.10
5.00 SQ
4.90
0.80
0.75
0.70
FOR PRO P E R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CO NFI GURATIO N AND
FUNCTION DES CRIPT IO NS
SECTION OF THIS DATA SHEET.
0.50
0.40
0.30
0.25 M IN
Rev. C | Page 19 of 20
