MP1482DN-LF-Z - Monolithic Power Systems, Inc.

MP1482

2A, 18V Synchronous Rectified

Step-Down Converter

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The Future of Analog IC Technology

DESCRIPTION

The MP1482 is a monolithic synchronous buck

regulator. The device integrates two 130m

MOSFETs, and provides 2A of continuous load

current over a wide input voltage of 4.75V to

18V. Current mode control provides fast

transient response and cycle-by-cycle current

limit.

An adjustable soft-start prevents inrush current

at turn-on, and in shutdown mode the supply

current drops to 1µA.

This device, available in an 8-pin SOIC

package, provides a very compact solution with

minimal external components.

FEATURES

• 2A Output Current

• Wide 4.75V to 18V Operating Input Range

• Integrated 130m Power MOSFET Switches

• Output Adjustable from 0.923V to 15V

• Up to 93% Efficiency

• Programmable Soft-Start

• Stable with Low ESR Ceramic Output Capacitors

• Fixed 340kHz Frequency

• Cycle-by-Cycle Over Current Protection

• Input Under Voltage Lockout

• 8–Pin SOIC

APPLICATIONS

• Distributed Power Systems

• Networking Systems

• FPGA, DSP, ASIC Power Supplies

• Green Electronics/ Appliances

• Notebook Computers

“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of

Monolithic Power Systems, Inc.

TYPICAL APPLICATION

INPUT

MP1482

BSIN

GND COMP

100

EFFICIENCY (%)

0 1.0 2.0 2.51.50.5

LOAD CURRENT (A)

Efficiency vs

Load Current

OUT

= 3.3V

OUT

= 2.5V

MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

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ORDERING INFORMATION

*For Tape & Reel, add suffix –Z (e.g. MP1482DS–Z);

For RoHS Compliant Packaging, add suffix –LF (eg. MP1482DS–LF–Z)

** For Tape & Reel, add suffix –Z (eg. MP1482DN–Z);

For RoHS Compliant Packaging, add suffix –LF (eg. MP1482DN–LF–Z)

PACKAGE REFERENCE

GND

COMP

TOP VIEW

SOIC8

GND

COMP

TOP VIEW

EXPOSED PAD

ON BACKSIDE

CONNECT TO GND

SOIC8E

ABSOLUTE MAXIMUM RATINGS (1)

Supply Voltage VIN ........................-0.3V to +20V

Switch Node Voltage VSW ............................ 21V

Boost Voltage VBS ..........VSW – 0.3V to VSW + 6V

All Other Pins..................................-0.3V to +6V

Junction Temperature...............................150°C

Continuous Power Dissipation (TA = +25°C)(2)

SOIC8……………………………………….1.38W

SOIC8E………………………………………2.5W

Lead Temperature ....................................260°C

Storage Temperature .............. -65°C to +150°C

Recommended Operating Conditions (3)

Input Voltage VIN ............................4.75V to 18V

Output Voltage VOUT.....................0.923V to 15V

Operating Junct. Temp (TJ)..........-40°C to +85°C

Thermal Resistance (4) θJA θJC

SOIC8..................................... 90 ...... 45... °C/W

SOIC8E .................................. 50 ...... 10... °C/W

Notes:

1) Exceeding these ratings may damage the device

2) The maximum allowable power dissipation is a function of the

maximum junction temperature TJ(MAX), the junction-to-

ambient thermal resistance JA, and the ambient temperature

TA. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by

PD(MAX)=(TJ(MAX)-TA)/ JA. Exceeding the maximum

allowable power dissipation will cause excessive die

temperature, and the regulator will go into thermal shutdown.

Internal thermal shutdown circuitry protects the device from

permanent damage..

3) The device is not guaranteed to function outside of its

operating conditions.

4) Measured on JESD51-7, 4-layer board.

Part Number Package Top Marking Free Air Temperature (TA)

MP1482DS* SOIC8 MP1482DS -40°C to +85°C

MP1482DN** SOIC8E MP1482DN

-40°C to +85°C

MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

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ELECTRICAL CHARACTERISTICS

VIN = 12V, TA = +25°C, unless otherwise noted.

Parameter Symbol Condition Min Typ Max Units

Shutdown Supply Current VEN = 0V 1 3.0 A

Supply Current VEN = 2.0V; VFB = 1.0V 1.3 1.5 mA

Feedback Voltage VFB 4.75V ≤ VIN ≤ 18V 0.900 0.923 0.946 V

Feedback Overvoltage Threshold 1.1 V

Error Amplifier Voltage Gain (5) A

EA 400 V/V

Error Amplifier Transconductance GEA ΔIC = ±10A 800 A/V

High-Side Switch On Resistance (5) R

DS(ON)1 130 m

Low-Side Switch On Resistance (5) R

DS(ON)2 130 m

High-Side Switch Leakage Current VEN = 0V, VSW = 0V 10 A

Upper Switch Current Limit Minimum Duty Cycle 2.4 3.4 A

Lower Switch Current Limit From Drain to Source 1.1 A

COMP to Current Sense

Transconductance GCS 3.5 A/V

Oscillation Frequency Fosc1 305 340 375 KHz

Short Circuit Oscillation Frequency Fosc2 V

FB = 0V 100 KHz

Maximum Duty Cycle DMAX V

FB = 1.0V 90 %

Minimum On Time (5) 220 ns

EN Shutdown Threshold Voltage VEN Rising 1.1 1.5 2.0 V

EN Shutdown Threshold Voltage

Hysteresis 210 mV

EN Lockout Threshold Voltage 2.2 2.5 2.7 V

EN Lockout Hysterisis 210 mV

Input Under Voltage Lockout

Threshold V

IN Rising 3.80 4.10 4.40 V

Input Under Voltage Lockout

Threshold Hysteresis 210 mV

Soft-Start Current VSS = 0V 6 A

Soft-Start Period CSS = 0.1F 15 ms

Thermal Shutdown (5) 160 °C

Note:

5) Guaranteed by design, not tested.

MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

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PIN FUNCTIONS

SOIC8

Pin # SOIC8E

Pin # Name Description

1 1 BS

High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-

Channel MOSFET switch. Connect a 0.01F or greater capacitor from SW to BS to

power the high side switch.

2 2 IN

Power Input. IN supplies the power to the IC, as well as the step-down converter

switches. Drive IN with a 4.75V to 18V power source. Bypass IN to GND with a

suitably large capacitor to eliminate noise on the input to the IC. See Input

Capacitor.

3 3 SW

Power Switching Output. SW is the switching node that supplies power to the

output. Connect the output LC filter from SW to the output load. Note that a

capacitor is required from SW to BS to power the high-side switch.

4 4 GND Ground.

5 5 FB

Feedback Input. FB senses the output voltage to regulate that voltage. Drive FB

with a resistive voltage divider from the output voltage. The feedback threshold is

0.923V. See Setting the Output Voltage.

6 6 COMP

Compensation Node. COMP is used to compensate the regulation control loop.

Connect a series RC network from COMP to GND to compensate the regulation

control loop. In some cases, an additional capacitor from COMP to GND is

required. See Compensation Com ponents.

7 7 EN

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to

turn on the regulator, drive it low to turn it off. Pull up with 100k resistor for

automatic startup.

8 8 SS

Soft-Start Control Input. SS controls the soft start period. Connect a capacitor from

SS to GND to set the soft-start period. A 0.1F capacitor sets the soft-start period

to 15ms. To disable the soft-start feature, leave SS unconnected.

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TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12V, VO = 3.3V, L = 10µH, C1 = 10µF, C2 = 22µF, TA = +25°C, unless otherwise noted.

Startup through Enable

VIN = 12V, VOUT = 3.3V

IOUT = 1A (Resistance Load)

Shutdown through Enable

VIN = 12V, VOUT = 3.3V

IOUT = 1A (Resistance Load)

Light Load Operation

Medium Load Operation

Load Transient

Steady State Test

VIN = 12V, VOUT = 3.3V

IOUT = 0A, IIN= 8.2mA

Heavy Load Operation

Short Circuit

Recovery

Short Circuit

Protection

5V/div.

OUT

2V/div.

10V/div.

1A/div.

5V/div.

OUT

2V/div.

10V/div.

1A/div.

20mV/div.

OUT

20mV/div.

10V/div.

1A/div.

OUT

2V/div.

2A/div.

OUT

2V/div.

2A/div.

OUT

200mV/div.

LOAD

1A/div.

IN, AC

200mV/div.

O, AC

20mV/div.

10V/div.

1A/div.

IN, AC

200mV/div.

O, AC

20mV/div.

10V/div.

1A/div.

IN, AC

20mV/div.

O, AC

20mV/div.

10V/div.

1A/div.

2ms/div. 2ms/div.

2A Load 1A Load No Load

MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

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OPERATION

FUNCTIONAL DESCRIPTION

The MP1482 is a synchronous rectified,

current-mode, step-down regulator. It regulates

input voltages from 4.75V to 18V down to an

output voltage as low as 0.923V, and supplies

up to 2A of load current.

The MP1482 uses current-mode control to

regulate the output voltage. The output voltage

is measured at FB through a resistive voltage

divider and amplified through the internal

transconductance error amplifier. The voltage at

the COMP pin is compared to the switch current

measured internally to control the output

voltage.

The converter uses internal N-Channel

MOSFET switches to step-down the input

voltage to the regulated output voltage. Since

the high side MOSFET requires a gate voltage

greater than the input voltage, a boost capacitor

connected between SW and BS is needed to

drive the high side gate. The boost capacitor is

charged from the internal 5V rail when SW is low.

When the MP1482 FB pin exceeds 20% of the

nominal regulation voltage of 0.923V, the over

voltage comparator is tripped and the COMP

pin and the SS pin are discharged to GND,

forcing the high-side switch off.

LOCKOUT

COMPARATOR

INTERNAL

REGULATORS

ERROR

AMPLIFIER

1.2V

OVP

RAMP

CLK

0.923V

0.3V

CURRENT

COMPARATOR

CURRENT

SENSE

AMPLIFIER

1.1V

SHUTDOWN

COMPARATOR

COMP

GND

OSCILLATOR

340KHz

OVP

IN < 4.1V

EN OK

1.5V

2.5V +

Figure 1—Functional Block Diagram

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APPLICATIONS INFORMATION

COMPONENT SELECTION

Setting the Output Voltage

The output voltage is set using a resistive

voltage divider from the output voltage to FB pin.

The voltage divider divides the output voltage

down to the feedback voltage by the ratio:

2R1R

VV OUTFB +

Where VFB is the feedback voltage and VOUT is

the output voltage.

Thus the output voltage is:

2R1R

923.0VOUT

×=

R2 can be as high as 100k, but a typical value

is 10k. Using the typical value for R2, R1 is

determined by:

)923.0V(83.101R OUT −×= (k)

For example, for a 3.3V output voltage, R2 is

10k, and R1 is 26.1k.

Inductor

The inductor is required to supply constant

current to the output load while being driven by

the switched input voltage. A larger value

inductor will result in less ripple current that will

result in lower output ripple voltage. However,

the larger value inductor will have a larger

physical size, higher series resistance, and/or

lower saturation current. A good rule for

determining the inductance to use is to allow

the peak-to-peak ripple current in the inductor

to be approximately 30% of the maximum

switch current limit. Also, make sure that the

peak inductor current is below the maximum

switch current limit. The inductance value can

be calculated by:

⎟

⎠

⎞

⎜

⎝

⎛−×

Δ×

OUT

Where VOUT is the output voltage, VIN is the

input voltage, fS is the switching frequency, and

IL is the peak-to-peak inductor ripple current.

Choose an inductor that will not saturate under

the maximum inductor peak current. The peak

inductor current can be calculated by:

⎟

⎠

⎞

⎜

⎝

⎛−×

××

OUT

LOADLP V

Lf2

Where ILOAD is the load current.

The choice of which style inductor to use mainly

depends on the price vs. size requirements and

any EMI requirements.

Optional Schottky Diode

During the transition between high-side switch

and low-side switch, the body diode of the low-

side power MOSFET conducts the inductor

current. The forward voltage of this body diode

is high. An optional Schottky diode may be

paralleled between the SW pin and GND pin to

improve overall efficiency. Table 1 lists example

Schottky diodes and their Manufacturers.

Table 1—Diode Selection Guide

Part Number Voltage/Current

Rating Vendor

B130 30V, 1A Diodes, Inc.

SK13 30V, 1A Diodes, Inc.

MBRS130 30V, 1A International

Rectifier

Input Capacitor

The input current to the step-down converter is

discontinuous, therefore a capacitor is required

to supply the AC current to the step-down

converter while maintaining the DC input

voltage. Use low ESR capacitors for the best

performance. Ceramic capacitors are preferred,

but tantalum or low-ESR electrolytic capacitors

may also suffice. Choose X5R or X7R

dielectrics when using ceramic capacitors.

Since the input capacitor (C1) absorbs the input

switching current it requires an adequate ripple

current rating. The RMS current in the input

capacitor can be estimated by:

⎟

⎠

⎞

⎜

⎝

⎛

×−×=

OUT

LOAD1C V

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The worst-case condition occurs at VIN = 2VOUT,

where IC1 = ILOAD/2. For simplification, choose

the input capacitor whose RMS current rating

greater than half of the maximum load current.

The input capacitor can be electrolytic, tantalum

or ceramic. When using electrolytic or tantalum

capacitors, a small, high quality ceramic

capacitor, i.e. 0.1F, should be placed as close

to the IC as possible. When using ceramic

capacitors, make sure that they have enough

capacitance to provide sufficient charge to

prevent excessive voltage ripple at input. The

input voltage ripple for low ESR capacitors can

be estimated by:

⎟

⎠

⎞

⎜

⎝

⎛−××

=Δ

OUT

LOAD

IN V

f1C

Where C1 is the input capacitance value.

Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic, tantalum, or low

ESR electrolytic capacitors are recommended.

Low ESR capacitors are preferred to keep the

output voltage ripple low. The output voltage

ripple can be estimated by:

⎟

⎠

⎞

⎜

⎝

⎛

××

+×

⎟

⎠

⎞

⎜

⎝

⎛−×

=Δ 2Cf8

ESR

OUT

Where C2 is the output capacitance value and

RESR is the equivalent series resistance (ESR)

value of the output capacitor.

In the case of ceramic capacitors, the

impedance at the switching frequency is

dominated by the capacitance. The output

voltage ripple is mainly caused by the

capacitance. For simplification, the output

voltage ripple can be estimated by:

⎟

⎠

⎞

⎜

⎝

⎛−×

×××

OUT

OUT V

2CLf8

V

In the case of tantalum or electrolytic capacitors,

the ESR dominates the impedance at the

switching frequency. For simplification, the

output ripple can be approximated to:

ESR

OUT

OUT R

V×

⎟

⎠

⎞

⎜

⎝

⎛−×

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP1482 can be optimized for a wide range of

capacitance and ESR values.

Compensation Components

MP1482 employs current mode control for easy

compensation and fast transient response. The

system stability and transient response are

controlled through the COMP pin. COMP pin is

the output of the internal transconductance

error amplifier. A series capacitor-resistor

combination sets a pole-zero combination to

control the characteristics of the control system.

The DC gain of the voltage feedback loop is

given by:

OUT

EACSLOADVDC V

AGRA ×××=

Where AVEA is the error amplifier voltage gain;

GCS is the current sense transconductance and

RLOAD is the load resistor value.

The system has two poles of importance. One

is due to the compensation capacitor (C3) and

the output resistor of the error amplifier, and the

other is due to the output capacitor and the load

resistor. These poles are located at:

VEA

1P A3C2

f××π

LOAD

2P R2C2

f××π

Where GEA is the error amplifier transconductance.

The system has one zero of importance, due to the

compensation capacitor (C3) and the compensation

resistor (R3). This zero is located at:

3R3C2

f1Z ××π

The system may have another zero of

importance, if the output capacitor has a large

capacitance and/or a high ESR value. The zero,

due to the ESR and capacitance of the output

capacitor, is located at:

ESR

ESR R2C2

f××π

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In this case (as shown in Figure 2), a third pole

set by the compensation capacitor (C6) and the

compensation resistor (R3) is used to

compensate the effect of the ESR zero on the

loop gain. This pole is located at:

3R6C2

f3P ××π

The goal of compensation design is to shape

the converter transfer function to get a desired

loop gain. The system crossover frequency

where the feedback loop has the unity gain is

important. Lower crossover frequencies result

in slower line and load transient responses,

while higher crossover frequencies could cause

system instability. A good rule of thumb is to set

the crossover frequency below one-tenth of the

switching frequency.

To optimize the compensation components, the

following procedure can be used.

1. Choose the compensation resistor (R3) to set

the desired crossover frequency.

Determine the R3 value by the following

equation:

OUT

CSEA

OUT

CSEA

f1.02C2

f2C2

3R ×

×××π

<×

××π

Where fC is the desired crossover frequency

which is typically below one tenth of the

switching frequency.

2. Choose the compensation capacitor (C3) to

achieve the desired phase margin. For

applications with typical inductor values, setting

the compensation zero, fZ1, below one-forth of

the crossover frequency provides sufficient

phase margin.

Determine the C3 value by the following equation:

f3R2

3C ××π

Where R3 is the compensation resistor.

3. Determine if the second compensation

capacitor (C6) is required. It is required if the

ESR zero of the output capacitor is located at

less than half of the switching frequency, or the

following relationship is valid:

R2C2

ESR

××π

If this is the case, then add the second

compensation capacitor (C6) to set the pole fP3

at the location of the ESR zero. Determine the

C6 value by the equation:

R2C

6C ESR

External Bootstrap Diode

An external bootstrap diode may enhance the

efficiency of the regulator, and it will be a must

if the applicable condition is:

z VOUT is 5V or 3.3V, and duty cycle is high:

OUT

V>65%

In these cases, an external BST diode is

recommended from the output of the voltage

regulator to BST pin, as shown in Figure.2

MP1482

BST

5V or 3.3V

OUT

External BST Diode

IN4148

Figure 2—Add Optional External Bootstrap

Diode to Enhance Efficiency

The recommended external BST diode is

IN4148, and the BST cap is 0.1~1µF.

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TYPICAL APPLICATION CIRCUIT

INPUT

MP1482

BSIN

GND COMP

Figure 3—MP1482 with 3.3V Output, 22µF/6.3V Ceramic Output Capacitor

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PCB LAYOUT GUIDE

PCB layout is very important to achieve stable

operation. It is highly recommended to duplicate

EVB layout for optimum performance.

If change is necessary, please follow these

guidelines and take Figure 4 for reference.

1) Keep the path of switching current short and

minimize the loop area formed by input cap,

high-side MOSFET and low-side MOSFET.

2) Bypass ceramic capacitors are suggested

to be put close to the Vin Pin.

3) Ensure all feedback connections are short

and direct. Place the feedback resistors

and compensation components as close to

the chip as possible.

4) Route SW away from sensitive analog

areas such as FB.

5) Connect IN, SW, and especially GND

respectively to a large copper area to cool

the chip to improve thermal performance

and long-term reliability.

INPUT

4.75V to 18V

OUTPUT

C3 D1

(optional)

MP1482

BSIN

GND COMP

MP1482 Typical Application Circuit

Top Layer Bottom Layer

Figure 4—MP1482 Typical Application Circuit and PCB Layout Guide

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PACKAGE INFORMATION SOIC8E (EXPOSED PAD)

SEE DETAIL "A"

0.0075(0.19)

0.0098(0.25)

0.050(1.27)

BSC

0.013(0.33)

0.020(0.51)

SEATING PLANE

0.000(0.00)

0.006(0.15)

0.051(1.30)

0.067(1.70)

TOP VIEW

FRONT VIEW

SIDE VIEW

BOTTOM VIEW

NOTE:

1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

BRACKET IS IN MILLIMETERS.

2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS.

3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH

OR PROTRUSIONS.

4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)

SHALL BE 0.004" INCHES MAX.

5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.

6) DRAWING IS NOT TO SCALE.

0.089(2.26)

0.101(2.56)

0.124(3.15)

0.136(3.45)

RECOMMENDED LAND PATTERN

0.213(5.40)

0.063(1.60)

0.050(1.27)

0.024(0.61)

0.103(2.62)

0.138(3.51)

0.150(3.80)

0.157(4.00)

PIN 1 ID

0.189(4.80)

0.197(5.00)

0.228(5.80)

0.244(6.20)

0.016(0.41)

0.050(1.27)

0o-8o

DETAIL "A"

0.010(0.25)

0.020(0.50) x 45o

0.010(0.25) BSC

GAUGE PLANE

MP1482 – 2A, 18V SYNCHRONOUS RECTIFIED, STEP-DOWN CONVERTER

NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.

Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS

products into any application. MPS will not assume any legal responsibility for any said applications.

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PACKAGE INFORMATION SOIC8

0.016(0.41)

0.050(1.27)

-8

DETAIL "A"

0.010(0.25)

0.020(0.50) x 45

SEE DETAIL "A"

0.0075(0.19)

0.0098(0.25)

0.150(3.80)

0.157(4.00)

PIN 1 ID

0.050(1.27)

BSC

0.013(0.33)

0.020(0.51)

SEATING PLANE

0.004(0.10)

0.010(0.25)

0.189(4.80)

0.197(5.00)

0.053(1.35)

0.069(1.75)

TOP VIEW

FRONT VIEW

0.228(5.80)

0.244(6.20)

SIDE VIEW

RECOMMENDED LAND PATTERN

0.213(5.40)

0.063(1.60)

0.050(1.27)

0.024(0.61)

NOTE:

1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN

BRACKET IS IN MILLIMETERS.

2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS.

3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH

OR PROTRUSIONS.

4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)

SHALL BE 0.004" INCHES MAX.

5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA.

6) DRAWING IS NOT TO SCALE.

0.010(0.25) BSC

GAUGE PLANE