ky7 SGS-THOMSON 28530 SERIAL COMMUNICATIONS CONTROLLER Thank you for your interest in the SCC, one of the most versatile and most popular Serial Data Com- munications |Cs. This document is intended to pro- vide answers to all technical questions about the 28530 Serial Communications Controller. Please ready this Preface where we try to anticipate your questions. a Ifyou are new to serial data communications, you will need additional tutorial information. Of the many introductory texts on this subject, Techni- cal Aspects of Data Communications by John E. McNamara, published by Digital Press (DEC) 1982, is one of the best. a If you have designed with simpier UARTs and USARTs, and HDLC/SDLC devices, the SCC of- fers you far greater flexibility, but also requires an in-depth study and understanding of the impact and the use of its many powerful features. This manual contains important information. PLOC44 If you are familiar with the Z80-SIO, you will feel right at home with the SCC, for it is really a func- tionally enhanced superset of the Z80-SIO. (Ordering Information at the end of the datasheet) PDIP-40 CDIP-40 Most users read only chapters that are of interest to them. If you are designing the microcomputer hard- Figure 1 : Logic Functions. ware structure using the SCC as a peripheral, you will want to read the Initialisation Worksheet and In- terrupt Routine Sections. ; . ++ D, TDA L_ | SERIAL If you are programming a system using the SCC, +41 0, RxDA } DATA you will be more interested, on the Initialization >| 05 TRKOA |@ | CHANNEL Worksheet Section. pata sus, +>) 4 ATXGA =} CLOCKS +1 SYNCA |e CHA Points To Watch Out For : +o wreon | | conTmoLs 1. Follow the worksheet for initialization (page ). 7% DTAREGA |e | OR Unexplainable operations may occur if this pro- 7% ATSA [ / OTHER cedure is not followed. rns {= FO 2. Watch out for Write Recovery time violation (In- AND RESET 7 a Foe | \ seruat terfacing Section). Both the CPU clock rate and contron { 9! cE os a7} DATA the SCC clock ate will affect the Write Recove- + 0 Trxce je | CHANNEL ry time. aw RIB =} cLocKs 3. Ensure Mode bits are not changed when writing + INTACK SYNCB fa cHB Commands. (Register Overview page 75). Each mneneuen | a et WREQR | CONTROLS Mode bit affects only one function and a Com- + ro BTRREGB) | FOR MODEM, mand bit entry requires a rewrite of the entire re- RTS8 |e | OER gister ; therefore, care must be taken to insure 20530 TSB + the integrity of the Mode bits whenever a new p08 le command Is issued. 4. Data must be valid prior to falling edge of WR or f f f DS. +5V GND PCLK 5. If not used, INTACK should be tied high. Januar 1989 1/93 44928530 CAPABILITIES a Two independent full-duplex channels. a Synchronous/Isosynchronous data rates : - Upto 1/4 of the PCLK (i.e., 1 Mbit/sec. maxi- mum data rate with 4 MHz PCLK. Using ex- ternal phase-lock loop. - Up to 375 Kbit/sec. with a 6 MHz clock rate. Up to 250 Kbit/sec. with a 4 MHz clock rate (FM encoding using digital phase-locked loop). - Up to 187.5 Kbit/sec. with a 6 MHz clock rate Up to 125 Kbit/sec. with a 4 MHz clock rate (NRZI encoding using digital phase-locked loop). a Asynchronous capabilities : - 5,6, 7, or 8 bits per character - 1, 1-1/2, or 2 stop bits - Odd or even parity - Times 1, 16, 32, or 64 clack modes - Break generation and detection - Parity, overrun and framing error detection. a Byte-oriented synchronous capabilities : - Internal or external character synchronization - 1 or 2sync characters (6 or 8 bits/character) in separate registers - Automatic Cyclic redundancy check (CRC) generation/detection. = SDLC/HDLC capabilities - ~ Abort sequence generation and checking - Automatic zero insertion and deletion - Automatic flag insertion between messages - Address field recognition - [field residue handling - CRC generation/detection - SDLC loop mode with EOP recognition/loop entry and exit. = Receiver data registers quadruply buffered. Transmitter data registered double buffered. a NRZ, NR2ZI, or FM encoding/decoding. a Baud-rate generator in each channel. a Digital phase-locked loop for clock recovery. a Crystal oscillator. 2/93 57 S&S-THOMSON GENERAL DESCRIPTION The SCC Serial Communications Controller is a dual-channel, multiprotocol data communications peripheral designed for use with 8-bit and 16-bit microprocessors. The SCC functions as a serial-to- parallel, parallel-to-serial converter/controller. The SCC can be software-configured to satisfy a wide variety of serial communications applications. The device contains a variety of new, sophisticated in- ternal functions including on-chip baud rate gene- rators, digital phase-lock loops, and crystal oscilla- tors, which dramatically reduce the need for exter- nal logic. The SCC handles asynchronous formats, Synchro- nous byte-oriented protocols such as IBM Bisync, and Synchronous bit-oriented protocols such as HDLC and IBM SDLC. This versatile device sup- ports virtually any serial data transfer application (te- lecommunications, cassette, diskette, tape drivers, etc.). The device can generate and check CRC codes in any Synchronous mode and can be programmed to check data integrity in various modes. The SCC al- so has facilities for modem controls in both chan- nels. in applications where these controls are not needed, the modem controls can be used for gene- ral-purpose V/O. With access to 14 Write registers and 7 Read regis- ters per channel, the user can configure the SCC so that it can handle all asynchronous formats regar- dless of data size, number of stop bits, or parity re- quirements. The SCC accommodates all synchro- nous formats including character, byte, and bit- oriented protocols. Within each operating mode, the SCC also allows for protocol variations by checking odd or even pa- rity bits, character insertion or deletion, CRC gene- ration and checking/oreak and abort generation and detection, and many other protocol-dependent fea- tures. The SCC 28530 is designed for non-multiplexed buses and is easily interfaced to CPUs such as the 8080, Z80, 6800, 68000 and *Multibus. MICROELECTRONICS 450GENERAL DESCRIPTION (cont'd) Figure 2 and Figure 5 show block diagrams of the SCC. Received data enters the receive data pins and follows one of severai data paths, depending on the state of the control logic. The contents of the registers and the state of the external control pins establish the internal control logic. Transmitted da- ta follows a similar pattern of control, register, and external pin definition. PIN DESCRIPTIONS The SCC pins are divided into seven functional groups : Address/Data, Bus Timing and Reset, De- vice Control, Interrupt, Serial Data (both channels), Peripheral Control (both channels), and Clocks (both channels). Figures 3 and 4 show the Pin Confi- Figure 2 : SCC Block Diagram. 28530 guration in both the proposed packages, Dual in Line and Chip Carrier. The Address/Data group consists of the bidirectio- nal lines used to transfer data between the CPU and the SCC. The direction of these lines depends on whether the SCC is selected and whether the ope- ration is a Read or a Write. The Timing and Control groups designate the type of transaction to occur and when this transaction will occur. The interrupt group provides inputs and out- puts to conform to the bus specifications for han- dling and prioritizing interrupts. The remaining groups are divided into Channel A and Channel B groups for serial data (transmit or receive), periphe- BAUD RATE GENERATOR a a] ! SERIAL DATA CHANNEL A INTERNAL CONTROL Locic CHANNEL A REGISTERS < tr | CHANNEL cLOcKs pe SYNC * WAITIREQUEST DISCRETE CONTROL e | MODEM, DMA, Of aE STATUS Pe? OTHER CONTROLS DOR A | Dara <8 aus vo INTERNAL BUS CONTROL cy crscrere CONTROL < | movem, oma, on a STATUS p / OTHER CONTROLS 8 i INTERRUPT CONTROL Locic iNTEARUPT CONTROL LINES tt +5 GNOPCLK CHANNEL B REGISTERS -~ | . j SERIAL DATA CHANNEL B Vo NY pare | CHANNEL cocks e SvNC P WAITIREQUEST BAUD RATE GENERATOR 5 3/93 yf Sieonacmoncs 451Z8530 PIN DESCRIPTION (cont'd) ral control (such as DMA or modem), and the input and output lines for the receive and transmit clocks. Here below are described the pin functions of the 28530 Serial Communications Controller. A/B. Channel A/ChannelB Select (input, Channel A active HIGH). This signal selects the channel in which the Read or Write operation occurs. CE. Chip Enable (input, active LOW). This signal se- lects the SCC for operation. It must remain active throughout the bus transaction. DO-D7. Data Lines (bidirectional, 3-state). These I/O lines carry sata or control information to and from the SCC. D/C. Data/Control (input, Data active HIGH). This signal defines the type of information transfer per- formed by the SCC : data or control. RD. Read (input, Active LOW). This signal indicates a Read operation and when the SCC is selected, enables the SCC bus drivers. During the interrupt acknowledge cycle, this signal gates the interrupt vector onto the bus if the SCC is the highest priori- ty device requesting an interrupt. WR. Write (input, active LOW). When the SCC is selected, this signal indicates a Write operation. The coincidence of RD and WR is interpreted as a Re- set. Figure 3 : DIP Pin Connections. CTSA, CTSB. Clear to Send (inputs, active LOW). If these pins are programmed as auto enables, a LOW on these inputs enables the respective trans- mitters. If not programmed as auto enables, they may be used as general-purpose inputs. Both inputs are Schmitttrigger buffered to accommodate slow rise-time inputs. The SCC detects transitions on these inputs and can interrupt the CPU on either jo- gic level transitions. DCDA, DCDB. Data Carrier Detect (inputs, active LOW). These pins function as receiver enables if they are programmed as auto enable bits ; other- wise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buffered to acco- modate slow rise-time signals. The SCC detects transitions on these pins and can interrupt the CPU on either logic level transitions. DTR/ REQA, DTR/ REQB. Data Carrier Detect (in- puts, active LOW). These pins function as receiver enables if they are programmed into the DTR bit. They can also be used as general-purpose outputs (transmit) or as request lines for the DMA controller. The SCC allows full duplex DMA transfers. IEI. Interrupt Enable In (input, active HIGH). IEI is used with IEO to form an interrupt daisy chain when there is more than one interrupt-driven device. A HIGH on IEI indicates that no other higher priority Figure 4 : Chip Carrier Pin Connection. oC! 0 [1] oy bs [] 2 a9 [] 0, o; (J 3 af] po, [J] 37 [J 9% Ego aeoroa & & int (J 5 36 [J aD @5 632 8 4443 a2 res ico C] 5 3s [) wr ie (J 7 4 a intack [] 8 33 [J cE vec [] 9 32] pc WIREOA 28530 WIREQA Qj. sce xO nD synca (J 11 30 [] wines RTxCA (] 12 29 [DJ svnce axpa (J 13 28 [] atxce Taxca () 4 27] rxpe txoa [I] 15 26 [} Trace eo 6 28 A 18 19 20 21 22:23:26 25 26 27 28 RTSA LJ 17 24} DTR/REQB 2 crsa (] 8 23 [ atse eee cf CES ocoa [] 19 22) ctse % peek (| 20 21 [[] ocos 488 (7 SGS-THOMSON yf MITROELECTRONICS 452PIN DESCRIPTION (cont'd) device has an Interrupt Under Service (US) oris re- questing an interrupt. IEO. Interrupt Enable Out (output, active HIGH). IEO is HIGH only if IEl is HIGH and the CPU is not ser- vicing an SCC or SCC interrupt, or the controller is not requesting an interrupt (interrupt acknowledge cycle only). EO is connected to the next lower prio- rity devices IEI input and thus inhibits interrupts from lower priority devices. INTACK. Interrupt Acknowledge (input, active LOW). This signal indicates an active interrupt ac- knowledge cycle. During this cycle, the interrupt dai- sy chain settles. When RD or DS becomes active, the SCC places an interrupt vector on the data bus (if Elis HIGH). INTACK is latched by the rising edge of AS or PCLK. INT. Interrupt Request (output, open-drain, active LOW). This signal is activated when the SCC is re- questing an interrupt. PCLK. Clock (input). This is the master clock used to synchronize internal signals. PCLK is not requi- red to have any phase relationship with the master system clock. PCLK is a TTL level signal. RTSA, RTSB. Request to Send (outputs, active LOW). When the Request to Send (RTS) bit in Write Register 5 (Figure 48) is set, the RTS signal goes LOW. When the RTS bit is reset in the Asynchro- nous mode and auto enables is on, the signal goes HIGH after the transmitter is empty. In Synchronous mode or in Asynchronous mode with auto enables off, the RTS pins strictly follow the state of the RTS bit. Both pins can be used as general-purpose out- puts. RTxCA, RTxCB. Receive/ Transmit Clocks (inputs, active LOW). The functions of these pins are under Program control. In each channel, RTxC may sup- ply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock for the di- gital phase-locked loop (refer to Section 4 for bit configurations). This pins can also be programmed for use the respective SYNC pins as a crystal os- cillator. The receive clock may be 1, 16, 32, or 64 times the data rate in asynchronous modes. RxDA, RxDB. Receive Data (inputs, active HIGH). These input signals receive serial data at standard TTL levels. 28530 SYNCA, SYNCB. Synchronization (inputs/outputs, active LOW). These pins can act as either inputs, outputs, or as part of the crystal oscillator circuit. In the Asynchronous Receive mode (crystal oscillator option not selected), these pins are inputs similar to CTS and DCD. In this mode, transitions on these lines affect the state of the Sync/ Hunt status bits in Read Register 0 (Figure 59), but have no other func- tion. In External Synchronization mode with the crystal oscillator not selected, these lines also act as inputs. in this mode, SYNC must be driven LOW two re- ceive clock cycles after the last bit in the sync cha- racter is received. Character assembly begins on the rising edge of the receive clock immediately pre- ceding the activation of SYNC. In the Internal Synchronization mode, (Monosync and Bisync) with the crystal oscillator not selected, these pins act as outputs and are active only during the part of the receive clock cycle in which sync cha- racters are recognized. The sync condition is not lat- ched, so these outputs are active each time a sync character is recognized (regardless of character boundaries). In SDLC mode, these pins act as out- puts and are valid on receipt of a flag. TRxCA, TRxCB. Transmit/ Receive Clocks (inputs or outputs, active LOW). The functions of these pins are under program control. TRxC may supply the receive clock or the transmit clock in the Input made or supply the output of the digital phase-locked loop, the crystal oscillator, the baud rate generator, or the transmit clock in the output mode. (Refer to Sec- tion 4 for bit configuration). TxDA, TxDB. Transmit Data (outputs, active HIGH). This output signal transmits serial data at standard TTL levels. W/ REQA, W/ REQB. Wait/ Request (outputs, open drain when programmed for Wait function, driven HIGH or LOW when programmed for a Request function). These dual-purpose outputs can be pro- grammed as Request (receive) lines for a DMA con- troller or as Wait lines to synchronize the CPU to the SCC data rate. The reset state is Wait. The SCC al- lows full duplex DMA transfer. L577 SGS-THOMSON 5/98 MICROELECTRONICS 453Z8530 OVERVIEW The SCC internal structure provides all the interrupt and control logic necessary to interface with non- multiplexed bus. Interface logic is also provided to monitor modem or peripheral control inputs and out- puts. All of the control signals are general purpose and can be applied to various peripheral devices as well as used for modem control. The center for data activity revolves around the in- ternal read and write registers. The programming of these registers provides the SCC with functional personality ; i.e., register values can be assigned before or during program sequencing to determine how the SCC will establish a given communication protocol. Register Functions All modes of communication are established by the bit values of the write registers. As data is received or transmitted, read register values may change. These changed values can promote software action or internal hardware action for further register changes. The register set for each channel includes 14 write registers and seven read registers. Ten write regis- ters are used for control, two for sync character ge- neration, and two for baud rate generation. In addi- tion there are two write registers which are shared by both channels ; one is the interrupt vector regis- ter and one is the master interrupt control and reset register. Four read registers indicate status informa- tion, two are for baud rate generation, and one for the receive buffer. In addition there are two read re- gisters which are shared by both channels ; one for the interrupt pending bits and one for interrupt vec- tor. Table 1 lists the assigned functions for each read and write register. The SCC contains only one WR2 {interrupt vector) and one WR9 (master interrupt control). Both registers are accessed and shared by Table 1 : Register Set. Read Register Functions RRO Transmitt/ Receive buffer status, and Ex- ternal status RR1 Special Receive Condition status, residue codes, error conditions RR2 Moditied (Channel B only) interrupt vec- tor and Unmodified interrupt vector (Channel A only) RR3 Interrupt Pending bits (Channel A only) RR8& Receive buffer RR1i0 ~ Miscellaneous XMTR, RCVR status para- meters RR12 Lower byte of baud rate generator time constant RR13 ~Upper byte of baud rate generator time constant RR15 ~~ External/ Status interrupt control informa- tion Write Register Functions WRO Command Register, CRC initialization re- sets for various modes WRI1 Interrupt conditions, Wait / DMA request control WRe Interrupt vector (access through either channel) WR3 Receive / Control parameters, number of bits per character, RxCRC enable WR4 Transmit / Receive miscellaneous para- meters and codes, clock rate, number of sync characters, stop bits, parity WR5 Transmit parameters and control, number of Tx bits per character, TxCRC enable WR6 Sync character (1 st byte) or SDLC flag WR8 Transmitt buffer WR9 Master interrupt control and reset (acces- sed through either channel), reset bits. control interrupt daisy chain either channel. Chapter 7 provides a detailed bit le- R10 Miscellaneous. transmitter/receiver con gend and description of each register. CRC re sat ; 9: WR11. Clock mode control, source of Rx and Tx clocks WRi2 Lower byte of baud rate generator time constant WR13 Upper byte of baud rate generator time constant WR14 = ~Miscellaneous control bits : baud rate generator, Phase-Locked Loop control auto echo, local loopback WR14__ External/ Status interrupt control informa: tion-control external conditions causing interrupts 6/93 L597 Sigactomanes 454OVERVIEW (cont'd) Data Paths Figure 6 illustrates the data paths involved in the six major areas of the SCC : a Transmitter a Receiver a Baud rate generator a DPLL a Clocking options a Data encoding All communication modes are established by pro- gramming the write registers. As data is received or transmitted, read register values may change, alte- ring the direction of the data path. These changed values can promote software action or internal hard- ware action for further register changes. Transmitter. The transmitter has an 8-bit Transmit Data register (WR8) loaded from the internal data bus and a Transmit Shift register loaded from either WR6, WR7, or the Transmit Data register. In byte- oriented modes, WR6 and WR7 can be program- med with sync characters. In Monosync mode, an 8-bit or 6-bit sync character is used (WR6), whereas a 16-bit syne character is used (WR6 and WR7) in Bisync mode. In bit-oriented synchronous modes, the flag contained in WR7 is loaded into the Trans- mit Shift register at the beginning and end of a mes- sage. If asynchronous data is processed, WR6 and WR7 are not used and the Transmit Shift register is for- matted with start and stop bits shifted out to the transmit multiplexer at the selected clock rate. Syn- chronous data (except SDLC/HDLC) is shifted to the CRC generator as well as to the transmit multiplexer. SDLC/HDLC data is shifted to the CRC Generator and out through the zero insertion logic (which is di- sabled while the flags are being sent). A "0" is inser- ted in all address, control, information, and frame check fields following five contiguous "1s" in the da- tastream. The result of the CRC generator for SDLC data is also routed through the zero insertion logic and then to the transmit multiplexer. Receiver. The receiver has a three deep 8-bit Data FIFO (paired with an 8-bit Error FIFO), and an 8-bit shift register. This arrangement creates a 3-byte de- lay time, which allows the CPU time to service an in- terrupt at the beginning of a block of high-speed da- ta. With each Receive Data FIFO, the error FIFO stores parity and framing errors and other types of status information. The error FIFO is readable in Read Register 1. Incoming data is routed through one of several paths depending on the mode and character length. In 28530 Asynchronous mode, serial data enters the 3-bit de- lay (Figure 5) if the character length of seven or eight bits is selected. If a character length of five or six bits is selected, data enters the receive shift register di- rectly. In synchronous modes, the data path is determined by the phase of the receive process currently in ope- ration. A synchronous receive operation begins with a hunt phase in which a bit pattern that matches the programmed sync characters (6-bit, 8-bit, or 16-bit is searched). The incoming data then passes through the Sync re- gister and is compared to a sync character stored in WRE6 or WR7 (depending on which mode it is in). The monosync mode matches the sync character programmed in WR7 and the character assembled in the Receive Sync register to establish synchroni- zation. Synchronization is achieved differently in the Bisync mode. Incoming data is shifted to the Receive Shift register while the next eight bits of the message are assembled in the Receive Sync register. If these two characters match the programmed characters in WR6 and WR7, synchronization is established. In- coming data can then bypass the Receive Sync re- gister and enter the 3-bit delay directly. The SDLC mode of operation uses the Receive Sync register to monitor the receive data stream and to perform zero deletion when necessary ; i.e., when five continuous "1s" are received, the sixth bit is ins- pected and deleted from the data stream if it is "0". The seventh bit is inspected only if the sixth bit equais one. If the seventh bit is "0", a flag sequence has been received and the receiver is synchronized to that flag. If the seventh bit is a'"1", an abort or an EOP (End Off Poll) is recognized, depending on the selection of either the normal SDLC mode or SDLC Loop mode. The same path is taken by incoming data for both SDLC modes. The reformatted data enters the 3-bit delay and is transferred to the Receive Shift regis- ter. The SDLC receive operation begins in the hunt phase by attempting to match the assembled cha- racter in the Receive Shift Register with the flag pat- tern in WR7. Then the flag character is recognized, subsequent data is routed through the same path, regardless of character length. Either the CRC - 16 or CRC - SDLC cyclic redun- dancy check (CRC) polynomial can be used for both Monosync and Bisync modes, but only the CRC - SDLC polynomial is used for SDLC operation. The data path taken for each mode is also different. yz S&S-THOMSON 788 MICROELECTROMICS 455OVERVIEW (cont'd) Figure 5 : Data Paths. 28530 tuoi THoso ONAS W9013 WOLVUANED HE <emmmmond ory 49073 140 -4 xo Pb 5 rac 13079 ~ 49070 LISHEL J inaino wa awe wOOTD AABDaN p+ ins ine worwwgnae we 4naino 1160 Le igus PEYOUEL Aviad uo BWI 10$ 49012 LINEN iguig'sl AMaSMI OWAT sag a aaa130 owaz 8 W3LSIDIE DNAS A103 L510 9H OMAS Aviad a2 XW LIWSNYHA | nivig | wasting sis | AMEN | + - nein Andel YALNAOD | NMOO LEH wOuvuaN ona oa NOLWUANaD UD Ownage we woud viva (aNASIG) SNOW LAH 43181034 | waisioan ANWASNOD BAIL ANVASNOO 3001 Or. TWNBRLM | viva LIWSNEL | | SNAG BUA | ONAS UA | SA139390 aAnae emo an ey AENOD 3M VANNVHS H3HLO OL $09 VIVO TWNUBIN? juaa.ane viva on! on ned WICROELECTROMES iy SGS-THOMSON 8/93 456OVERVIEW (cont'd) Bisync protocol is a byte-oriented operation that re- quires the CPU to decide whether or not a data cha- racter is to be included in CRC calculation. An 8-bit delay in all synchronous modes except SDLC is al- lowed for this process. In SDLC mode, all bytes are included in the CRC calculation. Baud Rate Generator. Each channel in the SCC contains a programmable baud rate gene-rator. Each generator consists of two 8-bit, time-constant registers forming a 16-bit time constant, a 16-bit down counter, and a flip-flop on the output that makes the output a square wave. On start-up, the flip-flop on the output is set High so that it starts ina known state, the value in the time-constant register is again loaded into the counter, and the counter be- gins counting down. When a count of zero is rea- ched, the output of the baud rate generator toggles, the value in the time-constant register is loaded in- to the counter, and the process starts over. The time constant can be changed at any time, but the new value does not take effect until the next load of the counter. No attempt is made to synchronize the loading of a new time constant with the clock used to drive the generator. When the time constant is to be changed, the generator should be stopped by writing to an en- Figure 6 : Data Encoding Methods. 28530 able bit in WR14. This ensures the loading of the correct time constant. If neither the transmit clock nor the receive clock are programmed to come from the TRXC pin, the out- put of the baud rate generator may be made availa- ble for external use on the TRXC pin. Digital Phase-locked Loop (DPLL). The SCC contains a digital phase-locked loop that can be used to recover clock information from a data stream with NRZI or FM coding. The DPLL is driven by a clock nominally 32 (NRZI) or 16 (FM) times the da- ta rate. The DPLL uses this clock, along with the da- ta stream, to construct a receive clock for the data. This clock can then be used as the SCC receive clock, the transmit clock, or both. Clocking Options. The SCC can select several clock sources for internal and external use. Write Register 11 is the Clock Mode Control register for both the receive and transmit clocks. It determines the type of signal on the SYNC and RTxC pins and the direction of the TRxC pin. Write Register 11 also controls the output of the baud rate generator, the DPLL output, and the se- lection of either a TT1 or XTAL output for the RTxC pin. DATA 1 1 9 0 1 0 &57 S&S:THOMSON 9/93 MICROELECTRONICS 45728530 OVERVIEW (cont'd) Data Encoding. Figure 6 illustrates the four enco- ding methods used by the SCC. In NRZ encoding, a"1"is represented by a High level and a "0" is rep- resented by a Low level. In NRZI encoding, a"1" is represented by no change in level and a "0" is rep- resented by a change in level. In FM1 (more pro- perly, biphase mark), a transition occurs at the be- ginning of every bit cell. A'"1" is represented by an additional transition at the center of the bit cell and a "0" is represented by the absence of a tran-sition at the center of the bit cell. In FMO (more properly, biphase space), a transition occurs at the beginning of every bit cell. A "0" is represented by an additio- nal transition at the center of the bit cell and a"1" is represented by the absence of a transition at the center of the bit cell. In addition to these four methods, the SCC can be used to decode Manchester (biphase level) data by using the DPLL in the FM mode and programming the receiver for NRZ data. Manchester encoding al- ways produces a transition at the center of the bit cell. If the transition is Low to High, the bit is 0. If the transition is High to Low, the bit is "1". Data Communications Capabilities SCC logic handles all asynchronous, byte-oriented synchronous, and bit-oriented synchronous modes of operation. The following section briefly describes asynchronous, synchronous, and SDLC modes of communication. Asynchronous. Figure 7 represents a typical asyn- chronous message format using one start bit, seven data bits, one parity bit, and one stop bit. A start bit is a High-to-Low transition detected by an asynchro- nous receiver and is actually an information bit no- tifying the receiver of an incoming message. The start bit also initiates a clock circuit to provide latching pulses during expected data bit intervals. The parity bit is provided for error checking. The pa- rity bit is calculated in both the receiver and the Figure 7 : Asynchronous Message Format. transmitter ; the two results are compared to ensure that the expected and the actual bit values match. The stop bit returns the message unit to the quies- cent marking state ;i.e., a constant high state condi- tion lasts until the next High-to-Low start bit indi- cates an incoming data byte. During reception, the start and stop bits are stripped away and checked for errors, jeaving only the working data for CPU in- teraction. The number of selected bits for each asynchronous function may differ between the transmitter and the receiver. Monosync Mode. Monosync and Bisync modes re- quire clocking information to be transmitted along with the data either by a method of encoding data that contains clocking information, or by a modem that encodes or decodes clock information in the modulation process. Start and stop bits are not required in synchronous modes. All bits are used to transmit data. This eli- minates the "waste" characteristic of asynchronous communication. Figure 8 shows the character format for synchro- nous transmission. For example, bits 1-8 might be one character and bits 9-13 part of another charac- ter ; or bit 1 might be part of one character, bits 2-9 part of a second character, and bits 10-13 part of a third character. The framing (where each character begins) of each character is accomplished by defi- ning a synchronization character, commonly called a "sync character. The CPU places the receiver in Hunt mode when- ever transmission begins (or whenever a data dro- pout has occurred and the hardware determines that resynchronization is necessary). In Hunt mode, the receiver shifts a bit into the Receive Shift regis- ter and compares the contents of the Receive Shift register and with the sync character (stored in ano- ther register), repeating the process until a match occurs. When a match occurs, the receiver begins transferring bytes to the receive FIFO. START Do Dy De D3 D o PARITY STOP x x x x x xX xX = HIGH OR LOW 10/93 {57 SGS-THOMSON yy MICROELECTROMICS 458OVERVIEW (cont'd) Bisynchronous Mode. The Bisync mode of opera- tion (Figure 9) is similar to the Monosync mode, ex- cept that two sync characters are provided instead of one. Bisyne attemps a more structured approach to synchronization through the use of special cha- racters as message "headers" or "trailers". A detai- led description of IBMs Bisync can be found in McNamaras Book (See Preface). External Syne Mode. External Sync mode (Figu- re 10) eliminates the use of sync characters in the serial data stream by providing an external sync si- gnal to mark the beginning of a data field ; i.e., an external input pin (Sync) waits for an active state change to indicate the beginning of an information field. SDLC Mode. Synchronous Data Link Control mode (SDLC) uses synchronization characters similar to Bisync and Monosync modes (such as flags and pad characters), but it is a bit-oriented protocol instead of byte-oriented protocol. Any data communication link involves at least two stations. The station that is responsible for the data link and issues the commands to control the link is called the "primary station". The other station is a secondary station. Not all information transfers need to be initiated by a primary station. In SDLC mode, a secondary station can be the initiator. The basic format for SDLC is a frame (Figu- re 11).The information field is not restricted in format or content and can be of any reasonable length (in- cluding zero). Its maximum length is that which can be expected to arrive at the receiver error-free most of time. Hence, the determination of maximum length is a function of communication channel error rate. Figure 8 : Monosync Data Character Format. Z8530 The two flags that delineate the SDLC frame serve as reference points when positioning the address and control fields, and they initiate the transmission error check. The ending flag indicates to the recei- ving station that the 16 bits just received constitute the frame check. The ending flag could be followed by another frame, another flag, or an idle. This means that when two frames fallow one another, the intervening flag may simultaneously be the ending flag of the first frame and the begin-ning flag of the next frame. Since the SDLC mode does notusecha- racters of defined length, but rather works on a bit- by-bit basis, the 01111110 (7EH) flag can be reco- gnized at any time. To ensure that the flag is not sent accidentally, SDLC procedures require a binary "0" to be inser- ted by the transmitter after the transmission of any five contiguous "1s". The receiver then removes the "0" following a received succession of five 1s". In- serted and removed "0s" are notincluded in the CRC calculation. The address field is 8 bits long and designates the number of secondary station to which the com- mands or data from the primary station are sent. The control field is eight bits long and is used to initiate all SDLC activities. The SCC can also serve the High-level synchronous Data Link Communication (HDLC) protocol, which is identical to SDLC except for differences in fra- ming. SDLC Loop Mode. The SCC supports SDLC Loop mode in addition to normal SDLC. SDLC Loop made is very similar to normal SDLC but is usually used in application where a point-to-point network is not ap- | je1 BIT TIME MODEM CLOCK at 1 2 3 4 5 6 Tr 3 10 Ww 12 Wo... BIT STATE 0 1 1 0 1 a oO 1 1 0 1 a 1 o 4 DATA iss l i t /-owe-__ SYNC CHARACTER DATA CHARACTER } I | | {7 SGS-THOMSON 11/93 YF MicroeectRomes 45928530 OVERVIEW (cont'd) propriate (for example, Point-Of-Sale terminals). In an SDLC Loop there is a primary station, called the controller, that manages the message traffic flow on the loop, and there are any number of secondary stations. A secondary station in an SDLC loop is always lis- tening to the messages being sent around the loop, and must pass these messages to the rest of the loop by retransmitting them with a one-bit-time de- lay. The secondary station can only place its own message on the loop at specific times. The control- ler signals that secondary stations may transmit messages by sending a special character, called an EOP (End of Poll), around the loop. The EOP cha- racter is the bit pattern 11111110. Because of zero insertion during messages this bit pattern is unique and thus is easily recognized. When a secondary station has a message to trans- mit and it recognizes an: EOP on the line , the first thing that it does is to change the last 1 or the EOP to a0" before transmitting it. This turns the EOP in- to a Flag sequence. The secondary station now places its message on the loop and terminates its message with an EOP. Any secondary stations fur- ther down the loop with messages to transmit can Figure 9 : Bisynchronous Message Format. then append its message to the message of the first secondary station by the same process. All secon- dary stations without messages to send merely echo the incoming messages and are prohibited from placing messages on the loop, except upon re- cognizing an EOP. There are also restrictions as to when and how a se- condary station physically becomes part of the loop. A secondary station that has just powered up must monitor the loop, without the one-bit-time delay, un- til it recognizes an EOP. When an EOP is recogni- zed the one-bit-time delay is switched on. This does not disturb the loop because the line is marking idle between the time that the controller sends the EOP and the time that it receives the EOP back. The se- condary station that has gone on-loop cannot place a message on the loop until the next time that an EOP is issued by the controller. A secondary station goes off-loop in a similar manner. When given a command to go off-loop, the secondary station waits until the next EOP to remove the one-bit-time delay. To operate the SCC in SDLC Loop mode, the SCC must first be programmed just as if normal SDLC were to be used. Loop mode is then selected by wri- ting the appropriate control word in WR10. The SCC con] weaver | [ere ETX TEXT OR acc ere ~_--__ DIRECTION OF SERIAL DATA FLOW Figure 10 : External Sync Format. SIGNAL { f 1 | { ? - EXTERNAL SYNC [ow [ow Po | Figure 11 : SDLC Message Format. FRAME | BEGINNING FLAG ADDRESS | CONTROL Ovtit80 eBITS esits a BITS INFORMATION ANY NUMBER ENDING FLAG Os1stsid sBits FRAME CHECK OF BITS 16 BITS 12/93 ii SGS-THOMSON MICROELECTRONICS 460OVERVIEW (cont'd) iS NOW waiting for the EOP so that it can go on loop. While waiting for the EOP, the SCC ties TxD to RxD with only the internal gate delays in the signal path. When the first EOP is recognized by the SCC, the Break/Abort/EOP bit is set in RRO, generating an External/Status interrupt (if so enabied). Atthe same time, the On-Loop bit in RR10 is set to indicate that the SCC is indeed on-loop, and a one-bit time delay is inserted in the TxD to the RxD patch. The SCC is now on-loop but cannot transmit a mes- sage until a flag and the next EOP are received. The requirement that a flag be received ensures that the SCC cannot erroneously send messages until the controller ends the current polling sequence and starts another one. A secondary station on the loop is prohibited from transmitting a message during a polling sequence unless it captures the line at the moment the EOP passes by. The SCC does this automatically. If the CPU in the secondary station with SCC needs to transmit a message, the Go-Active-On-Poll bit in WR10 must be set. If this bit is set when the EOP is detected, the SCC changes the EOP to a flag and starts sending another flag. The EOP is reported in the Break/Abort/EOP bit in RRO and the CPU should write its data bytes to the SCC, just as in normal SDLC frame transmission. When the frame is com- plete and CRC has been sent, the SCC closes with a flag and reverts to One-Bit-Delay mode. The last zero of the flag, along with the marking line echoed from the RxD pin, form an EOP for secondary sta- tions further down the loop. If the Go-Active-On-Poll bit is not set at the time the EOP passes by, the SCC cannot send a message until a flag (terminating the current polling sequence) and another EOP are re- ceived. While the SCC is actually transmitting a mes- sage, the loop-sending bit in R10 is set to indicate this. If SDLC loop is de-selected, the SCC is designed to exit from the loop gracefully . When SDLC Loop mode is de-selected by writing to WR10, the SCC waits until the next polling cycle to remove the on- bit time delay. If a polling cycle is in progress at the time the command is written, the SCC finishes sen- ding any message that it may be transmitting, ends with an EOP, and disconnects TxD from RxD. If no message was in progress, the SCC immediately dis- connects TxD from RxD. To ensure proper loop ope- ration after the SCC goes off the loop, and until the external relays take the SCC completely out of the loop, the SCC should be programmed for Mark idle instead of Flag idle. When the SCC goes off the loop, the On-Loop bit is reset. 28530 The SCC allows the user the option of using NRZI in SDLC Loop mode by programming WR20 appro- priately. With NRZI encoding, the outputs of secon- dary stations in the loop may be inverted from their inputs because of messages that they have trans- mitted. Removing the stations from the loop (remo- ving the one-bit time delay) may cause problems fur- ther down the loop because of extraneous transi- tions on the line. The SCC avoids this problem by making transparent adjustements at the end of each frame it sends in response to an EOP. A response frame from the SCC is terminated by a flag and an EOP. Normally, the flag and the EOP share a zero, but if such sharing would cause the RxD and TxD pins to be of opposite polarity after the EOP, the SCC adds another zero between the flag and the EOP. This causes an extra line transition so that RxD and TxD are identical after ihe EOP is sent. This ex- tra zero is completely transparent because it only means that the flag and the EOP no longer share a zero. All that a proper loop exit needs, therefore, is the removal of the one-bit time delay. V/O Capabilities. The SCC can work with three basic forms of I/O ope- rations : polling, interrupts, and block transfer. All three I/O types involve register manipulation during initialization and data transfer. Polling. During a polling sequence, the status of Read Register 0 is examined in each channel. This register indicates whether or not a receive or trans- mit data transfer is needed and whether or not any special conditions are present, e.g., errors. This method of I/O transfer avoids interrupts. Alt in- terrupt functions must be disabled in order to ope- rate the device in a polled environment. With no in- terrupts enabled, this mode of operation must initiate a read cycle of Read Register 0 to detect an inco- ming character before jumping to a data handler rou- tine. Interrupts. The SCC provides interrupt capability through the use of pins and a hardware scheme that enhances the maximum speed of serial data. Whe- never the interrupt (INT) pin is active, the SCC is rea- dy to transfer data. Read and write registers are programmed so that an interrupt vector points to an interrupt service routine. The interrupt vector can also be modified to reflect various status conditions. Therefore, as many as eight different interrupt routines can be referenced. Transmit interrupts, receive interrupts, and exter- nal/status interrupts are the main sources of inter- rupts. Each interrupt source is enabled under pro- &57 8SS:THoMson 13/93 MICROELECTRONICS 46128530 OVERVIEW (cont'd) gram control, with channel A having a higher priori- ty than channel B and with receive, transmit, and ex- ternal/status interrupts prioritized respectively within each channel. Block Transfers. The SCC provides a Block Trans- fer mode to accommodate CPU block transfer func- tions and DMA controllers. The Block Transfer mode uses the W/REQ output in conjunction with the Wait/Request bits in Write Register 1. TheV W/REQ output can be defined by software as a WATT line in the CPU Block Transfer mode or as a REQUEST line in the DMA Block Transfer mode. To a DMA controller, the SCC REQUEST output in- dicates that the SCC is ready to transfer data to or from memory. To the CPU, the WAIT output indi- cates that the SCC is not ready to transfer data, the- reby requesting the CPU to extend the I/O cycle. INTERFACING THE SCC This section covers the details of interfacing the 28530 to asystem. The general timing requirements for the device are described in the hardware infor- mation section. Interfacing the Z8530 Two control signals, RD and WR, are used by the Z8530 to time bus transactions. In addition, four other contro! signais, CE, D/ C, A/ B and INTACK, are used to control the type of bus transaction that will occur. A bus transaction start when the ad- dresses on D/C and A/ B are asserted before RD or WR fall. The coincidence of CE and RD or CE and WR latches the state of D/C and A/B and starts the internal operation. The INTACK signal must have been previously sampled High by a rising edge of PCLK for a read or write cycle to occur. In addition to sampling INTACK, PCLK is used by the interrupt section to set the IP bits. The Z8530 generates in- ternal control_signals in response to a register ac- cess. Since RD and WR have no phase relationship with PCLK, the circuitry generating these internal control signals provides time for metastable condi- tions to disappear. This results in a recovery time re- lated to PCLK. This recovery time applies only be- tween transactions involving the Z8530, and any in- terventing transactions are ignored. This recovery time is four PCLK cycles, measured from the falling edge of RD or WR in the case of a read or write of any register. 14/88 57 SGS:THOMSON 28530 Read Cycle Timing. The Read cycle timing for the Z8530 is shown in Figure 12. The address on A/B 3 and D/ Cis latched by the coincidence of RD and CE active. CE must remain LOW and INTACK must remain HIGH throughout the cycle. The Z8530 bus drivers are enabled while CE and RD are both LOW. A read with D/ C HIGH does not disturb the state of the pointers and a read cycle with D/C LOW resets the pointers to zero after the internal opera- tion is complete. 28530 Write Cycle Timing. The Write cycle timing for the Z8530 is shown in Figure 13. The address on A/Band D/C, as well as the data on DO-D7, is lat- ched by the coincidence of WR and CE active. CE must remain LOW and INTACK must remain HIGH throughout the cycle. A write cycle with D/ C HIGH does not disturb the state of pointers and a write cy- cle with D/ C LOW resets the pointers to zero after the internal operation is complete. 28530 Interrupt Acknowledge Cycle Timing. The interrupt Acknowledge cycle timing for the Z8530 is shown in Figure 14. The state of INTACK is latched by the rising edge of PCLK. While INTACK is LOW, the state of A/B, CE, D/C, and WR are ignored. Bet- ween the time INTACK is first sampled LOW and the time RD falls, the internal and external IEI/ IEO dai- sy chains settle ; this is A.C. parameter #38 TdlAi(RD). If there is an interrupt pending in the 28530, and [El is HIGH when RD falls, the Interrupt Acknowledge cycle was intended for the 28530. This being the case, the Z8530 sets the appropriate Interrupt Under Service latch, and places an inter- rupt vector on DO-D7. If the falling edge of RD sets an IUS bit in the 28530, the INT pin goes active in response to the falling edge. Note that there should be only one RD per Acknowledge cycle. Another im- portant fact is that the IP bits in the Z8530 are upda- ted by PCLK divided by two, and this clock to update IPs is stopped while the pointers point to RR2 and RR3. This prevents data changing during a read, but will delay interrupt requests if the pointers are left pointing at these registers. 28530 Register Access. The registers in the 28530 are accessed in a two-step process, using a Regis- ter Pointer to perform the addressing. To access a particular register, the pointer bits must be set by writing to WRO the pointer bits may be written in ei- ther channel because only one set exists in the 28530. After the pointer bits are set, the next read MICROELECTRONICS 462INTERFACING THE SCC (cont'd) or write cycle of the 28530 having D/C LOW will ac- cess the desired register. At the conclusion of this read or write cycle the pointer bits are reset to "Os", so that the next contro! write will be to the pointers in WRO. A read or RR8 (the receive data buffer) or a write to WR8 (the transmit data buffer) may either be done in this fashion or by accessing the 78530 having D/C pin HIGH. A read or write with D/C HIGH accesses the data registers directly, and inde- pendently, of the state of the pointer bits. This al- Figure 12 : 28530 Read Cycle Timing. 28530 lows single-cycle access to the data registers and does not disturb the pointer bits. The fact that the pointer bits are reset to "0", unless explicitly set otherwise, means that WRO and RRO may also be accessed in a single cycle. That is, it is not neces- sary to write the pointer bits with "0" before acces- sing WRO or RRO. There are three pointer bits in WRO, and these allow access to the registers with addresses 0 through 7. Note that a command may be written to WRO at the same time that the pointer AIB, DIC o ADDRESS VALID INTACK _/f <7 Nf X \ fT Do-O7 [- \ xX DATA VALID Figure 13 : 28530 Write Cycle Timing. ab, 0/T x ADDRESS VALIO INTACK / Do-D7 __( DATA VALID \_____ X \ a lo -}_ ki SGS-THOMSON 15/93 MIGROELECTRONIES 46328530 INTERFACING THE SCC (cont'd) Figure 14 : 28530 Interrupt Acknowledge Details. VECTOR ae Ro re 1EO le Ie =z PCLK Do-Dy int 16/93 Gs: Ky7 Zooniemomes 464INTERFACING THE SCC (contd) bits are written. To access the registers with ad- dresses 8 through 15, a special command must ac- company the pointer bits. This precludes concur- rently issuing a command when pointing to these re- 28530 The reset values of the various registers are shown in Figure 15. Table 2 : Z8530 Register Map. gisters. The register map for the AmZ8530 is shown A/B |PNT2|PNT, |PNT,| WRITE | READ in Table 2. If for some reason, the state of the poin- ter bits is unknown they may be reset to "0" by per- 9 9 0 0 | WROB | RROB forming a read cycle with the D/ C pin held LOW. 0 9 9 1 | WRIB | RAB Once the pointer bits have been set, the desired 0 0 1 WeOB ae ee channel is selected by the state of the A/ B pin du- 3 ; 4 4 Whee EAOB ring the actual read or write of the desired register. 0 4 0 i WRS5B (Rat 8) 28530 Reset. The 28530 may be reset by either 0 1 1 0 WR6B (RR2B) hardware or software. Hardware reset occurs when 0 1 1 1 WR7B (RR3B) RD and WR are both LOW, simultaneously, which i 0 0 0 | WROA RROA is normally an illegal condition. As long as both RD 1 0 0 1 WRIA RRIA and WR are LOW, the Z8530 recognizes the reset 1 0 1 Q | WR2 RR2A condition. Once this condition is removed, however, 1 0 1 1 WR3A RR3A the reset condition is asserted internally for an ad- 1 1 0 O | WR4A (RROA) ditional four to five PCLK cycles. During this time 1 1 0 1 | WR5A | (RRA) any attempt to access the 28530 will be ignored. 1 1 i O | WR6A | (RR2A) The Z8530 has three software resets, encoded into 1 1 1 1 WR7A {RA3A) command bits in WR9. There are two channel re- With the Point High Command sets, which affect only one channel in the device and 0 0 0 o | wRsB RR8B some of the bits in the write registers. The third com- 0 0 0 1 WR9O RR13B mand forces the same result as does a hardware 0 0 1 0 WR10B | RRi0B reset. As in the case of a hardware reset, the Z8530 ) 0 1 1 WR11B S| (RR15B) stretches the reset signal an additional four to five 0 1 0 0 WR12B | RR12B PCLK cycles beyond the ordinary valid access re- 0 1 0 1 WR13B | RR13B covery time. The bits in WR9 may be written at the 0 1 1 0 WR14B | (RAR10B) same time as the reset command because these 0 1 i i WR15B | RAI5B bits are affected only by a hardware reset. 1 0 0 O | WR8A RR8A 1 0 0 1 WR9 (RR13A) 1 0 1 0 WRI10A RR10A 1 0 1 1 WR11A_ | (RRI5A) 1 1 0 0 WR12A RR12A 1 1 0 1 WR13A | RRI3A 1 1 1 0 WRI14A RR14A 1 1 1 1 WRI5A | RRI5A ky SGS-THOMSON 17/98 IF menossctowies 46528530 INTERFACING THE SCC (cont'd) Figure 15 : 28530 Register Reset Values. HARDWARE RESET CHANNEL RESET 765 43210 7 6 5 4 3 1 0 [oo 000000) [00000 0 9} foo . o o . o of {oo . o 0 0 of} L. -) Ce J C =] ] [= ] I jo oo oo.) {e- a) 0 .] J -_ C 4 ] [1 10000. .J] |{.. 0 . | [fo 0 0 00000} fo. 0 0 o of [oo 0017000] |{.. . | [. - 100000] [. .1 00 - | Ee ee ee o o| [o 1 1 0 of fo oo] [ooo 0 011 of {2 0 0 0 0 1 0] 0000000 0;] #%|o 0 0 0 0 o 0} fo 0 00000 0f {oe o oo 0 0 0] WRO wRi WR2 WwR3 wra WRS WRE6 WR7 wre WR10 WRi1 WRi2 WR13 WRi4 WRI15 RRO RR1 RR3 ARO 18/93 7 SGS-THOMSON If MICROELECTRONICS 4661/0 PROGRAMMING CAPABILITIES Regardless of the version of the SCC, all commu- nication modes can use a choice of polling, inter- rupt and block transfer. These modes must be se- lected by the user to select the proper hardware and software required to supply data at the rate required. Polling This is the simpliest mode to implement. The soft- ware must poll the SCC to determine when data is to be inputted or outputted from the SCC.In this mode, MIE (WR9 bit 3), and Wait/ DMA Request En- abie (WR1 bit 7) are both reset to 0 to disable any requests. The software must then poll RRO to deter- mine the status of the receive buffer, transmit buf- fer and external status. Interrupt Operations The SCC, as a microprocessor peripheral, will re- quest an interrupt only when it needs servicing. This allows the CPU to perform other operations while the SCC does not need service. The SCC has an internal priority resolution method fo allow the hi- ghest priority interrupt to be serviced first. The SCC is flexible with its interrupt method. The in- terrupt may be acknowledged with a vector trans- ferred, acknowledged without a vector, or not ac- knowledged at all. Interrupt Without Acknowledge. |n this mode, the Interrupt Acknowledge signal does not have to be generated. This allows a simpler hardware design that does not have to meet _the Interrupt acknow- ledge timing. Soon after the INT goes active, the in- terrupt controller will jump to the interrupt routine. in the interrupt routine, the code must read RR2 from Channel B to read the vector including status. When the vector is read from Channel B, it always includes the status regardless of the VIS bit (WRg9 bit 0). The status given will decode the highest priority interrupt pending at the time it is read. The vector is not lat- ched so that the next read could produce a different vector if another interrupt occurs. The register is di- sabled from change during the read operation to prevent an error if a higher interrupt occurs exactly during the read operation. Once the status is read, the interrupt routine must decode the interrupt pending, and clear the condi- tion. Removing the interrupt condition will clear the IP and bring INT inactive, as long as there are no other IP bits set. For example, writing a character to he transmit buffer will clear the transmit buffer emp- y IP. 28530 When the interrupt IP, decoded from the status, is cleared RR2 can be read again. This allows the in- terrupt routine to clear all of the IPs within one in- terrupt request to the CPU. Interrupt With Acknowledge. After the SCC brings INT active, the CPU must respond by bringing IN- TACK active. After enough time has elapsed to al- low the daisy-chain to settle, the SCC will set the IUS bit for the highest priority IP. If the No Vector bit is not set (WRQ bit 1), the SCC will then place the interrupt vector on the data bus during a read. To speed the interrupt response time, the SCC can al- so modify 3 bits in the vector to indicate status. To include the status, the VIS bit (WR9 bit 0) must be set. The service routine must then clear the inter- rupting condition. For example, writing a character to the transmit buffer will clear the transmit buffer empty IP. After the interrupting condition is cleared, the routine can read RR3 to determine if any other IPs are set and clear them. At the end of the inter- rupt routine, a Reset |IUS command (WRO0) must be issued to unlock the daisy-chain and allow lower- priority interrupt requestes. This is the only way, short of a software or hardware reset, that an IUS bit may be reset. If the No Vector bit (WR9 bit 1) is set, the SCC will net place the vector on the data bus. An interrupt controller must then vector the code to the interrupt routine. The interrupt routine must then read RR2 from Channel B to read the status. This is the same as the case of an interrupt without an acknowledge except the 1US is set and the vector will not change until the Reset |US command in RRO is issued. Interrupt Sources. Each channel in the SCC contains 3 sources of interrupt, making a total of 6. These 3 sources of interrupts are the receiver, the transmitter, and External/ Status conditions. In ad- dition, there are several conditions that may cause these interrupts. The receive interrupt request may either be caused by a receive character available or a special condi- tion. The receive character available interrupt is ge- nerated when a character is loaded into the FIFO and is ready to be read. The special conditions are receive FIFO overrun, CRC/ framming error. End of frame, and parity. The parity special condition can be included as a special condition or not depending on bit 2 WR1. The special condition status can be read from RR1. The transmit interrupt request has only one source. It can only be set when the transmit buffer goes from yz S&S:THOMSON 19/98 MICROELECTRONICS 46728530 1/0 PROGRAMMING CAPABILITIES (cont'd) full to empty. Note that this means that the transmit interrupt will not be set until after the first character is written to the SCC. The External/ status interrupts have several sources which may be individually enabled in WR15. The sources are zero count, DCD, Sync/ Hunt, CTS, transmitter underrun/ EOM and Break/ Abort. Each source of interrupt in the SCC has three control/status bits associated with it. There are In- terrupt Enable ((E), Interrupt Pending (IP), and In- terrupt Under Service (IUS) (see Figure 16). The IE bit is written by the processor and serves to control interrupt requests from the SCC. If the IE bit is set for a given source of interrupt, then that source may cause an interrupt request when all of the necessa- ry conditions are met. {f the (E bit is reset, no inter- rupt request will be generated by that source. The IE bits are write-only in the SCC. The IP bit for a gi- ven source of interrupt condition in the SCC and is reset directly by the processor, or indirectly by some action that the processor may take. If the correspon- ding IE bit is not set, the IP bits in the SCC are read- only in RR3A. The IUS bits are completely hidden from the processor's view. An IUS is set during an Interrupt Acknowledge cycle for the highest-priority IP. See Table 3 for the interrupt priority. |IUS is used to control the operation of the interrupt daisy chain by masking lower-priority interrupts. At the end of an interrupt service routine, the processor must issue a Reset Highest IUS command in WRO to allow lo- wer-priority interrupts. This is the only way, short of a software or hardware reset, that an IUS bit may be reset. Figure 16 : Peripheral Interrupt Structure. Table 3 : Interrupt Source Priority. Receiver Channel A High Transmit Channel A External / Status Channel A L Receiver Channel B L Transmit Channel B External / Status Channel B Low Daisy-chain Priority Resolution. The six sources of interrupt in the SCC are prioritized in a fixed or- der via a daisy chain ; provision is made, via the IEI and IEO pins, for use of an external daisy chain as well. All Channel A interrupts are higher-priority than any Channel B interrupts, with the receiver, trans- mitter, and External/ Status interrupts prioritized in that order within each channel. The SCC requests an interrupt by pulling the INT pin Low from its open- drain state. This is controlled by the IP bits and the IE} input, among other things. A flowchart of the in- terrupt sequence for the SCC is shown in Figure 17. The internal daisy chain links the six sources of in- terrupt in a fixed order, chaining the IUS bits for each source. While an |US is set, all lower-priority inter- rupt requests are masked off ; during an Interrupt Acknowledge cycle the IP bits are also gated intc the daisy chain. This insures that the highest-priori- ty IP will be selected to have its IUS set. The inter- nal daisy chain may be controlled by the MIE bit ir WR%&. This bit, when reset, has the same effect as pulling the IE! pin Low, thus disabling all interrupt re- quests. External Daisy Chain Operations. The SCC ge. nerates an interrupt request by pulling INT Low, bu lel INTERRUPT VECTOR [=e] Lr] INT INTACK IO "| Bl PRIORITY DEVICE FROM PULLUP RESISTOR | TO [EL INPUT OR [EO LINE OF HIGHER OF LOWER PRIORITY DEVICE TOCPU = FROMCPU STATUS DECODER 20/93 i SGS-THOMSON MIGROELECTROMICS 46828530 VO PROGRAMMING CAPABILITIES (cont'd) only if such interrupt requests are enabled (IE is 1, MIE is 1), an IP is set without a higher-priority IUS being set, or no higher-priority US being set, or no higher-priority interrupt is being serviced (IEI is High), or no Interrupt Acknowledge transaction is ta- king place. It is not pulled Low by the SCC at this time, but instead continues to follow IEI until an In- terrupt Acknowledge transaction occurs. Some time after INT has been pulled Low, the processor ini- tiates an Interrupt Acknowledge transaction. Bet- ween the time the SCC recognizes that an Interrupt Acknowledge cycle is in progress and the time du- ring the acknowledge that the processor requests an interrupt vector, the IEI/IEO daisy chain settles. Any peripheral in the daisy chain having an Interrupt Pending (IP is 1) or an Interrupt Under Service (1US is 1) holds its IEO line Low and all others make IEO follow IEI. When the processor requests an interrupt vector, only the highest-priority interrupt source with a pen- ding interrupt (IP is 1) has its IE] input High, its IE bit set to "1", and its IUS bit set to "0". This is the inter- rupt source being acknowledged, and at this point it sets its IUS bit to "1". If its NV bit is "0", the SCC identifies itself by placing the interrupt vector from WR2 on the data bus. If the NV bit is "1", the SCC data bus remains floating, allowing external logic to supply a vector. If the VIS bit in the SCC is "1", the vector also contains status information, encoded as shown in Table 4, which further describes the na- ture of the SCC interrupt. If the VIS bit is "0", the vec- tor held in WR2 is returned without modification. If the SCC is programmed to include status informa- tion in the vector, this status may be encoded and placed in either bits 1-3 or in bits 4-6. This operation is selected by programming the Status High/Status Low bit in WR9. At the end of the interrupt service routine, the processor should issue the Reset Hi- ghest IUS command to unlock the daisy chain and allow lower-priority interrupt requests. The IP is re- set during the interrupt service routine either direct- ly by command, or indirectly, through some action taken by the processor. The extemal daisy chain may be controlled by the DLC bit in WR9. This bit, when set, forces IEO Low, disabling all lower-priori- ty devices. Receive Interrupts. The Receive interrupt mode is controlled by WR1 bits 4 and 3. These select one of the four interrupt modes. The four modes are, Inter- rupt disabled, Interrupt on first character or special conditions, Interrupt on all characters or special conditions, and Interrupt on special conditions. Receive Interrupts Disabied. This mode prevents the receiver from requesting an interrupt. It is used Table 4 : Interrupt Vector Modification. V3 | V2 | V1 | Status High / status Low =0 V4 | V5 | V6 | Status High / status Low = 1 0 0 0 | ChB Transmit Buffer Empty 0 0 1 Ch B External / Status Change 0 1 0 | ChB Receive Character Avail. 0 1 1 Ch B Special Receive Condition 1 0 0 Ch A Transmit Buffer Empty 4 0 1 Ch A External / status Change 1 1 0 Ch A Receive Character Avail. 1 1 1 Ch A Special Recieve Condition kyr SGS-THOMSON in a polled environment where either the status bits in RRO or the modified vector in RR2 (Channel B) is read. Although the receiver interrupts are disabled, the interrupt logic can still be used to provide status. When these bits indicate that a received character has reached the top of the FIFO, the status in RR1 should be checked and then the data should be read. If status is to be checked, it must be done be- fore the data is read, because the act of reading the data pops both the data and error FIFOs. Receive Interrupt On First Character Or Special Condition. This mode is designed for use with DMA transters of the receive characters. After this mode is selected, the first character received, or the first character already stored in the FIFO, will set the re- ceiver IP. This IP will be reset when this character is removed from the SCC. No further receive inter- rupts will occur until the processor issues an Enable Interrupt on Next Receive Character command in WRO until a special receive condition occurs. The SCC recognizes several special receive conditions. A receive overrun (where a character in the FIFO is written over) is a special receive condition, as is a framing error in Asynchronous mode, or the end-of- frame condition in SDLC mode. In addition, if D2 of WR1 is set, any character with a parity error will ge- nerate a special receive condition interrupt. The cor- rect sequence of events when using this mode is to first select the mode and wait for the receive cha- racter available interrupt. When the interrupt occurs the processor should read the character and then enable the DMA to transfer the remaining charac- ters. A special receive condition interrupt may occur any time after the first character is received, but is guaranteed to occur after the character having the special condition has been read. The status is not lost in this case, however, because the FIFO is locked by the special condition. In the service rou- tine the processor should read RR1 to obtain the status, and may read the data again if necessary. The FIFO is unlocked by issuing an Error Reset command in WRO. If the special condition was End- 21/93 MICROELECTRONICS 46928530 /O PROGRAMMING CAPABILITIES (cont'd) Figure 17 : Interrupt Flowchart. INTERRUPT CONDITION EXISTS. * SPECIFIC INTERRUPT ENABLE (E, =1) ? INTERRUPT PENDING SET UP =1) PERIPHERAL ENABLE PIN ACTIVE (EI=H) 2 PERIPHERAL REQUESTS INTERRUPT (INT =L) CPU INITIATES STATUS DECODE {INTACK = 1) 1EIMEO DAISY CHAIN SETTLES (WAIT FOR DS) UNIT SELECTED FOR CPU SERVICE (US = 1) SERVICE CPU SERVICES HIGHER ROUTINE PRIORITY PERIPHERAL COMPLETE ? PRIORITY (OPTION) CHECK OTHER SERVICE INTERNAL IP, BITS, COMPLETE RESET 1US AND EXIT ? INTERRUPT STILL PENDING P=) 22/93 ka SGS-THOMSON MICROELECTRONICS 4701/0 PROGRAMMING CAPABILITIES (cont'd) of-Frame, the processor should now issue the Ena- ble Interrupt on Next Receive Character command to prepare for the next frame. The first character in- terrupt and special condition interrupt are distinguis- hed by the status included in the interrupt vector. in all other respects they are identical, including sha- ring the IP and IUS bits. Interrupt On All Receive Characters Or Special Conditions. This mode is designed for an interrupt- driven system. In this mode the SCC will set the re- ceiver IP on every received character, whether or not it has a special receive condition. This includes characters already in the FIFO when this mode is selected. In this mode of operation the IP is reset when the character is removed from the FIFO, so if the processor requires status for any character, this status must be read before the data is removed from the FIFO. The special receive conditions are identi- cal to those previously mentioned, and as before, the only difference between a "receive character available interrupt and a "special receive condition" interrupt is the status encoded in the vector. In this mode a special receive condition does not lock the receive data FIFO so that the service routine must read the status in RR1 before reading the data. At moderate to high data rates, where the interrupt overhead is significant, time can usually be saved by checking for another received character before exiting the service routine. This technique elimi- nates the Interrupt Acknowledge and the processor- state-saving time, but care must be exercised be- cause this receive character must be checked for special receive conditions before it is removed from the SCC. Receive Interrupt On Special Conditions. This mode is designed for use with DMA transfers of the receive characters. In this mode, only receive cha- racters with special conditions will cause the recei- ver IP to be set. All other characters are assumed to be transferred via DMA. No special initialization sequence is needed in this mode. Usually the DMA is initialized and enabled, and then this mode is se- lected in the SCC. A special receive condition inter- rupt may occur at any time after this mode is selec- ted but the logic guarantees that the interrupt will not occur until after the character with the special condi- tion has been read from the SCC . The special condition locks the FIFO so that the status will be valid when read in the interrupt service routine, and it guarantees that the DMA will not transfer any cha- racters until the special condition has been serviced. In the service routine the processor should read RR1 to obtain the status and unlock the FIFO by is- suing an Error Reset command. DMA transfer of the receive characters will then resume. i SGS-THOMSON 28530 Transmit Interrupts. Transmit interrupts are con- trolled by the Transmit Interrupt Enable bit (D1) in WA1. If the interrupt capabilities of the SCC are not required, polling may be used. This is selected by disabling the transmit interrupts and polling the Transmit Buffer Empty bit in RRO. When the Trans- mit Buffer Empty is set a character may be written to the SCC without fear of writing over previous da- ta. Another way of polling the SCC is to enable the transmit interrupt and then reset the MIE bitin WR9. The processor may then poll the IP bits in RR3A to determine when the transmit buffer is empty. Trans- mit interrupts should also be disabled in the case of DMA transfer of the transmitted data. While the transmit interrupts are enabled the SCC will set the transmit IP whenever the transmit buff- er becomes empty. This means that the transmit buffer must have been full before the transmit IP can be set. Thus when the transmit interrupts are first enabled, the transmit iP will not be set until after the first character is written to the SCC. In synchronous modes one other condition can cause the transmit IP to be set. This occurs at the end of a transmis- sion after CRC is sent. When the last bit of CRC has cleared the Transmit Shift register and the flag or sync character is loaded into the Transmit Shift re- gister, the SCC will set the transmit IP. Data for the new frame or block to be transmitted may be writ- ten at this time. In this particular case the Transmit Buffer Empty bit in RRO is not set ; only the transmit IP is set. If the transmit Buffer Empty bit is, in fact, set for the transmit interrupt that occurs immediate- ly after CRC transmission, this indicates that data was written while CRC was being sent. This is an indication that the transmitter underflowed, without the CPU being aware of it. The transmit IP is reset either by writing data to the transmit buffer or by is- suing the Reset Transmit IP command in WRO. Or- dinarily the response to a transmit interrupt is to write more data to the SCC ; however, at the end of a frame or block of data where CRC is to be sent next, the Reset Transmit IP command should be is- sued in lieu of data. External/Status Interrupts. There are several sources of External/Status interrupts, each of which may be individually enabled in WR15. The master enable for the External/Status interrupts is located in WR1 (DO). The individual enable bits in WR15 control whether or not latches will be present in the path from the source of interrupt to the status bit in RRO. If an individual enable bit in WR15 is set to "0" the latches are not present in the signal path and the value read in RRO reflects the current status. An interrupt source whose individual enable in WR15 is O" is not a source of External/Siatus interrupts 23/93 MICROELECTRONICS 47128530 //O PROGRAMMING CAPABILITIES (cont'd) even though the External/Status Interrupt Enable bit is set. When an individual enable in WR15 is set to "{", the latch is present in the signal path. The latches for the sources of External/Status interrupts are not independent. Rather, they all close at the same time as a result of a state change by one of the sources of interrupt. Thus, a read of RRO returns the current status for any bits whose individual en- able is "0" and either the current state or the latched state of the remainder of the bits. To guarantee the current status the processor should issue a Reset Extemal/Status Interrupts command in WRO to open the latches. The External/Status IP is set by the closing of the latches and remains set as long as they are closed. If the master enable for the Ex- ternal/Status interrupts is not set, the IP will never be set, even though the latches may be present in the signal paths and working as described. Because the latches close on the current status but give no indication of change, the processor must maintain a copy of RRO in memory. When the SCC generates an External/Status interrupt the processor should read RRO and determine which condition changed state and take appropriate action. The copy of RRO in memory must then updated and the Reset Exter- nal/Status Interrupt command issued. Care must be taken in writing the interrupt service routine for the External/Status interrupts because it is possible for more than one status condition to change state at the same time. All of the latch bits in RRO should be compared to the copy of RRO in memory. If none have changed and the ZC interrupt is enabled, the Zero Count condition caused the interrupt. The operation of the individual enable bits in WR15 for each of the six sources of External/Status inter- rupts is identical, but subtle differences exist in the operation of each source of interrupt. The six sources are Break/Abort, Underrun/EOM, CTS, DCD, Sync/Hunt and Zero Count. The Break/Abort, Underrun/EOM, and Zero Count conditions are in- ternal to the SCC, while Sync/Hunt may be internal or external, and CTS and DCD are purely external signals. In the following discussions each source is assumed to be enabled, so that the latches are pre- sent, and the External/Status interrupts are enabled as a whole. Recail that the External/Status IP is set while the latches are closed and that the state of the signal is reflected immediately in RRO if the latches are not present. The Break/Abort status is used in asynchronous and SDLC modes but is always "0" in synchronous modes other than SDLC. In asynchronous modes this bit is set when a break sequence (null charac- ter plus framing error) is detected in the receive da- ta stream, and remains set as long as "Os" continue 24/93 &yr SGS-THOMSON to be received. This bit is reset when a "1" is recei- ved. A single null character is left in the receive Fl- FO each time that the break condition is terminated. This character should be read and discarded. In SDLC mode this bit is set by the detection of an abort sequence, which is seven or more contiguous "1s" in the receive data stream. The bit is reset when a "0" is received. A received abort forces the receiver into Hunt, which is also an external/status condition. Though these two bits change state at roughly the same time, one or two External/ Status interrupts may be generated as a result. The Break/Abort bit is unique in that both transitions are guaranteed to cause the latches to close, even if another External/ Status interrupt is pending at the time these transi- tions occur. This guarantees that a break or abort will be caught. The Transmit Underrun/ EOM bit is used in synchro- nous modes to control the transmission of CRC. This bit is reset by issuing the Reset Transmit Un- derrun/ EOM command in WRO. However, this transition does not cause the latches to close ; this occurs only when the bit is set. To inform the pro- cessor of this fact, the SCC sets this bit when CRC is loaded into the Transmit Shift register. This bit will also be set if the processor issues the Send Abort command in WRO. The bit is always set in Asynchro- nous mode. The CTS bit reports the state of the CTS input, and the DCD bit reports the status of the DCD input. Both bits latch on either input transition. !n both cases, af- ter the Reset External/ Status Interrupt command is issued, if the latches are closed, they remain closed if there is any odd number of transitions on an in- put ; they will be open if there is an even number of transi-tions on the input. The Zero Count bit is set when the counter in the baud rate generator reaches a count of 0 and is reset when the counter is reloaded. The latches are closed only when this bit is set to "1", and the status in RRO always reflects the current status.While the Zero Count IE bit in WR15 is reset this bit is forced to"O" . There are a variety of ways in which the Sync/ Hunt may be set and reset, depending on the SCCs mode operation. In Asynchronous mode this bit re- ports the state of the SYNC pin, latching on both in- put transitions. The same is true of External Sync mode. However, if the crystal oscillator is enabled while in Asynchronous mode this bit will be forced to "0" and the latches will not be closed. Selecting the crystal option in External Sync mode is illegal, but the result will be the same. In Synchronous modes other than SDLC the Sync/Hunt reports the MICROELECTRONICS 47228530 1/0 PROGRAMMING CAPABILITIES (cont'd) Hunt state of the receiver. Hunt mode is entered when the processor issues the Enter Hunt com- mand in WR3. This forces the receiver to search for a sync character match in the receive data stream. Because both transitions of the Hunt bit close the latches, issuing this command will cause an Exter- nal/Status interrupt. The SCC resets this bit when character synchronization has been achieved, cau- sing the latches to again be closed. In these syn- chronous modes the SCC will not reenter the Hunt mode automatically ; only the Enter Hunt command will set this bit. In SDLC mode this bit is also set by the Enter Hunt command, but the receiver will also automatically enter the Hunt mode if an Abort se- quence is received. The receiver leaves Hunt upon receipt of a flag sequence. Both transitions of the Hunt bit will cause the latches to be closed. In SDLC mode the receiver will automatically synchronize on Flag characters. The receiver is in Hunt mode when itis enabled, so the Enter Hunt command will pro- bably never be needed. If careful attention is paid to details, the interrupt ser- vice routine for External/Status interrupts is straight- forward. To determine which bit or bits changed state, the routine should first read RRO and compare it to a copy from memory. For each changed bit the appropriate action should be taken and the copy in memory updated. The service routine should close with a Reset External/Status interrupts command to reopen the latches. The copy of RRO in memory should always have the Zero Count bit set to "0", since this will be the state of the bit after the Reset External/Status interrupts command at the end of the service routine. When the processor issues the Reset Transmit Underrun/EOM latch command in WRO, the Transmit Underrun/EOM bit in the copy of RRO in memory should be reset because this trans- ition does not cause an interrupt. Block Transfers The SCC offers several alternatives for the block transfer of data. The various options are selected by WR1 (bits D7 through D5) and WR14 (bit D2). Each channel in the SCC has two pins which may be used fo control the block transfer data. Both pins in each channel may be programmed to act as DMA Re- quest signals, and one pin in each channel may be programmed to act as a Wait signal for the CPU. In either mode, it is advisable to select and enable the mode in two separate accesses of the appropriate register. The first access should select the mode and the second access should enabie the function. This procedure prevents glitches on the output pins. Reset forces Wait mode, with W/ REQ open-drain. iy SGS-THOMSON Wait On Transmit. The Wait function on transmit is selected by setting both D6 and D5 to "0" and then enabling the function by setting D7 of WR1 to "1". In this mode the W/ REQ pin carries the WAIT si- gnal, and is open-drain when inactive and Low when active. When the processor attempts to write to the transmit buffer when it is full, the SCC will assert WAIT until the buffer is empty. This allows the use of a block-move instruction to transfer the transmit data. In the Z8530, WAIT will go active in res-ponse to WR going active, but only if the data buf-fer is being accessed, either directly or via the pointers. The WAIT pin is released in response to the falling edge of PCLK. Details of the timing are shown in Fi- gure 18. Wait On Receive. The Wait function on receive is selected by setting D6 or WR1 to "0", D5 of WR1 to "1", and then enabling the function by set-tling D7 of WR1 to "1". In this mode the W/ REQ pin carries the WAIT signal, and is open-drain when inactive and Low when active. When the processor attempts to read data from the receive FIFO when it is emp- ty, the SCC will assert WAIT until a character has reached the top of the FIFO. This allows the use of a block-move instruction to transfer the receive da- ta. In the 28530, WAIT will go active in res-ponse to RD going active, but only if the receive data FIFO is being accessed, either directly or via the pointers. The WAIT pin is released in response to the falling edge of PCLK. Details of the timing are shown in Fi- gure 19. DMA Requests. The two DMA request pins W/ REQ and DTR/ REQ canbe programmed to be used as DMA requests. The W/ REQ pin can be used as either a transmit or a receive request and the DTR/ REQ pin can only be used as a receive request. For full-duplex operation, the W/ REQ is, therefore, used for transmit and the DTR/ REQ is used for receive. These modes are described below. DMA Request On Transmit (using W/REQ). The Request on Transmit function is selected by setting D6 of WR to "1", D5 of WR1 to "0", and then en- abling the function by setting D7 of WR1 to "i". In this mode the W/ REQ pin carries the REQUEST si- gnal, which is active Low. When this mode is selec- ted, but not yet enabled, the W/ REQ is driven High. When the enable bit is set, REQUEST goes Low if the transmit buffer is empty at the time, or will re- main High until the transmit buffer becomes empty. Note that the REQUEST pin will follow the state of the transmit buffer even though the transmitter is di- sabled. Thus, if the REQUEST is enabled, the DMA may write data to the SCC before the transmitter is enabled. This will not cause a problem in Asynchro- 25/93 MICROELECTRONICS 473Z8530 1/0 PROGRAMMING CAPABILITIES (cont'd) nous mode but may cause problems in Synchro- nous mode because the SCC will send data in pre- ference to flags or sync characters. It may also com- plicate the CRC initialization, which cannot be done until after the transmitter is enabled. With only one exception, the REQUEST pin directly follows the state of the transmit buffer in this mode. REQUEST goes Low when the transmit buffer empties and re- mains Low until the transmit buffer is filled. The SCC generates only one falling edge on REQUEST per character requested and the timing for this is shown in Figure 20. The one exception occurs in synchro- nous modes at the end of CRC transmission. At the end of CRC transmission, when the closing flag or sync character is loaded into the Transmit Shift re- gister, REQUEST is pulsed High for one PCLK cy- cle. The DMA may use this falling edge on RE- QUEST to write the first character of the next frame or block to the SCC. In the 28530, REQUEST will go High in response to the falling edge of WR, but only when the appro- priate transmit buffer in the SCC is accessed. This is shown in Figure 21. DMA Request On Transmit (using DIR/ REQ). A second Request on Transmit function is available on the DTR/ REQ pin. This mode is selected by set- ting D2 of WR14 to "1". When this bit is set to "1", REQUEST goes Low if the transmit buf-fer is emp- ty at the time, or will go High until the transmit buff- er becomes empty. While D2 of WR14 is set to "0", the DTR REQ pin is DTR and follows the inverted state of D7 in WRS. This pin will be High after a chan- nel or hardware reset and in the DTR made. In the Request mode REQUEST will follow the state of the transmit buffer even though the transmitter is di- sabled. Thus if REQUEST is enabled before the transmitter is enabled, the DMA may write data to the SCC before the transmitter is enabled. This will not cause a problem in Asynchronous mode, but may cause problems in Synchronous mode be- cause the SCC will send data in preference to flags or sync characters. It may also complicate the CRC initialization, which cannot be done until after the transmitter is enabled. With only one exception, the REQUEST pin directly follows the state of the trans- mit buffer in this mode. REQUEST goes Low when the transmit buffer empties and remains Low until the transmit buffer is filled. The SCC generates on- ly one falling edge on REQUEST per character re- quested. The one exception occurs in synchronous modes at the end of CRC transmission. At the end of CRC transmission, when the closing flag or sync character is loaded into the Transmit Shift register, REQUEST is pulsed High for one PCLK cycle. The DMA may use this falling edge on REQUEST to 26/93 ii SGS-THOMSON write the first character of the next frame or block to the SCC. The Request signal on DTR/ REQ differs from the one on W/ REQ in that it does not go im- mediately High in response to the access which writes to the transmit buffer. This is because the re- gisters in the SCC are not written during the actual access, but are delayed by some number of PCLK cycles. The Request signal on DTR/ REQ follows the state of the transmit buffer exactly while the Re- quest signal on W/ REQ goes inactive in anticipa- tion of the transmit buffer becoming full. The timing of the Request signal on both pins is shown in Fi- gure 21. DMA Request On Receive. The Request on Re- ceive function is selected by setting D6 and D5 of WA1 to "1" and then enabling the function by set- ting D7 of WR1 to "1". In this mode the W/ REQ pin carries the REQUEST signal, which is active Low. When this mode is selected, but not yet enabled, the W/ REQ pin is driven High. When the enable bit is set REQUEST goes Low if the receive buffer contains a character at the time, or will remain High until a character enters the receive buffer. Note that the REQUEST pin will follow the state of the receive buffer even though the receiver is disabled. Thus, if the receiver is disabled and REQUEST is still en- abled, the DMA will transfer the previously received data correctly. In this mode the REQUEST pin di- rectly follows the state of the receive buffer with on- ly one exception. REQUEST goes Low when a cha- racter enters the receive buffer and remains Low un- til this character is removed from the receive buf-fer. The SCC generates only one falling edge on RE- QUEST per character transfer requested and the ti- ming for this is shown in Figure 22. The one excep- tion occurs in the case of a special receive condition in the Receive Interrupt on First Character or Spe- cial Condition mode, or the Receive Interrupt on Special Condition Only mode. In the two interrupt modes any receive character with a special receive condition is locked at the top of the FIFO until an Er- ror Reset command is issued. This character in the receive FIFO would ordinarily cause additional DMA Requests after the first time it is read. However, the logic in the SCC guarantees only one falling edge on REQUEST by holding REQUEST High from the time the character with the special receive condition is read, and the FIFO locked, until after the Error Re- set command has been issued. Once the FIFO is unlocked by the Error Reset command, REQUEST again follows the state of the receive buffer. In the 28530, REQUEST will go High in response to the falling edge of RD, but only when the appropriate receive buffer in the SCC is accessed. This is shown in Figure 23. MICROELECTRONICS 47428530 1/0 PROGRAMMING CAPABILITIES (cont'd) Figure 18 : Wait on Transmit. Figure 19 : Wait on Receive. wo a a 3 g ~ = e | 12 L scene MODES "1 sere MODES 10 = RTc 1 2 3 4 5 neu VI VSI VSI VTS ', fs x ig x 2 = te rr {7 SGS-THOMSON 27/98 Y/ imcromecrnomes 47528530 1/0 PROGRAMMING CAPABILITIES (cont'd) Figure 20 : Transmit Request Assertion. Figure 21 : Transmit Request Release. 3 = z Pm] Q : Ps P< NY P< MI D<J = z = PLN s s < rt so a fp @ & & > Po @ & F = - z a ig 2 iS ig F ig F 4 [4 28/93 G7 SGS-THOMSON Tf imcnorectnomes 47628530 1/0 PROGRAMMING CAPABILITIES (cont'd) Figure 22 : Receive Request Assertion. Figure 23 : Z8530 Receive Request Release. Z a oo = z U, 3 ~ o = = 2 2 __ 10 IS aN . NEN io < s ws = o ~ iz 2 os Og e & @3 & Se s * * SGS-THOM 29/98 ii SGS-THOMSON 47728530 PROGRAMMING DATA COMMUNICATION MODES The SCC provides two independent full-duplex channels programmable for use in any common asynchronous or synchronous data communication protocol. These include asynchronous, synchro- nous byte-oriented protocols, monosync, IBM Bi- sync, and bit-oriented protocols such as HDLC and SDLC. This chapter is divided into 3 parts : Asyn- chronous, Synchronous, and SDLC. Asynchronous Mode The SCC supports Asynchronous mode with a num- ber of programmable options including the number of bits per character, the number of stop bits, the clock factor, modem interface signals and break de- tect and generation. Asynchronous mode is selec- ted by programming the desired number of stop bits in Dg and De of WR4. Programming these two bits with other than "00" places both the receiver and transmitter in Asynchronous mode. Inthis mode, the SCC ignores the state of bits D4, Ds, D2, and D1 of WR3, bits Ds and Da of WR4, bits D2 and Do of WR5, all of WR6 and WR7 and all of WR10 except De and Ds. Bits that are ignored may be programmed with "4" or "O" or not at all. Asynchronous Receive. Asynchronous mode is selected by specifying the number of stop bits per character in WR4. This selection applies only the transmitter, however, as the receiver always checks for one stop bit. If after character assembly the re- ceiver finds this stop bit to be a "0", the Framing Er- ror bit in the receive error FIFO is set at the same time that the character is transferred to the receive data FIFO. This error bit accompanies the data to the top of the FIFO, where it generates a special re- ceive condition. The Framing Error bit is not latched, and so must be read in RR1 before the accompa- nying data is read. The number of bits per character is controlled by bits D7 and D6 of WR3. Five, six, seven, or eight bits per character may be selected via these two bits. Data is right-justifed with the unused bits set to "1s". An additional bit, carrying parity information may be selected by setting bit DO of WR4 to "1". Note that this also enables parity for the transmitter. The parity sense is selected by bit D1 of WR4. If this bit is set to 1", the received character is checked for even parity, if set to "0", the received character is checked for odd parity. The additional parity bit per character is transferred to the receive data Fl- FO along with the data if the data plus parity is eight bits or less. The parity Error bit in the receive error FIFO may be programmed to cause a special re- ceive condition interrupt by setting bit D2 of WR1 to 30/93 i SGS-THOMSON "1". This error bit is latched and so will remain ac- tive, once set, until an Error Reset command has been issued. If interrupts are not used to transfer data, the Parity Error, Framing Error, and Overrun Error bits in RR1 should be checked before the da- ta is removed from the receive data FIFO. The break condition is continuous "Os", as opposed to the usual continuous ones during an idle. The SCC recognizes the Break condition upon seeing a null character (all "Os") plus a framing error. Upon recognizing this sequence the Break bit in RRO will be set and will remain set until a "1" is received. At this point the break condition is no longer present. At the termination of a break the receive data FIFO contains a single null character, which should be read and discarded. The Framing Error bit will not be set for this character, but if odd parity has been selected, the Parity Error bit will be set. Caution should be exercised if the receive data line contains a switch that is not debounced to generate breaks. Switch bounce may cause multiple breaks, recogni- zed by the SCC to be additional characters assem- bled in the receive data FIFO. it may also cause a receive overrun condition being latched. The SCC may be programmed to accept a receive clock that is one, sixteen, thirty-two, or sixty-four times the data rate. This is selected by bits D7 and D6 in WR4. The 1X mode is used when bits are syn- chronized external to the receiver. The 1X mode is the only mode in which a data encoding method other than NRZ may be used. The clock factor is common to the receiver and transmitter. The SCC provides up to three modem control si- gnais associated with the receiver. The SYNC pin iS a general-purpose input whose state is reported in the Sync/Hunt bit in RRO. If the crystal oscillator is enabled, this pin is not available and the Sync/Hunt bit is forced to "0". Otherwise, the SYNC pin may be used to carry the Ring Indicator signal. The DTR/ REQ pin carries the inverted state of the DTR bit (D7) in WRS unless this pin has been pro- grammed to carry a DMA Request signal. The DCD pin is ordinarily a simple input to the DCD bitin RRO. However, if the Auto Enables mode is selected by setting DS of WR3 to 1, this pin becomes an en- able for the receiver. That is, if Auto Enables is on and the DCD pin is HIGH, the receiver is disabled. While the DCD pin is LOW, the receiver is enabled. The initialization sequence for the receiver in Asyn- chronous mode is : WRa first to select the mode,then WR3 and WRS8 to select the various op- tions. At this point, the other registers should be ini- MICROELECTRONICS 47828530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) tialized as necessary. When all of this is complete the receiver may be enabied by setting bit Do or WR3 to "1". Asynchronous Transmit. Asynchronous mode is selected by specifying the number of stop bits per character in bits D3 and De of WR4. The three op- tions available are one, one-and-a-half, or two stop bits per character. These two bits only select the number of stop bits for the transmitter, as the recei- ver always checks for one stop bit. The number of bits per transmitted character is con- trolled both by Bits Ds and Ds in WR5 and the way the data is formatted within the transmit buffer. The bits in WR5 allow the option of five, six seven, or eight bits per character. When five bits per charac- ter is selected the data may be formatted before being written to the transmit buffer to allow transmis- sion of from one to five bits per character. This formatting is shown in Table 5. Table 5 : Data Format - Five Bits or Less. D7|D 6|D 5|D 4/D 3/D 2|/D 11D 5 One data bit Two data bits Three data bits Four data bits Five data bits Onuaaa oo+4-4 ooo-+4 oeoo0o0o- ogoo000 eo0000 eooo0n0 oco000 In all cases the data must be right-justified, with the unused bits being ignored except in the case of five bits per character. An additional bit, carrying parity information, may be automatically appended to eve- ry transmitted character by setting bit DO of WR4 to "1". This bit is sent in addition to the number of bits specified in WR4 or by the data format. The parity sense is selected by bit D1 of WR4. If this bit is set to"1", the transmitter sends even parity, if set to "0", the parity is odd. The transmitter may be programmed to send a Break by setting bit D4 of WR5 to "1". The transmit- ter will send continuous "Os" from the first transmit clock edge after this command is issued, until the first transmit clock edge after this bit is reset. The transmit clock edges referred to here are those that define transmitted bit cell boundaries. An additional status bit for use in Asynchronous mode is available in bit Do or RR1. This bit, called All Sent, is set when the transmitter is completely empty and any previous data or stop bits have rea- ched the TxD pin. The All Sent bit can be used by i SGS-THOMSON the processor as an indication that the transmitter may be safely disabled. The SCC may be programmed to accept a transmit clock that is one, sixteen, thirty-two, or sixty-four time the data rate. This is selected by bits D7 and De of WR4, in common with the clock factor for the receiver. Note that the chosen clock factor may re- strict the number of stop bits that may be transmit- ted. In particular, when the clock rate and data rate are identical, one-and-a-half stop bits are not allo- wed. If any length other than one stop bit is desired in the times one mode, only two stop bits may be used. There are two modem control signals associated with the transmitter provided by the SCC. The RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5, unless the Auto Enables bit (Ds) is set in WR3. When Auto Enables is set the RTS pin will immediately go LOW when the RTS bit is set. However, when the RTS bit is reset the RTS pin remains LOW until the transmitter is completely empty and the last stop bit has left the TxD pin. Thus the RTS pin may be used to disable external drivers for the transmit data. The CTS pin is ordinarily a sim- ple input to the CTS bit in RRO. However, if Auto En- ables mode is selected this pin becomes an enable for the transmitter. That is, if Auto Enables is on and the CTS pin is HIGH, the transmitter is disabled ; the transmitter is enabled while the CTS pin is LOW. The initialization sequence for the transmitter in Asynchronous mode is : WR4 first to select the mode, then WR3 and WR5 to select the various op- tions. At this point the other registers shouid be ini- tialized as necessary. When ail of this is complete, the transmitter may be enabled by setting bit D3 of WR5 to "1". Note that the transmitter and receiver may be initialized at the same time. Synchronous Mode In synchronous modes of operation a special bit pat- tern is used to provide character synchronization. The SCC offers several options to support Synchro- nous mode including various sync character lengths, the number of bits per data character, pa- rity generation and checking, CRC generation and checking, as well as modem controls and a trans- mitter to receiver synchronization function. Synchro- nous mode is selected by programming bits Ds and D2 of WR4 with "Os". This selects Synchronous mode, as opposed to Asynchronous mode, but this selection is further modified by bits Ds andD7 of WR4 as well as bits D1 and Do of WR10. 31/93 MICROELECTRONICS 47928530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) The sync character or characters are written in WR6 and WR7. In all synchronous modes, except Exter- nal Sync the state of bits D7 and Dg of WR4 are for- ced to "0" to select the times one clock made. In Ex- ternal Sync mode these two bits must be program- med with "Os". Synchronous Receive. The receiver in the SCC searches for character synchronization only while it is in Hunt mode. !n this mode the receiver is idle ex- cept that it is searching the incoming data stream for a sync character match. The receiver is in Hunt mode when it is first enabled, and may be placed in Hunt mode by command from the processor. This is accomplished by issuing the Enter Hunt Mode command in WR3. This bit (D4) is a command ; wri- ting a "0" to it has no effect. The Hunt status of the receiver is reported by the Sync/ Hunt bit in RRO. Sync/Hunt is one of the possible sources of exter- nal/status interrupts, with both transitions causing an interrupt. This is true even if the Sync/ Hunt bit is set as a result of the processor issuing the Enter Hunt Mode command. An 8-bit sync character is selected by setting bits Ds and D4 of WR4, as well as bit DO of WR10, to "0". With this option the receiver searches the data stream for a match will the eight bits in WR7. The 6- bit sync option requires the same programming ex- cept that DO of WR10 is set to "1" and the sync cha- racter is held in the high-order six bits of WR7. The SCC also allows the option of double length sync characters. This is selected by setting bit Ds of WR4 to "0" and bit D4 of WR4 to "1". The selection be- tween 12 and 16 bits of sync character is controlled by bit DO of WR10. A"0" selects 16 bits of sync cha- racter, while a1 in this bit selects a 12-bit sync cha- racter. The arrangement of the sync character in WRE6 and WR7 is shown in Figure 24. For those ap- plications requiring any other sync character length, the SCC makes provision for an external circuit to provide a character synchronization signal on the SYNC pin. This mode is selected by setting bit Ds and D4 of WR4 to "1". In this mode the Sync/Hunt bit in RRO reports the state of the SYNC pin but the receiver must still be placed in Hunt mode when the external logic is searching for a sync character match. When the receiver is in Hunt mode and the SYNC pin is driven LOW, two receive clock cycles after the last bit of the sync character is received, character assembly will begin on the rising edge of the receive clock immediately preceding the activa- tion of SYNC. This is shown in Figure 25. The recei- ver leaves Hunt mode when SYNC is driven LOW. In all cases except External Sync mode the SYNC pin is an output that is driven LOW by the SCC to 32/93 ik SGS-THOMSON signal that a sync character has been received. The SYNC pinis activated regardless of character boun- daries so any external circuitry using it should only respond the SYNC pulse that occurs while the re- ceiver is in Hunt mode. The timing for the SYNC si- gnal is shown in Figure 26. The number of bits per character is controlled by bits D7 and De of WR3. Five, six, seven, or eight bits per character may be selected via these two bits. The data is right-justified in the receive data buffer. The SCC merely takes a snapshot of the receive data stream at the appropriate times so the "unused" bits in the receive buffer are only the bits following the character in the data stream. An additional bit, car- rying parity information, may be selected by setting bit Do of WR4 to "1". If this bit is set to "1", the recei- ved character is checked for even parity, if set to "0", the received character is checked for odd parity. The additional bit per character is visible in the receive data FIFO if the data plus parity is eight bits or less. The parity bit is not visible when there are eight da- ta bits per character. The Parity Error bit in the re- ceive error FIFO may be programmed to cause a Special Receive Condition interrupt by setting bit D2 of WR1 to "1". This error bit is latched and so will re- main active, once set, until an Error Reset command has been issued. If interrupts are not used to trans- fer data the Parity Error, CRC Error, and Overrun Error bits in RR1 should be checked before the da- tais removed from the receive data FIFO. The cha- racter lenght may be changed at any time before the new number of bits has been assembled by the re- ceiver, but, care should be exercised as unexpec- ted results may occur. A representative example, switching from five bits to eight bits and back to five bits is shown in Figure 27. It is sometimes desirable to prevent sync characters in the receive data stream from being transferred to the receive data FIFO. This function is available in the SCC by set- ting the Sync Character Load Inhibit bit (D1) in WR3 to "1". While this bit is set to "1", character about to be loaded into the receive data FIFO is compared with the contents of WR6. If all eight bits match the character, it is not loaded into the receive data FI- FQ. Because the comparison is across eight bits, this function works correctly only when the number of bits per character is the same as the sync cha- racter length. Thus it cannot be used with 12- or 16- bit sync characters. Both leading sync characters and sync characters embedded in the data will be properly removed in the case of an 8-bit sync cha- racter, but only the leading sync characters may be properly removed in the case of a 6-bit sync charac- ter. Care must be exercised in using this feature be- MICROELECTRONICS 48028530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) cause sync characters not transferred to the receive data FIFO will automatically be excluded from CRC calculation. This works properly only in the 8-bit case. Either of two CRC polynomials may be used in syn- chronous modes, selected by bit D2 in WRB. If this bit is set to "1", the CRC-16 polynomial is used, if this bit is set to "0", the CRC-CCITT polynomial is used. This bit controls the polynomial selection for both the receiver and transmitter. The initial state of the generator and checker is controlled by bit D7 of WR10. When this bit is set to "1", both the generator and checker will have an initial value of all ones, if this bit is set to "0", the initial values will be all "Os". The SCC presets the checker whenever the recei- ver is in Hunt mode so a CRC reset command is not strictly necessary. However, the CRC checker may be preset by issuing the Reset CRC Checker com- mand in WRO. This command is encoded in bits Dz Figure 24 : Sync Character Programming. and De of WRO. If CRC is to be used the CRC checker must be enabled by setting bit DO of WR3 to"1". If sync characters are being stripped from the data stream, this may be done at any time before the first non-syne character is received. If the sync strip feature is not being used, CRC must not be en- abled until after the first data character has been transferred to the receive data FIFO. As previously mentioned, 8-bit sync characters stripped from the data stream are automatically excluded from CRC calculation. Some synchronous protocols require that certain characters be excluded from CRC calculation. This is possible in the SCC because CRC calculation may be enabled and disabled on the fly. To give the processor sufficient time to decide whether or not a particular character should be included in the CRC calculation, the SCC contains an 8-bit time delay be- tween the receive shift register and the CRC to] SYNC? SYNC, SYNCs SYNC, SYNC3 SYNC SYNC; SYNCo MONOSYNC., 8 BITS SYNC, SYNCo SYNC5 SYNC, SYNC} SYNC2 SYNC, SYNCp MONOSYNC. 6 BITS SYNC? SYNC. SYNCs SYNC, SYNCy SYNC2 SYNC, SYNCo BISYNC, 16 BITS SYNC SYNC2 SYNC; SYNCp 1 1 1 1 BISYNC, 12 BITS ADR, ADRs ADRs ADR, ADR; ADR2 ADR, ADRg SDLC ADR; ADRs ADRs ADR, x x x x SDLC (ADDRESS RANGE) SYNC; SYNCg SYNCs SYNC, SYNC SYNC2 SYNC, SYNCo MONOSYNC. 8 BITS SYNCs SYNC, SYNC3 SYNC? SYNC, SYNCo x x MONOSYNC, 6 BITS SYNCi5 SYNC SYNC33 SYNCi2 SYNCH SYNCi9 SYNCg SYNC, BISYNC. 16 BITS SYNC: SYNCio SYNCg SYNCa SYNC; SYNC5 SYNCs SYNC, BISYNC. 12 BITS o 1 1 1 1 1 1 Oo SBLC SGS-THOMSON 39/93 MICROELECTRONICS 48128530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) Figure 25 : SYNC as an Output. Figure 26 : SYNC as an Input. RTx >< DATA DATA, DATAg va x SYNC Last SYNCLasT-1 X RTxc PCLK N 34/93 482 by SGS-THOMSON MICROELECTRONICS28530 PROGRAMMING DATA COMMUNICATION MODES (contd) checker. The logic also guarantees that the caicu- lation will only start or stop on a character boundary by delaying the enable or disable until the next cha- racter is loaded into the receive data FIFO. To un- derstand how this works refer to Figure 28 and the following explanation. Consider a case where the SCC receives a sequence of eight bytes, called A, B, C, D, E, F, Gand H with A receiver first. Now sup- pose that A is the sync character, that CRC is to be calculated on B, C, E, and F, and that F is the last byte of this message. Before A is received the re- ceiver is in Hunt mode and the CRC is disabled. When A is in the receive shift register it is compared with the contents of WR7. Since A is the sync cha- racter, the bit patterns match and receiver leaves Hunt mode, but character A is not transferred to the receive data FIFO. The CRC remains disabled even though somewhere during the next eight-bit-time processor reads B and enables CRC. At the end of Figure 27 : Changing Character Length. an eight-bit-time, B is in the 8-bit delay and C is in the receive shift register. At this point, B is loaded into the receive data FIFO. The CRC remains disa- bled even though somewhere during the next eight bit times the processor reads B and enables CRC. At the end of the eight-bit-time, B is in the 8-bit de- lay and C is in the receive shift register. Character C is loaded into the receive data FIFO and at the same time the CRC checker is enabled. During the next eight-bit-time, the processor reads C and leaves the CRC enabled. At the end of these eight- bit-times the SCC has calculated CRC on B, cha- racter C is the 8-bit delay and D is in the Receive Shift register. D is then loaded into the receive data buffer and at some point during the next eight-bit- time the processor reads D and disables CRC. At the end of these eight-bit-times CRC has been cal- culated on C, character D is in the 8-bit delay and E is in the Receive Shift register. ky IOMSON MICRORLECTRONICS RECEIVE DATA BUFFER Js 7 6 4 3 2 4 | 5 BITS TIME | 13 42 vi 10 9 8 7 6 | 8 BITS CHANGE FROM FIVE TO EIGHT >- | 2 20019 18 17 16~15:st | 8 BITS | 29 28 27 26 25 24 23 22 | 5 81TS CHANGE FROM EIGHT TO FIVE -> J 30 3300 32 3t 36 29 28 a] 5 BITS | 39 38 O37 36 35 34 330032 | SGS-TH 35/93 48328530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) Now E is loaded into the receiver data FIFO and, at the same time, the CRC is disabled. During the next eight-bit-times the processor reads E and enables the CRC. During this time E shifts into the 8-bit de- lay, F enters the Receive Shift register and CRC is not being calculated on D. After these eight-bit-times have elapsed, E is in the 8-bit delay, and F is in the Receive Shift register. Now F is transferred to the receive data FIFO and CRC is enabled. During the next eight-bit-times the processor reads F and leaves the CRC enabled. The processor is usually aware that this is the last character in the message and so prepares to check the result of the CRC com- putation. However, another sixteen bit-times are re- quired before CRC has been calculated on all of character F. At the end of eight-bit-times F is in the 8-bit delay and Gis in the Receive Shift register. At this time G is transferred to the receive data FIFO. Character G must be read and discarded by the pro- cessor. Eight bit times later H is transferred to the receive data FIFO also. The result of a CRC calcu- lation is latched in the receive error FIFO atthe same time as datais written to the receive data FIFO. Thus the CRC result through character F accompanies Figure 28 : Receive CRC Data Path. character H in the FIFO and will be valid in RR1 un- til character H is read from the receive data FIFO. The CRC checker may be disabled and reset at any time after character H is transferred to the receive data FIFO. Recall, however, that internally CRC will not be disabed until a character is loaded into the receive data FIFO so the reset command should not be issued until after this occurs. A better alternative is to place the receiver in Hunt mode, which auto- matically disables and resets the CRC checker. Up to two modem control signals associated with the receiver are available is synchronous modes. The DTR/ REQ pin carries the inverted state of the DTR bit (D7) in WR5 unless this pin has been pro- grammed to carry a DMA Request signal. The DCD pin is ordinarily a simple input to the DCD bitin RRO. However, if the Auto Enables mode is selected by setting DS of WR3 to "1", this pin becomes an en- able for the receiver. That is, if Auto Enables is on and the DCD pin is HIGH the receiver is disabled ; while the DCD pin is LOW the receiver is enabled. The initialization sequence for the receiver in syn- chronous modes is WR4 first, to select the mode, Lt iti i tt Liid tit | RECEIVE DATA FIFO ,7y ytd RECEIVE DATA___ RECEIVE SHIFT REGISTER | EIGHT BIT TIME DELAY CRC CHECKER | 36/93 kr SGS-THOMSON MICROELECTRONICS 484Z8530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) then WR10 to madify it if necessary, WR6 and WR7 to program the sync characters and then WR3 and WRS to select the various options. At this point the other registers should be initialized as necessary. When all of this is complete the receiver is enabled by setting bit D of WR3 to "1". Synchronous Transmit. Once Synchronous mode has been selected, any of three sync character lengths may be selected. An 8-bit sync character is selected by setting bits Ds and D4 or WR4, as well as bit DO of WR10 to "0". With this option selected the transmitter sends the contents of WR6 when it has no data to send. The 6-bit sync option requires the same programming except that bit DO of WR10 is set to "1" and only the least significant six bits of WR6 and used as a time fill. For a 16-bit sync cha- racter, set bit Da of WR4 to 1 and Ds of WR4 and bit Do of WR10 to "0". In this mode the transmitter sends the concatenation of WR6 and WR7 as atime fill. Because the receiver requires that sync charac- ters be left-justified in the registers, while the trans- mitter requires them to be right-justified, only the re- ceiver will work with a 12-bit sync character. While the receiver is in External Sync mode the transmit- ter sync length may be six or eight bits, as selected by bit DO of WR10. The number of bits per transmitted character is con- trolled by bits Dg and Ds of WR5 and the way the data is formatted within the transmit buffer. The bits in WRS allow the option of five, six, seven, or eight bits per character. When five bits per character is selected the data may be formatted before being written to the transmit buffer to allow transmisssion of from one to five bits per character. This format- ting is shown in Table 5. In all cases the data must be right-justified, with the unused bits being ignored except in the case of five bits per character. An ad- ditional bit, carrying parity information, may be auto- matically appended to every transmitted character by setting bit Do of WR4 to "1". This parity bit is sent in addition to the number of bits specified in WR4 or by the data format. If this bit is set to "1", the trans- mitter will send even parity, if set to "0", the trans- mitted parity will be odd. Either of two CRC polynomials may be used in syn- chronous modes, selected by bit D2 in WRS. If this bit is set to "1", the CRC-16 polynomial is used and, if this bit is set to "0", the CRC-CCITT polynomial is used. This bit controls the selection for both the transmitter and receiver. The initial state of the gen- erator and checker is controlled by bit D7 of WR10. When this bit is set to "1", both the generator and checker will have an initial value of all ones, if this ir SGS-THOMSON bit is set to "0", the initial values will be all zeros. The SCC does not automatically preset the CRC gene- rator, so this must be done in software. This is ac- complished by issuing the Reset Tx CRC Genera- tor command, which is encoded in bits D7 and De of WRO. For proper results this command must be is- sued while the transmitter is enabled and sending sync characters. If CRC is to be used, the transmit CRC generator must be enabled by setting bit DO of WR5 to "1". This bit may also be used to exclude certain characters from the CRC calculation. Sync characters are automatically excluded from the CRC calculation and any characters written as da- ta may also be excluded from the caiculation by using bit Do of WR5. Internally, the CRC is enabled or disabled for a particular character at the same time as the character is loaded from the transmit buffer to the Transmit Shift register. Thus, to exclude a character from CRC calculation bit, Do of WR5 should be set to "0" before the character is written to the transmit buffer. This guarantees that the in- ternal disable will occur when the character moves from the buffer to the shift register. Once the buffer becomes empty, the Tx CRC Enable bit may be writ- ten for the next character. Enabling the CRC generator is not sufficient to control the transmission of CRC. In the SCC this function is controlled by the Tx Underrun/EOM bit, which may be reset by the processor and set by the SCC. When the transmitter underruns (both the transmit buffer and Transmit Shift register are emp- ty) the state of the Tx Underrun/EOM bit determines the action taken by the SCC. If the tx Underrun/EOM bit is set when the underrun occurs, the transmitter will send sync characters, if this bit is reset when the underrun occurs, the transmitter will send the accu- mulated CRC followed by sync characters. When the CRC is loaded into the transmit Shift register for transmission, the SCC will set the Tx Under- run/EOM bit to indicate this. This transition may be programmed to cause an external/status interrupt, or the Tx Underrun/EOM is available in RRO. The Reset Tx Underrun/EOM Latch command is enco- ded in bits D7 and Dg in WRO. For correct transmis- sion of the CRC at the end of a block of data, this command must be issued after the first character is written to the SCC but before the transmitter under- runs after the last character written to the SCC. The command is usually issued immediately after the first character is written to the SCC so that CRC will be sent if an underrun occurs inadvertently during the block of data. In synchronous modes, if the transmitter is disabled during transmission of a character, that character 37/93 MICROELECTRONICS 48528530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) willbe sent completely. This applies to both data and sync characters. However, if the transmitter is disa- bled during the transmission of CRC, the 16-bit transmission will be completed, but the remaining bits will come from the SYNC registers rather than the remainder of the CRC. There are two modem contro! signals associated with the transmitter provided by the SCC. The RTS pin is a simple output that carries the inverted state of the RTS bit (Di) in WR5. The CTS pin is ordina- rily a simple input to the CTS bit in RRO. However, if Auto Enables mode is selected this pin becomes an enable for the transmitter. Thatis, if Auto Enables is on and the CTS pin is HIGH the transmitter is di- sabled. While the CTS pin is LOW, transmitter is en- abled. The initialization sequence for the transmitter in syn- chronous modes is : WR4 first, to select the mode, then WR10 to modify it if necessary, WR6 and WR7 to program the sync characters, then WR3 and WR5 to program the sync characters, and then WR3 and WRS to select the various options. At this point, the other registers should be initialized as necessary. When all of this is complete the transmitter may be enabled by setting bit D3 or WR5 to "1". Now that the transmitter is enabled the CRC generator may be initialized by issuing the Reset Tx CRC Genera- tor command in WRO. Transmitter To Receiver Synchronization. The SCC contains a transmitter-to-receiver synchroni- zation function that may be used to guarantee that the character boundaries for the received and trans- mitted data are the same. In this mode the receiver is in Hunt and the transmitter is idle, sending either all"1s" or "Os". When the receiver recognizes a sync character, it leaves Hunt mode and one character time later the transmitter is enabled and begins sen- ding sync characters. Beyond this point the receiver and transmitter are again completely independent, except that the character boudaries are now ali- gned. This is shown in Figure 29. There are several restrictions on the use of this feature in the SCC. First, it will only work with 6-bit, 8-bit or 16-bit sync characters, and the data character length for both the receiver and the transmitter must be six bits with a 6-bit syne character or eight bits with an 8-bit or 16-bit syne character. Of course, the receive and transmit clocks must have the same rate as well as the proper phase relation-ship. A specific sequence of operations must be followed to synchronize the transmitter to the receiver. Both the receiver and transmitter must have been initia- lized for operation in Synchronous mode sometime in the past, although this initialization need not be redone each time the transmitter is synchronized to the receiver. The transmitter is disabled by setting bit D3 of WRS to "0". At this point the transmitter will send continuous "1s". If it is desired that continuous "1s". If itis desired that continuous "Os" be transmit- ted, the Send Break bit (D4) in WR5 should be set to "1". The transmitter is now idling but must still be placed in the transmitter to receiver synchronization mode. This is accomplished by setting the Loop Figure 29 : Transmitter to Receiver Synchronization. DIRECTION OF MESSAGE FLOW RxD I | _sNe SYNC | | | SYNC | TxD SYNC ] RECEIVER LEAVES HUNT 38/93 (7 SGS-THOMSON yy MICROELECTRONICS 48628530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) the processor should set the Go Active on Poll bit (Da) in WR10. The final step is to force the receiver to search for sync characters. If the receiver is cur- rently disabled the receiver will enter Hunt mode when it is enabled by setting bit Do of WR3 to "1". If the receiver is already enabled it may be placed in Hunt mode by setting bit D4 of WR3 to "1". Once the receiver leaves Hunt mode the transmitter is acti- vate on the following character boundary. SDLC Mode SDLC mode is useful in bit-oriented protocols. That is, protocols which use the technique of "0" insertion to achieve data transparency. In SDLC mode, frames of information are opened and closed by a unique bit pattern called a flag. The Flag character has a bit pattern of "01111110" and this sequence is unique because all data between the opening and closing flags is prohibited from having more than five consecutive "1s". The transmitter guarantees this by watching the transmit data stream and inserting a "0" after five consecutive ones, irrespective of cha- racter boundaries. In turn, the receiver searches the receive data stream for five consecutive "1s" and deletes the next bit if it is a "O". CRC may be used in SDLC mode but only with the CRC-CCITT poly- nomial, because the transmitter in the SCC automa- tically inverts the CRC before transmission, and the receiver - to compensate for this - checks the CRC result for the bit pattern "0001110100001111". This is consistent with bit-oriented protocols such as SDLC, HDLC, and ADCCP. There are two unique bit patterns in SDLC mode besides the flag se- quence. They are the Abort and EOP (End of Poll) sequence. An Abart is a sequence of from seven to thirteen consecutive "1s" and is used to signal the premature termination of a frame. The EOP is the bit pattern "11111110", which is used in loop appli- cations as a signal to a secondary station that it may begin transmission. Table 6 : Residue Codes. SDLC mode is selected by setting bit Ds of WR4 to "{" and bits Da, D3, and D2 of WR4 to "0". In addi- tion, the flag sequence must be written to WR7. Ad- ditional control bits for SDLC mode are located in WR10. SDLC Receive. The receiver in the SCC always searches the receive data stream for flag characters in SDLC mode. Ordinarily, the receiver transfers all received data between flags to the receive data Fl- FO. However, if the receiver is in Hunt mode no flag is received. The receiver is in Hunt mode when first enabled, or the receiver may be placed in Hunt mode by the processor issuing the Enter Hunt mode command in WR3. This bit (D4) is a command, and writing a O" to it has no effect. The Hunt status of the receiver is reported by the Sync/Hunt bit in RRO. Sync/Hunt is one of the possible sources of external/status interrupts, with both transitions cau- sing an interrupt. This is true even if the Sync/Hunt bit is set as a result of the processor issuing the En- ter Hunt mode command. The receiver will automa- tically enter Hunt mode if an abort is received. Be- cause the receiver always searches the receive da- ta stream for flags and automatically enter Hunt Mode when an abort is received, the receiver will al- ways handle frames correctly, and the Enter Hunt Mode command should never to needed. The SCC will drive the SYNC pin LOW to signal that a flag has been recognized. The timing for the SYNC signal is shown in Figure 30. The first byte in an SDLC frame is assumed by the SCC to be the address of the secondary station for which the frame is intended. The SCC provides se- veral options for handling this address. If the Ad- dress Search Mode bit (Dz) in WR3 is set to "0", the address recognition logic is disabled and all recei- ved frames are transferred to the receive data FI- FO. In this mode the software must perform any ad- dress recognition. If the Address Search Mode bit is ir SGS-THOMSON Residue Code Bits in Previous Byte Bits in See te Previous Bits in Third Previous Byte 2 1 0 |8 B/C|7 B/C|6 B/C!|5 B/C|8 B/C|7 B/C |6 B/C|5 B/C |8 B/C|7 B/C |6 B/C|5 BIC 1 0 0 0 0 0 0 3 1 0 0 8 7 5 2 0 1 0 0 0 0 0 4 2 0 0 8 7 6 3 1 1 0 0 0 0 0 5 3 1 0 8 7 6 4 0 0 1 0 0 0 0 6 4 2 0 8 7 6 5 1 0 1 0 0 0 0 7 5 3 1 8 7 6 5 0 1 1 0 0 0 - 8 6 4 : 8 7 6 - 1 1 1 1 0 - 8 7 : 8 7 - 0 0 0 2 - 8 - 8 - 39/93 MICROELECTRONICS 48728530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) set to "1", only those frames whose address matches the address programmed in WR6 or the global address (all 1s") will be transferred to the re- ceive data FIFO. The address comparison will be across all eight bits of WR6 if the Sync Character Load Inhibit bit (D1) in WR3 is set to 0. The com- parison may be modified so that only the four most significant bits of WR6 must match the received ad- dress. This mode is selected by setting the Sync Character Load Inhibit bit to "1". In this mode, ho- wever, the address field is still eight bits wide. The address field is transferred to the receive data FIFO in the same manner as data. It is not treated diffe- rently than data. The number of bits per character is controlled by bits D7 and Dg of WRG. Five, six, seven, or eight bits per character may be selected via these two bits. The data is right-justified in the receive buffer. The SCC merely takes a snapshot of the receive data stream at the appropriate times, so the unused bits in the receive buffer are only the bits following the charac- ter in the data stream. An additional bit carrying pa- rity information may be selected by setting bit Dg of WR4 to "1". This also enables parity in the transmit- ter. The parity sense is selected by bit Di of WR4. Parity is not normally used in SDLC mode. The cha- racter length may be changed at any time before the new number of bits have been assembled by the re- ceiver. Care should be exercised, however, as unexpected results may occur. A representative example, switching from five bits to eight bits and back to five bits is shown in Figure 31. Most bit-oriented protocols allow an arbitrary num- ber of bits between opening and closing Flags. The SCC allows for this by providing three bits of Resi- due Code in RR1 that indicate which bits in the last few bytes transferred from the receive data FIFO by the processor are actually valid data bits. The mea- ning of these three bits with each character length option is shown in Table 6. As indicated in the table, these bits allow the processor to determine those bits in the information (and not CRC) field. This al- lows transparent retransmission of the received frame. The Residue Code bits do not go through a FIFO so they change in RR1 when the last charac- ter of the frame is loaded into the receive data FI- FO. If there are any characters already in the receive data FIFO the Residue Code will be updated before they are read by the processor. Thus these three bits off RR1 should be ignored by the processor un- less the End of Frame bit in RR1 is set. Only the CRC-CCITT polynomial may be used for CRC calculation in SDLC mode, although the gene- 40/08 57 S&S:THOMSON Figure 30 : SYNC as an Output. DATA2 DATA; DATAg X SYNCcast X 6 an ft $ co z > a 2 2 r & Mm MICROELECTRONICS 48828530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) rator and checker may be preset to all"1s" or all"Os". The CRC-CCITT polynomial is selected by setting D2 of WR5 to "0", bit D7 of WR10 controls the pre- set value. if this bit is set to "1", the generator and checker are preset to "1s", if this bit is reset, the gen- erator and checker are preset to all "Os". The recei- ver expects the CRC to be inverted before transmis- sion and so checks the CRC result against the va- jue "0001110100001111". The SCC presets the CRC checker whenever the receiver is in Hunt mode or whenever a flag is received so a CRC reset com- mand is not strictly necessary. However, the CRC checker may be preset by issuing the Reset CRC Checker command in WRO. The CRC checker is automatically enabled for all data between the ope- ning and closing flags by the SCC in SDLC mode, and the Rx CRC Enable bit (D3) in WR3 is ignored. The result of the CRC calculation for the entire frame is valid in RR1 only when accompagnied by the end of Frame bit being set in RR1. At all other times the CRC Error bit in RR1 should be ignored by the pro- cessor. Care must be exercised so that the proces- sor does not attempt to use the CRC bytes that are Figure 31 : Changing Character Length. transferred as data because not all of the bits are transferred properly. The last two bits of CRC are never transferred to the receive data FIFO and are not recoverable. A frame is terminated by a closing flag. When the SCC recognizes this flag the contents of the Receive Shift register are transferred to the receive data Fl- FO, the Residue Code is latched, the CRC Error bit is latched in the status FIFO and the End Of Frame bit is set in the receive status FIFO. The End Of Frame bit, upon reaching the top of the FIFO, will cause a special receive condition. The processor may then read RR1 to determine the result of the CRC calculation as well as the Residue Code. If ei- ther the Rx Interrupt on Special Condition Only or the Rx Interrupt on First Character or Special Condi- tion mode are selected, the processor must issue and Error Reset command in WRO to unlock the re- ceive FIFO. In addition to searching the data stream for flags, the receiver in the SCC also watches for seven consecutive "is", which is the abort condition. The (77 | 8 7 6 5 4 3 2 i | 5 BITS TIME | 13 12 wi 10 9 8 7 6 | 8 BITS CHANGE FROM FIVE TO EIGHT > | 21 20 19 18 7 16 16 14 | 8 BITS | 29 28 27 26 25 24 23 22 | 5 BITS CHANGE FROM EIGHT TO FIVE | 36 3332 O01 30 28 #28 27 | BITS | 39 38 O37 36 35 34 33 32 | SGS-THOMSON 41/98 MICROELECTRONICS 48928530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) presence of seven consecutive "1s" is reported in the Break/Abort bit in RRO. This is one of the possi- ble external/status interrupts, so transitions of this status may be programmed to cause interrupts. Upon receipt of an abort the receiver is forced into Hunt mode, where it looks for flags. The Hunt sta- tus is also a possible external/status condition whose transition may be programmed to cause an interrupt. The transitions of these two bits occur ve- ry close together but either one or two external/sta- tus interrupts may result. The abort condition is ter- minated when a "0" is received, either by itself or as the leading "0" of a flag. The receiver does not leave Hunt mode until a flag has been received so two dis- crete external/status conditions will occur at the end of an abort. An abort received in the middle of a frame terminates the frame reception, but no in an orderly manner, because the character being as- sembled is lost. Up to two modem control signals associated with the receiver are available in SDLC mode. The DTR/ REQ pin carries the inverted state of the DTR bit (D7) in WR5 unless this pin has been program- med to carry a DMA Request signal. The DCD pin is ordinarily a simple input to the DCD bit in RRO. However, if the Auto Enables mode is selected by setting bit D5 of WR3 to "1", this pin becomes an en- able for the receiver. That is, if Auto Enable is on and the DCD pin is HIGH the receiver is disabled. While the DCD pin is LOW, the receiver is enabled. The initialization sequence for the receiver in SDLC mode is : WR4 first, to select the mode, then WR10 to modify it if necessary, WR6 to program the ad- dress, WR7 to program the flag and the WR3 and WRS5 to select the various options. At this point the other registers should be initialized as necessary. When all of this is complete the receiver may be en- abled by setting bit De of WR3 to "1". SDLC Transmit. Once SDLC mode has been se- lected, the flag must be written in WR7, to be used to open and close the transmitted frames. The SCC does not automatically send the address byte ; it me- rely encapsulates the data supplied by the proces- sor with flags and CRC. Ordinarily, a frame will be terminated by the SCC with CRC and a flag but the SCC may be programmed to send an abort and a flag in place of the CRC. This option allows the SCC to abort a frame transmission in progress if the trans- mitter is accidentally allowed to underrun. This is controlled by the Abort/ Flag On Underrun bit (D2) in WR10. When this bit is set to "1" the transmitter will send an abort and a flag in place of the CRC when an underrun occurs. The frame will be termi- 42/93 ki SGS-THOMSON nated normally, with CRC and a flag, if this bit is set to"0". The SCC is also able to send an abort by com- mand of the processor. The Send Abort command, issued in WRO, will send eight consecutive "1s" and then the transmitter will idle. Since up to five conse- cutive "1s" may have been sent prior to the com- mand being issued, a Send Abort will cause a se- quence of from eight to thirteen "1s" to be transmit- ted. The Send Abort command also empties the transmit buffer register. The idle condition for the transmitter is continuous flags, but this is under pro- gram control. By setting the Mark/ Flag Idle bit (D3) in WR10 to "1", the transmitter will send continuous "1s" in place of the idle flags. Note that the closing flag will be transmitted_correctly even if this mode is selected. The Mark/ Flag Idle must be set to "0", allowing a flag to be transmitted, before data is writ- ten to the transmit buffer. Care must be exercised in doing this because the continuous "1s" are trans- mitted eight at a time, and all eight must leave the Transmit Shift register, so that flag may be loaded into it before the first data is written to the transmit buffer. When using the transmitter in SDLC mode, recall that all data passes through the zero inserter, which adds an extra five bit times of delay between the Transmit Shift register and the Transmit Data pin. The number of bits per transmitted character is con- trolled by bits De and Ds of WR5 and the way the data is formatted within the transmit buffer. The bits in WR8S allow the option of five, six, seven, or eight bits per character. When five bits per character is selected, the data may be formatted before being written to the transmit buffer, to allow transmission of one to five bits per character. This formatting is shown in Table 4-1. In all cases the data must be right-justified, with the unused bits being ignored, except in the case of five bits per character. An additional bit, carrying parity information, may be automatically appended to every transmitted cha- racter by setting bit De of WR4 to "1". This bit is sent in addition to the number of bits specified in WR4 or by the data format. The parity sense is selected by bit D1 of WR4. Parity is not normally used in SDLC mode. The character length may be changed on the fly, but the desired length must be selected before the character is loaded into the transmit shift regis- ter from the transmit buffer. The easiest way to en- sure this is to write to WRS5 to change the character length before writing the data to the transmit buffer. Only the CRC-CCITT polynomial may be used in SDLC mode. This is selected by setting bit De in WRS to "0". This bit controls the selection for both MICROELECTRONICS 490Z8530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) the transmitter and receiver. The initial state of the generator and checker is controlled by bit D7 of WR10. When this bit is set to "1", both the genera- tor, and checker sill have an initial value of all "1s" and, if this bit is set to "0", the initial values will be all "Os". The SCC does not automatically preset the CRC generator so this must be done in software. This is accomplished by issuing the Reset Tx CRC generator command, which is encoded in bits D7 and Dg of WRO. For proper results, this command must be issued while the transmitter is enabled and idling. If CRC is to be used the transmit CRC gene- rator must be enabled by setting bit DO of WR5 to "1", CRC is normally calculated on alt characters be- tween opening and closing flags, so this bit is usual- ly set to "1" at initialization and never changed. Enabling the CRC generator is not sufficient to control the transmission of CRC. In the SCC this function is controlled by the Tx Underrun/ EOM bit, which may be reset by the processor and set by the SCC. When the transmitter underruns (both the transmit buffer and transmit shift register are emp- ty) the state of the Tx Underrun EOM bit determines the action taken by the SCC. If the Tx Under- run/EOM bit is set to "i" when the underrun occurs, the transmitter will send flags ; if this bit is reset to "O" when the underrun occurs, the transmitter will send either the accumulated CRC followed by flags, or an abort followed by flags, depending the state of the Abort/ Flag on Underrun bit in the WR10. When the CRC or abort is loaded into the Transmit Shift register for transmission, the SCC will set the Tx Un- derrun/EOM bit to indicate this. This transition may be programmed to cause an external/status inter- rupt, or the Tx Underrun/ EOM bitis available in RRO. The Reset Tx Underrun/EOM Latch command is en- coded in bits D7 and Dg of WRO. For correct transmission of the CRC at the end of a frame, this command must be issued after the first character is written to the SCC but before the trans- mitter underruns after the last character written the SCC. The command is usually issued immediately after the first character is written to the SCC so that the abort or CRC is sent if an underrun occurs inad- vertently. The Abort Flag on Underrun bit (D2) in WR10 is usually set to "1" at the same time as the Tx Underrun/EOM bit is reset so that an abort sill be sent if the transmitter underruns. The bit is then set to "O" near the end of the frame to allow the correct transmission of CRC. In this paragraph the term "completely sent" means shifted out of the Transmit Shift register, not shifted out of the zero inserter, which is an additional five ir SGS-THOMSON bit times of delay. In SDLC mode, if the transmitter is disabled during transmission of a character, that character will be "completely sent". This applies to both data and flags. However, if the transmitter is di- sabled during the transmission of CRC, the 16-bit transmission will be completed but the remaining bits will be from the Flag register rather than the re- mainder of the CRC. There are two modem control signals associated with the transmitter provided by the SCC. The RTS pin is a simple output that carries the inverted state of the RTS bit (D1) in WR5. The CTS pin is ordina- rily a simple input to the CTS bit in RRO. However, if Auto Enables mode is selected, this pin becomes an enable for the transmitter. Thatis, if Auto Enables is on and the CTS pin is HIGH the transmitter is di- sabled. If the CTS pin is LOW, the transmitter is en- abled. The initialization sequence for the transmitter in SDLC mode is : WR4 first, to select the mode, then WR10 to modify it if necessary, WR7 to program the flag, and then WR3 and WRS to select the various options. At this point the other registers should be initialized as necessary. When all of this is complete, the transmitter may be enabled by setting bit D3 of WRS5 to "1". Now that the transmitter is enabled, the CRC generator may be initialized by issuing the Re- set Tx CRC Generator command in WRO. SDLC Loop Mode. SDLC Loop mode is quite simi- lar to SDLC mode except that two additional control bits are used. They are the Loop Mode bit (D1) and the Go Active on Poll bit (D4) in WR10. In addition to these two extra control bits, there are also two sta- tus bits in RR10. They are the On Loop bit (D1) and the Loop Sending bit (D4). Before Loop mode is se- lected both the receiver and transmitter must be completely initialized for SDLC operation. Once this is done, Loop mode is selected by setting bit D; of WR10 to "1". At this point the SCC connects TxD to RxD with only gate delays in the path. At the same time a flag is loaded into the Transmit Shift register, and is shifted to the end of the zero inserter, ready for transmission. The SCC will remain in this state until the Go Active on Poll bit (D4) in WR10 is set to "1". When this bit is set to "1" the receiver begins looking for a sequence of seven consecutive "1s", indicating either an EOP or an idle line. When the receiver detects this condition the Break/Abort bit in RRO is set to" 1 and a one-bit time delay is inserted in the path from RxD to TxD. The On Loop bit in RR10 is also set to "1" at this time, and the receiver enters the Hunt mode. The SCC cannot transmit on the loop until a flag is received, causing the receiver 43/93 MICROELECTRONICS 49128530 PROGRAMMING DATA COMMUNICATION MODES (cont'd) to leave Hunt mode, and another EOP (bit pattern 11111110") is received. The SCC is now on the loop and capable of transmitting on the loop. As soon as this status is recognized by the processor, the Go Active On Poll bit in WR10 should be set to O" to prevent the SCC from transmitting on the loop without the consent of the processor. To transmit a message on the loop, the Go Active On Polt bit in WR10 must be set to "1". Once this is done, the SCC will change the next received EOP into Flag and begin transmitting on the loop. When the EOP is received, the Break/Abort and Hunt bits in RRO w,. 3 set to "1", and the Loop Sending bit in RR10 will also be set to "1". Data to be transmit- ted may be written after the Go Active On Poll bit has been set ox after the receiver enter Hunt mode. If the data is written immediately after the Go Active On Poll bit has been set, the SCC will only insert one flag after the EOP is changed into a flag. If the data is not written until after the receiver enters the Hunt mode, flags will be transmitted until the data is written. If only one frame is to be transmitted on the loop in response to an EOP, the processor must set the Go Active on Poll bit to "0" before the last data is written to the transmitter. In this case the trans- mitter will close the frame with a single flag, and then revert to the one-bit delay. The Loop Sending bit in RR10 is set to "0" when the closing Flag has been sent. If more than one frame is to be transmitted, the Go Active On Poll bit should not be set to "0" un- til the last frame is being sent. If this bit is not set to "0" before the end of a frame, the transmitter will send Flags until either more data is written to the transmitter, or until the Go Active On Poll_bit is set to "0". Note that the state of the Abort/ Flag on Un- derrun and Mark/ Flag Idle bits in WR10 are igno- red by the SCC in SDLC Loop mode. To go off the loop in an orderly manner requires ac- tions similar to those taken to go the loop. First, the Go Active On Poll bit must be set to O" and any transmission in progress completed, if the SCC is currently sending on the loop. Once the SCC is not sending on the loop, an exit from the loop is accom- plished by setting the Loop Mode bit in WR10 to "0", and at the same time writing the Abort/ Flag on Un- derrun and Mark/Fiag Idle bits with the desired va- 483 57 S&S-THOMSON lues. The SCC will revert to normal SDLC operation as soon as an EOP is received, or immediately, if the receiver is already in Hunt mode because of the receipt of an EOP. The initialization sequence for the SCC in SDLC Loop mode is similar to the sequence used in SDLC mode, except that it is somewhat longer. The pro- cessor should program WR4 first, to select SDLC mode, and then WR10 to select the CRC preset va- lue and program the Mark/Flag Idle bit. The Loop Mode and Go Active On Poll bits in WR10 should not be set to"1 yet. The flag is written in WR7 and the various options are selected in WR3 and WR5. At this point the other registers should be initialized as necessary, then Loop Mode bit (D1) in WR10 should be set to 1". When all of this is complete the transmitter may be enabled by setting bit D3 of WR5 to "1". Now that the transmitter is enabled, the CRC generator may be initialized by issuing the Reset TxCRC Generator command in WRO. The receiver is enabled by setting the Go Active on Poll bit (D4) in WR10 to "1". The SCC will go on the loop when seven consecutive "is" are received, and will signal this by setting the On Loop bit in RR10. Note that the seven consecutive "1s" will set the Break/Abort and Hunt bits in RRO also. Once the SCC is on the loop, the Go Active on Poll bit should be set to "0" until a message is to be transmitted on the loop. To transmit a message on the loop, the Go Active on Poll bit should be set to "1". At this point the proces- sor may either write the first character to the trans- mit buffer and wait for a transmit buffer empty condi- tion, or wait for the Break/Abort and Hunt bits to be set in RR10 and the Loop Sending bit to be set in RR10 before writing the first data to the transmitter. The Go Active On Poll bit should be set to "0" after the transmission of the frame has begun. To go off of the loop, the processor should set the Go Active On Poll bit in WR10 to "0" and then wait for the Loop Sending bit in RR10 to be set to "0". At this point the Loop Mode bit (D1) in WR10 is set to "0" to request an orderly exit from the loop. The SCC will exit SDLC Loop mode when seven consecutive "1s" have been received ; at the same time the Break/Abort and Hunt bits in RRO will be set to "1, and the On Loop bit in RR10 will be set to "0". MICROELECTRONICS 492SUPPORT CIRCUITRY PROGRAMMING The SCC incorporates additional circuitry to aid in serial communications. This circuitry includes clocking options, baud rate generator, data enco- ding, and internal loopback. This section discusses how to program these functions. Clock Options The SCC may be programmed to select one of se- veral sources to provide the transmit and receive clocks. In addition, the SCC requires a fundamen- tal, parallel resonant crystal oscillator in each chan- nel, as well as the ability to echo one of several in- ternal clock sources to the outside world. These op- tions are controlled by the bits in WR11. The crystal oscillator option is controlled by bit D7 in WR11. When this is set to "0", the crystal oscillator is disabled and all pins function normally. When this bit is set to "1" the crystal oscillator is enabled and a_high-gain amplifier_is connected between the RTxC pin and the SYNC pin. While the crystal os- cillator is enabled, anything that has RTxC selected as its clock source will automatically be connected to the output of the crystal oscillator. While the crys- tal oscillator is enabled, the SYNC pin is obviously unavailable for other use. In synchronous modes no sync pulse is output, and the External Sync mode cannot be selected. In asynchronous modes the state of the Sync/ Hunt bit in RRO is no longer con- trolled by the SYNC pin. Instead, the Sync/ Hunt bit is forced to O". The crystal oscillator requires some finite time to stabilize. The oscillator must be allo- wed to stabilize before it is used as a clock source. The source of the receive clock is controlled by bits De and Ds of WR11. The receive clock may be pro- grammed to come from the RTxC pin , the TRxC pin, the output of the baud rate generator, or the transmit output of the DPLL. The source of the transmit clock is controlled by bits D4 and D3 of WR11. The transmit clock may be pro- grammed to come from the RTxC pin, the TRxC pin, the output of the baud rate generator, or the trans- mit output of the DPLL. Ordinarily the TRxC pin is an input, but it becomes on output if this pin has not been selected as the source for the transmitter or the receiver, and bit D2 of WR11 is set to "1". The selection of the signal provided on the TRxC ouput pin is controlled by bits Dy and DO of WR11. The TRxC pin may be pro- grammed to provide the output of the crystal oscil- kyr SGS-THOMSON 28530 lator, the output of the baud rate generator, the re- ceive output of the DPLL or the actual transmit clock. If the output of the crystal oscillator is selec- ted but the crystal oscillator has not been enabled the TRxC pin will be driven HIGH. The option of pla- cing the transmit colck signal on the TRxC pin when it is an output allows access to the transmit output of the DPLL. Figure 32 shows a simplified schematic diagram of the circuitry used in the clock multiplexing. It shows the inputs to the multiplexer section as well as the various signal inversions that occur in the paths to the outputs. Also shown are the edges used by the receiver, transmitter, baud rate generator and DPLL to sample or send data or otherwise change state. For example, the receiver samples data on the fal- ling edge, but since there is an inversion in the clock path between the RTXxC pin and the receiver, a ri- sing edge of the RTxC pin samples the data for the receiver. Selection of the clocking options may be done any- where in the initialization sequence, but the final va- lues must be selected before the receiver, transmit- ter, baud rate generator, or DPLL are enabled to prevent problems from arbitrarily narrow clock si- gnals out of the multiplexers. The same is true of the crystal osciliator, in that the output should be al- lowed to stabilize before it is used as a clock source. Baud Rate Generator Figure 33 shows a block diagram of the baud rate generator. It consists of a 16-bit down-counter, two 8-bit time constant registers and an output divide- by-two. The baud rate generator input comes from the output of a two-input multiplexer, the zero count condition is output to the External/ Status Interrupt Section. The baud rate generator may be enabled and disabled by command and is disabled by a hardware reset. The time constant for the baud rate generator is pro- grammed in WR12 and WR13, with the least-signi- ficant byte in WR12. The formulas relating the baud rate to the time constant and vice versa are shown with an example. In these formulas the baud rate generator clock frequency is in Hertz, the desired baud rate in bits/ second and the time constant is dimensionless. The example in Table 7 assumes a 2.4576 MHz clock factor of 16 and shows the time constant for a number of popular baud rates. 45/93 MICROELECTRONICS 49328530 SUPPORT CIRCUITRY PROGRAMMING (cont'd) Time Constant Formulas : Table 7 : Baud Rate Example. Baud Rate Divider : Clock Frequenc Time Constant = men rreauency -2 Decimal Hex 2 (Clock Mode) - (Baud Rate) 38400 0 0000H 19200 2 0002H Clock Frequency 9600 6 0006H Baud Rate = 4800 14 000EH 2 (Clock Mode) - (Time Const. + 2) 2400 30 001EH 1200 62 003EH . 600 126 007EH The clock source for the baud rate generator is se- 300 254 OOFEH lected by bit D1 of WR14. When this bit is set to "0" 150 510 01FEH the baud rate generator uses the signal on the TxC For 2.4576 MHz Clock, X 16 Mode Figure 32 : Clock Multiplexer. osc SYNC RECEIVER an RATxc TRxC BAUD RATE GENERATOR OUT TX DPLL OUT RX DPLL OUT PCLK BPLL BAUD RATE GENERATOR TRANSMITTER _f- _f- oe 46/93 57 S&S:THOMson MICROELECTRONICS 494SUPPORT CIRCUITRY PROGRAMMING (cont'd) pin as its clock, independent of whether the TxC pin is a simple input or part of the crystal oscillator cir- cuit. When this bit is set to "1" the baud rate gene- rator is clocked by PCLK. To avoid metastable pro- blems in the counter, this bit should be changed on- Figure 33 : Baud Rate Generator. 28530 ly while the baud rate generator is disabled, since arbitrarily narrow pulses can be generated at the output of the multiplexer when it changes status. The baud rate generator is enabled while bit Do of WRi14 is set to 1" and is disabled while this bit is WRI3 | SELECT WM ML 16 BIT DOWN COUNTER BAUD RATE GENERATOR CLOCK RATxC PIN _______ PCLK PIN WARI2 + COUNT t+ | OUTPUT 2 + A Figure 34 : Baud Rate Generator Start-Up. WRITE TO WRI4 / j COUNTER CLOCK _ OF WRITE TO WRi4 WITH ENABLE \S\S\S\ COUNTER FIRST DECREMENTED (AFTER HARDWARE RESET) COUNTER FIRST DECREMENTED (AFTER PREVIOUS DISABLE) Gy SGS-THOMSON 47/93 fy MIGROELECTROMICS 49528530 SUPPORT CIRCUITRY PROGRAMMING (cont'd) set to O". To prevent metastable problems when the baud rate generator is first enabled, the enable bitis synchronized to the baud rate ge-nerator clock. This introduces an additional delay then the baud rate generator is first enabled and this is shown in Figure 5-3. The baud rate generator is disabled im- mediately when bit Do of WR14 is set to "0", because the delay is only necessary on startup. The baud rate generator may be enabled and disabled on the fly, but this delay on startup must be taken into consi- deration. Upon reaching a count of "0" the time constant held in WR12 and WA13 is reloaded into the downcoun- ter so that the process of counting down may start over. In addition to reloading the time constant, the output of the baud rate generator toggles, and for the clock cycle with a zero count, the zero count si- gnal goes active to the External/Status Section. This zero count condition from the baud rate generator does not persist, so if it is to be used by the proces- sor, it should be latched in the External/Status latch. While the baud rate generator is disabled the state of the zero count signal is held. This signal is forced active by a hardware reset. Figure 35 : Data Encoding Methods. Initializing the baud rate generator is done in four steps. First, the time constant is determined and loa- ded into WR12 and WR13. Next, the processor must select the clock source for the baud rate generator by writing to bit Di of WR14. Finally, the baud rate generator is enabled by setting bit Do of WR14 to "1". Note that the first write to WR14 is not neces- sary after a hardware reset if the clock source is to be the RTXC pin. This is because a hardware reset automatically selects the RTxC pin as the baud rate generator clock source. Data Encoding The SCC provides four different data encoding me- thods, selected by bits Ds and Ds in WR10. An example for these four encoding methods is shown in Figure 35. Any encoding method may be used in any X1 mode in the SCC, asynchronous or synchro- nous. The data encoding selected is active even though the transmitter or receiver may be idling or disabled. In NRZ encoding a "1" is represented by a HIGH le- vel and a "0" is represented by a LOW level. in this encoding method only a minimal amount of clocking ora | + [ + [ 0 ee ee ee | BIT CELL LEVEL: HIGH = 1 LOW =0 NAZI | | FM1 (BIPHASE MARK) FIMO (BIPHASE SPACE) HIGH > LOW = 1 NO CHANGE = 1 CHANGE = 0 BIT CENTER TRANSITION: TRANSITION = 1 NO TRANSITION = 0 NO TRANSITION = 4 TRANSITION = 0 48/93 ki SGS-THOMSON MICROELECTRONICS 496SUPPORT CIRCUITRY PROGRAMMING (cont'd) information is available in the data stream in the form of transitions on bit-cell boundaries. In an arbitrary data pattern this may not be sufficient to generate a clock for the data from the data itself. In the case of SDLC, where the number of consecutive "1s" in the data stream is limited, a minimum number of trans- itions to generate a clock are guaranteed. In FM1 encoding, also known as biphase mark, a transition is present on every bit cell boundary, and an addition transition may be present in the middle of the bit cell. In FM1 a "0" is sent as no transition in the center of the bit cell anda "1" is sent as a transi- tion in the center of the bit cell. FM1 encoded data contains sufficient information to recover a clock from the data. In FMO encoding, also known as biphase space, a transition is present on every bit cell boundary and an additional transition may be present in the mid- dle on the bit cell. In FMO a"1" is sent as no transi- tion in the center of the bit cell and a "0" is sent as a transition in the center of the bit cell. FMO enco- ded data contains sufficient information to recover a clock from the data. The data encoding method should be selected in the initialization procedure before the transmitter and receiver are enabled but no other restrictions apply. Note, in Figure 35, that in NRZ and NRZ1 the receiver samples the data only on one edge. Howe- ver, in FM1 and FMO the receiver samples the data on both edges. Also, as shown in Figure 5-4, the transmitter defines bit cell boundaries by one edge in all cases and uses the other edge in FM1 and FMO to create the mid-bit transition. Digital Phase-locked Loop Figure 36 shows a block diagram of the digital phase-locked loop. It consists of a 5-bit counter, an edge detector, and a pair of output decoders. The clock for the DPLL comes from the output of a two- input multiplexer, and the two outputs go to the transmitter and receive clock multiplexers. The Figure 36 : Digital Phase-Locked Loop. 28530 DPLL is controlled by the seven commands that are encoded in bits D7, De and Ds of WR14. The clock for the DPLL is selected by two of the com- mands in WR14. One command selects the output of the baud rate generator as the clock source, and the other command selects the RTxC pin_as the clock source, independent of whether the RTxC pin is a simple input or part of the crystal oscillator cir- cuit. To avoid metastable problems in the counter, the clock source selection should be made only while DPLL is disabled, since arbitrarily narrow pulses can be generated at the output of the multi- plexer when it changes status. The DPLL is enabled by issuing the Enter Search Mode command in WR14. This command is also used to reset the DPLL to a known state if it is sus- pected that synchronization has been lost. When used to enable the DPLL, the Enter Search Mode command unlocks the counter, which is held while the DPLL is disabled and enables the edge detec- tor. If the DPLL is already enabled when this com- mand is issued, the DPLL also enters Search Mode. While in Search mode, the counter is held at a spe- cific count and no outputs are provided. The DPLL remains in this status until an edge is detected in the receive data stream. This first edge is assumed to occur on a bit cell boundary, and the DPLL will be- gin providing an output to the receiver that will pro- perly sample the data. From this point on the DPLL will adjust its output to remain in phase with the re- ceive data. If the first edge that the DPLL sees does not occur on a bit celi boundary, the DPLL will even- tually lock on to the receive data but it will take lon- ger to do so. The DPLL may be programmed to operate in either of two modes, as selected by command in WR14. In the NRZI mode the DPLL clock must be 32 times the date rate. In this mode the transmit and receive clock outputs of the DPLL are indentical, and the clocks are phased so that the receiver samples the data in the middle of the bit cell. In NRZI mode the DPLL does not require a transition in every bit cell, fxd ] EDGE DETECTOR | RECEIVE COUNT MODIFIER j++ DECODE # RECEWV [ 5-8IT COUNTER | q TRANSMIT pot DECODE + cLock iy SGS-THOMSON 49/93 MICROELECTROMICS 49728530 SUPPORT CIRCUITRY PROGRAMMING (cont'd) so this mode is useful for recovering the clocking in- to construct receive and transmit clock outputs that formation from NRZ and NRZI data streams. In the are phased to properly receive and transmit data. FM mede the DPLL clock must be 16 times the da- To do this, the DPLL divides each bit cell into four ta rate. In this mode the transmit clock output of the regions, and makes an adjustment to the count cy- DPLL lags the receive clock outputs by 900, to make cle of the 5-bit counter dependent upon in which re- the transmit and receive bit cell boundaries the gion a transition on the receive data input occured. same, because the receiver must sample FM data This is shown in Figure 37. Ordinarily, a bit cell at one-quarters and three-quarters bit time. In FM boundary will occur between count 15 and count 16, mode the DPLL requires a transition in every bit cell, and the DPLL output will cause the data to be sam- and if this transition is not present in two consecuti- pled in the middle of the bit cell. The DPLL actually vely sampled bit cells, the DPLL will automatically allows the transition marking a bit cell boundary to enter the search mode. As in the case of the clock occur anywhere during the second half of count 15 source selection, the mode of operation should on- or the first half of count 16 without making a correc- ly be changed while the DPLL is disabled to prevent tion to its count cycle. However, if the transition mar- unpredictable results. king a bit cell boundary occurs between the middle . of count 16 and count 31 the DPLL is sampling the NR2I Mode Operation data too early in the bit cell. In response to this the To operate in NRZI mode the DPLL must be sup- DPLL extends its count by one during the next 0 to plied with a clock that is 32 times the data rate. The 31 counting cycle, which effectively moves the edge DPLL uses this clock, along with the receive data, of the clock that samples the receive data closer to Figure 37 : DPLL in NRZI Mode. * BiT CELL | ] com be PP PPP EEE PET PPLE correction} | ADD ONE COUNT | SUBTRACT ONE COUNT I] tro CHANGE NO cancel DPLL OUT | | Figure 38 : DPLL Operating Example. veceveosrsf | ff Lf Lf L__J. ouourur | [| Ll LJ LJ LI LJ LJ LJ 1 comemt(e ee ee eT] COUNT LENGTH 32 | a2 | 32 | Hv | un | Hn | 33 | 8 | 33 | 50/98 . hyy Sisaeemsnns 498SUPPORT CIRCUITRY PROGRAMMING (cont'd) the center of the bit cell. In a similar manner, if the transition occurs between count 0 and the middle of count 15, the output of the DPLL is sampling the da- ta too late in the bit cell. To correct this, the DPLL shortens its count by one during the next 0 to 31 counting cycle, which effectively moves the edge of the clock that samples the receive data closer to the center of the bit cell. In NRZI mode, if the DPLL does not see any transition during a counting cycle, no adjustment is made in the following counting cycle. If an adjustment to the counting cycle is necessary the DPLL modifies count five, either deleting it or doubling it. Thus only the LOW time of the DPLL out- put will be lengthened or shortened. While the DPLL is in search made, the counter remains at count 16, where the DPLL outputs are both HIGH. The mis- sing clock latches in the DPLL which may be acces- sed in RR10, are not used in NRZI mode. An exam- ple of the DPLL in operation is shown in Figure 38. FM Mode Operation To operate in FM mode the DPLL must be supplied with a clock that is 16 times the data rate. The DPLL uses this clock, along with the receive data, to construct receive and transmit clock outputs that are phased to receive and transmit data properly. In FM mode that the counter in the DPLL still counts from 0 to 31 but now each cycle corresponds to 2-bitcells. To make adjustments to remain in phase with the receive data, the DPLL divides a pair of bit cells in- to five regions, making the adjustment to the coun- Figure 39 : DPLL in FM Mode. 28530 ter dependent upon which region the transition on the receive data input occured. This is shown in Fi- gure 39. Ordinarily a bit cell boundary will occur be- tween count 15 or count 16, and the DPLL receive output will cause the data to be sampled at one- fourth and three-fourths of the way through the bit cell. The DPLL actually allows the transition marking a bit-cell boundary to occur anywhere during the se- cond half of count 15 or the first half of count 16 wi- thout making a correction to its count cycle. Howe- ver, if the transition marking a bit cell boundary oc- curs between the middle of count 16 and the mid- dle of count 19 the DPLL is sampling the data too early in the bit cell.In response to this the DPLL ex- tends its count by 1 during the next 0 to 31 counting cycle, which effectively moves the receive clock edges closer to where they should be. In FM mode any transitions occurring between the middle of count 19 in one cycle and the middle of count 12 du- ring the next cycle are ignored by the DPLL. This is necessary to guarantee that any data transitions in the bit cells will not cause an adjustment to the coun- ting cycle. In FM mode the transmit clock and receive clock out- puts from the DPLL are not in phase. This is neces- sary to make the transmit and receive bit cell boun- daries coincide, since the receive clock must sam- ple the data one-fourth and three-fourths of the way through the bit cell. As in NRZI mode, if an adjus- tment to the counting cycle is necessary, the DPLL err cent | count []=]]]#]>]#|>]]2]<]2]@l@]>]>)o) eb)? b l=) ]] CORRECTION | L +f I f NO CHANGE TX DPLL OUT | | | f | RX DPLL OUT j | f | iGNORED j= tf NO CHANGE ky SGS-THOMSON 51/93 MICROELECTRONICS 49928530 SUPPORT CIRCUITRY PROGRAMMING (cont'd) modifies count 5, either deleting it or doubling it. If no adjustment is necessary, the count sequence proceeds normally. While the DPLL is in search mode, the counter remains at count 16, where the receive output is LOW and the transmit output is LOW. This fact can be used to provide a transmit clock under software control since the DPLL is in search mode while it it disabled. While the DPLL is lisabled the transmit clock output of the DPLL may e toggled by alternately selecting FM and NRZI move in the DPLL. The same is true of the receive clock. In addition to FM encoded data, the DPLL may al- so be used to recover the clock from Manchester encoded data, which contains a transition at the center of every bit cell. Here it is the direction of the transition that distinguishes a "1" from a "0". Ano- ther way of looking at Manchester encoding is to realize that, during the first half of the bit cell the da- ta is sent, during the second haif of the bit cell the complement of the data is sent. This is shown in Fi- gure 40, along with the DPLL output if it thinks that the mid-bit transitions are really bit cell boundaries. As is obvious from the figure, if the receiver samples the data on the falling edge of the DPLL receive clock output, the Manschester data will be properly decoded. This occurs if the receiver is programmed to accept NRZ data. From the above discussion together with an exami- nation of FMO and FM1 data encoding, it should be obvious that only clock transitions should exist on the receive data pin when the DPLL is programmed to enter search mode. If this is not case the DPLL may attempt to lock on to the data transitions. With FMO encoding this requires continuous "1s" recei- ved when leaving search. In FM1 encoding it is continuous "Os" ; which Manchester encoded data this means alternating "1s" and "Os". With all three of these data encoding methods there will always be at least one transition in every bit cell, and in FM Figure 40 : Manchester Clock Recovery. mode the DPLL is designed to expect this transition. In particular, if no transition occurs between the mid- dle of count 12 and the middle of count 19, the DPLL is propably not locked onto the data properly. When the DPLL misses an edge the One Clock Missing bit is RR10 is set to "1" and latched. It will hold this va- lue until a Reset Mission Clock command is issued in WR14 or until the DPLL is disabled or program- med to enter the Search mode. Upon missing this one edge the DPLL takes no other action and does not modify its count during the next counting cycle. However, if the DPLL does not see an edge between the middle of count 12 and the middle of count 19 in two successive 0 to 31 count cycles, a line error condition is assumed. If this occurs, the two Clocks Mission bit in RR10 is set to "1" and latched. At the same time the DPLL enters the Search mode. The DPLL makes the decision to enter Search mode du- ring count 2, where both the receive clock and trans- mit clock outputs are LOW. This prevents any glitches on the clock outputs when search mode is entered. While in search mode no clock outputs are provided by the DPLL. The Two Clocks Missing bit in RR10 is latched until a Reset Missing Clock com- mand is issued in WR14, or until the DPLL is disa- bled or programmed to enter the Search mode. DPLL Initialization Initialization of the DPLL may be done at any time during the initialization sequence, but should proba- bly be done after the clock modes have been selec- ted in WR11, and before the receiver and transmit- ter are enabled. When initializing the DPLL the clock source should be selected first, followed by the se- lection of the operating mode. At this point the DPLL, may be enabled by issuing the Enter Search Mode command in WR14. Note that a channel or hard- ware reset disables the DPLL, selects the RTxC pin as the clock source for the DPLL, and places it in the NRZI mode. DATA 1 t a MANCHESTER ~~ VS VY Sf VS NN Sf o 1 G moor \ f \ Jf \_f \f \S \ Ss momo J \ Vf ND VLD NSD NV 52/93 ky SGS-THOMSON MICROELECTRONICS 50028530 SUPPORT CIRCUITRY PROGRAMMING (cont'd) Internal Loopback/Auto Echo The SCC contains two other features useful for dia- gnostic purposes, controlled by bits in WR14. They are local loopback and auto echo. Local loopback is selected when bit D4 of WR14 is set to "1". In this mode the output of the transmitter is internally connected to the input of the receiver. At the same time the TxD pin remains connected to the transmitter. In this mode the DCD pin is ignored as a receive enable and the CTS pin is ignored as a transmitter enable even if the Auot Enables mode has been selected. Note that the DPLL input is connected to the RxD pin, not to the input of the re- ceiver. This precludes the use of the DPLL in local loopback. Figure 41 : Local Loopback. Auto echo is selected when bit D3 of WR14 is set to "1". In this mode the TxD pin is connected directly to the RxD pin, and the receiver input is connected to the RxD pin. In this mode the CTS pin is ignored as a transmitter enable and the output of the trans- mitter does not connect to anything. If both the Lo- cal Loopback and Auto Echo bits are set to "1", the auto echo mode will be selected, but both the CTS pin and DCD pin will be ignored as auto enables. This, however, should not be considered a norma! operating mode, however. Local Loopback is shown schematically in Figure 41 and auto echo is shown schematicaily in Figure 42. mo [ene veo 1} ref} q TX ENABLE ! af} Db LOCAL LOOPBACK lL Figure 42 : Auto Echo. oC] A RX ENABLE a TX ENABLE s[} FD" AUTO ECHO N.C. { TRANSMITTER ki SGS-THOMSON 53/93 MICROELECTRONICS 501Z8530 REGISTERS DESCRIPTION The following section describes the SCC registers. Each register is detailed in terms of bit configuration, the active states (See Table 8) of each bit, their de- finitions, their functions, and their effects upon the internal hardware and external pins. Table 8 : SCC Registers Description. Read Register RRO Xmit/Receive Buffer Status and Ext Status RR1 Receive Condition Status/Residue Codes RR2 Interrupt Vector (modified in BChannel) RR3 Interrupt Pending (Channel Aonly) RR8 Receive Buffer Description RR10_~_Loop/Clock Status RR12 Lower Byte of Time Constant RR1i3 ~Upper Byte of Time Constant RRi5_ External Status Interrupt Enable Write Description Register WRO = Command Register WRi Tx/Rx Interrupt and Data Xter Mode Definition WR2 Interrupt Vector WR3 Receive Parameters and Control WR4 ~ Tx/Rx Miscellaneous Parameters and Modes WR5 Transmit Parameter and Controls WR6 Sync Character or SDLC Address Field WR7 Sync Character or SDLC Flag WR8 Transmit Buffer WR9 Master Interrupt Control WR10_ Misc Transmitter/Receiver Control Bits WR11- Clock Mode Controi WR12_ Lower Byte Baud Rate Generator Time Constant WR13 Upper Byte of Baud Rate Generator Time Constant WR14_ Miscellaneous Control Bits WR15___ External Status/Interrupt Control WRITE REGISTERS The SCC write register set in each channel includes ten control registers (among them is the transmit buffer), two sync character registers, and two baud rate time constant registers. The interrupt control re- gister and the master interrupt controi and reset re- gister are shared by both channels. Write Register 0 (command register). WRO is the command register and the CRC reset code register. Figure 43 shows the bit configuration for the 28530 and includes register select bits in addition to com- mand and reset codes. Bits D7 and D6 : CRC Reset Codes 0 And 1 Null Code (00). This command has no effect on the SCC and is used when a write to WRO is necessa- ry for some reason other than a CRC Reset com- mand. 54/93 K57 S&S:THOMSON Reset Receive CRC Checker (01). This command is used to initialize the receive CRC circuitry. It is necessary in synchronous modes (except SDLC) if the Enter Hunt Mode command in Write Register 3 is not issued between received messages. Any ac- tion that disables the receiver initializes the CRC cir- cuitry. Resetting the Receive CRC Checker com- mand is accomplished automatically in SDLC mode. Reset Transmit CRC Generator (10). This com- mand initializes the CRC generator. It is usually is- sued in the initialization routine and after the CRC has been transmitted. A Channel Reset will not ini- tialize the generator and this command should not be issued until after the transmitter has been en- abled in the initialization routine. Reset Transmit Underrun/EOM Latch (11). This command controls the transmission of CRC at the end of transmission (EOM). If this latch has been reset, and a transmit underrun occurs, the SCC automatically appends CRC to the mes-sage. In SDLC mode with Abort on Underrun se-lected, the SCC sends an abort, and Flag on under-run if the TX Underrun/EOM latch as been reset. At the start of CRC transmission, the Tx Under- rur/EOM latch is set. The Reset command can be issued at any time during a message. If the trans- mitter is disabled, this command will not reset the latch. However, if no External Status interrupt is pending, or if a Reset External Status Int command accompanies this command while the transmitter is disabled, an External/Status interrupt is generated with the Tx Underrun/ EOM bit reset in RRO. Bits D5-D3 : Command Codes Null Code (000). The Null command has no effect on the SCC. Point High (001). This command effectively adds eight to the Register Pointer (B2-BO) by allowing WR8 through WR 15 to be accessed. The Point High command and the Register Pointer bits are written simultaneously. Reset External/Status Interrupts (010). After an External/Status interrupt (a change on a modem line or a break condition, for example), the status bits in RRO are latched. This command re-enables the bits and allows interrupts to occur again as a re- sult of astatus change. Latching the status bits cap- tures short pulses until the CPU has time to read the change. The SCC contains simple queueing lo- gic associated with most of the external status bits MICROELECTRONICS 502REGISTERS DESCRIPTION (cont'd) in RRO. If another External/Status condition changes while a previous condition is still pending (Reset External/Status Interrupts has not yet been issued) and this condition persists until after the command is issued, this second change causes another External/Status interrupt. However, if this second status change does not persist (there are two transitions), another interrupt is not generated. Exceptions to this rule are detailed in the RRO des- cription. Figure 43 : Write Register 0 (28530). [7 15] 5 [D4 [3 05 | Os | De REGISTER O REGISTER 1 REGISTER 2 REGISTER 3 REGISTER 4 REGISTER 5 REGISTER 6 REGISTER 7 REGISTER 8 REGISTER 9 REGISTER 10 REGISTER 11 REGISTER 12 REGISTER 13 REGISTER 14 REGISTER 15 0 1 o 1 Q 1 o 1 0 1 o 1 o 1 Q 1 alualsal/alololololo[a)~ju|/alolola wleloafols/-_/ololstalala;s|sl/ola NULL CODE POINT HIGH RESET EXT/STATUS INTERRUPTS SEND ABORT (SDLC) ENASLE INT ON NEXT Ax CHARACTER RESET TaiNT PENDING ERROR RESET RESET HIGHEST [US apa lami fololola alelalalsa/alalo alalaje|[-lol/alo NULL CODE RESET Rx CRC CHECKER ESET Tx CRC GENERATOR RESET Tx UNDERRUN/EOM LATCH WITH POINT HIGH COMMAND ky SGS-THOMSON 28530 Send Abort (011). This command is used in SDLC mode to transmit a sequence of eight to thirteen "1s". This command always empties the transmit buffer and sets Tx Underrun/EOM bit in Read Re- gister 0. Enable interrupt On Next Rx Character (100). If the interrupt on the First Received Character mode is selected, this command is used to reactivate that mode after each message is received. The next cha- racter to enter the receive FIFO causes a Receive interrupt. Alternatively, the first previously stored character in the FIFO will cause a Receive interrupt. Reset Tx Interrupt Pending (101). This command is used in cases where there are no more charac- ters to be sent ; e.g., at the end of a message. This command prevents further transmit interrupts until after the next character has been loaded into the transmit buffer or until CRC has been completely sent. This command is necessary to prevent the transmitter from requesting an interrupt when the transmit buffer becomes empty (with Transmit Inter- rupt Enabled). Error Reset (110). This command resets the error bits in RR1. If Interrupt on First Rx Character or In- terrupt on Special Condition modes are selected and a special condition exists, the data with the spe- cial condition is held in the receive FIFO until this command is issued. If either of these modes is se- lected and this command is issued before the data has been read from the receive FIFO, the data is lost. Reset Highest IUS (111). This command resets the highest priority Interrupt Under Service (JUS) bit, al- lowing lower priority conditions to request interrupts. This command allows the use of the internal daisy chain (even in systems without an extenal daisy chain) and should be the last operation in an inter- rupt service routine. Bits 2 through 0: Register Selection Code These three bits select Registers 0 through 7. With the Point High command, Registers 8 through 15 are selected. The following is a summary of the bit descriptions for each write register (WR1-WR15) Write Register 1 (transmit/receive interrupt and data transfer mode definition).Write Register 1 is the control register for the various SCC interrupt and Wait/Request modes. Figure 44 shows the bit assi- gnments for WR1. 55/93 MICROELECTRONICS 50328530 REGISTERS DESCRIPTION (cont'd) Bit 7 : WAIT/DMA Request Enable This bit enables the Wait/Request function in conjunction with the Request/Wait Function Select bit (B6). If bit 7 is set to "1", the state of bit 6 deter- mines the activity of the WAIT/REQUEST pin (Wait or Request). If bit 7 is set to "0", the selected func- tion (bit 6) forces the WAIT/REQUEST pin in to the appropriate inactive state (High for Request, floating for Wait). Bit 6 : WAIT/DMA Request Function The request function is selected by setting this bit to "1". In the Request mode, the WAIT/REQUEST pin switches from High to Low when the SCC is ready to transfer data. When this bit is "0", the wait func- tion is selected. In the Wait mode, the WAIT/RE- QUEST pin switches from floating to Low when the CPU attempts to transfer data before the SCC is ready. Bit 5 : WAIT/DMA Request On Receive Transmit This bit determines whether the WAIT/REQUEST pin operates in the Transmit mode or the Receive mode. When set to 1", this bit allows the wait/re- quest function to follow the state of the receive buftf- er_; ie., depending on the state of bit 6, the WAIT/REQUEST pin is active or inactive in relation to the empty or full state of the receive buffer. Conversely, if this bit is set to "0", the state of the WAIT/REQUEST pin is determined by bit 6 and the state of the transmit buffer. (Note that a transmit re- quest function is available on the DTR/REQUEST Figure 44 : Write Register 1. pin. This allows full-duplex operation under DMA control for both channels.) The request function may occur only when the SCC is not selected ; e.g., if the internal request becomes active while the SCC is in the middie of a read or write cycle, the external request will not become ac- tive until the cycle is complete. An active request output causes a DMA controller to initiate a read or write operation. If the request on Transmit mode is selected in either SDLC or Synchronous Mode, the Request pin is pulsed Low for one PCLK cycle at the end of CRC transmission to allow the immediate transmission of another block of data. If the Wait On Receive mode, the WAIT pin is active if the CPU attempts to read SCC data that has not yet been received. In the Wait On Transmit mode, the WAIT pin is active if the CPU attempts to write data when the transmit buffer is still full. Both situa- tions can occur frequently when block transfer in- structions are used. Bits 4 and 3 : Receive Interrupt Modes These two bits specify the various character-availa- ble conditions that may cause interrupt requests. Receive Interrupts Disabled (00). This mode pre- vents the receiver from requesting an interrupt and is normally used in a polled environment where ei- ther the status bits on RRO or the modified vector in RR2 (Channel B) can be monitored to initiate a ser- vice routine. Although the receiver interrupts are di- sabled, a special condition can still provide a unique vector status in RR2. | L EXT INT. ENABLE Tx INT ENABLE PARITY IS SPECIAL CONDITION Rx INT DISABLE Rx INT ON FIRST CHARACTER OR SPECIAL CONDITION INT ON ALL Ax CHARACTERS OR SPECIAL CONDITION x INT ON SPECIAL CONDITION ONLY WAITIOMA REQUEST ON RECEIVE/TRANSMIT WAITIOMA REQUEST FUNCTION WAITIDMA REQUEST ENABLE 56/93 ki SGS-THOMSON MICROELECTRONICS 504REGISTERS DESCRIPTION (cont'd) Receive Interrupt On First Character Or Special Condition (01). The receiver requests an interrupt in this mode on the first available character (or sto- red FIFO character) or on a special condition. Sync characters to be stripped from the message stream do not cause interrupts. Special receive conditions are : receiver overrun, framing error, end of frame, or parity error (if selec- ted). If a special receive condition occurs, the data containing the error is stored in the receive FIFO un- til an Error Reset command is issued by the CPU. This mode is usually selected when a Block Trans- fer mode is used. In this interrupt mode, a pending special receive condition remains set until either an Error Reset command, a channel or hardware re- set, or until receive interrupts are disabled. The Receive Interrupt on First Character or Special Condition mode can be re-enabled by the Enable Rx Interrupt on Next Character command in WRO. Interrupt On All Receive Characters Or Special Condition (10). This mode allows an interrupt for every character received (or character in the receive FIFO) and provides a unique vector when a special condition exists. The receiver Overrun bit and the Parity Error bit in RR1 are two special conditions that are latched. These two bits must be reset by the Er- ror Reset command. Receiver overrun is always a special receive condi-tion, and parity can be pro- grammed to be a special condition. Data characters with special receive conditions are not held in the receive FIFO in the Interrupt On All Receive Characters or Special Conditions Mode as they are in the other receive interrupt modes. Receive interrupt On Special Condition (11). This mode allows the receiver to interrupt only on cha- Figure 45 : Write Register 2. 28530 racters with a special receive condition. When an in- terrupt occurs, the data containing the error is held in the receive FIFO until an Error Reset command is issued. When using this mode in conjunction with a DMA, the DMA can be initialized and enabled be- fore any characters have been received by the SCC. This eliminates the time critical section of code re- quired in the Receive Interrupt on First Character or Special condition mode ; i.e., all data can be trans- ferred via the DMA so that the CPU need not han- die the first received character as a special case. Bit 2: Parity Is Special Condition If this bit is set to "1", any received characters with parity not matching the sense programmed in WR4 give rise to a Special Receive Condition. If parity is disabled (WR4), this bit is ignored. A special condi- tion modifies the status of the interrupt vector sto- red in WR2. During an interrupt acknowledge cycle, this vector can be placed on the data bus. Bit 1 : Transmitter Interrupt Enable If this bit is set to "1", the transmitter requests an in- terrupt whenever the transmit buffer becomes emp- ly. Bit 0 : External/Status Master Interrupt Enable This bit is the master enable for External/Status in- terrupts including DCD, CTS, SYNC pins, break, abort, the beginning of CRC transmission when the Transmit/Underrun/EOM latch is set, or when the counter in the baud rate generator reaches "0". Write Register 15 contains the individual enable bits for each of these sources of External/Status inter- rupts. This bit is reset by a channel or hardware re- set. Figure 46 : Write Register 3. Vo Vy V2 Vs Va Vs Ve Vr = INTERRUPT VECTOR Ax ENABLE SYNC CHARACTER LOAD INHIBIT ADDRESS SEAACH MODE (SOLC) Rx CAC ENABLE ENTER HUNT MODE AUTO ENABLES r= Ra 5 BITSICHARACTEA Aa 7 BITSICHARACTER fix 6 BITSICHARACTER Ax 6 BITSICHARACTER 57 SGS-THOMSON 57/93 MICROELECTRONICS 505Z8530 REGISTERS DESCRIPTION (cont'd) Write Register 2 (interrupt vector). WR2 is the in- terrupt vector register. Only one vector register exists in the SCC, but it can be accessed through either channel. The interrupt vector can be modified by status information. This is controlled by the Vec- tor Includes Status (VIS) and the Status High/Sta- tus Low bits in WR9. The bit positions for WR2 are shown in Figure 45. Write Register 3 (receive parameters and control). This register contains the control bits and parameters for the receiver logic as illustrated in Fi- gure 46. Bits 7 and 6 : Receiver Bits/Character The state of these two bits determines the number of bits to be assembled as a character in the recei- ved serial data stream. The number of bits per cha- racter can be changed while a character is being as- sembled but only before the number of bits current- ly programmed is reached. Unused bits in the Re- ceived Data Register (RR8) are set to "1" in asyn- chronous modes and SDLC modes, the SCC mere- ly transfers an 8-bit section of the serial data stream to the receive FIFO at the appropriate time. Table 9 lists the number of bits per character in the assem- bled character format. Table 9 : Receive Bits/Character B 7 B 6 0 0 5 Bits / Character 0 1 7 Bits / Character 1 0 6 Bits / Character 1 1 8 Bits / Character Bit 5 : Auto Enables This bit programs the function for both the DCD and CTS pins. CTS becomes the transmitter enable and DCD becomes the receiver enable when this bit is setto1. However, the Receiver Enable and Trans- mit Enable bits must be set before the DCD and CTS pins can be used in this manner. When the Auto En- ables bit is set to "0", the DCD and CTS pins are merely inputs to the corresponding status bits in Read Register 0. The state of DCD is ignored in the Local Loopback mode. The state of CTS is ignored in both Auto Echo and Local Loopback modes. Bit 4 : Enter Hunt Mode This command forces the comparison of sync cha- racters or flags to assembled receive characters for the purpose of synchronization. After reset, the SCC automatically enters the Hunt mode (except asyn- chronous). Whenever a flag or sync character is matched, the Syne/Hunt bit in Read Register 0 is re- 58/93 GS SGS-THOMSON set and, if External/Status Interrupt Enable is set, an interrupt sequence is initiated. The SCC auto- matically enters the Hunt mode when an abort condition is received or when the receiver is disa- bled. Bit 3 : Receiver CRC Enable This bit is used to initiate CRC calculation at the be- ginning of the last byte transferred from the Recei- ver Shift register to the receive FIFO. This opera- tion occurs independently of the number of bytes in the receive FIFO. When a particular byte is to be excluded from CRC calculation, this bit should be reset before the next byte is transferred to the re- ceive FIFO. If this feature is used, care must be ta- ken to ensure that eight bits per character is selec- ted in the receiver because of an inherent delay from the Receive Shift register to the CRC checker. This bit is internally set to "1" in SDLC mode and the SCC calculates CRC on all bits except inserted ze- ros between the opening and closing character flags. This bit is ignored in asynchronous mode. Bits 2 : Adress Search Mode (SDLC) Setting this bit in SDLC mode causes messages with addresses not matching the address program- med in WR6 to be rejected. No receiver interrupts can occur in this mode unless there is an address match. The address that the SCC attempts to match can be unique (1 in 256) or multiple (16 in 256), de- pending on the state of Sync Character Load Inhi- bit bit. The Address Search mode bit is ignored in all modes except SDLC. Bit 1 : SYNC Character Load Inhibit If this bit is set to "1" in any synchronous mode ex- cept SDLC, the SCC compares the byte in WR6 with the byte about to be stored in the FIFO, and it inhi- bits this load if the bytes are equal. The SCC does not calculate the CRC on bytes stripped from the Data stream in the manner. If the 6-bit sync option is selected while in Monosync mode, the compare is still across eight bits, so WR6 must be program- med for proper operation. If the 6-bit syne option is selected with this bit set to "1", all syne characters except the one immediate- ly preceding the data are stripped from the mes- sage. If the 6-bit sync option is selected while in the Bisync mode, this bit is ignored. The address recognition logic of the receiver is mo- dified in SDLC mode if this bit is set to "1", i.e., on- ly the four most significant bits of WR6 must match the receiver address. This procedure allows the MICROELECTRONICS 506REGISTERS DESCRIPTION (cont'd) SCC to receive frames from up to 16 separate sources without programming WR6 for each source {if each station address has the four most significant bits in common). The address field in the frame is still eight bits long. This bit is ignored in SDLC mode if Address Search mode has not been selected. Bit 0 : Receiver Enable When this bit is set to "1", receiver operation begins. This bit should be set only after all other receiver pa- rameters are established and the receiver is com- pletely initialized. This bit is reset by a channel or hardware reset command, and it disables the recei- ver. Write Register 4 (transmit/receiver miscella- neous parameters and modes). WR4 contains the control bits for both the receiver and the transmitter. These bits should be set in the transmit and recei- ver initialization routine before issuing the contents of WR1, WR3, WR6, and WR7. Bit positions for WR4 are shown in Figure 47. Bits 7 and 6 : Clock Rate 1 And 0 These bits specify the multiplier between the clock and data rates. In synchronous modes, the 1S mode is forced internally and these bits are ignored unless External Sync mode has been selected. 1X Mode (00). The clock rate and data rate are the same. In External Sync mode, this bit combination specifies that only the SYNC pin can be used to achieve character synchronization. 16X Mode (01). The clock rate is 16 times the data rate. In External Sync mode, this bit combin-ation specifies that only the SYNC pin can be used to achieve character synchronization. 32X Mode (10). The clock rate is 32 times the data rate. In External Sync mode, this bit combination specifies that either the SYNC pin or a match with the character stored in WR7 will signal character synchronization. The sync character can be either six or eight bits long as specified by the 6-bit/8-bit Sync bit in WR10. 64X Mode (11). The clock rate is 64 times the data rate. With this bit combination in External Sync mode, both the receiver and transmitter are placed in SDLC mode. The only variation from normal SDLC operation is that the SYNC pin can be used to start or stop the reception of a frame by forcing the receiver to act as though a flag had been recei- ved. ky SGS-THOMSON 28530 Bits 5 and 4: SYNC Modes 1 And 0 These two bits select the various options for charac- ter synchronization. They are ignored unless syn- chronous modes are selected in the stop bits field of this register. Monosync (00). In this mode, the receiver achieves character synchronization by matching the charac- ter stored in WR7 with an identical character in the received data stream. The transmitter uses the cha- racter stored in WR6 as a time fill. The sync charac- ter can be either six or eight bits, depending on the state of the 6-bit/8-bit Sync bit in WR10. If the Sync Character Load Inhibit bit is set, the receiver strips the contents of WR6 from the data stream if recei- ved within character boundaries. Bisync (01). The concatenation of WR7 with WR6E is used for receiver synchronization and as a time fillby the transmitter. The sync character can be 12 or 16 bits in the receiver, depending on the state of the 6-bit/8-bit Sync bit in WR10. The transmitted character is always 16 bits. SDLC Mode (10). in this mode, SDLC is selected Figure 47 : Write Register 4. jo, |. [ 0: [o.]0;]o, [o, [05] | L PARITY ENABLE PARITY EVEN/ODD SYNC MODES ENABLE 1 STOP BITICHARACTER 1% STOP BITSICHARACTER 2 STOP BITSICHARACTER 8 BIT SYNC CHARACTER 18 BIT SYNC CHARACTER SDLC MODE (01111110 FLAG) EXTERNAL SYNC MOOE X1 CLOCK MODE 416 CLOCK MODE X32 CLOCK MODE X64 CLOCK MODE 59/93 MICROELECTROMIES 50728530 REGISTERS DESCRIPTION (cont'd) and requires a Flag (01111110) to be written to WR. The receiver address field should be written to WR6. The SDLC CRC polynomial must also be selected (WRS5) in SDLC mode. External Sync Mode (11). In this mode, the SCC expects external logic to signal character synchro- nization via the SYNC pin. If the crystal oscillator op- tion is selected (in WR11), the internal SYNC signal is forced to "0". In this mode, bits B7-B6 of this re- gister select special version of External Sync mode. In this mode, the transmitter is in Monosync mode using the contents of WR6 as the time fill with the sync character length specified by the 6-bit/8-bit Sync bit in WR10. Bits 3 and 2: Stop Bits 1 and 0 These bits determine the number of stop bits added to each asynchronous character that is transmitted. The receiver always checks for one stop bit in Asyn- chronous mode. A Special mode specifies that a Synchronous mode is to be selected. B2 is always set to "1" by a channel or hardware reset to ensure that the SYNC pin is in a known state after a reset. Synchronous Modes Enable (00). This bit combi- nation selects one of the synchronous modes spe- cified by bits B4, B5, B6, and B7 of this register and forces the 1X Clock mode internally. 1 Stop Bit/Character (01). This bit selects Asyn- chronous mode with one stop bit per character. 1 1/2 Stop Bits/Character (10). These bits select Asynchronous mode with 1-1/2 stop bits per charac- ter. This mode can not be used with the 1X clock mode. Figure 48 : Write Register 5. | be CRC ENABLE [be SDLTicRC.18 Tx ENABLE SEND BREAK Tx S BITS (OR LESSYCHARACTER 2 Stop Bits/Character (11). These bits select Asyn- chronous mode with two stop bits per transmitted character and check for one received stop bit. Bit 1 : Parity Even/Odd This bit determines whether parity is checked as even or odd. A "1" programmed here selects even parity, and a "0" selects odd parity. This bit is igno- red if the Parity Enable bit is not set. Bit 0 : Parity Enable When this bit is set, an additional bit position beyond those specified in the bits/character control is added to the transmitted data and is expected in the re- ceive data. The Received Parity bit is transferred to the CPU as part of the data unless eight bits per cha- racter is selected in the receiver. Write Register 5 (transmit parameter and controls). WR5 contains control bits that affect the operation of the transmitter. B2 affects both the transmitter and the receiver. Bit positions for WR5 are shown in Figure 48. Bit 7 : Data Terminal Ready This is the control bit for the DTR/REQ pin while the pin is in the DTR mode (selected in WR14). When set, DTR is Low ; when reset, DTR is High. This bit is ignored when DTRVREQi is programmed to act as a REQUEST pin. This bit is reset by a channel or hardware reset. Bits 6 and 5 : TXBits/Character 1 and 0 These bits control the number of bits in each byte transferred to the transmit buffer. Bits sent must be right justified with lease significant bits first. The Five Or Less mode allows transmission of one to five bits per character ; however, the CPU should form at the data character as shown below in Ta- ble 10. In the Six or Seven Bits/Character modes, unused data bits are ignored. Table 10 : Tx Bits/Character 1 and 0. Tx BITS / | Tx BITS / CHAR i CHAR 0 0 0 5 or less bits / character 0 1 7 bits / character 1 0 6 bits / character 1 1 8 bits / character Tx 7 BITSICHARACTER D7|Ds Ds D, D3|D2 Dy Do Tk 6 BITSICHARACTER * 111(1]/1101/0]0|0)| Sends one data bit Tx 8 BITSICHARACTER 1/1]1]/0/0/0]0]0] Sends two data bits OTA 1;1/0/0|0|0|0]0| Sends three data bits 11/0/0/0/0/0/0)0]| Sends four data bits 0|0;0)0,/0/0/0/0;| Sends five data bits S088 (7 SGS-THOMSON IF imcRomzcraomies 508REGISTERS DESCRIPTION (cont'd) Bit 4 : Send Break When set, this bit forces the TxD output to send continuous "Os" beginning with the following trans- mit clock, regardless of any data being transmitted at the time. This bit functions whether or not the transmitter is enabled. When reset, TxD continues to send the contents of the Transmit Shift register, which might be syncs, data or all "1s". If this bit is set while in the X21 mode (Monosync and Loop mode selected) and character synchronization is achieved in the receiver, this bit is automatically re- set and the transmitter begins sending syncs or da- ta. This bit can also be reset by a channel or hard- ware reset. Bit 3 : Transmit Enable Data is not transmitted until this bit is set, and the TxD output sends continuous "1s" unless Auto Echo mode or SDLC Loop mode is selected. If this bit is reset after transmission started, the transmission of data or sync characters is completed. If the trans- mitter is disabled during the transmission of a CRC character, sync or flag characters are sent instead of CRC. This bit is reset by a channel or hardware reset. Bit 2: SDLC/CRC-16 This bit selects the CRC polynomial used by both the transmitter and receiver. When set, the CRC-16 polynomial is used ; when reset, the SDLC polyno- mial is used. The SDLC/CRC polynomial must be selected when SDLC mode is selected. The CRC generator and checker can be preset to all "Os" or all"1s", depending on the state of the Preset 1/ Pre- set 0 bit in WR10. Bit 1 : Request To Send This is the control bit for the RTS pin. When the RTS bit is set, the RST pin goes Low ; when reset, RTS Figure 49 : Write Register 6. 28530 goes High. In the Asynchronous mode with the Auto Enables bit set, RST goes High only after all bits of the character have been sent and the transmit buf- fer is empty. In synchronous modes of the Asyn- chronous mode with auto enables off, the pin direct- ly follows the state of this bit. This bit is reset by a channel or hardware reset. Bit 0: Transmit CRC Enable This bit determines whether or not CRC is caicula- ted on a transmit character. If this bit is set at the time the character is loaded from the transmit buf- fer to the Transmit Shift register, CRC is calculated on that character. CRC is not automatically sent un- less this bit is set when the transmit underrun exists. Write Register 6 (sync characters or SDLC ad- dress field). WR6 is programmed to contain the transmit sync character in the Monosync mode, the first byte of a 16-bit sync character in the External Sync mode. WR6 is not used in asynchronous modes. In the SDLC modes, it is programmed to contain the secondary address field used to com- pare against the address field of the SDLC Frame. In SDLC mode, the SCC does not automatically transmit the station address at the beginning of the response frame. Bit positions for WR6 are shown in Figure 49. Write Register 7 (sync character or SDLC flag). WR7 is programmed to contain the receive sync character in the Monosync mode, a second byte (the last eight bits) of a 16-bit sync character in the Bi- syne mode, or a Flag character (01111110) in the SDLC modes. WR7 may hold the receive sync cha- racter or a flag if one of the special versions of the External Sync mode is selected. WR7 is not used in Asynchronous mode. Bit positions for WR7 are shown in Figure 50. SYNC; SYNCs SYNCs SYNC, SYNCs SYNC? SYNC SYNCg MONOSYNC, @ BITS SYNCS SYNC, SYNC3 SYNC2 SYNC, SYNCo x MONOSYNC, 6 BITS SYNCis SYNC SYNC SYNC SYNC), SYNCi0 SYNCy SYNCs BISYNC, 16 BITS SYNC, SYNC10 SYNCy SYNC, SYNC; SYNC, SYNCS SYNC, BISYNC, 12 BITS o 1 1 1 1 1 1 6 SDLC (57 SGS-THOMSON 61/93 MICROELECTRONICS 50928530 REGISTERS DESCRIPTION (cont'd) Figure 50 : Write Register 7. Pit NO RESET SYNC; SYNC5 SYNCs SYNC, = SYNC3 SYNCz2 = SYNCy SYNCo MONOSYNC, 8 BITS SYNC; SYNCo SYNCS SYNC, = SYNC SYNC, = SYNCy SYNCg MONOSYNC, 6 BITS SYNC; - SYNCe SYNCs SYNC, SYNC3; SYNCz = SYNC; SYNCo _BISYNC, 16 BITS SYNC; SYNC? SYNC; SYNCp 1 1 1 1 BISYNC, 12 BITS ADR, ADRs ADRs ADA, ADRs ADR2 ADR: ADRAg = SDLC AOR, ADRs ADRs ADR, x x x x SDLC (ADDRESS RANGE) Figure 51 : Write Register 9 . | L ws NV DLC MIE STATUS HIGH/STATUS LOW o CHANNEL RESET B CHANNEL RESET A FORCE HARDWARE RESET Write Register 8 (transmit buffer). WR8 is the transmit bufffer register. Write Register 9 (master interrupt control). WR9 is the Master Interrupt Control register and contains the Reset command bits. Only one WR@ exists in the SCC and can be accessed from either channel. The interrupt control bits can be programmed at the same time as the Reset command because these bits are only reset by a hardware reset. Bit positions for WR are shown in Figure 51. Bits 7 and 6 : Reset Command Bits Together, these bits select one of the reset com- 62/93 ky SGS-THOMSON mands for the SCC. Setting either of these bits to 1" disables both the receiver and the transmitter in the corresponding channel, forces TxD for that channel marking, forces the modem control signals High in that channel, resets all IPs and |USs and di- sables all interrupts in that channel. Four extra PCLK cycles must be allowed beyond the usual cy- cle time after any of the active reset commands is issued before any additional commands or controls are written to the channel affected. Four extra PCLK cycles must be allowed beyond the usual cycle time before any additional command or controls are writ- ten to the SCC. MICROELECTRONICS 51028530 REGISTERS DESCRIPTION (cont'd) No Reset (00). This command has no effect. It is used when a write to WR9 is necessary for some reason other than an SCC Reset command. Channel Reset B (01). Issuing this command causes a channel reset to be performed on Chan- net B. Channel Reset A (10). Issuing this command causes a channel reset to be performed on Chan- nel A. Force Hardware Reset (11). The effects of this command are identical to those of a hardware re- set, except that the Shift Right/Shift Left bit is not changed and the MIE, Status High/Status Low and DLC bits take the programmed values that accom- pany this command. Bit 5 : Not Used Must be 0. Bit 4 : Status High/Status Low This bit controls which vector bits the SCC will mo- dify to indicate status. When set fo"1", the SCC mo- difies bits V6, V5, and V4 according to Table 11. When set to "0", the SCC modifies bits V1, V2, and V3 according to Table 11. This bit controls status in both the vector returned during an interrupt acknow- ledge cycle and the status in RR2B. This bit is reset a hardware reset. Table 11 : Interrupt Vector Modification. V3 | V2 | V1 | Status High / Status Low =0 V4 | V5 | V6 | Status High / Status Low = 1 0 0 0 | ChB Transmit Buffer Empty 0 0 1 Ch B External / Status Change 0 1 0 Ch B Receive Character Avail. 0 1 1 Ch B Special Receive Condition 1 0 0 | ChA Transmit Buffer Empty 1 0 1 Ch A External / Status Change 1 1 0 | ChA Receive Character Avail. 1 1 1 Gh A Special Receive Condition Bit 3 : Master Interrupt Enable This bit is set to 1 to globally enable interrupts, and cleared to zero to disable interrupts. Clearing this bit to zero forces the IEO pin to follow the state of the IEI pin unless there is an IUS bit set in the SCC. No [US bit can be set after the MIE bit is cleared to zero, This bit is reset by a hardware reset. Bit 2 : Disable Lower Chain The Disable Lower Chain bit can be used by the CPU to control the interrupt daisy chain. Setting this bit to "1" forces the IEO pin Low, preventing lower- i SGS-THOMSON priority devices on the daisy chain from requesting interrupts. This bit is reset by a hardware reset. Bit 1: No Vector The No Vector bit controls whether or not the SCC will respond to an interrupt acknowledge cycle by placing a vector on the data bus if the SCC is the hi- ghest-priority device requesting an interrupt. If this bit is set, no vector is returned ; i.e., ADO-AD7 re- main three-stated during an interrupt acknowledge cycle, even if the SCC is the highest-priority device requesting an interrupt. Bit 0 : Vector Includes Status The Vector Includes Status Bit controls whether or not then SCC will include status information in the vector it places on the bus in response to an inter- rupt acknowledge cycle. If this bit is set, the vector returned is variable, with the variable field depen- ding on the highest-priority IP that is set. Table 11 shows the encoding of the status information. This bit is ignored if the No Vector (NV) bit is set. Figure 52 : Write Register 10. | bs BITr BIT SYNC THe LOOP MODE ABORTIFLAG ON UNDERRUN MARK/FLAG IDLE GO ACTIVE ON POLL NAZ NRZI FM1 (TRANSITION = 1) FMO (TRANSITION = 0) CRC PRESET 1/0 Write Register 10 (miscellaneous transmitter/re- ceiver control bits). WR10 contains miscellaneous control bits for both the receiver and the transmitter. Bit positions for WR10 are shown in Figure 52. Bit 7: CRC Preset I/O This bit specifies the initialized condition of the re- ceive CRC checker and the transmit CRC gener- ator. If this bit is set to "1", the CRC generator and checker are preset to "1". If this bit is set to "0", the CRC generator and checker are preset to "0" Either option can be selected with either CRC polynomial. 63/93 MICROELECTROMIES 51428530 REGISTERS DESCRIPTION (cont'd) In SDLC mode, the transmitted CRC is inverted be- fore transmission and the received CRC is checked against the bit pattern "0001110100001111". This bit is reset by a channel or hardware reset. This bit is ignored in Asynchronous mode. Bit 6 and 5 : Data Encoding 1 and 2 These bits control the coding method used for both the transmitter and the receiver, as illustrated in Ta- ble 12. All of the clocking options are available for all coding methods. The DPLL in the SCC is useful for recovering clocking information in NRZI and FM modes. A hardware reset forces NRZ mode. Timing for the various modes in shown in Figure 53. Table 12 : Data Encoding Data Data Encoding Encoding 0 0 NRZ 0 1 NRZi 1 0 FM1 (transition = 1) 1 1 FMO (transition = 1) Bit 4: Go Active On Poll When Loop mode is first selected during SDLC ope- ration, the SCC connects RxD to TxD with only gate delays in the path. The SCC does not go on-loop and insert the 1-bit delay between RxD and TxD un- til this bit has been set and an EOP received. When the SCC is on-loop, the transmitter cannot go active unless this bit is set at the time an EOP is received. The SCC examines this bit whenever the transmit- ter is active in SDLC Loop mode and is sending a flag. If this bit is set at the time the flag is leaving the Transmit Shift register, another flag or data byte (if the transmit buffer is full) is transmitted. If the Go Ac- tive on Poll bit is not set at this time, the transmitter finishes sending the flag and reverts to the 1-Bit De- lay mode. Thus, to transmit only one response frame, this bit should be reset after the first data byte is sent to the SCC but before CRC has been trans- mitted. If the bit is not reset before CRC is transmit- ted, extra flags are sent, slowing down response time on the loop. If this bit is reset before the first da- ta is written, the SCC completes the transmission of the present flag and reverts to the 1-Bit Delay mode. Atter gaining control of the loop, the SCC is not able to transmit again until a flag and another EOP have been received. Though not strictly necessary, it is good practice to set this bit only upon receipt of a poll frame to ensure that the SCC does not go on loop without the CPU noticing it. In synchronous modes other than SDLC with the Loop Mode bit set, this bit must be set before the 64/93 kr SGS-THOMSON transmitter can go active in response to a received sync character. This bit is always ignored in Asynchronous mode and Synchronous modes unless the Loop Mode bit is set. This bit is reset by a channel or hardware re- set. Bit 3 : Mark/ Flag Idle This bit affects only SDLC operation and is used to control the idle line condition. If this bit is set to "0", the transmitter sends flags an idle line. If this bit is set to "1", the transmitter sends continuous "1s" af- ter the closing flag of a frame. The idle line condi- tion is selected byte by byte ; Le., either a flag or eight "1s" are transmitted. The primary station in an SDLC loop should be programmed for Mark Idle to create the EOP sequence . Mark Idle must be de- selected at the beginning of a frame before the first data is written to the SCC, so that an opening flag can be transmitted. This bit is ignored in Loop mode, but the programmed value takes effect upon exiting the Loop mode. This bit is reset by achannel or hard- ware reset. Bit 2 : Abort/Flag On Underrun This bit affects only SDLC operation and is used to control how the SCC responds to a transmit under- run condition. If this bit is set to "1" and a transmit underrun occurs, the SCC sends an abort and a flag instead of CRC. If this bit is reset, the SCC sends CRC on atransmit underrun. At the beginning of this 16-bit transmission, the Transmit Underrun/EOM bit is set, causing an External/Status interrupt. The CPU uses this status, along with the byte count from memory or the DMA, to determine whether the frame must be retransmitted. A transmit buffer Emp- ty interrupt occurs at the end of this 16-bit transmis- sion to start the next frame. If both this bit and the Mark/Flag Idle bit are set to "1", all "1s" are trans- mitted after the transmit underrun. This bit should be set after the first byte of data is sent to the SCC and reset immediately after the last byte of data so that the frame will be terminated properly with CRC and a flag. This bit is ignored in Loop mode, but the programmed value is active upon exiting Loop mode. This bit is reset by a channel or hardware re- set. Bit 1 : Loop Mode In SDLC mode, the initial set condition of this bit forces the SCC to connect TxD to TxD and to be- gin searching the incoming data stream so that it can go on loop. All bits pertinent to SDLC mode ope- ration in other registers must be set before this mode MECROELECTRONICS $12REGISTERS DESCRIPTION (cont'd) Figure 53 : NRZ(NRZI)FM1(FMO) Timing. 28530 LS \ Aw LS] DATA J aia J BIT CELL g 5 Sort [ Dy BiT CELL - J 65/93 513Z8530 REGISTERS DESCRIPTION (cont'd) is selected. The transmitter and receiver should not be enabled until after this mode has been selected. As soon as the Go Active Onn Poll bit is set and an EOP is received the SCC goes on loop. If this bit is reset after the SCC is on loop, the SCC waits for the next EOP to go off loop. In synchronous modes, the SCC uses this bit, along with the Go Active On Poll bit, to synchronize the transmitter to the receiver. The receiver should not be enabled until after this mode is selected. The TxD pin is held marking when this mode is selected un- less a break condition is programmed. The receiver waits for a sync character to be received and then enables the transmitter on a character boundary. The break condition, if programmed, is removed. This mode works properly with sync characters of 6,8, or 16 bits. This bit is ignored in Asynchronous mode and is reset by a channel or hardware reset. Bit 0: 6 Bit/8 Bit SYNC This bit is used to select a special case of synchro- nous modes. If this bit is set to "1" in Monosync mode, the receiver and transmitter sync characters are six bits long instead of the usual eight. If this bit is set to "1" in Bisync mode, the received sync will be 12 bits and the transmitter sync character will re- main 16 bits long. This bit is ignored in SDLC and Asynchronous modes but still has effect in the spe- cial external sync modes. This bit is reset by a chan- nel or hardware reset. Write Register 11 (clock mode control). WR11 is the Clock Mode Control register. The bits in this re- gister control the sources of the both the receive and transmit clocks, the type of signal on the SYNC and RTxC pins, and the direction of the TRxC pin. Bit po- sitions for WR11 are shown in Figure 54. Bit 7 : RTxC-XTAL/NO XTAL This bit controls the type of input signal the SCC ex- pects to see on the RTxC pin. If this bit is set to "0", the SCC expects a TTL-compatible signal as an in- put to this pin. If this bit is set to "1", the SCC connects a high-gain amplifier between the RTxC and SYNC pins in expectation of a quartz crystal being placed across the pins. The output of this oscillator is available for use as a clocking source. In this mode of operation, the SYNC pin is unavailable for other use. The SYNC- signal is forced to "0" internally. A hardware reset forces NO XTAL. (At least 20 ms should be allowed after this bit is set to allow the oscillator to stabilize.) 66/93 Bits 6 and 5 : Receiver Clock 1 And 0 These bits determine the source of the receive clock as shown in Table 13. They do not interfere with any of the modes of operation in the SCC but simply control a multiplexer just before the internal receive clock input. A hardware reset forces the receive clock to come from the TRxC pin. Table 13 : Receive Clock Source. Receive | Receive Clock 1 | Clock 0 0 0 Receive Clock = RTxC Pin 0 1 Receive Clock = TRxC Pin 1 0 Receive Clock = BR Output 1 1 Receive Clock = DPLL Output Bits 4 and 3 : Transmit Clock 1 and 0 These bits determine the source of the transmit clock as shown in Table 14. They do not interfere with any of the modes of operation of the SCC but simply control a multiplexer just before the internal transmit clock input. The DPLL output that may be used to feed the transmitter in FM modes lags by 90 the output of the DPLL used by the receiver. This makes the received and transmitted bit cells occur simultaneously, neglecting delays. A hardware re- set selects the TRxC pin as the source of the trans- mit clocks. Table 14 : Transmit Clock Source. Transmit|Transmit Clock 1 | Clock 0 IST SGS-THOMSON 0 0 Transmit Clock = RTxC Pin 0 1 Transmit Clock = TRxC Pin 1 0 Transmit Clock = BR Output 1 1 Transmit Clock = DPLL Output Bit2: TRxC O/ This bit determines the direction of the TRxC pin. If this bit is set to "1", the TRxC pin is an output and carries the signal selected by D1 and DO of this re- gister. However, if either the receive or the transmit clock is programmed to come from the TRxC pin, TRxC will be an input, regardless of the state of this bit. The TRxC pin is also an input if this bit is set to "0". A hardware reset forces this bit to "0". Bits 1 and 0 : TRxC Output Source 1 And 0 These bits determine the signal to be echoed out of the SCC via the TRxC pin. No signal is produced if TRxC has been programmed as the source of either MICROELECTRONICS 514REGISTERS DESCRIPTION (cont'd) Figure 54 : Write Register 11. 28530 [; [6 ] 0s JD [a | O2 | Os | Oo | t TRC OUT = XTAL OUTPUT TRxC OUT = TRANSMIT CLOCK TRaC OUT = BR GENERATOR OUTPUT TRxC OUT = DPLL OUTPUT TRxc Ol TRANSMIT CLOCK = RTxC PIN TRANSMIT CLOCK = TRxC PIN TRANSMIT CLOCK TRANSMIT CLOCK RECEIVE CLOCK = ATxC PIN RECEIVE CLOCK = TRxC PIN RECEIVE CLOCK = 8R GENERATOR OUTPUT RECEIVE CLOCK = DPLL OUTPUT RTxG XTALINO XTAL 8A GENERATOR OUTPUT DPLL OUTPUT the receive or the transmit clock. If TRxC O/ (bit 2) is set to "0", these bits are ignored. If the XTAL oscillator output is programmed to be echoed, and the Xtal oscillator has not been en- abled, the TRxC pin goes High. The DPLL signal that is echoed is the DPLL signal used by the recei- ver. Hardware reset selects the XTAL oscillator as the output source. Tabie 15 : Transmit External Control Selec- tion. Output | Output Signal | Signal 0 0 TRxC = XTAL Oscillator Output 0 1 TRxC = Transmit Clock 1 0 TRxC = BR Output 1 1 TRxC = DPLL Output (Receive) &y SGS-THOMSON Write Register 12 (lower byte of baud rate gene- rator time constant). WR12 contains the lower byte of the time constant for the baud rate gener- ator. The time constant can be changed at any time, but the new value does not take effect until the next time the time constant is loaded into the down coun- ter. No attempt is made to synchronize the loading of the time constant into WR12 and WR13 with the clock driving the down counter. For this reason, it is advisable to disable the baud rate generator while the new time constant is loaded into WR12 and WR13. Ordinarily, this is done anyway to prevent a load of the down counter between the writing of the upper and lower bytes of the time constant. The formula for determining the appropriate time constant for a given baud is shown below with the desired rate in bits per second and the BR clock pe- 67/93 MICROELECTRONICS 51528530 REGISTERS DESCRIPTION (cont'd) riod in seconds. This formula is derived because the counter decrements from N down to 0"- plus-one- cycle for reloading the time constant and is then fed to a toggle flip-flop to make the output a square wave. Bit positions for WR12 are shown in Figu- re 55. Time constant = [1/2 desired rate - BR clock pe- riod] - Figure 55 : Write Register 12. = Tes | Lower Byte oF Tce f TIME CONSTANT Tes TCs C? Write Register 13 (upper byte of baud rate gene- rator time constant). WR13 contains the upper byte of the time constant for the baud rate gener- ator. Bit positions for WR13 are shown in Figure 56. Write Register 14 (miscellaneous control bits). WR14 contains some miscellaneous control bits. Bit positions for WR14 are shown in Figure 57. Bits 7 and 5 : Digital Phase-Locked Loop Command Bits These three bits encode the eight commands for the Digital Phase-Locked Loop. A channel or hardware reset disables the DPLL, resets the mission clock latches, sets the source to the RTxC pin and selects NRZI mode. The Enter Search Mode command en- ables the DPLL after a reset. Null Command (000). This command has no effect on the DPLL. Enter Search Mode (001). Issuing this command causes the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the inco- ming data stream. The action taken by the DPLL upon receipt of this command depends on the ope- rating mode of the DPLL. 68/93 ks SGS-THOMSON Figure 56 : Write Register 13. | L Cs Te, Tew Tet | uppeR BYTE OF TC12 (TIME CONSTANT Tig TO Tas Figure 57 : Write Register 14. BEBE EEE [| BR GENERATOR ENABLE BR GENERATOR SOURCE DTRUREQUEST FUNCTION AUTO ECHO LOCAL LOOPBACK NULL COMMAND ENTER SEARCH MODE RESET MISSING CLOCK DISABLE DPLL SET SOURCE = BR GENERATOR SET SOURCE = ATxt SET FM MODE SET NRZt MODE 9 0 Q Q 1 1 1 1 wleloaloel=a|alalo MICROELECTRONICS 516REGISTERS DESCRIPTION (cont'd) In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in the incoming da- tastream. After the Search mode is entered, the first edge the DPLL sees is assumed to be a valid data edge, and the DPLL begins the clock recovery ope- ration from that point. The DPLL clock rate must be 32 times the data rate in NRZI mode. Upon leaving the Search mode, the first sampling edge of the DPLL occurs 16 of these 32X clocks after the first data edge and the second sampling edge occurs 48 of these 32X clocks after the first data edge. Beyond this point, the DPLL begins normal operation, adjus- ting the output to remain in sync with the incoming data. In FM mode, the output of the DPLL is Low while the DPLL is waiting for an edge in the incoming da- ta stream. The first edge the DPLL detects is assu- med to be a valid clock edge. For this to be the case, the line must contain only clock edges ; i.e., with FM1 encoding, the line must be continuous "Os". With FMO encoding the line must be continuous "1s", whereas Manchester encoding requires alter- nating "1s" and "Os" on the line. The DPLL clock rate must be 16 times the data rate in FM mode. The DPLL output causes the receiver to sample the da- ta stream in the nominal center of the two halves of the bit cell to decide whether the data was a "1" or a "0". After this command is issued, as in NRZI mode, the DPLL starts sampling immediately after the first edge is detected. (In FM mode, the DPLL examines the clock edge of every other bit cell to decide what correction must be made to remain in sync). If the DPLL does not see an edge during the expected window, the one clock mission bit in RR10 is set. If the DPLL does not see an edge after two successive attempts, the two clocks missing bit in RR10 is set and the DPLL automatically enters the Search mode. This command resets both clock mis- sing latches. Reset Clock Missing (010). Issuing this command disables the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state. Disable DPLL (001). issuing this command disa- bles the DPLL, resets the clock missing latches in RR10, and forces a continuous Search mode state. Set Source = BR Gen (100). Issuing this command forces the clock for the DPLL to come from the out- put of the baud rate generator. Set Source = RTxC (101). Issuing the command forces the clock for the DPIi to come from the RTxC pin or the crystal oscillator, de-pending on the state i SGS-THOMSON 28530 of the XTAL/no XTAL bit in WR11. This mode is se- lected by a channel or hardware reset. Set FM Mode (110). This command forces the DPLL to operate in the FM mode and is used to re- cover the clock from FM or Manchester-encoded data. (Manchester is decoded by placing the recei- ver in NRZ made while the DPLL is in FM mode.) Set NRZI Mode (111). Issuing this command forces the DPLL to operate in the NRZI mode. This mode is also selected by a hardware or channel reset. Bit 4 : Local Loopback Setting this bit to "1" selects the local Loopback mode of operation. In this mode, the internal trans- mitted data is routed back to the receiver, as well as to the TxD pin. The CTS ans DCD inputs are igno- red as enables in Local Loopback mode, even if auto enables is selected. (If so programmed, transitions on these inputs still cause interrupts.) This mode works with any Transmit/Receive mode ex-cept Loop mode. For meaning-ful results, the frequency of the transmit and receive clocks must be the same. This bit is reset by a channel or hardware reset. Bit 3 : Auto Enable Setting this bit to "1" selects the Auto Enable mode of operation. In this mode, the TxD pin is connected to RxD, as in Local Loopback mode, but the recei- ver still listens to the RxD input. Transmitted data is never seen inside or outside the SCC in this mode, and CTS is ignored as a transmit enable. This bit is reset by a channel or hardware reset. Bit 2: DTR/Request Function This bit selects the function of the DTR/REQ pin fol- lows the state of the DTR bit in WAS. If this bit is set to"1", the DTR/REQ pin follows the state of the DTR bit in WRS. If this bit is set to "1", the DTR/REQ pin goes Low whenever the transmit buffer becomes empty and in any of the synchronous mode when CRC has been sent at the end of a message. The request function on the DTR/REQ pin differs some- what from the transmit request function available on the W/REQ pin in that REQUEST does not go inac- tive until the internal operation satisfying the request is complete, which occurs four to five PCLK cycles after the rising edge of DS, READ or WRITE. If the DMA used is edge-triggered, this difference is unim- portant. This bit is reset by a channel or hardware reset. Bit 1 : Baud Rate Generator Source This bit selects the source of the clock for the baud rate generator. If this bit is set to "0", the baud rate 69/93 MICROELECTRONICS 517Z8530 REGISTERS DESCRIPTION (cont'd) generator clock comes from either the RTxC pin or the XTAL oscillator (depending on the state of the XTAL/no XTAL bit). If this bit is set to "1", the clock for the baud rate generator is the SCCs PCLK in- put. Hardware reset sets this bit to "0", selecting the RTxC pin as the clock source for the baud rate ge- nerator. Bit 0 : Baud Rate Generator Enable This bit controls the operation of the baud rate ge- nerator. The counter in the baud rate generator is enabled for counting when this bit is set to 1", and counting is inhibited when this bit is set to "0". When this bit is set to "1", change in the state of this bit is not reflected by the output of the baud rate gener- ator for two counts of the counter. This allows the command to be synchronized. However, when set to "0", disabling is immediate. This bit is reset by a hardware reset. Write Register 15 (external/status interrupt control). WR15 is the External/Status Source Control register. If the External/Status interrupts are enabled as a group via WRY1, bits in this register control which External/Status conditions can cause an interrupt. Only the External/Status conditions that occur after the controlling bit are sent to "1" will cause an interrupt. This is true even if an Exter- nal/Status condition is pending at the time the bit is set. Bit positions for WR15 are shown in Figure 58. Bit 7: Break/Abort IE If this bit is set to "1", a change in the Break/Abort status of the receiver causes an External/Status in- terrupt. This bit is set by a channel or hardware re- set. Bit 6 : Tx Underrun/EOM If this bit is set to "1", a change of state by the Tx Underrun/EOM latch in the transmitter causes an External/Status interrupt. This bit is setto "1" a chan- nei or hardware reset. BitS: CTS IE If this bit is set to "1", a change of state on the CTS pin causes an External/Status interrupt. This bit is set by a channel or hardware reset. Bit 4: SYNC/Hunt IE If this bit is set to "1", a change of state on the SYNC pin causes an External/Status interrupt in Asyn- chronous mode, and a change of state in the Hunt 70/93 57 S&S;THOMSON bit in the receiver causes and External/Status inter- ruptin synchronous modes. This bit is set by a chan- nel or hardware reset. Bit3 : DCDIE If this bit is set to "1", a change of state on the DCD pin causes an External/Status interrupt. This bit is set by a channel or hardware reset. Bit 2 : Not Used Must be "0". Bit 1 : Zero Count IE If this bit is set to "1, an External/Status interrupt is generated whenever the counter in the baud rate generator reaches "0". This bit is set to "0" by achan- nel or hardware reset. Bit 0 : Not Used Must be "0". READ REGISTERS The 28530 SCC contains seven read registers in each channel. In addition there are two registers which are shared by both channels. The status of these registers is continually changing and depends on the mode of communication, received and trans- mitted data, and the manner in which this data is transferred to and from the CPU. The following des- cription details the bit assignments for each regis- ter. Read Register 0 (transmit/ receiver buffer status and external status). Read Register 0 contains the status of the receive and transmit buffers. RRO also contains the status bits for the six sources of Exter- nal/Status interrupts. The bit configuration is illustra- ted in Figure 59. Bit 7 : Break/Abort In the Asynchronous mode, this bit is set when a Break sequence (null character plus framing error) is detected in the receive data stream. This bit is re- set when the sequence is terminated, leaving a sin- gle null character in the receive FIFO. This charac- ter should be read and discarded. In SDLC mode, this bit is set by the detection of an Abort sequence (seven or more "1s"), then reset automatically at the termination of the Abort sequence. In either case, if the Break/Abort IE bit is set, an External/Status in- terrupt is initiated. Unlike the remainder of the Ex- ternal/Status bits, both transitions are guaranteed to MICROELECTROMIES 518REGISTERS DESCRIPTION (cont'd) cause an External/Status interrupt, even if another External/Status interruptis pending at the time these transitions occur. This procedure is necessary be- cause Abort or Break conditions may not persist. Bit 6 : TX Underrun/EOM This bit is set by a channel or hardware reset and when the transmitter is disabled or a Send Abort command is issued. This bit can only be reset by the reset Tx Underrrun/EOM Latch command in WRO. When the Transmit Underrun occurs, this bit is set and causes an External/Status interrupt (if the Tx Underrun/EOM IE bit is set). Only the 0-to-1 transition of this bit causes an inter- rupt. This bit is always "1" in Asynchronous mode, unless a reset Tx Underrun/EOM Latch command has been erroneously issued. In this case, the Send Abort command can be used to set the bit to one and at the same time cause an External/Status in- terrupt. Bit 5 : Clear to Send If the CTS IE bit in WR15 is set, this bit indicates the state of the CTS pin the last time any of the enabled External/Status bits changed. Any transition on the CTS pin while no interrupt is pending latches the state of the CTS pin and generates an External/Sta- tus interrupt. Any odd number of transitions on the CTS pin while another External/Status interrupt is pending also causes an External/Status interrupts condition. If the CTS IE bit is reset, it merely reports the current unlatched state of the CTS pin. Bit 4: SYNC/Hunt The operation of this bit is similar to that of the CTS Figure 58 : Write Register 15. 28530 bit, except that the condition monitored by the bit va- ties depending on the mode in which the SCC is operating. When the XTAL oscillator option is selected in asyn- chronous modes, this bit is forced to "0" (no Exter- nal/Status interrupt is generated). Selecting the XTAL oscillator in synchronous or SDLC modes had no effect on the operation of this bit. The XTAL oscillator should not be selected in Exter- nal Sync mode. in Asynchronous mode, the operation of this bit is identical to that of the CTS status bit, except that this bit reports the state of the SYNC pin. in External sync mode the SYNC pin is used by ex- ternal logic to signal character synchronization. When the Enter Hunt Mode command is issued in External Sync mode, the SYNC pin must be held High by the external sync logic until character syn- chronization is achieved. A High on the SYNC pin holds the Sync/Hunt bit in the reset condition. When external synchronization is achieved, SYNC must be driven Low on the second rising edge of the Receive Clock after the last rising edge of the Re- ceive Clock on which the last bit of the receive cha- racter was received. Only SYNC is forced Low, it is good practice to keep it Low until the CPU informs the external sync logic that synchronization has been lost or that a new message is about to start. Both transitions on the SYNC pin cause Exter- nal/Status interrupts if the Sync/Hunt IE bit is set to "1" The Enter Hunt Mode command should be issued Figure 59 : Read Register 0. [Le re [o.72. [8 0510.1.) | L Rx CHARACTER AVAILABLE ZERO COUNT Tx BUFFER EMPTY bco DCD IE SYNC/HYNT SYNC/HUNT IE cts CTS IE Tx UNDERRUNIEOM Tx UNDERRUN/EOM IE BREAK/ABORT BREAK/ABORT IE 57 SGS:THOMSON nes MICROELECTRONICS 51928530 REGISTERS DESCRIPTION (cont'd) whenever character synchronization is lost. At the same time, the CPU should inform the external lo- gic that character synchronization has been lost and that the SCC is waiting for SYNC to become active. In the Monosync and Bisync Receive modes, the Sync/Hunt status bit is initially set to "1" by the En- ter Hunt Mode command. The Sync/Hunt bit is re- set when the SCC established character synchroni- zation. Both transitions cause External/Status inter- rupts if the Sync/Hunt IE bit is set. When the CPU detects the end of message or the loss of character synchronization, the Enter Hunt Mode command should be issued to set the Sync/Hunt bit and cause an External/Status interrupt. In this mode, the SYNC pin is an output, which goes Low every time a sync pattern is detected in the data stream. In the SDLC modes, the Sync/Hunt bit is initially set by the Enter Hunt Mode command or when the re- ceiver is disabled. It is reset when the opening flag of the first frame is detected by the SCC. An Exter- nal/Status interrupt is also generated if the Sync/Hunt IE bit is set. Unlike the Monosync and Bi- sync modes, once the Sync/Hunt bit is resetin SDLC mode, it does not need to be set when the end of the frame is detected. The SCC automatically main- tains synchronization. The only way the Sync/Hunt bit can be set again is by the Enter Hunt Mode com- mand or by disabling the receiver. Bit 3 : Data Carrier Detect If the DCD bit in WR15 is set, this bit indicates the state of the DCD pin the last time the Enabled Ex- ternal/Status bits changed. Any transition on the DCD pin while_no interrupt is pending latches the state of the DCD pin, and generates an Exter- nal/Status interrupt. Any odd number of transitions on the DCD pin while another External/Status inter- rupt is pending also causes an External/Status in- terrupt condition. If the DCD IE is reset, this bit me- rely reports the current, unlatched state of the DCD pin. Bit 2: TX Buffer Empty This bit is set to "1" when the transmit buffer is emp- ty. It is reset while CRC is sent in a synchronous or SDLC mode and while the transmit buffer is full. The bit is reset when a character is loaded into the trans- mit buffer. This bit is always in the set condition af- ter a hardware or channel reset. Bit 1 : Zero Count If the Zero Count Interrupt Enable bit is set in WR15, 72/93 ki SGS-THOMSON this bit is set to one while the counter in the baud rate generator is at the count of zero. If there is no other External / Status interrupt condition pending at the time this bit is set, an External/Status interrupt is generated. However, if there is another Exter- nal/Status interrupt pending at this time, no interrupt is initiated until interrupt service is complete. If the Zero Count condition does not persit beyond the end of the interrupt service routine, no interrupt will be generated. This bit is not latched High, even thought the other External/Status latches close as a result of the Low-to-High transition on ZC. The interrupt service routine should check the other External / Status conditions for changes. If none changed, ZC was the source. In polled applications, check the IP bit in RR3A for a status change and then proceed as in the interrupt service routine. Bit 0 : RX Character Available This bit is set to "1" when at least one character is available in the receive FIFO and is reset when the receive FIFO is complety empty. A channel or hard- ware reset empties the receive FIFO. Read Register 1. RR1 contains the Special Re- ceive Condition status bits and the residue codes for the I-field in SDLC mode. Figure 60 shows the bit positions for RR1. Bit 7 : End of Frame (SDLC) This bit is used only in SDLC mode and indicates that a valid closing flag has been received and that the CRC Error bit and residue codes are valid. This bit can be reset by issuing the Error Reset com- mand. It is also updated by the first character of the following frame. This bit is reset in any mode other than SDLC. Bit 6 : CRC/Framing Error If a framing error occurs (in Asynchronous mode), this bit is set (and not latched) for the receive cha- racter in which the framing error occurred. Detection of a framing error adds an additional one-half bit to the character time so that the framing error is not in- terpreted as a new Start bit. In Synchronous and SDLC modes, this bit indicates the result of compa- ting the CRC checker to the apppropriate check va- lue. This bit is reset by issuing an Error Reset com- mand, but the bit is never latched. Therefore, it is al- ways updated when the next character is received. When used for CRC error status in Synchronous or SDLC modes, this bit is usually set since most bit combination, except for a correctly completed mes- sage, result in a non-zero CRC. MICROELECTRONICS 520REGISTERS DESCRIPTION (contd) Figure 60 : Read Register 1. ALL SENT RESIDUE CODE 2 RESIDUE CODE 1 RESIDUE CODE 0 PARITY ERROR Rx OVERRUN ERROR CRC/FRAMING ERROR END OF FRAME (SOLC) i= Bit 5 : Receiver Overrun Error This bit indicates that the receive FIFO has overtio- wed. Only the character that has been written over is flagged with this error, and when the character is read, the Error condition is latched until reset by the Error Reset command. The overrun character and all subsequent characters received until the Error Reset command is issued causes a Special Receive Condition vector to be returned. Bit 4 : Parity Error When parity is enabled, this bit is set for the charac- ters whose parity does not match the programmed sense (even/odd). This bit is latched so that once an error occurs, it remains set until the Error Reset command is issued. If the parity in Special Condi- tion bit is set, a parity error causes a Special Re- ceive Condition vector to be returned on the charac- ter containing the error and on all subsequent cha- racters until the Error Reset command is issued. Bit 3,2, and 1: Residue Codes 2,1, And 0 In those cases in SDLC mode where the received |- Field is not an integral multiple of the character length, these three bits indicate the length of the I- Field and are meaningful only for the transfer in which the end of frame bit is set. This field is set to "011" by a channel or hardware reset and is forced to this state in Asynchronous mode. These three bits can leave this state only if SDLC is selected and a character is received. The codes signify the follo- wing (Reference Table 16 when a receive charac- ter length is eight bits per character). |-Fieid bits are right-justified in all cases. if a receive character length other than eight bits is used for the |-Field, a table similar to Table 16 can be construc- ted for each different character length. Table 17 kr SGS-THOMSON 28530 shows the residue codes for no residue (The I-Field boundary lies on a character boundary). Table 16 : |-Field Bit Selection (8 Bits only). . : : I-Field Bits | !-Field Bits in Residue|Residue|Residue in Last Byte|Previous Byte 1 0 0 0 3 0 4 0 0 4 1 4 0 0 5 0 0 1 0 6 1 0 1 0 7 0 1 1 0 8 1 1 1 1 8 0 0 0 2 8 Bit 0: Al Sent In Asynchronous mode, this bit is set when all cha- racters have completely cleared the transmitter pins. Most modems contain additional delays in the data path, which requires the modem control signals to remain active until after the data has cleared both the transmitter and the modem. This bit is always set in synchronous and SDLC modes. Table 17 : Residue Bits/Character. Bits / Char| Residue Residue Residue 8 0 1 1 7 0 0 0 6 0 1 0 5 0 0 1 Read Register 2. RR2 contains the interrupt vector written into WR2. When the register is accessed in Channel A, the vector returned is the vector actual- ly stored in WR2. When this register is accessed in Channe! B, the vector returned includes status in- formation in bits 1, 2, and 3, or in bits 6, 5, and 4, depending on the state of the Status High/Status Low bit in WR9 and independent of the state of the VIS bit in WR9. The vector is modified according to Table 11 shown in the explanation of the VIS bit in WRg. If no interrupts are pending, the status is V3, V2, V1=011, or V6, V5, V4 = 110. Figure 61 shows the bit positions for RR2. Read Register 3. RR3 is the interrupts Pending re- gister. The status of each of the Interrupt Pending bits in the SCC is reported in this register. This re- gister exists only in Channei A. If this register is ac- cessed in Channel B, all "Os" are returned. The two unused bits are always returned as "0". Figure 62 shows the bit positions for RR3. 73/93 MICROELECTRONICS 52128530 REGISTERS DESCRIPTION (cont'd) Read Register 8. RR8 is the Receive Data register. Read Register 10. RR10 contains some miscella- neous status bits. Unused bits are always "0". Bit positions for RR10 are shown in Figure 63. Bit 7 : One Clock Missing While operating in the FM mode, the DPLL sets this bit to "1" when it does not see a clock edge on the incoming lines in the window where it expects one. This bit is latched until reset by a Reset Missing Clock or Enter Search Mode command in WR14. In the NRZI mode of operation and while the DPLL is disabled, this bit is always "0". Bit 6 : Two Clocks Missing While operating in the FM mode, the DPLL sets this bit to "1" when it does not see a clock edge in two successive tries. At the same time the DPLL enters the Search mode. This bit is latched until reset by a Reset Missing Clock or Enter Search Mode com- mand in WR10. In the NRZI mode of operation and while the DPLL is disabled, this bit is always "0". Bit 4 : Loop Sending This bit is set to "1" in SDLC Loop mode while the transmitter is in control of the Loop, that is, while the Figure 61 : Write Register 2. SCC is actively transmitting on the loop. This bit is reset at all other times. This bit can be polled in SDLC mode to determin when the closing flag has been sent. Bit 1: On Loop This bit is set to "1" while the SCC is actually onloop in SDLC Loop mode. This bit is set to "1" in the X.21 mode (Loop mode selected while in monosync) when the transmitter goes active. This bit is "0" at all other times. This bit can also be pulled in SDLC mode to determine when the closing flag hass been sent. Read Register 12. RR12 returns the value stored in WR12, the lower byte of the time constant for the baud rate generator. Figure 64 shows the bit posi- tions for RR12 Read Register 13. RR13 returns the value stored in WR13, the upper byte of the time constant for the baud rate generator. Figure 65 shows the bit posi- tions for RR13. Read Register 15. RR15 reflects the value stored in WR15, the External/Status IE bits. The two unu- sed bits are always returned as "Os". Figure 66 shows the bits positions for RR15. Figure 62 : Write Register 3. INTERRUPT VECTOR Ax ENABLE SYNC CHARACTER LOAD INHIBIT ADDRESS SEARCH MODE (SOLC) Ax CRC ENABLE ENTER HUNT MODE AUTO ENABLES = Rx 5 BITSICHARACTER Ra 7 BITSICHARACTER Ra & BITSICHARACTER Rx 8 BITSICHARACTER 74/93 i SGS-THOMSON MICROELECTROMIES 522REGISTERS DESCRIPTION (cont'd) 28530 NRZI FAI (TRANSITION = 1) FMO (TRANSITION = 0) Figure 63 : Write Register 10. Figure 65 : Write Register 13. EEESEh ET = BIG BIT SYNC |B, | Oy [Os fs [D {03 | D, | Oe | | MODE L TC. ABORT/FLAG ON UNDERRUN te MARWFLAG IDLE GO ACTIVE ON POLL Teta NR vert A UPPER BYTE OF T12 ( TIME CONSTANT CRC PRESET VO Figure 64 : Write Register 12. Figure 66 : Write Register 15. Lr | Bs [Bs [Bs] Bs [D2 [Os | Oo} [oe Te, TC2 TC; Ty TCs TCs TC; LOWER BYTE OF TIME CONSTANT [Ee DCD IE SYNC/HUNT IE CYS IE Tx UNDERRUN/EOM IE BREAKJAGORT IE by SGS-THOMSON 75/93 MICROELECTRONICS 52328530 SCC INITIALIZATION WORKSHEET This section describes the software initialization pro- cedure for the Serial Communications Controller (SCC). Figure 68 provides a worksheet that can be used as an aid when initializing the SCC. Since all SCC ope- ration modes are initialized in a similar manner, the worksheet can be used to tailor the SCC device to the user's individual need. Specific examples are gi- ven in the following sections. Register Overview Each of the SCC's two channels has its own sepa- rate Write registers that are programmed to initialize different operating modes. There are two types of bits in the Write registers : Command bits and Mode bits. An example of a register that contains both types of bits is Write Register 9 (WR9), and is shown in figure 67. Figure 67 : Write Register 2. STATUS HIGH / STATUS LOW e CHANNEL MESET A FORCE HARDWARE RESET O513A 8-2 WR@ is the Master Interrupt Control register and contains the Reset command bits. Command bits are denoted by having boxes drawn around them in register diagrams. Bit D5 in this register is not used in this register and must be 0 at all times. The Command bits, D7 and D6, select one of the reset commands for the SCC. Setting either of these bits to 1 disables both the receiver and the transmit- ter in the corresponding channel, forces TxD for the channel marking, forces the modem contro! signals High in that channel, resets all IPs and [USs, and di- 76/93 &7 S&S-THOMSON sables all interrupts in that channel. Functions con- trolled by the Command bits can only be enabled or disabled, they cannot be toggled. Bits D4-D0 are Mode bits that can be enabled or di- sabled either by being set to "1" or reset to "0". Each Mode bit affects only one function. For example, Bit D1 is the No Vector mode bit, it controls whether or not the SCC will respond to an interrupt acknow- ledge cycle by placing a vector on the data bus. If this bit is set, no vector is returned. In command bits entry, each new command requires a separate rewrite of the entire register. Care must be taken when issuing a command, so that the Mode bits are not changed accidentally. Initialization Procedure The SCC initialization procedure is divided into three parts. The first part consists of programming the operation modes (e.g. bits-per-character, parity) and leading the constants (e.g., interrupt vector, time constants). The second part enables the hard- ware functions (e.g., transmitter, receiver, baud-rate generator). It is important that the operating modes are programmed before the hardware functions are enabled. The third part, if required, consists of enabling the different interrupts. Table 18 shows the order (from top to bottom) in which the SCC registers are to be programmed. Those registers that need not be programmed are listed as optional in the comments column. The bits in the registers that are marked with an "X" are to be programmed by the user. The bits marked with an "S" are to be set to their previous programmed value. For example, in part 2, Write Register 3, bits Di-D7 are shown with an "S" because they have been programmed in part 1 and must remain set to the same value. Initialization Table Generation Figure 68 is a worksheet for the initialization of the SCC. Ail the bits that must be programmed as ei- thera "0" ora "1" are already filled in ; the remaining bits are left blank and are to be programmed by the user according to the desired mode of operation. The binary value can then be converted to a hexa- decimal number and placed in the table, following the Write register notation in the column labeled "HEX". A Program Initialization Table is produced when this worksheet is completed. MICROELECTRONICS 624SCC INITIALIZATION WORKSHEET (cont'd) Figure 68 : SCC Initialization Worksheet. 28530 Label of SCC Table: Description: SCC Base Add: REGISTER MODES i IWTERRUPT 74 r ENABLES wro wre a 5 3 : wre WR wrio weit WRI2 WRIT HEX BINARY 7 6 5S 4 302 1 494 : a i | , COMMENTS SOFTWARE AESET RESET TaCAC RESET Ext/STATUS RESET Ext/STATUS &rr SGS-THOMSON MIGROELECTROMICS 77/93 52528530 SCC INITIALIZATION WORKSHEET (cont'd) Table 18 : SCC Initialization Order. Part 1. Modes and Constants WR9 | 1100000 | Hardware Reset WRO | GO0000XX | Select Shift Mode (8030 only) WR4 | XXXXXXXX] Tx/Rx Con, Asyne or Sync Mode WR1 | OXX00X00 | Select W/REQ (opt) WR2 | XXXXXXXX| Program Interrupt Vector (opt) WR3 | XXXXXXX0O| Select Rx Controi WRS | XXXXOXXX | Selects Tx Control WR6 | XXXXXXXX| Program Syne Character (opt) WR7 | XXXXXXXX] Program Syne Character (opt) WR39 | 000X0XXX | Select Interrupt Control WR10| XXXXXXXX| Miscellaneous Control (opt) WR11 | XXXXXXXX]| Clock Control WR12| XXXXXXXX| Time Constant Lower Byte (opt) WR13] XXXXXXXX| Time Constant Upper Byte (opt) WR14] XXXXXXX0 | Miscellaneous Control WR14| XXXSSSSS | Commands (opt) Part 2. Enables WR14| 000SSSS1 | Baud Rate Enable WR3 |SSSSSSS1 | Rx Enable WR5 |SSSS1SSS | Tx Enable WRO | 10000000 | Reset Tx CRG (opt) WR1 | XSS00S00 | DMA Enable (opt) Part 3. Interrupt Status WR15 | XXXXXXXX| Enable External/status WRO | 00010000 | Reset External Status WRO | 00010000 | Reset External Status Twice WR1 |SSSXXSXX| Enable Rx, Tx and Ext/status WR9 | 00O0SXSSS | Enable Master Interrupt Enable 1 = Set to one X = User defined 0 = Reset to zero) S = Same as previously prog. Reset Conditions Prior the initialization, the SCC should be reset by either hardware or software. A hardware reset can POLLED ASYNCHRONOUS MODE This section describes the use of the SCC in polled Asynchronous Mode. The device can be set with 5 to 8 bits per character, 1, 1.5, or 2 stop bits, and a wide range of baud rates. In this particular example, 8 bits per character, 2 stop bits and 9600 baud rate are used. An external 2.4576MHz, crystal oscillator is used for baud-rate generation. The SCC can be programmed for local loopback for on-board diagno- stics. The user can make use of this feature to test- program the part without additional hardware to si- miulate an actual transmit and receive environment. SCC Interface Figure 69 shows the SCC to CPU interface required for this application. The 8-bit data bus and control lines all come from the user's CPU. The 8530 control lines are RD, WR, A/B, D/C and CE. PCLK comes from the system clock, or an external crystal, up to the maximum rate of the SCC (ex. 6MHz for the Z8530A). The IE| and the INTACK pins should be pulled up. The baud-rate generator clock is connec- ted to the RTXC pin. SCC Initialization Initialization of the SCC for polled asynchronous communication is divided into two parts ; part one programs the operating modes of the SCC and part two enables them. Care must be taken when writing 78/93 526 k SCS-THOMSON Tf micnosLecTRemes be accomplished by simultaneously grounding. A software reset can be executed by writing a 0H to Write Register 9. the software to meet the SCCs Cycle and Reset Re- covery times. The Cycle Recovery time, 6 PCLK cy- cles, applies to the period between any Read or Write cycles affecting the SCC. The Reset Recove- ry time is the period after a hardware reset caused either by hardware or software ; this recovery time extends the Cycle Recovery time to 11 PCLK cy- cles. For more details about these recovery times, see the section Interfacing the SCC. Table 19 : Polled Asynchronous Initialization Pro- cedure. Register |Value Comments WR9 COH | Force Hardware Reset WR4_ =| 4CH | x16 Clock, 2 Stop Bits, no Parity WR3 COH | Rx8 Bits, Rx Disabled WR5 60H | Tx8 Bits, DTR, RTS, Tx off WRQ OOH | int. Disabled WR10 | OOH | NRZ WR11_ | 56H | Tx & Rx = BRG out, TRxC =BRG oul WR12 | O6H | Time Constant = 6 WR13 | OOH | Time Constant High = 0 WR14 | 10H | BRG in = RTxC, BRG off, Loopback Enables WR14 | 11H | BRG Enabie WR3 C1H | Rx Enable WR5 68H | Tx EnablePOLLED ASYNCHRONOUS MODE (cont'd) Figure 69. 28530 00-07 | Veo Vee SYSTEM PIN 12 FOR CHANNEL A PIN 28 FOR CHANNEL 8 PCLK ATxC XTAL 24576 MHz ost osc SCC Operating Mode Programming WRS resets the SCC to a known state by writing a CO hex. The command, Force Hardware Reset, is identical to a hardware reset. WR4 selects the asynchronous, x 16 mode, with 2 stop bits and no parity. The x 16 mode means that clock rate is 16 times the data rate. WR3 selects 8 bits per character and does not enable the receiver. The 8 bits per character allows 8 bits to be assembled from the data stream. The receiver is not enabled at this time because the SCC has not been initialized. WRS selects 8 bits per character and does not enable the transmitter. The 8 bits per character al- lows 8 bits to be sent, as data, with the least signi- ficant bit first. The transmitter is not enabled at this time because the SCC has not been initialized. WR3 selects that there are no interrupts enabled. This inhibits the SCC from requesting an interrupt from the CPU. WR10 selects NRZ encoding. This NRZ coding is used on the transmitter as well as the receiver. WR11 selects the RTxC pin to TTL clock ; the baud- rate generator is the transmit and receive clocks source, and the TRxC pin as a baud-rate generator output. WR12 & WR13 and select the baud-rate generator's time constant. The WR13 time constant is determi- ned by the equation : Clock Frequency Time Constant = ____________ - 2 2 x Baud Rate x clock mode In this example, the clock frequency is 2.4576MHz, the baud rate is 9600, and the clock made is 16, the time constant is, therefore, 6 ; expressed as a 16- bit, hexadecimal number, it is QO06H. The time constant LOW (WR12) is, therefore, O6H and the time constant HIGH (WR13) is OOH. The baud rate for this example can be varied, as long as the data rate is less than 1/4 of the PCLK rate. Table 20 shows the time constants for other com- mon baud rates. Table 20 : Time Constants for Common Baud Rates. Baud Rate Divider Decimal Hex 38400 0 0000H 19200 2 0002H 9600 6 0006H 4800 14 OOOEH 2400 30 001EH 1200 62 003EH 600 126 007EH 300 254 OOFEH 150 510 01FEH For 2.4576 MHz Clock, X 16 Mode i SGS-THOMSON 79/93 MICROELECTRONICS 527Z8530 POLLED ASYNCHRONOUS MODE (conid) WR14 selects the baud-rate generator as the RTxC pin, baud-rate generator disabled, and internal loop- back. The baud-rate generator uses the RTxC pin as the clock source and is not enabled at this time because the SCC initialization is not complete. SCC Operating Mode Enables WR14 enables the baud-rate generator. Bit 0 (LSB) is changed to a 1 to enable the baud-rate generator ; all other bits must maintain the value selected du- ring initialization. WR3 enables the receiver. Bit 0 (LSB) is changed toa 1 to enable the receiver, all other bits must main- tain the value selected during initialization. WR85 enables the transmitter. Bit 3 is changed to a 1 to enable the transmitter, all other bits must main- tain the value selected during initialization. Transmit and Receive Routines After initialization, and after all enables have been selected, the SCC is ready for communication. The transmitter buffer and the receive FIFO are empty. The example shown below is coded to trans- mit and receive characters. Figure 70 : Transmit and Receive Routine. ; Transmit a character TXCHAR: INPUT RRO ;Read RRO Test Bit 2 Test transmit buffer empty JZ TXCHAR __ ;Loop if not empty QUTPUT CHAR ;Output chara cter to data port RET Return ; Receive a character RXCHAR: INPUT RRO ;Read RRO TEST BITO ;sTest Receive buffer JZ RXCHAR_;Loop if not full INPUT CHAR ;Input charac ter from data port RET ; Return Figure 71. INTERRUPT , CONTROLLER int cor Veco Voc scc SYSTEM 1 WNTACK PIN 12 FOR CHANNEL A PiN 26 FOR CHANNEL B [>] Pctk RTC XTAL | 24576 MHz osc osc i 80/93 {7 SGS-THOMSON fs MICROELECTRONICS 52828530 INTERRUPT WITHOUT INTACK ASYNCHRONOUS MODE This section describes the use of the SCC for inter- rupt-driven Asynchronous Mode. As with the exam- ple in the previous chapter, the SCC is set with 8 bits per character, 2 stop bits, at 9600 baud rate. An external 2.4576MHz, crystal oscillator is used for baud-rate generation. Interrupt acknowledge is not generated because of the extra hardware required to produce this signal. In this chapter, the SCC is al- so programmed for local loopback so that no exter- nal loop between the transmit and the receive data lines is needed for on-board diagnostics. This fea- ture allows the user to test-program the part without additional hardware to simiulate an actual transmit and receive environment. SCC Interface Figure 71 shows the SCC to CPU interface required for this application. The 8-bit data bus and control lines all come from the user's CPU. For the 8530, the control lines are RD, WR, A/B, D/C and CE. The INT signal goes to an interrupt controller which must produce the interrupt vector to the CPU. The PCLK comes from the system clock, or an external crystal oscillator, up to the maximum rate of the SCC (ex. 6MHz for the Z8530A). The IEI and the INTACK pins should be pulled up. The baud-rate generator clock is connected to the RTXC pin. SCC Initialization The initialization of the SCC for interrupt-driven asynchronous communication is divided into three parts. Part one programs the operating modes of the SCC, part two and three enable them. Care must be taken when writing the code to meet the SCCs Cy- cle and Reset Recovery times. The Cycle Recove- ry time applies to the period between any Read or Write cycles to the SCC, and is 6PCLK cycles. The Reset Recovery time applies to a hardware reset caused either by hardware or software ; this reco- very time extends the Cycle Recovery time to 11PCLK cycles. More details about these recovery times can be found in the section Interfacing the SCC. ky SGS-THOMSON Table 21. Register |Value Comments WRS_ | COH | Force Hardware Reset WR4 | 4CH | x16 Clock, 2 Stop Bits, no Parity WR2 00H | Interrupt Vector OOWR3 COH | Rx8 Bits, Rx Disabled WRS5 jj 60H | Tx8 Bits, DTR, RTS, Tx off WRS_ | OOH | Int. Disabled WR10 00H | NRZ WR11 56H | Tx & Rx =BRG out, TRxC =BRG out WR12 | O6H | Time Constant = 6 WR13 | OOH | Time Constant High =0 WR14 | 10H | BRG in = RTxC, BRG off, Loopback Enables WR14 | 11H | BRG Enable WR3 C1H | Rx Enable WR5 68H | Tx Enable Enable Interrupts WRi1 12H | Rx Int on All Char and Tx int Enables WRQ =| 08H | MIE SCC Operating Modes Programming WRS resets the SCC to a known state by writing a CO hex. This command, Force Hardware Reset, is identical to a hardware reset. WR4 selects asynchronous mode, x16 mode, 2 stop bits and no parity. The x16 mode means that the clock rate is 16 times the data rate. WR2 is the interrupt vector of the SCC. Even though a vector is not placed on the bus in this mode the vector including status in read from RR2. By writing OOH to this register the status read will be the only bits set in RR2. WR3 selects 8 bits per character and does not en- able the receiver. The 8 bits per character allows 8 bits to be assembled from the data stream. The re- ceiver is not enabled at this time because the SCC is not completely initialized. WRS selects 8 bits per character and does not 81/93 MICROELECTRONICS 52928530 INTERRUPT WITHOUT INTACK ASYNCHRONOUS MODE (cont'd) enable the transmitter. The 8 bits per character al- lows 8 bits to be sent as data with the least signifi- cant bit first. The transmitter is not enabled at this time because the SCC is not completely initialized. WRg selects that there are no interrupts enabled. This will inhibit the SCC from requesting an interrupt from the CPU. WR10 selects NRZ encoding. This selects NRZ co- ding is to be used on the transmitter and the recei- ver. WR11 selects the RTxC pin to TTL clock, the trans- mit and receive clocks source as the baud-rate ge- nerator and the TRxC pin as a baud-rate generator output. WR12 & WR13 select the baud-rate generators time constant. The time constant is determined by the equation : Clock Frequency Time Constant = __-_____ - 2 2 x Baud Rate x clock mode In this example, the clock frequency is 2.4576MHz, the baud rate is 9600, and the clock mode is 16 ; the time constant is 6. Converting this time constant to a 16-bit hexadecimal number, it becomes OO06H. The time constant LOW (WR12) is O6H and the time constant HIGH (WR13) is OOH. The baud rate for this example can be varied for as long as the data rate is less than 1/4 of the PCLK rate. Table 22 gives the time constants for other common baud rates. Table 22 : Time Constants for Common Baud Rates. Baud Rate Divider Decimal Hex 38400 0 0000H 19200 2 0002H 9600 6 0006H 4800 14 OO0EH 2400 30 001EH 1200 62 003EH 600 126 007EH 300 254 OOFEH 150 510 01FEH For 2.4576 MHz Clock, X 16 Mode WR14 selects the baud rate source as the RTxC pin, baud rate generator disabled, and internal _loop- back. The baud-rate generator will use the RTxC pin as the clock source for the baud-rate generator. The baud-rate generator is not enabled at this time be- cause the SCC initialization is not complete. 82/93 ki SGS-THOMSON SCC Operating Mode Enables WR14 enables the baud-rate generator. Bit 0 (LSB) is changed to a 1 to enable the baud-rate generator ; all other bits must maintain the value selected du- ring initialization. WR3 enables the receiver. Bit 0 (LSB) is changed to a 1 to enable the receiver ; all other bits must maintain the value selected during initialization. WR8S enables the transmitter. Bit 3 is changed to a 1 to enable the transmitter ; all other bits must main- tain the value selected during initialization. SCC Operating Mode Interrupts WR1 enables the Tx and the Rx interrupts. The Rx interrupt is programmed to generate an interrupt an all received characters or special conditions. This provides an interrupt on every character received by the SCC. The external/status interrupts are not en- abled in this application. WR9 sets the master interrupt enable (MIE) bit 3. Seting this bit enables the interrupts pending to ge- nerate and interupt on the INT pin. Interrupt Routine When the SCC has been initialized and enabled, it is ready for communication. The transmitter buffer and the receive FIFO are both empty. An interrupt will not be generated until the software writes the first character to the transmit buffer. Once the first character is in the SCC shift register, the first trans- mit interrupt will occur. The SCC will then keep set- ting transmit and receive interrupts to the interrupt controller until the end of the message. At the end of the message, a Reset Transmitter Interrupt Pen- ding (WR0) is issued to clear the transmit interrupt. After the last character is read into the SCC, the in- terrupts will cease until another message is written into the transmitter. Once an interrupt is received and the interrupt con- troller vectors to the interrupt routine, RR2 is read from channel B. The vaiue read from RR2 is the vec- tor, including status. This vector shows the status of the highest priority interrupt pending (IP) at the time it is read. Once the highest priority interrupt condi- tion is cleared, RR2 will show the status of the next highest interrupt pending, if one is present. This al- lows multiple interrupts to be serviced without the overhead of the interrupt acknowledge cycle of the interrupt controller. The following example shows how the interrupt rou- tine shouid be coded. MICROELECTRONICS 530HARDWARE INFORMATION Absolute Maximum Ratings Z8530 Parameter Test Conditions Unit Operating Temperature Z8530 B1/D1/C1 Oto + 70 C B6/D6/C6 40 to + 85 C Storage Temperature 65 to + 150 C Voltages on any Pin with Respect to GND -0.310+7 Vv Total Power Dissipation 700 mw Oscillator Frequency 28530 0to4 MHz Z8530A 0 tos Z8530B 0to8 Note : Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Test Conditions The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the reference pin. Figure 73 : Standard Test Load. Standard conditions are as follows : - +4.76VsVecs+5.25V - GND=0V ~ 0C<Tas+70C All ac parameters assume a load capacitance of 50 pf max. Figure 74 : Open-Drain Test Load. +50 +Sv 241K FROM OUTPUT 22K UNDER TEST FROM = UNDER TEST 100 | ae i DC Characteristics Symbol Parameter Test Conditions Min. | Max. Unit Vin Input High Voltage 2.0 |Vec+0.3) V Vit Input Low Voltage - 0.3 0.8 Vv Vou Output High Voltage lon = 250 pA 24 Vv VoL Output Low Voltage lol =+2.0 mA 0.4 v tiv Input Leakage 04<sVine+24V + 10.0 pA lo Output Leakage 0.4< Vour<+24V + 10.0 HA lec Voc Supply Current 250 mA Vcc = 5 V +5 % unless otherwise specified, over specified temperature range. ir SGS-THOMSON 83/93 MICROELECTRONICS 53128530 HARDWARE INFORMATION (cont'd) Capacitance Symbol Parameter Test Conditions Min. Max. Unit Cin Input Capacitance 10 pf Cout Output Capacitance 15 pf Cro Bidirectional Capacitance 20 pf f= 1 MHz, over specified temperature range. Unmeasured pins returned to ground. AC Timing Characteristics Figure 75 : Read and Write Timing. ass, OT IMTACK Bo-Dr REAO Oo-Dy WRITE whRegq wart wihta REQUEST OTR/AEG REQUEST 84/93 ik 532 SGS-THOMSON MICROELECTRONICSHARDWARE INFORMATION (cont'd) Table 23 : AC Timing Characteristics. 28530 Z8530 Z8530A Z8530B N} Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. |Notes* (ns) (ns) a) (ns) (ns) (ns) 1 | TwPc1 | PCLK Low Width 105 | 2000 | 70 | 1000 | 50 | 1000 2 | TwPCh | PCLK High Width 105 | 2000 | 70 | 1000 | 50 | 1000 3 TIPC PCLK Fall Time 20 10 10 4 TrPC PCLK Rise Time 20 15 10 5 | TcPC | PCLK Cycle Time 250 | 4000 | 165 | 2000 | 125 | 2000 6 | TsA(WR) | Address to WR 1 Setup Time 80 80 70 7 | ThA(WR) | Address to WR T Hold Time 0 0 0 8 | TsA(RD) | Address to RD | Setup Time 80 80 70 9 | ThA(RD) | Address to RD T Hold Time 0 0 0 10] TsIA(PC) | INTACK to PCLK T Setup Time | 10 10 10 11 | TsIAi(wR) | INTACK to WA J Setup Time 200 160 145 1 12 | ThIA(WR) | INTACK to WR 7 Hold Time 0 0 0 13 | Ts!Ai(RD) | INTACK to RD J Setup Time 200 160 145 1 14| ThIA(RD) | INTACK to RD T Hold Time ) 0 0 15| ThIA(PC) | INTACK to PCLK T Hold Time | 100 100 85 16 |TsCE1(WR)| CE Low to WR J Setup Time 0 0 17 | ThCE(WR) | CE to WR 7 Hold Time 0 0 18 |TsCEh(WR)| CE High to WR J Setup Time 100 70 60 19 |TsCE1(RD)| CE Low to RD | Setup Time 0 1 20 | ThCE(RD) | CE to RD 7 Hold Time i) 1 21 |TsCEh(RD)| CE High to RD J Setup Time 100 70 60 1 22| TwRD1 | RD Low Width 240 200 150 1 23 |TdRD(DRA)| RD J to Read Data Active Delay| 0 0 0 24 |TdRDr(DR)| RD 7 to Read Data Not Valid 0 0 0 Delay 25 | TdRDf(DR) | RD L to Read Data Valid Delay 250 180 140 26 | TARD(DRz) RD 7 to Read Data Float Delay 70 45 40 2 Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time required for a + 0.5 V change in the output with a maximum de load and minimum ac load. * Timings are preliminary and subject to change. ky SGS-THOMSON MICROELECTRONICS 85/93 53328530 HARDWARE INFORMATION (cont'd) Figure 76 : Interrupt Acknowledge Timing. Figure 77 : Reset Timing. Figure 78 : Cycle Timing. 8608 Ky S&S:THOMsoN MICROELECTRONICS 534HARDWARE INFORMATION (cont'd) Table 24 : AC Timing Characteristics. 28530 Z8530 Z8530A Z8530B N] Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max, |Notes* (ns) (ns) (ns) (ns) (ns) (ns) 27 | TdA(DR) Address Required Valid to 300 280 220 Read Data Valid Delay 28) TwWRi | WR Low Width 240 200 150 29 |TsDW(WR)| Write Data to WR Setup Time] 10 10 10 30 | ThDW(WR) | Write Data WR 7 Hold Time 0 0 0 31 | TaWR(W) | WR J to Wait Valid Delay 240 200 170 32 | TdRD(W) | RD J to Wait Valid Delay 240 200 170 33 |TAWRI(REQ)| WR 1 to W/ REQ Not Valid 240 200 170 Delay 34 | TdRDA(REG)} RD J to W/ REQ Not Valid 240 200 170 Delay 35 |TAWRr(REQ)| WR 7 to DTR / REQ Not Valid ATcPC 4TcPC 4TcPC Delay 36 | TARDr(REQ)| RD T to DTR / REQ Not Valid 4TcPC 4TcPC 4TcPC Delay 37 | TAPC(INT) | PCLK | to INT Valid Delay 500 500 500 4 38 | TdIA(RD) | INTACK to RD J (Acknowledge) | 250 200 150 5 Delay 39] TwRDA | RD (Acknowledge) Width 250 200 150 40 | TdRDA(DR) RD J (Acknowledge) to Read 250 180 140 Data Valid Delay 41 | TsIEI(RDA) | IE! to RD J (Acknowledge) 120 100 95 Setup Time 42 |THIE(RDA)| IEI to RD T (Acknowledge) Hold| 0 0 0 Time 43 | TdlEI(IEO) | IEI to IEO Delay Time 120 100 95 44 | TAPC(IEO) | PCLK T to IEO Delay 250 250 200 45 | TARDAUINT) | RD J to INT Inactive Delay 500 500 450 4 46 | TdRD(WRQ)| RD T WR J Delay for No Reset] 30 15 15 47 | TAWRQ(AD)| WRT to RD | Delay for No 30 30 20 Reset 48 | TwRES | WR and AD Coincident Low for | 250 200 150 Reset 49 Tre Valid Access Recovery Time 4TcPC 4TcPC 4TcPC 3 Notes: 3. Parameter applies only between transactions involving the SCC. 4, Open-drain output, measured with open-drain test load. 5. Parameter is system dependent. For any SCC in the daisy chain, TdlAi(RD) must be greater than the num of TdPC(tEO) for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdlEIf(IEO) for each device separating them in the daisy chain. * Timings are preliminary and subject to change. 17] SGS-THOMSON MICROELECTRONICS 87/93 535Z8530 HARDWARE INFORMATION (cont'd) Figure 79 : General Timing. winked REQUEST WIREQ wait RTKC, TRE WECENE SYNe EXTERNAL Tart, ATzc TRANSMIT se 88/93 G7 SGS-THOMSON Jf MICROELECTRONICS 536HARDWARE INFORMATION (cont'd) Table 25 : General Timing Characteristics (cont'd). 28530 28530 Z8530A 28530B N) Symbol Parameter Min. | Max. | Min. | Max. | Min. | Max. |Notes* (ns) _| (ns) | (ns) | (ns) | (ns) | (ns) 1 | TdPC(REQ)| PCLK | to W / REQ Valid Delay 250 250 250 TaPC(w) PCLK J to Wait Inactive Delay 350 350 350 TsRXC(PC) | RxC 7 to PCLK T Setup Time 80 TwPCL 70 | TwPCL 60 TwPCL 1.4 (PCLK = 4 case only) 4 |TsRXD(RXCr)| RxD to RxC T Setup Time 0 0 0 1 (X1 Mode) 5 |TARXD(RXCr)| RxD to RxC T Hold Time 150 . 150 150 1 (X1 Mode} 6 |TsRXD(RXCf}} RxD to RxC ~ Setup Time 0 0 0 15 (X1 Mode) 7 |ThRXD(RXCf)} RxD to RxC J Hold Time 150 150 150 1.5 (X1 Mode) 8 | TsSY(RXC) | SYNC to RxC 7 Setup Time 200 200 200 1 9 | ThSY(RXC) | SYNC to RxC 7 Hold Time 3TcPC 3TcPC 3TcPC 1 + 400 + 320 + 250 10| TsTXC(PC) | TxC J to PCLK T Setup Time 0 0 0 24 11] TdTXCH(TXD)| TxC J to TxD Delay (X1 Mode) 300 230 200 2 12|TdTXCr(TXD}| TxC T to TxD Delay (X1 Mode) 300 230 200 25 13 | TATXD(TRX) | TxD to TRxC Delay 200 200 200 (Send Clock Echo) 14] TwRTXh RTxC High Width 180 180 150 6 15) TwRTX1 RTxC Low Width 180 180 150 6 16} TcRTX RTxC Cycle Time 1000 640 500 6.7 17| TcRTXX Crystal Oscillator Period 250 1000 165 1000 125 1000 18| TwTRXh TRxC High Width 180 180 150 19] TwTRX1 TRxC Low Width 180 180 150 20] TcTRX TRxC Cycle Time 1000 640 500 6.7 21 TwEXT DCD or CTS Pulse Width 200 200 200 | 22 TwSY SYNC Pulse Width 200 200 200 Notes: 1. RxC is RTxC or TRXC, whichever is supplying the receive clock. 2. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 3. Both RTxC and SYNC have 30 pF capacitors to ground connected to them. _ 4, Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between RxC and POLK or TxC and PCLK is required. Qa Parameter applies only to FM encoding/decoding. . Parameter applies only for transmitter and receiver ; DPLL and baud rate generator timing requirements are identical to chip PCLK requirements. aN by The maximum receive on transmit data is 1/4PLCK. Timings are preliminary and subject to change. SGS-THOMSON MICROELECTRONICS 89/93 53728530 HARDWARE INFORMATION (cont'd) Figure 80 : System Timing. Aine, TAT RECEIVE Wwinga REQUEST wikia WAIT Suc OuTPur WAC, TRt TRANSMIT winta REQUEST winka WATT Stange REQUEST int CTs, Bo .AT Svne inpuT 90/93 Gi -THOMSON Jf SGS-THOMSON 53828530 HARDWARE INFORMATION (cont'd) Table 26 : System Timing Characteristics (cont'd). 28530 Z8530A Z8530B 4 N Symbol Parameter - - - Notes Min. | Max. | Min. | Max. | Min. | Max. t 1 | TdRXC(REQ) | RxC T to W/ REQ Valid Delay 8 12 8 12 8 12 2 2 TdRXC(wW) RxC T to Wait Inactive Delay 8 12 8 12 8 14 1.2 3 | TdRXC(SY) | RxC T to SYNC Valid Delay 4 7 4 7 4 7 2 4 | TdRXC(INT) | RxC T to INT Valid Delay 10 16 10 16 10 16 1.2 5 | TdTXC(REQ) | TxC J to W/ REQ Valid Delay 5 8 5 8 5 8 3 6 | TdTXC(W) | TxC J to Wait Inactive Delay 5 8 5 8 5 i1 1.3 7 | TdTXC(DRQ) | TxC J to DTR/ REQ Valid 4 7 4 7 4 7 3 Delay 8 | TdTXC(INT) | TxC J to INT Valid Delay 10 6 10 6 10 1.3 9 | TdSY(INT) | SYNC Transition to INT Valid 2 6 2 6 2 6 1 Delay 10 | TdEXT(INT) | DCD or CTS Transition to INT 2 6 2 6 2 6 1 Valid Delay Notes: 1. Open-drain output, measured with open-drain test load. 2. Rx is RTxC or TRxC, whichever is supplying the receive clock. 3. Tx is TRxC or RTxC, whichever is supplying the transmit clack. * Timings are preliminary and subject to change. T Units equal to TePC. PACKAGES MECHANICAL DATA Figure 81: 28530 40-Pin Dual in Line Plastic mm Inches Dim - Min | Typ | Max | Min | Typ | Max A al 0.63 024 b 0.45 O17 bt | 0.23 0.31 | .009 012 b2 1.27 .050 c D 52,58 2.07 5 E [45.20 16.68| 598 656 l 7 Tenn e 2.54 100 = = | moe | 03 48.26 1.90 60 nd o4 Ki De ee t ee a F 14.10 555 ' | 4.45 AWS Jo | 20 L 3.30 129 or wor =a So c P043-B/6 KI K2 {7 SGS-THOMSON 91/93 Y7 incromscrromes 53928530 PACKAGE MECHANICAL DATA (cont'd) Figure 82: 28530 40-Pin Dual in Line Ceramic Multilayer. mm inches Dim K + F Min | Typ | Max | Min | Typ | Max Pyle s i. [A BO ote b2 : al 1.27 .050 | a2 . + 8 1.27 050 b1 0.45 017 . _ D . b2 0.25 010 c 2.33 .091 1 D 51.30 2.01 nD * E 15.24 600 4 : _ i I e 2.54 100 : [ e3 48.26 1.90 . . F 15.36 604 ssc L 3.30 129 K 12.80 503 Ki 12.80 503 Figure 83 : 28530 44-Lead Plastic Leaded Chip Carrier. mm Inches Dim. Min | Typ | Max | Min | Typ | Max A 117.40 17.65 | 0.685 0.694 B 16.51 18.65 | 0.650 0.655 c | 3.65 3,70 | 0.143 0.145 cl D | 4.20 4.87 |0.165 0.179 di | 259 2.74 |0.104 0.107 d2 0.68 0.026 E | 14.99 16.00} 0.590 0.629 @ 1.27 0.050 e3 12.70 0.500 e4 1.98 0.077 F 0.46 0.018 Fi 0.71 0.027 G 0.101 0.004 M 1.16 0.045 M1 1.14 0.044 a 1.57 92/93 ky 540 SGS-THOMSON MICROELECTRONICSORDERING INFORMATION 28530 Sales Type Frequency Supply Voltage Temp. Range Package 28530B1V 4 MHz 5Vt5% 0 to + 70 C PDIP-40 Z8530B6V 4 MHz 5Vt5% ~ 40 to + 85 C PDIP-40 Z8530D1N 4 MHz 5Vt5% 0 to + 70C CDIP-40 Z8530D6N 4 MHz 5Vt5% 40 to + 85 C CDIP-40 Z8530D2N 4 MHz 5Vt5% 55 to + 125 C CDIP-40 Z8530C1V 4 MHz 5V+t5% 0 to + 70 C PLCC44 Z8530C6V 4 MHz 5Vt5% 40 to + 85 C PLOC44 Z8530AB1V 6 MHz 5Vt5% 0 to + 70C PDIP-40 Z8530ABE6V 6 MHz 5Vt5% 40 to + 85 C PDIP-40 Z8530AD1N 6 MHz 5Vt5% 0 to + 70C CDIP-40 Z8530AD6N 6 MHz 5V45% 40 to + 85 C CDIP-40 Z8530AD2N 6 MHz 5V+t5% 55 to + 125 C CDIP-40 Z8530AC1V 6 MHz 5V+t5% 0 to + 70 C PLOC44 Z8530AC6V 6 MHz 5V+5% - 40 to + 85 C PLOC44 Z8530BB1V 8 MHz 5V+5% 0 to + 70 C PDIP-40 Z8530BB6V 8 MHz 5V+45% 40 to + 85 C PDIP-40 Z8530BD1N 8 MHz 5V4+5% 0 to + 70 C CDIP-40 Z8530BD6N 8 MHz 5V+45% 40 to + 85C CDIP-40 Z8530BC1V 8 MHz 5V+5% 0 to + 70C PLCC44 Z8530BC6V 8 MHz 5V+5% 40 to + 85 C PLOG44 Note : PDIP = Plastic DIP ; CDIP = Ceramic Multilayer DIP ; PLCC = Plastic Leaded Chip Carrier. kyr SGS-THOMSON MICROELECTRONICS 93/93 541