1
LTC1628/LTC1628-PG
1628fb
High Efficiency, 2-Phase
Synchronous Step-Down Switching Regulators
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter
■
Out-of-Phase Controllers Reduce Required Input
Capacitance and Power Supply Induced Noise
■
OPTI-LOOP
®
Compensation Minimizes C
OUT
■
±1% Output Voltage Accuracy
■
Dual N-Channel MOSFET Synchronous Drive
■
Power Good Output Voltage Monitor (LTC1628-PG)
■
DC Programmed Fixed Frequency 150kHz to 300kHz
■
Wide V
IN
Range: 3.5V to 36V Operation
■
Very Low Dropout Operation: 99% Duty Cycle
■
Adjustable Soft-Start Current Ramping
■
Foldback Output Current Limiting
■
Latched Short-Circuit Shutdown with Defeat Option
■
Output Overvoltage Protection
■
Remote Output Voltage Sense
■
Low Shutdown I
Q
: 20µA
■
5V and 3.3V Standby Regulators
■
Selectable Constant Frequency or Burst Mode
®
Operation
■
Available in 5mm × 5mm QFN and
28-Pin SSOP Packages
The LTC
®
1628/LTC1628-PG are high performance dual
step-down switching regulator controllers that drive all
N-channel synchronous power MOSFET stages. A con-
stant frequency current mode architecture allows adjust-
ment of the frequency up to 300kHz. Power loss and noise
due to the ESR of the input capacitors are minimized by
operating the two controller output stages out of phase.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance and
ESR values. The precision 0.8V reference and power good
output indicator are compatible with future microproces-
sor generations, and a wide 3.5V to 30V (36V maximum)
input supply range encompasses all battery chemistries.
A RUN/SS pin for each controller provides both soft-start
and optional timed, short-circuit shutdown. Current
foldback limits MOSFET dissipation during short-circuit
conditions when overcurrent latchoff is disabled. Output
overvoltage protection circuitry latches on the bottom
MOSFET until V
OUT
returns to normal. The FCB mode pin
can select among Burst Mode, constant frequency mode
and continuous inductor current mode or regulate a
secondary winding. The LTC1628-PG includes a power
good output pin that replaces the FLTCPL, fault coupling
control pin of the LTC1628.
■
Notebook and Palmtop Computers, PDAs
■
Battery Chargers
■
Portable Instruments
■
Battery-Operated Digital Devices
■
DC Power Distribution Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP and Burst Mode are registered trademarks of Linear Technology Corporation.
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO
U
+
4.7µFD3 D4
D1 M2
M1
C
B1
, 0.1µF
R2
105k
1%
1000pF
L1
6.3µH
C
C1
220pF
1µF
CERAMIC
C
IN
22µF
50V
CERAMIC
+
C
OUT1
47µF
6V
SP
R
SENSE1
0.01Ω
R1
20k
1% R
C1
15k
V
OUT1
5V
5A
D2
M4
M3
C
B2
, 0.1µF
R4
63.4k
1%
L2
6.3µH
C
C2
220pF
1000pF
+
C
OUT
56µF
6V
SP
R
SENSE2
0.01Ω
R3
20k
1%
R
C2
15k
V
OUT2
3.3V
5A
TG1 TG2
BOOST1 BOOST2
SW1 SW2
BG1 BG2
SGND PGND
SENSE1
+
SENSE2
+
SENSE1
–
SENSE2
–
V
OSENSE1
V
OSENSE2
I
TH1
I
TH2
V
IN
INTV
CC
RUN/SS1 RUN/SS2
V
IN
5.2V TO 28V
M1, M2, M3, M4: FDS6680A
1628 F01
C
SS1
0.1µFC
SS2
0.1µF
LTC1628
2
LTC1628/LTC1628-PG
1628fb
ORDER PART
NUMBER
LTC1628CG
LTC1628IG
LTC1628CG-PG
LTC1628IG-PG
Input Supply Voltage (V
IN
).........................36V to –0.3V
Top Side Driver Voltages
(BOOST1, BOOST2) ...................................42V to –0.3V
Switch Voltage (SW1, SW2) .........................36V to –5V
INTV
CC,
EXTV
CC
, RUN/SS1, RUN/SS2, (BOOST1-SW1),
(BOOST2-SW2), PGOOD .............................7V to –0.3V
SENSE1
+
, SENSE2
+
, SENSE1
–
,
SENSE2
–
Voltages........................ (1.1)INTV
CC
to –0.3V
FREQSET, STBYMD, FCB,
FLTCPL Voltage ................................... INTV
CC
to –0.3V
T
JMAX
= 125°C, θ
JA
= 95°C/W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN/SS1
SENSE1
+
SENSE1
–
V
OSENSE1
FREQSET
STBYMD
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
–
SENSE2
+
FLTCPL*
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
*PGOOD ON THE LTC1628-PG
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
I
TH1,
I
TH2
, V
OSENSE1
, V
OSENSE2
Voltages ...2.7V to –0.3V
Peak Output Current <10µs (TG1, TG2, BG1, BG2) ... 3A
INTV
CC
Peak Output Current ................................ 50mA
Operating Temperature Range
LTC1628C/LTC1628C-PG ........................ 0°C to 85°C
LTC1628I/LTC1628I-PG ..................... –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
(G Package Only) .................................................. 300°C
(Note 1)
ORDER PART
NUMBER
LTC1628CUH
LTC1628IUH
32 31 30 29 28 27 26 25
9 10 11 12
TOP VIEW
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
13 14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1V
OSENSE1
FREQSET
STBYMD
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
NC
SENSE1
–
SENSE1
+
NC
RUN/SS1
FLTCPL
TG1
SW1
V
OSENSE2
NC
SENSE2
–
SENSE2
+
RUN/SS2
TG2
SW2
NC
The ● denotes the specifications which apply over the full operating
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
V
OSENSE1, 2
Regulated Feedback Voltage (Note 3); I
TH1, 2
Voltage = 1.2V ●0.792 0.800 0.808 V
I
VOSENSE1, 2
Feedback Current (Note 3) –5 –50 nA
V
REFLNREG
Reference Voltage Line Regulation V
IN
= 3.6V to 30V (Note 3) 0.002 0.02 %/V
V
LOADREG
Output Voltage Load Regulation (Note 3)
Measured in Servo Loop; ∆I
TH
Voltage = 1.2V to 0.7V ●0.1 0.5 %
Measured in Servo Loop; ∆I
TH
Voltage = 1.2V to 2.0V ●–0.1 –0.5 %
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
θ
JA
= 34°C/W
EXPOSED PAD IS SGND
(MUST BE SOLDERED TO PCB)
UH PART
MARKING
1628
1628I
3
LTC1628/LTC1628-PG
1628fb
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
g
m1, 2
Transconductance Amplifier g
m
I
TH1, 2
= 1.2V; Sink/Source 5uA; (Note 3) 1.3 mmho
g
mGBW1, 2
Transconductance Amplifier GBW I
TH1, 2
= 1.2V; (Note 3) 3 MHz
I
Q
Input DC Supply Current (Note 4)
Normal Mode V
IN
= 15V; EXTV
CC
Tied to V
OUT1
; V
OUT1
= 5V 350 µA
Standby V
RUN/SS1, 2
= 0V, V
STBYMD
> 2V 125 µA
Shutdown V
RUN/SS1, 2
= 0V, V
STBYMD
= Open; 20 35 µA
V
FCB
Forced Continuous Threshold ●0.76 0.800 0.84 V
I
FCB
Forced Continuous Pin Current V
FCB
= 0.85V –0.30 –0.18 –0.1 µA
V
BINHIBIT
Burst Inhibit (Constant Frequency) Measured at FCB pin 4.3 4.8 V
Threshold
UVLO Undervoltage Lockout V
IN
Ramping Down ●3.5 4 V
V
OVL
Feedback Overvoltage Lockout Measured at V
OSENSE1, 2
●0.84 0.86 0.88 V
I
SENSE
Sense Pins Total Source Current (Each Channel); V
SENSE1
–
, 2
–
= V
SENSE1
+
, 2
+
= 0V –85 –60 µA
V
STBYMD
MS
Master Shutdown Threshold V
STBYMD
Ramping Down 0.4 0.6 V
V
STBYMD
KA Keep-Alive Power On-Threshold V
STBYMD
Ramping Up, RUN
SS1, 2
= 0V 1.5 2 V
DF
MAX
Maximum Duty Factor In Dropout 98 99.4 %
I
FLTCPL
V
FLTCPL
Input Current 0.5V > V
FLTCPL
–3 µA
LTC1628 Only INTV
CC
– 0.5V < V
FLTCPL
< INTV
CC
3 µA
V
FLTCPL
Fault Coupling Threshold; For FCB Signal and Individual Overcurrent 2 V
LTC1628 Only Faults to Affect Both Controllers
I
RUN/SS1, 2
Soft-Start Charge Current V
RUN/SS1, 2
= 1.9V 0.5 1.2 µA
V
RUN/SS1, 2
ON RUN/SS Pin ON Threshold V
RUN/SS1,
V
RUN/SS2
Rising 1.0 1.5 1.9 V
V
RUN/SS1, 2
LT RUN/SS Pin Latchoff Arming Threshold V
RUN/SS1,
V
RUN/SS2
Rising from 3V 4.1 4.5 V
I
SCL1, 2
RUN/SS Discharge Current Soft Short Condition V
OSENSE1, 2
= 0.5V; 0.5 2 4 µA
V
RUN/SS1, 2
= 4.5V
I
SDLHO
Shutdown Latch Disable Current V
OSENSE1, 2
= 0.5V 1.6 5 µA
V
SENSE(MAX)
Maximum Current Sense Threshold V
OSENSE1, 2
= 0.7V,V
SENSE1
–
, 2
– = 5V ●62 75 88 mV
V
OSENSE1, 2
= 0.7V,V
SENSE1
–
, 2
– = 5V, LTC1628 Only 65 75 85 mV
TG Transition Time: (Note 5)
TG1, 2 t
r
Rise Time C
LOAD
= 3300pF 50 90 ns
TG1, 2 t
f
Fall Time C
LOAD
= 3300pF 50 90 ns
BG Transition Time: (Note 5)
BG1, 2 t
r
Rise Time C
LOAD
= 3300pF 40 90 ns
BG1, 2 t
f
Fall Time C
LOAD
= 3300pF 40 80 ns
TG/BG t
1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time C
LOAD
= 3300pF Each Driver 90 ns
BG/TG t
2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time C
LOAD
= 3300pF Each Driver 90 ns
t
ON(MIN)
Minimum On-Time Tested with a Square Wave (Note 6) 180 ns
INTV
CC
Linear Regulator
V
INTVCC
Internal V
CC
Voltage 6V < V
IN
< 30V, V
EXTVCC
= 4V 4.8 5.0 5.2 V
V
LDO
INT INTV
CC
Load Regulation I
CC
= 0 to 20mA, V
EXTVCC
= 4V 0.2 1.0 %
V
LDO
EXT EXTV
CC
Voltage Drop I
CC
= 20mA, V
EXTVCC
= 5V, LTC1628 120 240 mV
V
LDO
EXT-PG EXTV
CC
Voltage Drop I
CC
= 20mA, V
EXTVCC
= 5V, LTC1628-PG 80 160 mV
V
EXTVCC
EXTV
CC
Switchover Voltage I
CC
= 20mA, EXTV
CC
Ramping Positive ●4.5 4.7 V
V
LDOHYS
EXTV
CC
Hysteresis 0.2 V
4
LTC1628/LTC1628-PG
1628fb
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC1628G/LTC1628G-PG: T
J
= T
A
+ (P
D
• 95°C/W)
LTC1628CUH: T
J
= T
A
+ (P
D
• 34°C/W)
Note 3: The LTC1628/LTC1628-PG are tested in a feedback loop that
servos V
ITH1, 2
to a specified voltage and measures the resultant
V
OSENSE1, 2.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels.
Note 6: The minimum on-time condition is specified for an inductor
peak-to-peak ripple current ≥40% of I
MAX
(see minimum on-time
considerations in the Applications Information section).
Note 7: V
FREQSET
pin internally tied to 1.19V reference through a large
resistance.
Efficiency vs Output Current
and Mode (Figure 13)
OUTPUT CURRENT (A)
0.001
0
EFFICIENCY (%)
10
30
40
50
100
70
0.01 0.1 1
1628 G01
20
80
90
60
10
FORCED
CONTINUOUS
MODE
CONSTANT
FREQUENCY
(BURST DISABLE)
Burst Mode
OPERATION
V
IN
= 15V
V
OUT
= 5V
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
70
80
10
1628 G02
60
50 0.01 0.1 1
100
90
V
IN
= 10V
V
IN
= 15V
V
IN
= 7V
V
IN
= 20V
V
IN
= 15V
V
OUT
= 5V
INPUT VOLTAGE (V)
5
EFFICIENCY (%)
70
80
1628 G03
60
50 15 25 35
100 V
OUT
= 5V
I
OUT
= 3A
90
Efficiency vs Output Current
(Figure 13) Efficiency vs Input Voltage
(Figure 13)
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator
f
OSC
Oscillator frequency V
FREQSET
= Open (Note 7) 190 220 250 kHz
f
LOW
Lowest Frequency V
FREQSET
= 0V 120 140 160 kHz
f
HIGH
Highest Frequency V
FREQSET
= 2.4V 280 310 360 kHz
I
FREQSET
FREQSET
Input Current V
FREQSET
= 0V –2 –1 µA
3.3V Linear Regulator
V
3.3OUT
3.3V Regulator Output Voltage No Load ●3.25 3.35 3.45 V
V
3.3IL
3.3V Regulator Load Regulation I
3.3
= 0 to 10mA 0.5 2 %
V
3.3VL
3.3V Regulator Line Regulation 6V < V
IN
< 30V 0.05 0.2 %
PGOOD Output (LTC1628-PG Only)
V
PGL
PGOOD Voltage Low I
PGOOD
= 2mA 0.1 0.3 V
I
PGOOD
PGOOD Leakage Current V
PGOOD
= 5V ±1µA
V
PG
PGOOD Trip Level, Either Controller V
OSENSE
Respect to Set Output Voltage
V
OSENSE
Ramping Negative –6 –7.5 –9.5 %
V
OSENSE
Ramping Positive 6 7.5 9.5 %
5
LTC1628/LTC1628-PG
1628fb
Internal 5V LDO Line Reg Maximum Current Sense Threshold
vs Duty Factor
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
INPUT VOLTAGE (V)
0
4.8
4.9
5.1
15 25
1628 G07
4.7
4.6
510 20 30 35
4.5
4.4
5.0
INTV
CC
VOLTAGE (V)
I
LOAD
= 1mA
DUTY FACTOR (%)
0
0
V
SENSE
(mV)
25
50
75
20 40 60 80
1628 G08
100
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
0
V
SENSE
(mV)
40
50
60
100
1628 G09
30
20
025 50 75
10
80
70
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start)
V
RUN/SS
(V)
0
0
V
SENSE
(mV)
20
40
60
80
1234
1628 G10
56
V
SENSE(CM)
= 1.6V
Maximum Current Sense Threshold
vs Sense Common Mode Voltage
COMMON MODE VOLTAGE (V)
0
V
SENSE
(mV)
72
76
80
4
1628 G11
68
64
60 1235
Current Sense Threshold
vs ITH Voltage
V
ITH
(V)
0
V
SENSE
(mV)
30
50
70
90
2
1628 G12
10
–10
20
40
60
80
0
–20
–30 0.5 11.5 2.5
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INTVCC and EXTVCC Switch
Voltage vs Temperature
Supply Current vs Input Voltage
and Mode (Figure 13)
INPUT VOLTAGE (V)
05
0
SUPPLY CURRENT (µA)
400
1000
10 20 25
1628 G04
200
800
600
15 30 35
BOTH
CONTROLLERS ON
STANDBY
SHUTDOWN
EXTVCC Voltage Drop
CURRENT (mA)
0
EXTV
CC
VOLTAGE DROP (mV)
150
200
250
40
1628 G05
100
50
010 20 30 50
TEMPERATURE (°C)
–50
INTV
CC
AND EXTV
CC
SWITCH VOLTAGE (V)
4.95
5.00
5.05
25 75
1628 G06
4.90
4.85
–25 0 50 100 125
4.80
4.70
4.75
INTV
CC
VOLTAGE
EXTV
CC
SWITCHOVER THRESHOLD
6
LTC1628/LTC1628-PG
1628fb
TEMPERATURE (°C)
–50 –25
70
V
SENSE
(mV)
74
80
050 75
1628 G17
72
78
76
25 100 125
OUTPUT CURRENT (A)
0
0
DROPOUT VOLTAGE (V)
1
2
3
4
0.5 1.0 1.5 2.0
1628 G18
2.5 3.0 3.5 4.0
R
SENSE
= 0.015Ω
R
SENSE
= 0.010Ω
V
OUT
= 5V
Maximum Current Sense
Threshold vs Temperature Dropout Voltage vs Output Current
(Figure 13)
Soft-Start Up (Figure 13)
V
OUT
5V/DIV
V
RUN/SS
5V/DIV
I
OUT
2A/DIV
V
IN
= 15V 5ms/DIV 1628 G19
V
OUT
= 5V
Load Step (Figure 13)
V
OUT
200mV/DIV
I
OUT
2A/DIV
V
IN
= 15V 20µs/DIV 1628 G20
V
OUT
= 5V
LOAD STEP = 0A TO 3A
Burst Mode OPERATION
Load Step (Figure 13)
V
OUT
200mV/DIV
I
OUT
2A/DIV
V
IN
= 15V 20µs/DIV 1628 G21
V
OUT
= 5V
LOAD STEP = 0A TO 3A
CONTINUOUS MODE
RUN/SS Current vs Temperature
TEMPERATURE (°C)
–50 –25
0
RUN/SS CURRENT (µA)
0.2
0.6
0.8
1.0
75 10050
1.8
1628 G25
0.4
0 25 125
1.2
1.4
1.6
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Load Regulation
LOAD CURRENT (A)
0
NORMALIZED V
OUT
(%)
–0.2
–0.1
4
1628 G13
–0.3
–0.4 1235
0.0 FCB = 0V
V
IN
= 15V
FIGURE 1
VITH vs VRUN/SS
V
RUN/SS
(V)
0
0
V
ITH
(V)
0.5
1.0
1.5
2.0
2.5
1234
1628 G14
56
V
OSENSE
= 0.7V
SENSE Pins Total Source Current
V
SENSE
COMMON MODE VOLTAGE (V)
0
I
SENSE
(µA)
0
1628 G15
–50
–100 24
50
100
6
7
LTC1628/LTC1628-PG
1628fb
Current Sense Pin Input Current
vs Temperature EXTVCC Switch Resistance
vs Temperature
TEMPERATURE (°C)
–50 –25
25
CURRENT SENSE INPUT CURRENT (µA)
29
35
050 75
1628 G26
27
33
31
25 100 125
V
OUT
= 5V
TEMPERATURE (°C)
–50 –25
0
EXTV
CC
SWITCH RESISTANCE (Ω)
4
10
050 75
1628 G27
2
8
6
25 100 125
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–50
200
250
350
25 75
1628 G28
150
100
–25 0 50 100 125
50
0
300
FREQUENCY (kHz)
V
FREQSET
= 5V
V
FREQSET
= OPEN
V
FREQSET
= 0V
Undervoltage Lockout
vs Temperature
TEMPERATURE (°C)
–50
UNDERVOLTAGE LOCKOUT (V)
3.40
3.45
3.50
25 75
1628 G29
3.35
3.30
–25 0 50 100 125
3.25
3.20
Shutdown Latch Thresholds
vs Temperature
TEMPERATURE (°C)
–50 –25
0
SHUTDOWN LATCH THRESHOLDS (V)
0.5
1.5
2.0
2.5
75 10050
4.5
1628 G30
1.0
0 25 125
3.0
3.5
4.0 LATCH ARMING
LATCHOFF
THRESHOLD
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Input Source/Capacitor
Instantaneous Current (Figure 13)
I
IN
2A/DIV
V
IN
200mV/DIV
V
SW1
10V/DIV
V
IN
= 15V 1µs/DIV 1628 G22
V
OUT
= 5V
I
OUT5
= I
OUT3.3
= 2A
Burst Mode Operation (Figure 13)
V
OUT
20mV/DIV
I
OUT
0.5A/DIV
V
IN
= 15V 10µs/DIV 1628 G23
V
OUT
= 5V
V
FCB
= OPEN
I
OUT
= 20mA
Constant Frequency (Burst Inhibit)
Operation (Figure 13)
V
OUT
20mV/DIV
I
OUT
0.5A/DIV
V
IN
= 15V 2µs/DIV 1628 G24
V
OUT
= 5V
V
FCB
= 5V
I
OUT
= 20mA
V
SW2
10V/DIV
8
LTC1628/LTC1628-PG
1628fb
RUN/SS1, RUN/SS2: Combination of soft-start, run con-
trol inputs and short-circuit detection timers. A capacitor
to ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below
1.0V causes the IC to shut down the circuitry required for
that particular controller. Latchoff overcurrent protection
is also invoked via this pin as described in the Applications
Information section.
SENSE1
+
, SENSE2
+
: The (+) Input to the Differential
Current Comparators. The I
th
pin voltage and controlled
offsets between the SENSE
–
and SENSE
+
pins in conjunc-
tion with R
SENSE
set the current trip threshold.
SENSE1
–
, SENSE2
–
: The (–) Input to the Differential
Current Comparators.
V
OSENSE1
, V
OSENSE2
: Receives the remotely-sensed feed-
back voltage for each controller from an external resistive
divider across the output.
FREQSET: Frequency Control Input to the Oscillator. This
pin can be left open, tied to ground, tied to INTV
CC
or driven
by an external voltage source. This pin can also be used
with an external phase detector to build a true phase-
locked loop.
STBYMD: Control pin that determines which circuitry re-
mains active when the controllers are shut down and/or
provides a common control point to shut down both con-
trollers. See the Operation section for details.
FCB: Forced Continuous Control Input. This input acts on
the first controller (or both controllers depending upon
the FLTCPL pin—see pin description), and is
normally used to regulate a secondary winding. Pulling
this pin below 0.8V will force continuous synchronous
operation for the first and optionally the second control-
ler. Do not leave this pin floating.
I
TH1,
I
TH2
: Error Amplifier Output and Switching Regulator
Compensation Point. Each associated channels’ current
comparator trip point increases with this control voltage.
SGND: Small Signal Ground common to both con-
trollers, must be routed separately from high current
grounds to the common (–) terminals of the C
OUT
capacitors.
3.3V
OUT
: Output of a linear regulator capable of supplying
10mA DC with peak currents as high as 50mA.
PGND: Driver Power Ground. Connects to the sources of
bottom (synchronous) N-channel MOSFETs, anodes of the
Schottky rectifiers and the (–) terminal(s) of C
IN
.
INTV
CC
: Output of the Internal 5V Linear Low Dropout
Regulator and the EXTV
CC
Switch. The driver and control
circuits are powered from this voltage source. Must be
decoupled to power ground with a minimum of 4.7µF tanta-
lum or other low ESR capacitor. The INTV
CC
regulator
standby function is determined by the STBYMD pin.
EXTV
CC
: External Power Input to an Internal Switch Con-
nected to INTV
CC
. This switch closes and supplies V
CC
power, bypassing the internal
low dropout regulator, when-
ever EXTV
CC
is higher than 4.7V. See EXTV
CC
connection
in Applications section. Do not exceed 7V on this pin.
BG1, BG2: High Current Gate Drives for Bottom (Synchro-
nous) N-Channel MOSFETs. Voltage swing at these pins is
from ground to INTV
CC
.
V
IN
: Main Supply Pin. A bypass capacitor should be tied
between this pin and the signal ground pin.
BOOST1, BOOST2: Bootstrapped Supplies to the Top Side
Floating Drivers. Capacitors are connected between the
boost and switch pins and Schottky diodes are tied be-
tween the boost and INTV
CC
pins. Voltage swing at the
boost pins is from INTV
CC
to (V
IN
+ INTV
CC
).
SW1, SW2: Switch Node Connections to Inductors. Volt-
age swing at these pins is from a Schottky diode (external)
voltage drop below ground to V
IN
.
TG1, TG2: High Current Gate Drives for Top N-Channel
MOSFETs. These are the outputs of floating drivers with a
voltage swing equal to INTV
CC
– 0.5V superimposed on
the switch node voltage SW.
FLTCPL: (LTC1628 Only) Fault Coupling Control Pin that
determines if fault/normal conditions on one controller
will act on the other controller. FLTCPL = INTV
CC
to couple
channels; FLTCPL = 0V to decouple.
UU
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PI FU CTIO S
9
LTC1628/LTC1628-PG
1628fb
Figure 2
SWITCH
LOGIC
–
+
0.8V
4.8V
5V
VIN
VIN
4.5V BINH
RUN/SS2
RUN/SS1
CLK2
CLK1
0.18µA
R6
R5
+
–
FCB
+
–
–
+
–
+
–
+
VREF
MERGE LOGIC
INTERNAL
SUPPLY
3.3VOUT
VSEC 3V
FCB
FLTCPL
EXTVCC
INTVCC
SGND
STBYMD
+
5V
LDO
REG
SW
SHDN
0.55V
TOP
BOOST
TG CB
CIN
D1
DB
PGND
BOT BG
INTVCC
INTVCC
VIN
+
CSEC
C
OUT
V
OUT
1628 FD/F02
DSEC
RSENSE
R2
+
VOSENSE
DROP
OUT
DET
RUN
SOFT
START
BOT
TOP ON
S
R
Q
Q
OSCILLATOR
FREQSET
FCB
EA
0.86V
0.80V
OV
VFB
1.2µA
6V
R1
–
+
RC
4(V
FB
)
RST
SHDN
RUN/SS
ITH CC
CC2
CSS
1.19V
1M
+
4(VFB)
0.86V
SLOPE
COMP
3mV
+
–
–
+
SENSE–
SENSE+
INTVCC
30k
45k
2.4V
45k
30k
I1 I2
B
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
+– –+
UU
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PI FU CTIO S
FU CTIO AL DIAGRA
UU
W
PGOOD: (LTC1628-PG Only) Open-Drain Logic Output.
PGOOD is pulled to ground when the voltage on either
V
OSENSE
pin is not within ±7.5% of its set point.
NC: These “No Connect” pins are not tied internally to
anything. On the PC layout, these pin landings should be
connected to the SGND plane under the IC.
10
LTC1628/LTC1628-PG
1628fb
(Refer to Functional Diagram)
Main Control Loop
The LTC1628 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal opera-
tion, each top MOSFET is turned on when the clock for that
channel sets the RS latch, and turned off when the main
current comparator, I
1
, resets the RS latch. The peak
inductor current at which I
1
resets the RS latch is con-
trolled by the voltage on the I
TH
pin, which is the output of
each error amplifier EA. The V
OSENSE
pin receives the
voltage feedback signal, which is compared to the internal
reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in V
OSENSE
relative to
the 0.8V reference, which in turn causes the I
TH
voltage to
increase until the average inductor current matches the
new load current. After the top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I
2
, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor C
B
, which normally is recharged during
each off cycle through an external diode when the top
MOSFET turns off. As V
IN
decreases to a voltage close to
V
OUT
, the loop may enter dropout and attempt to turn on
the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 500ns
every tenth cycle to allow C
B
to recharge.
The main control loop is shut down by pulling the RUN/SS
pin low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches 1.5V, the main control loop is enabled with the
I
TH
voltage clamped at approximately 30% of its maximum
value. As C
SS
continues to charge, the I
TH
pin voltage is
gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all
LTC1628 controller functions are shut down, and the
STBYMD pin determines if the standby 5V and 3.3V
regulators are kept alive.
Low Current Operation
The FCB pin is a multifunction pin providing two func-
tions: 1) to provide regulation for a secondary winding by
temporarily forcing continuous PWM operation on
controller 1 (or both controllers depending upon the
FLTCPL pin); and 2) select between
two
modes of low
current operation. When the FCB pin voltage is below
0.800V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB pin is below V
INTVCC
␣ –␣ 2V but greater than
0.80V, the controller enters Burst Mode operation. Burst
Mode operation sets a minimum output current level
before inhibiting the top switch and turns off the synchro-
nous MOSFET(s) when the inductor current goes nega-
tive. This combination of requirements will, at low cur-
rents, force the I
TH
pin below a voltage threshold that will
temporarily inhibit turn-on of both output MOSFETs until
the output voltage drops. There is 60mV of hysteresis in
the burst comparator B tied to the I
TH
pin. This hysteresis
produces output signals to the MOSFETs that turn them
on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
output voltage ripple is held to a very small value by
having the hysteretic comparator after the error amplifier
gain block.
Constant Frequency Operation
When the FCB pin is tied to INTV
CC
, Burst Mode operation
is disabled and the forced minimum output current re-
quirement is removed. This provides constant frequency,
discontinuous (preventing reverse inductor current) cur-
rent operation over the widest possible output current
range. This constant frequency operation is not as efficient
as Burst Mode operation, but does provide a lower noise,
constant frequency operating mode down to approxi-
mately 1% of designed maximum output current.
Continuous Current (PWM) Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, current will be
forced back into the main power supply potentially boost-
ing the input supply to dangerous voltage levels—
BEWARE!
OPERATIO
U
11
LTC1628/LTC1628-PG
1628fb
Frequency Setting
The FREQSET pin provides frequency adjustment of the
internal oscillator from approximately 140kHz to 310kHz.
This input is nominally biased through an internal resistor
to the 1.19V reference, setting the oscillator frequency to
approximately 220kHz. This pin can be driven from an
external AC or DC signal source to control the instanta-
neous frequency of the oscillator.
INTV
CC
/EXTV
CC
Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTV
CC
pin.
When the EXTV
CC
pin is left open, an internal 5V low
dropout linear regulator supplies INTV
CC
power. If EXTV
CC
is taken above 4.7V, the 5V regulator is turned off and an
internal switch is turned on connecting EXTV
CC
to INTV
CC
.
This allows the INTV
CC
power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information.
Standby Mode Pin
The STBYMD pin is a three-state input that controls
common circuitry within the IC as follows: When the
STBYMD pin is held at ground, both controller RUN/SS
pins are pulled to ground providing a single control pin to
shut down both controllers. When the pin is left open, the
internal RUN/SS currents are enabled to charge the
RUN/SS capacitor(s), allowing the turn-on of either con-
troller and activating necessary common internal biasing.
When the STBYMD pin is taken above 2V, both internal
linear regulators are turned on independent of the state on
the RUN/SS pins of the two switching regulator control-
lers, providing an output power source for “wake-up”
circuitry. Decouple the pin with a small capacitor (0.01µF)
to ground if the pin is not connected to a DC potential.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi-
tions that may overvoltage the output. In this case, the top
MOSFET is turned off and the bottom MOSFET is turned on
until the overvoltage condition is cleared.
Fault Coupling Pin
The FLTCPL pin (LTC1628 only) controls two functions
that can operate individually (FLTCPL = 0V) or unilaterally
(FLTCPL = INTV
CC
) between the two controllers. When the
FLTCPL pin is grounded (internally tied default mode for
the LTC1628-PG), 1) the FCB input forces continuous
operation only on the first controller when the applied
voltage drops below 0.8V and 2) the short-circuit latchoff
function only latches off the controller having the shorted
output. When the FLTCPL pin is tied to INTV
CC
, 1) the FCB
input forces continuous operation on
both
controllers
when the applied voltage drops below 0.8V and 2) the
short-circuit latchoff function latches off
both
controllers
when either has a shorted output.
Power Good (PGOOD) Pin
The PGOOD pin (LTC1628-PG only) is connected to an
open drain of an internal MOSFET. The MOSFET turns on
and pulls the pin low when both the outputs are not within
±7.5% of their nominal output levels as determined by
their resistive feedback dividers. When both outputs meet
the ±7.5% requirement, the MOSFET is turned off within
10µs and the pin is allowed to be pulled up by an external
resistor to a source of up to 7V.
Foldback Current, Short-Circuit Detection
and Short-Circuit Latchoff
The RUN/SS capacitors are used initially to limit the inrush
current of each switching regulator. After the controller
has been started and been given adequate time to charge
up the output capacitors and provide full load current, the
RUN/SS capacitor is used in a short-circuit time-out
circuit. If the output voltage falls to less than 70% of its
nominal output voltage, the RUN/SS capacitor begins
discharging on the assumption that the output is in an
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period as determined by the size of
the RUN/SS capacitor, the controller (or both controllers
as determined by the FLTCPL pin, LTC1628 only) will be
shut down until the RUN/SS pin(s) voltage(s) are recycled.
This built-in latchoff can be overridden by providing a
>5µA pull-up at a compliance of 5V to the RUN/SS pin(s).
This current shortens the soft start period but also pre-
vents net discharge of the RUN/SS capacitor(s) during an
(Refer to Functional Diagram)
OPERATIO
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12
LTC1628/LTC1628-PG
1628fb
overcurrent and/or short-circuit condition. Foldback cur-
rent limiting is also activated when the output voltage falls
below 70% of its nominal level whether or not the short-
circuit latchoff circuit is enabled. Even if a short is present
and the short-circuit latchoff is not enabled, a safe, low
output current is provided due to internal current foldback
and actual power wasted is low due to the efficient nature
of the current mode switching regulator.
THEORY AND BENEFITS OF 2-PHASE OPERATION
The LTC1628 dual high efficiency DC/DC controller brings
the considerable benefits of 2-phase operation to portable
applications for the first time. Notebook computers, PDAs,
handheld terminals and automotive electronics will all
benefit from the lower input filtering requirement, reduced
electromagnetic interference (EMI) and increased effi-
ciency associated with 2-phase operation.
Why the need for 2-phase operation? Up until the LTC1628,
constant-frequency dual switching regulators operated
both channels in phase (i.e., single-phase operation). This
means that both switches turned on at the same time,
causing current pulses of up to twice the amplitude of
those for one regulator to be drawn from the input capaci-
tor and battery. These large amplitude current pulses
increased the total RMS current flowing from the input
capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
With 2-phase operation, the two channels of the dual-
switching regulator are operated 180 degrees out of
phase. This effectively interleaves the current pulses drawn
by the switches, greatly reducing the overlap time where
they add together.
The result is a significant reduction in
total RMS input current, which in turn allows less expen-
sive input capacitors to be used, reduces shielding re-
quirements for EMI and improves real world operating
efficiency.
Figure 3 compares the input waveforms for a representa-
tive single-phase dual switching regulator to the new
LTC1628 2-phase dual switching regulator. An actual
measurement of the RMS input current under these con-
ditions shows that 2-phase operation dropped the input
current from 2.53A
RMS
to 1.55A
RMS
. While this is an
impressive reduction in itself, remember that the power
losses are proportional to I
RMS2
, meaning that the actual
power wasted is reduced by a factor of 2.66. The reduced
input ripple voltage also means less power is lost in the
input power path, which could include batteries, switches,
trace/connector resistances and protection circuitry. Im-
provements in both conducted and radiated EMI also
directly accrue as a result of the reduced RMS input
current and voltage.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulator’s relative
duty cycles which, in turn, are dependent upon the input
voltage V
IN
(Duty Cycle = V
OUT
/V
IN
). Figure 4 shows how
(b)
(a)
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
I
IN(MEAS)
= 1.55A
RMS
DC236 F03b
I
IN(MEAS)
= 2.53A
RMS
DC236 F03a
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation
for Dual Switching Regulators Converting 12V to 5V and 3.3V at 3A Each. The
Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows Less Expensive
Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
(Refer to Functional Diagram)
OPERATIO
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13
LTC1628/LTC1628-PG
1628fb
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase
operation are not just limited to a narrow operating range,
but in fact extend over a wide region. A good rule of thumb
for most applications is that 2-phase operation will reduce
Figure 4. RMS Input Current Comparison
Figure 1 on the first page is a basic LTC1628 application
circuit. External component selection is driven by the
load requirement, and begins with the selection of R
SENSE
and the inductor value. Next, the power MOSFETs and D1
are selected. Finally, C
IN
and C
OUT
are selected. The
circuit shown in Figure 1 can be configured for operation
up to an input voltage of 28V (limited by the external
MOSFETs).
R
SENSE
Selection For Output Current
R
SENSE
is chosen based on the required output current.
The LTC1628 current comparator has a maximum thresh-
old of 75mV/R
SENSE
and an input common mode range of
SGND to 1.1(INTV
CC
). The current comparator threshold
sets the peak of the inductor current, yielding a maximum
average output current I
MAX
equal to the peak value less
half the peak-to-peak ripple current, ∆I
L
.
Allowing a margin for variations in the LTC1628 and
external component values yields:
RmV
I
SENSE MAX
=50
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
the internal compensation required to meet stability crite-
rion for buck regulators operating at greater than 50%
duty factor. A curve is provided to estimate this reducton
in peak output current level depending upon the operating
duty factor.
Selection of Operating Frequency
The LTC1628 uses a constant frequency architecture with
the frequency determined by an internal oscillator capaci-
tor. This internal capacitor is charged by a fixed current
plus an additional current that is proportional to the
voltage applied to the FREQSET pin.
A graph for the voltage applied to the FREQSET pin vs
frequency is given in Figure 5. As the operating frequency
INPUT VOLTAGE (V)
0
INPUT RMS CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
010 20 30 40
1628 F04
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
VO1 = 5V/3A
VO2 = 3.3V/3A
the input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
A final question: If 2-phase operation offers such an
advantage over single-phase operation for dual switching
regulators, why hasn’t it been done before? The answer is
that, while simple in concept, it is hard to implement.
Constant-frequency current mode switching regulators
require an oscillator derived “slope compensation” signal
to allow stable operation of each regulator at over 50%
duty cycle. This signal is relatively easy to derive in single-
phase dual switching regulators, but required the develop-
ment of a new and proprietary technique to allow 2-phase
operation. In addition, isolation between the two channels
becomes more critical with 2-phase operation because
switch transitions in one channel could potentially disrupt
the operation of the other channel.
The LTC1628 is proof that these hurdles have been sur-
mounted. The new device offers unique advantages for the
ever-expanding number of high efficiency power supplies
required in portable electronics.
(Refer to Functional Diagram)
OPERATIO
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14
LTC1628/LTC1628-PG
1628fb
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 310kHz.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge losses. In addition to this basic
trade-off, the effect of inductor value on ripple current and
low current operation must also be considered.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆I
L
decreases with higher induc-
tance or frequency and increases with higher V
IN
:
∆IfLVV
V
L OUT OUT
IN
=
11
()() –
Accepting larger values of ∆I
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I
L
=0.3(I
MAX
). Remember, the
maximum ∆I
L
occurs at the maximum input voltage.
The inductor value also has secondary effects. The transi-
tion to Burst Mode operation begins when the average
inductor current required results in a peak current below
25% of the current limit determined by R
SENSE
. Lower
inductor values (higher ∆I
L
) will cause this to occur at
lower load currents, which can cause a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to decrease.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy, or Kool Mµ
®
cores. Actual core loss is
independent of core size for a fixed inductor value, but it
is very dependent on inductance selected. As inductance
increases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they generally lack a bobbin, mounting is more
difficult. However, designs for surface mount are available
that do not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for each
controller with the LTC1628: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
voltage. This voltage is typically 5V during start-up (see
Kool Mµ is a registered trademark of Magnetics, Inc.
Figure 5. FREQSET Pin Voltage vs Frequency
OPERATING FREQUENCY (kHz)
120 170 220 270 320
FREQSET PIN VOLTAGE (V)
1628 F05
2.5
2.0
1.5
1.0
0.5
0
APPLICATIO S I FOR ATIO
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LTC1628/LTC1628-PG
1628fb
EXTV
CC
Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected
(V
IN
< 5V); then, sub-logic level threshold MOSFETs
(V
GS(TH)
< 3V) should be used. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; most of the
logic level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage and maximum output current. When the
LTC1628 is operating in continuous mode the duty cycles
for the top and bottom MOSFETs are given by:
Main SwitchDuty Cycle V
V
OUT
IN
=
Synchronous SwitchDuty Cycle VV
V
IN OUT
IN
=–
The MOSFET power dissipations at maximum output
current are given by:
PV
VIR
kV I C f
MAIN OUT
IN MAX DS ON
IN MAX RSS
=
()
+
()
+
()( )( )()
2
2
1
δ
()
PVV
VIR
SYNC IN OUT
IN MAX DS ON
=
()
+
()
–
()
2
1
δ
where δ is the temperature dependency of R
DS(ON)
and k
is a constant inversely related to the gate drive current.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V
IN
< 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
RSS
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1+δ) is generally given for a MOSFET in the form
of a normalized R
DS(ON)
vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs. C
RSS
is usually specified in the MOS-
FET characteristics. The constant k = 1.7 can be used to
estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
MOSFET from turning on, storing charge during the dead-
time and requiring a reverse recovery period that could
cost as much as 3% in efficiency at high V
IN
. A 1A to 3A
Schottky is generally a good compromise for both regions
of operation due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
C
IN
and C
OUT
Selection
The selection of C
IN
is simplified by the multiphase archi-
tecture and its impact on the worst-case RMS current
drawn through the input network (battery/fuse/capacitor).
It can be shown that the worst case RMS current occurs
when only one controller is operating. The controller with
the highest (V
OUT
)(I
OUT
) product needs to be used in the
formula below to determine the maximum RMS current
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease
the input RMS ripple current from this maximum value
(see Figure 4). The out-of-phase technique typically re-
duces the input capacitor’s RMS ripple current by a factor
of 30% to 70% when compared to a single phase power
supply solution.
The type of input capacitor, value and ESR rating have
efficiency effects that need to be considered in the selec-
tion process. The capacitance value chosen should be
sufficient to store adequate charge to keep high peak
battery currents down. 20µF to 40µF is usually sufficient
for a 25W output supply operating at 200kHz. The ESR of
the capacitor is important for capacitor power dissipation
as well as overall battery efficiency. All of the power (RMS
ripple current • ESR) not only heats up the capacitor but
wastes power from the battery.
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Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
and switcher-rated electrolytic capacitors can be used as
input capacitors, but each has drawbacks: ceramic voltage
coefficients are very high and may have audible piezoelec-
tric effects; tantalums need to be surge-rated; OS-CONs
suffer from higher inductance, larger case size and limited
surface-mount applicability; electrolytics’ higher ESR and
dryout possibility require several to be used. Multiphase
systems allow the lowest amount of capacitance overall.
As little as one 22µF or two to three 10µF ceramic capaci-
tors are an ideal choice in a 20W to 35W power supply due
to their extremely low ESR. Even though the capacitance
at 20V is substantially below their rating at zero-bias, very
low ESR loss makes ceramics an ideal candidate for
highest efficiency battery operated systems. Also con-
sider parallel ceramic and high quality electrolytic capaci-
tors as an effective means of achieving ESR and bulk
capacitance goals.
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current of one channel must
be used. The maximum RMS capacitor current is given by:
C quiredI I VVV
V
IN RMS MAX OUT IN OUT
IN
Re
/
≈−
()
[]
12
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT
/2. This simple worst case condition is com-
monly used for design because even significant deviations
do not offer much relief. Note that capacitor manufacturer’s
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may also be
paralleled to meet size or height requirements in the
design. Always consult the manufacturer if there is any
question.
The benefit of the LTC1628 multiphase can be calculated
by using the equation above for the higher power control-
ler and then calculating the loss that would have resulted
if both controller channels switch on at the same time. The
total RMS power lost is lower when both controllers are
operating due to the interleaving of current pulses through
the input capacitor’s ESR. This is why the input capacitor’s
requirement calculated above for the worst-case control-
ler is adequate for the dual controller design. Remember
that input protection fuse resistance, battery resistance
and PC board trace resistance losses are also reduced due
to the reduced peak currents in a multiphase system.
The
overall benefit of a multiphase design will only be fully
realized when the source impedance of the power supply/
battery is included in the efficiency testing.
The drains of
the two top MOSFETS should be placed within 1cm of each
other and share a common C
IN
(s). Separating the drains
and C
IN
may produce undesirable voltage and current
resonances at V
IN
.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment is satisfied the capacitance is adequate for filtering.
The output ripple (∆V
OUT
) is determined by:
∆∆V I ESR fC
OUT L OUT
≈+
1
8
Where f = operating frequency, C
OUT
= output capacitance,
and ∆I
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ∆I
L
increases
with input voltage. With ∆I
L
= 0.3I
OUT(MAX)
the output
ripple will typically be less than 50mV at max V
IN
assum-
ing:
C
OUT
Recommended ESR < 2 R
SENSE
and C
OUT
> 1/(8fR
SENSE
)
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran-
tees that the output capacitance does not significantly
discharge during the operating frequency period due to
ripple current. The choice of using smaller output capaci-
tance increases the ripple voltage due to the discharging
term but can be compensated for by using capacitors of
very low ESR to maintain the ripple voltage at or below
50mV. The I
TH
pin OPTI-LOOP compensation compo-
nents can be optimized to provide stable, high perfor-
mance transient response regardless of the output capaci-
tors selected.
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Manufacturers such as Nichicon, United Chemicon and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications multiple capacitors may
need to be used in parallel to meet the ESR, RMS current
handling and load step requirements of the application.
Aluminum electrolytic, dry tantalum and special polymer
capacitors are available in surface mount packages. Spe-
cial polymer surface mount capacitors offer very low ESR
but have lower storage capacity per unit volume than other
capacitor types. These capacitors offer a very cost-effec-
tive output capacitor solution and are an ideal choice when
combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
and are often used as output capacitors for switching
regulators having controlled soft-start. Several excellent
surge-tested choices are the AVX TPS, AVX TPSV or the
KEMET T510 series of surface mount tantalums, available
in case heights ranging from 2mm to 4mm. Aluminum
electrolytic capacitors can be used in cost-driven applica-
tions providing that consideration is given to ripple current
ratings, temperature and long term reliability. A typical
application will require several to many aluminum electro-
lytic capacitors in parallel. A combination of the above
mentioned capacitors will often result in maximizing per-
formance and minimizing overall cost. Other capacitor
types include Nichicon PL series, NEC Neocap, Pansonic
SP and Sprague 595D series. Consult manufacturers for
other specific recommendations.
INTV
CC
Regulator
An internal P-channel low dropout regulator produces 5V
at the INTVCC pin from the VIN supply pin. INTVCC powers
the drivers and internal circuitry within the LTC1628. The
INTVCC pin regulator can supply a peak current of 50mA
and must be bypassed to ground with a minimum of
4.7µF tantalum, 10µF special polymer, or low ESR type
electrolytic capacitor. A 1µF ceramic capacitor placed
directly adjacent to the INTVCC and PGND IC pins is highly
recommended. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
drivers and to prevent interaction between channels.
Higher input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the maxi-
mum junction temperature rating for the LTC1628 to be
exceeded. The system supply current is normally domi-
nated by the gate charge current. Additional external
loading of the INTV
CC
and 3.3V linear regulators also
needs to be taken into account for the power dissipation
calculations. The total INTV
CC
current can be supplied by
either the 5V internal linear regulator or by the EXTV
CC
input pin. When the voltage applied to the EXTV
CC
pin is
less than 4.7V, all of the INTV
CC
current is supplied by the
internal 5V linear regulator. Power dissipation for the IC in
this case is highest: (V
IN
)(I
INTVCC
), and overall efficiency
is lowered. The gate charge current is dependent on
operating frequency as discussed in the Efficiency Consid-
erations section. The junction temperature can be esti-
mated by using the equations given in Note 2 of the
Electrical Characteristics. For example, the LTC1628 V
IN
current is limited to less than 24mA from a 24V supply
when not using the EXTV
CC
pin as follows:
T
J
= 70°C + (24mA)(24V)(95°C/W) = 125°C
Use of the EXTV
CC
input pin reduces the junction tempera-
ture to:
T
J
= 70°C + (24mA)(5V)(95°C/W) = 81°C
Dissipation should be calculated to also include any added
current drawn from the internal 3.3V linear regulator. To
prevent maximum junction temperature from being ex-
ceeded, the input supply current must be checked operat-
ing in continuous mode at maximum V
IN
.
EXTV
CC
Connection
The LTC1628 contains an internal P-channel MOSFET
switch connected between the EXTV
CC
and INTV
CC
pins.
When the voltage applied to EXTV
CC
rises above
4.7V, the
internal regulator is turned off and the switch closes,
connecting the EXTV
CC
pin to the INTV
CC
pin thereby
supplying internal power. The switch remains closed as
long as the voltage applied to EXTV
CC
remains above 4.5V.
This allows the MOSFET driver and control power to be
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derived from the output during normal operation (4.7V <
V
OUT
< 7V) and from the internal regulator when the output
is out of regulation (start-up, short-circuit). If more cur-
rent is required through the EXTV
CC
switch than is speci-
fied, an external Schottky diode can be added between the
EXTV
CC
and INTV
CC
pins. Do not apply greater than 7V to
the EXTV
CC
pin and ensure that EXTV
CC␣
<␣ V
IN
.
Significant efficiency gains can be realized by powering
INTV
CC
from the output, since the V
IN
current resulting
from the driver and control currents will be scaled by a
factor of (Duty Cycle)/(Efficiency). For 5V regulators this
supply means connecting the EXTV
CC
pin directly to V
OUT
.
However, for 3.3V and other lower voltage regulators,
additional circuitry is required to derive INTV
CC
power
from the output.
The following list summarizes the four possible connec-
tions for EXTV
CC:
1. EXTV
CC
Left Open (or Grounded). This will cause INTV
CC
to be powered from the internal 5V regulator resulting in
an efficiency penalty of up to 10% at high input voltages.
2. EXTV
CC
Connected directly to V
OUT
. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTV
CC
Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
power EXTV
CC
providing it is compatible with the MOSFET
gate drive requirements.
Figure 6a. Secondary Output Loop & EXTVCC Connection Figure 6b. Capacitive Charge Pump for EXTVCC
4. EXTV
CC
Connected to an Output-Derived Boost Net-
work. For 3.3V and other low voltage regulators, efficiency
gains can still be realized by connecting EXTV
CC
to an
output-derived voltage that has been boosted to greater
than 4.7V. This can be done with either the inductive boost
winding as shown in Figure 6a or the capacitive charge
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.
Topside MOSFET Driver Supply (C
B
, D
B
)
External bootstrap capacitors C
B
connected to the BOOST
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor C
B
in the functional diagram is charged though
external diode D
B
from INTV
CC
when the SW pin is low.
When one of the topside MOSFETs is to be turned on, the
driver places the C
B
voltage across the gate-source of the
desired MOSFET. This enhances the MOSFET and turns on
the topside switch. The switch node voltage, SW, rises to
V
IN
and the BOOST pin follows. With the topside MOSFET
on, the boost voltage is above the input supply: V
BOOST
=
V
IN
+ V
INTVCC
. The value of the boost capacitor C
B
needs
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter-
nal Schottky diode must be greater than V
IN(MAX)
. When
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the
input current decreases, then the efficiency has improved.
If there is no change in input current, then there is no
change in efficiency.
EXTV
CC
FCB
SGND
V
IN
TG1
SW
BG1
PGND
LTC1628
R
SENSE
V
OUT
V
SEC
+
C
OUT
+
1µF
1628 F06a
N-CH
N-CH
R6
+
C
IN
V
IN
T1
1:N
OPTIONAL EXTV
CC
CONNECTION
5V < V
SEC
< 7V
R5
EXTV
CC
V
IN
TG1
SW
BG1
PGND
LTC1628
R
SENSE
V
OUT
VN2222LL
+
C
OUT
1628 F06b
N-CH
N-CH
+
C
IN
+
1µF
V
IN
L1
BAT85 BAT85
BAT85
0.22µF
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Output Voltage
The LTC1628 output voltages are each set by an external
feedback resistive divider carefully placed across the
output capacitor. The resultant feedback signal is com-
pared with the internal precision 0.800V voltage reference
by the error amplifier. The output voltage is given by the
equation:
VV
R
R
OUT
=+
08 1 2
1
.
SENSE
+
/SENSE
–
Pins
The common mode input range of the current comparator
sense pins is from 0V to (1.1)INTV
CC
. Continuous linear
operation is guaranteed throughout this range allowing
output voltage setting from 0.8V to 7.7V, depending upon
the voltage applied to EXTV
CC
. A differential NPN input
stage is biased with internal resistors from an internal
2.4V source as shown in the Functional Diagram. This
requires that current either be sourced or sunk from the
SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
pins to the main output. The output can be easily preloaded
by the V
OUT
resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
current flowing out of each pair of SENSE pins is:
I
SENSE+
+ I
SENSE–
= (2.4V – V
OUT
)/24k
Since V
OSENSE
is servoed to the 0.8V reference voltage, we
can choose R1 in Figure 2 to have a maximum value to
absorb this current.
Rk
V
VV
MAX OUT
124
08
24
()
.
.–
=
for V
OUT
< 2.4V
Regulating an output voltage of 1.8V, the maximum value
of R1 should be 32K. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the
sense currents; however, R1 is still bounded by the
V
OSENSE
feedback current.
Soft-Start/Run Function
The RUN/SS1 and RUN/SS2 pins are multipurpose pins
that provide a soft-start function and a means to shut
down the LTC1628. Soft-start reduces the input power
source’s surge currents by gradually increasing the
controller’s current limit (proportional to V
ITH
). This pin
can also be used for power supply sequencing.
An internal 1.2µA current source charges up the C
SS
capacitor
.
When the voltage on RUN/SS1 (RUN/SS2)
reaches 1.5V, the particular controller is permitted to start
operating. As the voltage on RUN/SS increases from 1.5V
to 3.0V, the internal current limit is increased from 25mV/
R
SENSE
to 75mV/R
SENSE
. The output current limit ramps
up slowly, taking an additional 1.25s/µF to reach full
current. The output current thus ramps up slowly, reduc-
ing the starting surge current required from the input
power supply. If RUN/SS has been pulled all the way to
ground there is a delay before starting of approximately:
tV
ACsFC
DELAY SS SS
=µ=µ
()
15
12 125
.
../
tVV
ACsFC
IRAMP SS SS
=−µ=µ
()
315
12 125
.
../
By pulling both RUN/SS pins below 1V and/or pulling the
STBYMD pin below 0.2V, the LTC1628 is put into low
current shutdown (IQ = 20µA). The RUN/SS pins can be
driven directly from logic as shown in Figure 7. Diode D1
in Figure 7 reduces the start delay but allows CSS to ramp
up slowly providing the soft-start function. Each RUN/SS
pin has an internal 6V zener clamp (See Functional
Diagram).
Figure 7. RUN/SS Pin Interfacing
3.3V OR 5V RUN/SS
VIN INTVCC
RUN/SS
D1
CSS
RSS*
CSS
RSS*
1628 F07
(a) (b)
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
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Fault Conditions: Overcurrent Latchoff
The RUN/SS pins also provide the ability to latch off the
controller(s) when an overcurrent condition is detected.
The RUN/SS capacitor, C
SS
, is used initially to turn on and
limit the inrush current. After the controller has been
started and been given adequate time to charge up the
output capacitor and provide full load current, the RUN/SS
capacitor is used for a short-circuit timer. If the regulator’s
output voltage falls to less than 70% of its nominal value
after C
SS
reaches 4.1V, C
SS
begins discharging on the
assumption that the output is in an overcurrent condition.
If the condition lasts for a long enough period as deter-
mined by the size of the C
SS
and the specified discharge
current, the controller will be shut down until the RUN/SS
pin voltage is recycled. If the overload occurs during start-
up, the time can be approximated by:
t
LO1
≈ [C
SS
(4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
= 2.7 • 10
6
(C
SS
)
If the overload occurs after start-up the voltage on C
SS
will
begin discharging from the zener clamp voltage:
t
LO2
≈ [C
SS
(6 – 3.5)]/(1.2µA) = 2.1 • 10
6
(C
SS
)
The FLTCPL pin (LTC1628 only) determines whether an
overload on one channel will latch off only that channel
(FLTCPL = 0V) or both channels (FLTCPL = INTVCC). This
built-in overcurrent latchoff can be overridden by provid-
ing a pull-up resistor to the RUN/SS pin as shown in
Figure 7. This resistance shortens the soft-start period
and prevents the discharge of the RUN/SS capacitor
during an over current condition. Tying this pull-up resis-
tor to VIN as in Figure 7a, defeats overcurrent latchoff.
Diode-connecting this pull-up resistor to INTVCC , as in
Figure 7b, eliminates any extra supply current during
controller shutdown while eliminating the INTVCC loading
from preventing controller start-up.
Why should you defeat overcurrent latchoff? During the
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection
circuit to latch off. Defeating this feature will easily allow
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. After the design is complete, a decision can be
made whether to enable the latchoff feature.
The value of the soft-start capacitor C
SS
may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
) (10
–4
) (R
SENSE
)
The minimum recommended soft-start capacitor of
C
SS
= 0.1µF will be sufficient for most applications.
Fault Conditions: Current Limit and Current Foldback
The LTC1628 current comparator has a maximum sense
voltage of 75mV resulting in a maximum MOSFET current
of 75mV/R
SENSE
. The maximum value of current limit
generally occurs with the largest V
IN
at the highest ambi-
ent temperature, conditions that cause the highest power
dissipation in the top MOSFET.
The LTC1628 includes current foldback to help further
limit load current when the output is shorted to ground.
The foldback circuit is active even when the overload
shutdown latch described above is overridden. If the
output falls below 70% of its nominal output level, then the
maximum sense voltage is progressively lowered from
75mV to 25mV. Under short-circuit conditions with very
low duty cycles, the LTC1628 will begin cycle skipping in
order to limit the short-circuit current. In this situation the
bottom MOSFET will be dissipating most of the power but
less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
ON(MIN)
of
the LTC1628 (less than 200ns), the input voltage and
inductor value:
∆I
L(SC)
= t
ON(MIN)
(V
IN
/L)
The resulting short-circuit current is:
ImV
RI
SC SENSE LSC
=+
25 1
2∆()
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Fault Conditions: Overvoltage Protection (Crowbar)
The overvoltage crowbar is designed to blow a system
input fuse when the output voltage of the regulator rises
much higher than nominal levels. The crowbar causes
huge currents to flow, that blow the fuse to protect against
a shorted top MOSFET if the short occurs while the
controller is operating.
A comparator monitors the output for overvoltage condi-
tions. The comparator (OV) detects overvoltage faults
greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
off and the bottom MOSFET is turned on until the overvolt-
age condition is cleared. The output of this comparator is
only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
as the OV condition persists; if V
OUT
returns to a safe level,
normal operation automatically resumes. A shorted top
MOSFET will result in a high current condition which will
open the system fuse. The switching regulator will regu-
late properly with a leaky top MOSFET by altering the duty
cycle to accommodate the leakage.
The Standby Mode (STBYMD) Pin Function
The Standby Mode (STBYMD) pin provides several choices
for start-up and standby operational modes. If the pin is
pulled to ground, the RUN/SS pins for both controllers are
internally pulled to ground, preventing start-up and thereby
providing a single control pin for turning off both control-
lers at once. If the pin is left open or decoupled with a
capacitor to ground, the RUN/SS pins are each internally
provided with a starting current enabling external control
for turning on each controller independently. If the pin is
provided with a current of >3µA at a voltage greater than
2V, both internal linear regulators (INTV
CC
and 3.3V) will
be on even when both controllers are shut down. In this
mode, the onboard 3.3V and 5V linear regulators can
provide power to keep-alive functions such as a keyboard
controller. This pin can also be used as a latching “on” and/
or latching “off” power switch if so designed.
Frequency of Operation
The LTC1628 has an internal voltage controlled oscillator.
The frequency of this oscillator can be varied over a 2 to 1
range. The pin is internally self-biased at 1.19V, resulting
in a free-running frequency of approximately 220kHz. The
FREQSET pin can be grounded to lower this frequency to
approximately 140kHz or tied to the INTV
CC
pin to yield
approximately 310kHz. The FREQSET pin may be driven
with a voltage from 0 to INTV
CC
to fix or modulate the
oscillator frequency as shown in Figure 5.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest time duration
that the LTC1628 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty cycle
applications may approach this minimum on-time limit
and care should be taken to ensure that
tV
Vf
ON MIN OUT
IN
() ()
<
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1628 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC1628 is generally less
than 200ns. However, as the peak sense voltage decreases
the minimum on-time gradually increases up to about
300ns. This is of particular concern in forced continuous
applications with low ripple current at light loads. If the
duty cycle drops below the minimum on-time limit in this
situation, a significant amount of cycle skipping can occur
with correspondingly larger current and voltage ripple.
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FCB Pin Operation
The FCB pin can be used to regulate a secondary winding
or as a logic level input. Continuous operation is forced
when the FCB pin drops below 0.8V. During continuous
mode, current flows continuously in the transformer pri-
mary. The secondary winding(s) draw current only when
the bottom, synchronous switch is on. When primary load
currents are low and/or the V
IN
/V
OUT
ratio is low, the
synchronous switch may not be on for a sufficient amount
of time to transfer power from the output capacitor to the
secondary load. Forced continuous operation will support
secondary windings providing there is sufficient synchro-
nous switch duty factor. Thus, the FCB input pin removes
the requirement that power must be drawn from the
inductor primary in order to extract power from the
auxiliary windings. With the loop in continuous mode, the
auxiliary outputs may nominally be loaded without regard
to the primary output load.
The secondary output voltage V
SEC
is normally set as
shown in Figure 6a by the turns ratio N of the transformer:
V
SEC
≅ (N + 1) V
OUT
However, if the controller goes into Burst Mode operation
and halts switching due to a light primary load current,
then V
SEC
will droop. An external resistive divider from
V
SEC
to the FCB pin sets a minimum voltage V
SEC(MIN)
:
VV
R
R
SEC MIN()
.≈+
08 1 6
5
If V
SEC
drops below this level, the FCB voltage forces
temporary continuous switching operation until V
SEC
is
again above its minimum.
In order to prevent erratic operation if no external connec-
tions are made to the FCB pin, the FCB pin has a 0.18µA
internal current source pulling the pin high. Include this
current when choosing resistor values R5 and R6.
The following table summarizes the possible states avail-
able on the FCB pin:
Table 1
FCB Pin Condition
0V to 0.75V Forced Continuous (Current Reversal
Allowed—Burst Inhibited)
0.85V < V
FCB
< 4.3V Minimum Peak Current Induces
Burst Mode Operation
No Current Reversal Allowed
Feedback Resistors Regulating a Secondary Winding
>4.8V Burst Mode Operation Disabled
Constant Frequency Mode Enabled
No Current Reversal Allowed
No Minimum Peak Current
The FLTCPL pin determines whether only the first or both
controllers are temporarily forced into continuous mode
when the FCB pin falls below 0.8V. Tying the FLTCPL pin
to ground will send only the first controller into continuous
operation while tying the FLTCPL pin to INTV
CC
will send
both controllers into continuous operation.
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC1628 by loading the I
TH
pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage of the error amplifier, or 1.2V
(see Figure 8).
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
I
TH
R
C
R
T1
INTV
CC
C
C
1628 F08
LTC1628
R
T2
Figure 8. Active Voltage Positioning Applied to the LTC1628
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LTC1628/LTC1628-PG
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loss from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
SENSE
,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of L,
R
SENSE
and ESR to obtain I
2
R losses. For example, if each
R
DS(ON)
= 30mΩ, R
L
= 50mΩ, R
SENSE
= 10mΩ and R
ESR
= 40mΩ (sum of both input and output capacitance
losses), then the total resistance is 130mΩ. This results in
losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Efficiency varies as the inverse
square of V
OUT
for the same external components and
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7) V
IN2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having a maxi-
mum of 20mΩ to 50mΩ of ESR. The LTC1628 2-phase
architecture typically halves this input capacitance re-
quirement over competing solutions. Other losses includ-
ing Schottky conduction losses during dead-time and
inductor core losses generally account for less than 2%
total additional loss.
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear.com.)
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC1628 circuits: 1) LTC1628 V
IN
current (in-
cluding loading on the 3.3V internal regulator), 2) INTV
CC
regulator current, 3) I
2
R losses, 4) Topside MOSFET
transition losses.
1. The V
IN
current has two components: the first is the DC
supply current given in the Electrical Characteristics table,
which excludes MOSFET driver and control currents; the
second is the current drawn from the 3.3V linear regulator
output. V
IN
current typically results in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
CC
to
ground. The resulting dQ/dt is a current out of INTV
CC
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
=f(Q
T
+Q
B
), where Q
T
and Q
B
are the gate charges of the topside and bottom side
MOSFETs.
Supplying INTV
CC
power through the EXTV
CC
switch input
from an output-derived source will scale the V
IN
current
required for the driver and control circuits by a factor of
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
CC
current results in approxi-
mately 2.5mA of V
IN
current. This reduces the mid-current
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Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values.
The availability of the I
TH
pin not only allows
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response
. Assuming a pre-
dominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
TH
series R
C
-C
C
filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80% of
full-load current having a rise time of 1µs to 10µs will
produce output voltage and I
TH
pin waveforms that will
give a sense of the overall loop stability without breaking
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This is
why it is better to look at the I
TH
pin signal which is in the
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
C
and the bandwidth of the loop will be
increased by decreasing C
C
. If R
C
is increased by the same
factor that C
C
is decreased, the zero frequency will be kept
the same, thereby keeping the phase shift the same in the
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability of
the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than1:50, the switch rise time
should be controlled so that the load rise time is limited to
approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current to
about 200mA.
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LTC1628/LTC1628-PG
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Automotive Considerations: Plugging into the
Cigarette Lighter
As battery-powered devices go mobile, there is a natural
interest in plugging into the cigarette lighter in order to
conserve or even recharge battery packs during operation.
But before you connect, be advised: you are plugging into
the supply from hell. The main power line in an automobile
is the source of a number of nasty potential transients,
including load-dump, reverse-battery, and double-bat-
tery.
Load-dump is the result of a loose battery cable. When the
cable breaks connection, the field collapse in the alternator
can cause a positive spike as high as 60V which takes
several hundred milliseconds to decay. Reverse-battery is
Figure 9. Automotive Application Protection
just what it says, while double-battery is a consequence of
tow-truck operators finding that a 24V jump start cranks
cold engines faster than 12V.
The network shown in Figure 9 is the most straight forward
approach to protect a DC/DC converter from the ravages
of an automotive power line. The series diode prevents
current from flowing during reverse-battery, while the
transient suppressor clamps the input voltage during
load-dump. Note that the transient suppressor should not
conduct during double-battery operation, but must still
clamp the input voltage below breakdown of the converter.
Although the LTC1628 has a maximum input voltage of
36V, most applications will be limited to 30V by the
MOSFET BVDSS.
V
IN
1628 F09
LTC1628
TRANSIENT VOLTAGE
SUPPRESSOR
GENERAL INSTRUMENT
1.5KA24A
50A I
PK
RATING
12V
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LTC1628/LTC1628-PG
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Design Example
As a design example for one channel, assume V
IN
=
12V(nominal), V
IN
= 22V(max), V
OUT
= 1.8V, I
MAX
= 5A,
and f = 300kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the FREQSET pin
to the INTV
CC
pin for 300kHz operation. The minimum
inductance for 30% ripple current is:
∆IV
fL
V
V
LOUT OUT
IN
=
()() –1
A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current
will also help ensure that the minimum on-time of 200ns
is not violated. The minimum on-time occurs at maximum
V
IN
:
tV
Vf
V
V kHz ns
ON MIN OUT
IN MAX
() ()
.
()
== =
18
22 300 273
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
RmV
A
SENSE
≤≈Ω
50
584 001
..
Since the output voltage is below 2.4V the output resistive
divider will need to be sized to not only set the output
voltage but also to absorb the SENSE pins specified input
current.
Rk
V
VV
KV
VV k
MAX OUT
124
08
24
24 08
24 18 32
()
.
.–
.
.–.
=
=
=
Choosing 1% resistors; R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the top side MOSFET can be
easily estimated. Choosing a Siliconix Si4412DY results
in; R
DS(ON)
= 0.042Ω, C
RSS
= 100pF. At maximum input
voltage with T(estimated) = 50°C:
PV
VCC
V A pF kHz
mW
MAIN
=
()
+°°
[]
Ω
()
+
()()( )( )
=
18
22 5 1 0 005 50 25
0 042 1 7 22 5 100 300
220
2
2
.(. )( – )
..
A short-circuit to ground will result in a folded back current
of:
ImV ns V
HA
SC
=Ω+µ
=
25
001
1
2
200 22
33 32
.
()
..
with a typical value of R
DS(ON)
and δ = (0.005/°C)(20) =
0.1. The resulting power dissipated in the bottom MOSFET
is:
PVV
VA
mW
SYNC
=
()()
Ω
()
=
22 1 8
22 32 11 0042
434
2
–. ...
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. C
OUT
is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR(∆IL)
= 0.02Ω(1.67A) = 33mV
P–P
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PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1628. These items are also illustrated graphically in
the layout diagram of Figure 10. The Figure 11 illustrates
the current waveforms present in the various branches of
the 2-phase synchronous regulators operating in the
continuous mode. Check the following in your layout:
1. Are the top N-channel MOSFETs M1 and M3 located
within 1cm of each other with a common drain connection
at C
IN
? Do not attempt to split the input decoupling for the
two channels as it can cause a large resonant loop.
2. Are the signal and power grounds kept separate? The
combined LTC1628 signal ground pin and the ground
return of C
INTVCC
must return to the combined C
OUT
(–)
terminals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to the
(–) terminals of the input capacitor by placing the capaci-
tors next to each other and away from the Schottky loop
described above.
3. Do the LTC1628 V
OSENSE
pins resistive dividers con-
nect to the (+) terminals of C
OUT
? The resistive divider
must be connected between the (+) terminal of C
OUT
and
Figure 10. LTC1628 Recommended Printed Circuit Layout Diagram
C
B2
C
B1
FLTCPL R
PU
PGOOD
V
PULL-UP
(<7V)
C
INTVCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
C
IN
D1
M1 M2
M3 M4
D2
+
C
VIN
V
IN
R
IN
INTV
CC
3.3V
R4R3
*PGOOD ON THE LTC1628-PG
R2
R1
RUN/SS1
SENSE1
+
SENSE1
–
V
OSENSE1
FREQSET
STBYMD
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
–
SENSE2
+
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC1628
L1
L2
C
OUT1
V
OUT1
GND
V
OUT2
1628 F10
+
C
OUT2
+
R
SENSE
R
SENSE
FLTCPL
(PGOOD)*
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Figure 11. Branch Current Waveforms
APPLICATIO S I FOR ATIO
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signal ground and a small V
OSENSE
decoupling capacitor
should be as close as possible to the LTC1628 SGND pin.
The R2 and R4 connections should not be along the high
current input feeds from the input capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE
+
and SENSE
–
should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between
the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current peaks.
An additional 1µF ceramic capacitor placed immediately
next to the INTV
CC
and PGND pins can help improve noise
performance substantially.
6. Is the I
TH
pin filter capacitor connected close to the IC,
between I
TH
and the signal ground pins? This capacitor
helps to filter the effects of PCB noise and output voltage
ripple voltage from the compensaton loop
7. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2), and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from the
R
L1
D1
L1
SW1 R
SENSE1
V
OUT1
C
OUT1
+
V
IN
C
IN
R
IN
+
R
L2
D2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH.
L2
SW2
1628 F11
R
SENSE2
V
OUT2
C
OUT2
+
29
LTC1628/LTC1628-PG
1628fb
APPLICATIO S I FOR ATIO
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opposites channel’s voltage and current sensing feedback
pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
of the LTC1628 and occupy minimum PC trace area.
8. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
PC Board Layout Debugging
Start with one controller on at a time. It is helpful to use a
DC-50MHz current probe to monitor the current in the
inductor while testing the circuit. Monitor the output
switching node (SW pin) to synchronize the oscilloscope
to the internal oscillator and probe the actual output
voltage as well. Check for proper performance over the
operating voltage and current range expected in the appli-
cation. The frequency of operation should be maintained
over the input voltage range down to dropout and until the
output load drops below the low current operation thresh-
old—typically 10% to 20% of the maximum designed
current level in Burst Mode operation.
The duty cycle percentage should be maintained from
cycle to cycle in a well-designed, low noise PCB imple-
mentation. Variation in the duty cycle at a subharmonic
rate can suggest noise pickup at the current or voltage
sensing inputs or inadequate loop compensation. Over-
compensation of the loop can be used to tame a poor PC
layout if regulator bandwidth optimization is not required.
Only after each controller is checked for their individual
performance should both controllers be turned on at the
same time. A particularly difficult region of operation is
when one controller channel is nearing its current com-
parator trip point when the other channel is turning on its
top MOSFET. This occurs around 50% duty cycle on either
channel due to the phasing of the internal clocks and may
cause minor duty cycle jitter.
Short-circuit testing can be performed to verify proper
overcurrent latchoff, or 5µA can be provided to the RUN/
SS pin(s) by resistors from V
IN
to prevent the short-circuit
latchoff from occurring.
Reduce V
IN
from its nominal level to verify operation of the
regulator in dropout. Check the operation of the
undervoltage lockout circuit by further lowering V
IN
while
monitoring the outputs to verify operation.
Investigate whether any problems exist only at higher
output currents or only at higher input voltages. If prob-
lems coincide with high input voltages and low output
currents, look for capacitive coupling between the BOOST,
SW, TG, and possibly BG connections and the sensitive
voltage and current pins. The capacitor placed across the
current sensing pins needs to be placed immediately
adjacent to the pins of the IC. This capacitor helps to
minimize the effects of differential noise injection due to
high frequency capacitive coupling. If problems are en-
countered with high current output loading at lower input
voltages, look for inductive coupling between C
IN
, Schottky
and the top MOSFET components to the sensitive current
and voltage sensing traces. In addition, investigate com-
mon ground path voltage pickup between these compo-
nents and the SGND pin of the IC.
An embarrassing problem, which can be missed in an
otherwise properly working switching regulator, results
when the current sensing leads are hooked up backwards.
The output voltage under this improper hookup will still be
maintained but the advantages of current mode control
will not be realized. Compensation of the voltage loop will
be much more sensitive to component selection. This
behavior can be investigated by temporarily shorting out
the current sensing resistor—don’t worry, the regulator
will still maintain control of the output voltage.
30
LTC1628/LTC1628-PG
1628fb
Figure 12. LTC1628 High Efficiency Low Noise 5V/3A, 3.3V/5A, 12/120mA Regulator
0.1µF
0.1µF
4.7µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
22µF
50V
D1
MBRM
140T3
MBRS1100T3
D2
MBRM
140T3
M1 M2
M3 M4
1µF
10V
CMDSH-3TR
CMDSH-3TR
0.1µF
10Ω
0.01Ω
0.015Ω
INTV
CC
3.3V
0.1µF
20k
1%
105k, 1%
33pF
15k
33pF
15k
*PGOOD ON THE LTC1628-PG
1000pF
1000pF
1000pF
1000pF
0.1µF
20k
1%
63.4k
1%
RUN/SS1
SENSE1
+
SENSE1
–
V
OSENSE1
FREQSET
STBYMD
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
–
SENSE2
+
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC1628
T1, 1:1.8
10µH
L1
6.3µH
150µF, 6.3V
PANASONIC SP 1µF
25V
180µF, 4V
PANASONIC SP
GND
ON/OFF
85
123
V
OUT2
3.3V
5A; 6A PEAK
V
OUT2
12V
120mA
33µF
25V
V
OUT1
5V
3A; 4A PEAK
V
IN
7V TO
28V
1628 F12
+ +
V
IN
: 7V TO 28V
V
OUT
: 5V, 3A/3.3V, 6A, 12V, 150mA
SWITCHING FREQUENCY = 300kHz
MI, M2, M3, M4: NDS8410A
L1: SUMIDA CEP123-6R3MC
T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
LT1121
+
+
220k
100k
1M
FLTCPL
PGOOD
100k V
PULL-UP
(<7V)
59k
180pF
180pF
0.01µF
FLTCPL*
(PGOOD)
U
TYPICAL APPLICATIO
31
LTC1628/LTC1628-PG
1628fb
G Package
28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
G28 SSOP 1098
0.13 – 0.22
(0.005 – 0.009)
0° – 8°
0.55 – 0.95
(0.022 – 0.037)
5.20 – 5.38**
(0.205 – 0.212)
7.65 – 7.90
(0.301 – 0.311)
12345678 9 10 11 12 1413
10.07 – 10.33*
(0.397 – 0.407)
2526 22 21 20 19 18 17 16 1523242728
1.73 – 1.99
(0.068 – 0.078)
0.05 – 0.21
(0.002 – 0.008)
0.65
(0.0256)
BSC 0.25 – 0.38
(0.010 – 0.015)
NOTE: DIMENSIONS ARE IN MILLIMETERS
DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
*
**
UH32 Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
5.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO INCLUDE JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
PIN 1
TOP MARK
0.40 ± 0.10
31
1
2
32
BOTTOM VIEW—EXPOSED PAD
3.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.23 ± 0.05
(UH) QFN 0102
0.50 BSC
0.200 REF
0.00 – 0.05
0.57 ±0.05
3.45 ±0.05
(4 SIDES)
4.20 ±0.05
5.35 ±0.05
0.23 ± 0.05
PACKAGE OUTLINE
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
(For purposes of clarity, drawings are not to scale)
32
LTC1628/LTC1628-PG
1628fb
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1998
LT/TP 0302 1.5K REV B • PRINTED IN USA
Figure 13. LTC1628 5V/4A, 3.3V/4A Regulator
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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OUT
≤ 3.5V, Current Mode Ensures
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IN
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≤ 36V
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No Heat Sink, 3.5V ≤ V
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0.1µF
4.7µF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
22µF
50V
D1
MBRM
140T3
D2
MBRM
140T3
M1A M1B
M2A M2B
1µF
10V
0.1µF
10Ω
0.015Ω
0.015Ω
INTV
CC
3.3V
0.1µF
20k
1%
105k
1%
33pF
15k
33pF
15k 220pF
220pF
1000pF
1000pF
0.1µF
20k
1%
63.4k
1%
RUN/SS1
SENSE1
+
SENSE1
–
V
OSENSE1
FREQSET
STBYMD
FCB
I
TH1
SGND
3.3V
OUT
I
TH2
V
OSENSE2
SENSE2
–
SENSE2
+
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
RUN/SS2
LTC1628
L1
8µH
L2
8µH
47µF
6.3V
56µF, 4V
GND
V
OUT2
3.3V
3A; 4A PEAK
V
OUT1
5V
3A; 4A PEAK
V
IN
5.2V TO
28V
1628 F13
+ +
V
IN
: 5.2V TO 28V
V
OUT
: 5V, 4A/3.3V, 4A
SWITCHING FREQUENCY = 300kHz
MI, M2: FDS8936A
L1, L2: 8µH SUMIDA CEP1238R0MC
OUTPUT CAPACITORS: PANASONIC SP SERIES
27pF
27pF
0.1µF
CMDSH-3TR
CMDSH-3TR
0.01µF
FLTCPL
PGOOD
V
PULL-UP
(<7V)
FLTCPL*
(PGOOD)
*PGOOD ON THE LTC1628-PG
U
TYPICAL APPLICATIO
