© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 0
1Publication Order Number:
NCN3612B/D
NCN3612B
6-Channel Differential 1:2
Switch for PCIe 3.0 and
DisplayPort 1.2
The NCN3612B is a 6−Channel differential SPDT switch designed
to route PCI Express Gen3 and/or DisplayPort 1.2 signals. Due to the
ultra−low ON−state capacitance (2.1 pF typ) and resistance (8 W typ),
this switch is ideal for switching high frequency signals up to a signal
bit rate (BR) of 8 Gbps. This switch pinout is designed to be used in
BTX form factor desktop PCs and is available in a space−saving
5x11x0.75 mm WQFN56 package. The NCN3612B uses 80% less
quiescent power than other comparable PCIe switches.
Features
•BTX Pinout
•VDD Power Supply from 3 V to 3.6 V
•Low Supply Current: 250 mA typ
•6 Differential Channels, 2:1 MUX/DEMUX
•Compatible with Display Port 1.2 & PCIe 3.0
•Data Rate: Supports 8 Gbps
•Low RON Resistance: 8 W typ
•Low CON Capacitance: 2.1 pF
•Space Saving, Small WQFN−56 Package
•This is a Pb−Free Device
Typical Applications
•Notebook Computers
•Desktop Computers
•Server/Storage Networks
Figure 1. Application Schematic
Graphics and
Memory
Controller Hub
(GMCH)
Display Port Connector
PCIe Graphics (PEG) Connector
PCI
Express
Graphics
(PEG)
NCN3612B
IN_0 +/−
IN_1 +/−
IN_2 +/−
IN_3 +/−
X +/−
OUT +/−
D0 +/−
D1 +/−
D2 +/−
D3 +/−
HPD1/HPD2
AUX +/−
Tx0 +/−
Tx1 +/−
Tx2 +/−
Tx3 +/−
Rx0 +/−
Rx1 +/−
PCIe BUFF1
PCIe BUFF2
PCIe BUFF3
PCIe BUFF4
PCIe IN
AUX
Device Package Shipping†
ORDERING INFORMATION
NCN3612BMTTWG WQFN56
(Pb−Free)
2000 /
Tape & Reel
WQFN56
CASE 510AK
MARKING
DIAGRAM
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A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
NCN3612B
AWLYYWWG
1
NCN3612B
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2
Logic Control
Figure 2. NCN3612B Block Diagram
IN_0+
OUT+
SEL
LE
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
IN_0−
IN_1+
IN_1−
IN_2+
IN_2−
IN_3+
IN_3−
OUT−
X+
X−
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx3+
Tx3−
AUX+
AUX−
HPD1
HPD2
Rx0+
Rx0−
Rx1+
Rx1−
Tx2−
TRUTH TABLE (SEL Control)
Function SEL
PCI Express Gen3 Path is Active (Tx, Rx) L
Digital Video Port is Active (D, HPD, AUX) H
TRUTH TABLE (Latch Control)
LE Internal Mux Select
LRespond to Changes on SEL
H Latched
NCN3612B
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3
1
2
3
4
5
21
48
47
46
45
44
18
19
20
31
30
29
Figure 3. Pinout
(Top View)
22
23
25
26
27
28
56
55
54
53
52
51
50
49
GND
VDD
Rx1−
Rx1+
Rx0−
Rx0+
VDD
GND
GND
VDD
D0+
D0−
D1+
D1−
VDD
GND
GND
GND
GND
GND
SEL
LE
IN_0+
IN_0−
X+
X−
D2+
D2−
D3+
D3−
HPD1
HPD2
24
6
7
8
9
10
11
12
13
14
15
16
17
43
42
41
40
39
38
36
35
34
33
32
VDD
IN_1+
IN_1−
IN_2+
IN_2−
GND
IN_3+
IN_3−
OUT+
OUT−
GND
VDD
Tx0+
Tx0−
Tx1+
Tx1−
Tx2+
Tx2−
Tx3+
Tx3−
GND
VDD
AUX+
AUX−
37
Exposed Pad on
Underside
(solder to external
Gnd)
NCN3612B
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PIN FUNCTION AND DESCRIPTION
Pin Name Description
6, 17, 22, 27,
34,50, 55
VDD DC Supply, 3.3 V $10%
1, 11, 16, 20, 21,
28, 29, 35, 48,
49, 56
GND Power Ground.
Exposed Pad −The exposed pad on the backside of package is internally connected to Gnd. Externally the exposed
pad should also be user−connected to GND.
2 SEL SEL controls the mux through a flow−through latch. Do not float this pin.
SEL = 0 for PCIE Mode; SEL = 1 for DP Mode
3 LE LE controls the latch gate. Do not float this pin.
4 IN_0+ Differential input from GMCH PCIE outputs. IN_0+ makes a differential pair with IN_0−.
5 IN_0−Differential input from GMCH PCIE outputs. IN_0− makes a differential pair with IN_0+.
7 IN_1+ Differential input from GMCH PCIE outputs. IN_1+ makes a differential pair with IN_1−.
8 IN_1−Differential input from GMCH PCIE outputs. IN_1− makes a differential pair with IN_1+.
9 IN_2+ Differential input from GMCH PCIE outputs. IN_2+ makes a differential pair with IN_2−.
10 IN_2−Differential input from GMCH PCIE outputs. IN_2− makes a differential pair with IN_2+.
12 IN_3+ Differential input from GMCH PCIE outputs. IN_3+ makes a differential pair with IN_3−.
13 IN_3−Differential input from GMCH PCIE outputs. IN_3− makes a differential pair with IN_3+.
14 OUT+ Pass−through output from AUX+ input when SEL = 1. Pass−through output from Rx0+ input when
SEL = 0.
15 OUT−Pass−through output from AUX− input when SEL = 1. Pass−through output from Rx0− input when
SEL = 0.
18 X+ X+ is an analog pass−through output corresponding to Rx1+.
19 X−X− is an analog pass−through output corresponding to the Rx1− input. The path
from Rx1− to X− must be matched with the path from Rx1+ to X+. X+ and X− form a
differential pair when the pass−through mux mode is selected.
23 Rx1−Differential input from PCIE connector or device. Rx1− makes a differential pair with Rx1+. Rx1− is
passed through to the X− pin on the path that matches the Rx1+ to X+ pin.
24 Rx1+ Differential input from PCIE connector or device. Rx1+ makes a differential pair with Rx1−. Rx1+ is
passed through to the X+ pin when SEL = 0.
25 Rx0−Differential input from PCIE connector or device. Rx0− makes a differential pair with Rx0+. Rx0− is
passed through to the OUT− pin when SEL = 0.
26 Rx0+ Differential input from PCIE connector or device. Rx0+ makes a differential pair with Rx0−. Rx0+ is
passed through to the OUT+ pin when SEL = 0.
30 HPD2 Negative low frequency HPD input handshake protocol signal (normally not connected).
31 HPD1 Positive low frequency HPD input handshake protocol signal.
32 AUX−Differential input from HDMI/DP connector. AUX− makes a differential
pair with AUX+. AUX− is passed through to the OUT− pin when SEL = 1.
33 AUX+ Differential input from HDMI/DP connector. AUX+ makes a differential
pair with AUX−. AUX+ is passed through to the OUT+ pin when SEL = 1.
37, 36 Tx3+, Tx3−Analog pass−through output#2 corresponding to IN_3+ and IN_3− when SEL = 0.
39, 38 Tx2+, Tx2−Analog pass−through output#2 corresponding to IN_2+ and IN_2− when SEL = 0.
41, 40 Tx1+, Tx1−Analog pass−through output#2 corresponding to IN_1+ and IN_1− when SEL = 0.
43, 42 Tx0+, Tx0−Analog pass−through output#2 corresponding to IN_0+ and IN_0− when SEL = 0.
45, 44 D3+, D3−Analog pass−through output#1 corresponding to IN_3+ and IN_3−, when SEL = 1.
47, 46 D2+, D2−Analog pass−through output#1 corresponding to IN_2+ and IN_2−, when SEL = 1.
52, 51 D1+, D1−Analog pass−through output#1 corresponding to IN_1+ and IN_1−, when SEL = 1.
54, 53 D0+, D0−Analog pass−through output#1 corresponding to IN_0+ and IN_0−, when SEL = 1.
NCN3612B
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MAXIMUM RATINGS
Parameter Symbol Rating Unit
Power Supply Voltage VDD −0.5 to 5.3 VDC
Input/Output Voltage Range of the Switch
(Tx, Rx, D, HPD, AUX, IN_, OUT, X)
VIS −0.5 to VDD + 0.3 VDC
Selection Pin Voltages (SEL and LE) VIN −0.5 to VDD + 0.3 VDC
Continuous Current Through One Switch Channel IIS ±120 mA
Maximum Junction Temperature (Note 1) TJ150 °C
Operating Ambient Temperature TA−40 to +85 °C
Storage Temperature Range Tstg −65 to +150 °C
Thermal Resistance, Junction−to−Air (Note 2) RqJA 37 °C/W
Latch−up Current (Note 3) ILU ±100 mA
Human Body Model (HBM) ESD Rating (Note 4) ESD HBM 7000 V
Machine Model (MM) ESD Rating (Note 4) ESD MM 400 V
Moisture Sensitivity (Note 5) MSL Level 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded.
2. This parameter is based on EIA/JEDEC 51−7 with a 4−layer PCB, 80 mm x 80 mm, two 1oz Cu material internal planes and top planes of
2oz Cu material.
3. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78.
4. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ±7.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) ±400 V per JEDEC standard: JESD22−A115 for all pins.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
NCN3612B
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ELECTRICAL CHARACTERISTICS (VDD = +3.3V ±10%, TA = −40°C to +85°C, unless otherwise noted. All Typical values are at
VDD = +3.3 V, TA = +25°C, unless otherwise noted.)
Symbol Characteristics Conditions Min Typ Max Unit
POWER SUPPLY
VDD Supply Voltage Range 3.0 3.3 3.6 V
IDD Power Supply Current VDD = 3.6 V, VIN = GND or VDD 250 350 mA
DATA SWITCH PERFORMANCE (for both PCIe and DisplayPort applications, unless otherwise noted)
VIS Data Input/Output Voltage
Range
0 1.2 V
RON On Resistance (Tx, Rx) VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA 8.0 13 W
RON On Resistance (D, HPD, AUX) VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA 9.0 13 W
RON(flat) On Resistance Flatness VDD = 3 V, VIS = 0 V to 1.2 V, IIS = 15 mA
(Note 6)
0.1 1.24 W
DRON On Resistance Matching
(Tx, Rx)
VDD = 3 V, VIS = 0 V, IIS = 15 mA 0.35 W
DRON On Resistance Matching
(D, HPD, AUX)
VDD = 3 V, VIS = 0 V, IIS = 15 mA 0.35 W
CON On Capacitance f = 1 MHz, Switch On, Open Output 2.1 pF
COFF Off Capacitance f = 1 MHz, Switch Off 1.6 pF
ION On Leakage Current
(IN_/ X/OUT)
VDD = 3.6 V, VIN_ = Vx = VOUT = 0 V, 1.2 V;
Switch On to D/HPD/AUX or Tx/Rx; outputs
unconnected
−1 +1 mA
IOFF Off Leakage Current
(D/Tx/HPD/Rx/AUX)
VDD = 3.6 V, VIN_ = VX_ = VOUT_ = 0 V, 1.2 V;
Switch Off; VD = VHPD = VAUX or VD = VHPD =
VAUX set to 1.2 V, 0 V
−1 +1 mA
CONTROL LOGIC CHARACTERISTICS (SEL and LE pins)
VIL Off voltage input 0 0.8 V
VIH High voltage input 2 VDD V
IIN Off voltage input VIN = 0 V or VDD −1 +1 mA
CIN High voltage input f = 1 MHz 1 pF
DYNAMIC CHARACTERISTICS
BR Signal Data Rate 8 Gbps
DIL Differential Insertion Loss f = 100 MHz −0.7 dB
f = 2.7 GHz −1.3
f = 4 GHz −2
DISO Differential Off Isolation f = 100 MHz −54 dB
f = 2.7 GHz −23
f = 4 GHz −18
DCTK Differential Crosstalk f = 100 MHz −50 dB
f = 2.7 GHz −32
f = 4 GHz −30
DRL Differential Return Loss f = 100 MHz −20 dB
f = 3.7 GHz −10
f = 4 GHz −5
6. Guaranteed by characterization and/or design.
NCN3612B
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SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified)
Symbol Characteristics Conditions Min Typ Max Unit
tb−bBit−to−bit skew Within the same differential pair 7 ps
tch−ch Channel−to−channel skew Maximum skew between all channels 55 ps
SELECTION PINS SWITCHING CHARACTERISTICS (VDD = +3.3 V, TA = 25°C, unless otherwise specified)
Symbol Characteristics Conditions Min Typ Max Unit
TSELON SEL to Switch turn ON time VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF 9.5 ns
TSELOFF SEL to Switch turn OFF time VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100pF 5 ns
TSET LE setup time SEL to LE VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF 1 ns
THOLD LE hold time LE to SEL VIS = 1 V, RL = 50 W, VLE = VDD, CL = 100 pF 1 ns
NCN3612B
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TYPICAL OPERATING CHARACTERISTICS
Figure 4. Reference DisplayPort 1.2 Eye Diagram
without Switch at 5.4 Gbps, 340 mVpp Differential
Swing
Figure 5. DisplayPort 1.2 Eye Diagram through
NCN3612B at 5.4 Gbps, 340 mVpp Differential
Swing
Figure 6. Reference PCIe 3.0 Eye Diagram without
Switch at 8 Gbps, 800 mVpp Differential Swing
Figure 7. PCIe 3.0 Eye Diagram through NCN3612B
at 8 Gbps, 800 mVpp Differential Swing
NCN3612B
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TYPICAL OPERATING CHARACTERISTICS
0
100000000 1E+09 1E+10
−2
−4
−6
−8
−10
−12
−14
FREQUENCY (Hz)
MAGNITUDE (dB)
Figure 8. Differential Insertion Loss
0
10000000 100000000 1E+09 1E+1
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
MAGNITUDE (dB)
FREQUENCY (Hz)
Figure 9. Differential Crosstalk
0
10000000 100000000 1E+09 1E+10
−10
−20
−30
−40
−50
−60
−70
−80
FREQUENCY (Hz)
MAGNITUDE (dB)
Figure 10. Differential Off Isolation
0
100000000 1E+09 1E+1
0
−5
−10
−15
−20
−25
MAGNITUDE (dB)
FREQUENCY (Hz)
Figure 11. Differential Return Loss
5
7
9
10
11
0 0.5 1 1.5 2
12
VCC=3.0
VCC=3.3
VCC=3.6
8
6
Figure 12. RON vs. VIS
VIS (V)
RON, ON RESISTANCE (W)
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PARAMETER MEASUREMENT INFORMATION
Figure 13. Differential Insertion Loss (SDD21) and
Differential Return Loss (SDD11)
Figure 14. Differential Off Isolation (SDD21)
Figure 15. Differential Crosstalk (SDD21)Figure 16. Bit−to−Bit and Channel−to−Channel Skew
Figure 17. tON and tOFF
Figure 18. Off State Leakage Figure 19. On State Leakage
tskew = |tPLH1-tPLH2| or |tPHL1-tPHL2|
NCN3612B
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PACKAGE DIMENSIONS
WQFN56 5x11, 0.5P
CASE 510AK−01
ISSUE A
SEATING
0.15 C
(A3) A
A1
b
1
56
56X
L
56X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA B
E
0.15 C
ÉÉÉ
ÉÉÉ
ÉÉÉ
PIN ONE
LOCATION
0.10 C
0.08 C
C
e
A0.10 B
C
0.05 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A0.70 0.80
A1 −−− 0.05
A3 0.20 REF
b0.20 0.30
D5.00 BSC
D2 2.30 2.50
E11.00 BSC
8.50E2 8.30
e0.50 BSC
L0.30 0.50
K
PLANE
SOLDERING FOOTPRINT*
L1 −−− 0.15
NOTE 4
e/2
E2
D2
NOTE 3
DETAIL B
L1
DETAIL A
L
ALTERNATE
CONSTRUCTIONS
L
ÉÉ
ÉÉ
ÉÉ
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTION
DETAIL A
A0.10 BC
K
DIMENSIONS: MILLIMETERS
5.30
8.50
2.50
0.50
0.63
0.35
56X
56X
PITCH
11.30
PKG
OUTLINE
1
RECOMMENDED
A0.10 BC
0.20 MIN
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
NCN3612B/D
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