ACS8510 Rev2.1 SETS Synchronous Equipment Timing Source for SONET or SDH Network Elements FINAL ADVANCED COMMUNICATIONS Description Features The ACS8510 is a highly integrated, single-chip solution for the Synchronous Equipment Timing Source (SETS) function in a SONET or SDH Network Element. The device generates SONET or SDH Equipment Clocks (SEC) and frame synchronization clocks. The ACS8510 is fully compliant with the required specifications and standards. The device supports Free-run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. Two ACS8510 devices can be used together in a Master/Slave configuration mode allowing system protection against a single ACS8510 failure. A microprocessor port is incorporated, providing access to the configuration and status registers for device setup and monitoring. The ACS8510 supports IEEE 1149.1 JTAG boundary scan. Rev2.1 adds choice of edge alignment for 8kHz input, as well as a low jitter n x E1/DS1 output mode. Other minor changes are made, with all described in Appendix A. *Suitable for Stratum 3E*, 3, 4E and 4 SONET or SDH Equipment Clock (SEC) applications *Meets AT&T, ITU-T, ETSI and Telcordia specifications *Accepts 14 individual input reference clocks *Generates 11 output clocks *Supports Free-run, Locked and Holdover modes of operation *Robust input clock source quality monitoring on all inputs *Automatic `hit-less' source switchover on loss of input *Phase build out for output clock phase continuity during input switchover and mode transitions *Microprocessor interface - Intel, Motorola, Serial, Multiplexed, EPROM *Programmable wander and jitter tracking attenuation 0.1 Hz to 20 Hz *Support for Master/Slave device configuration alignment and hot/standby redundancy *IEEE 1149.1 JTAG Boundary Scan *Single +3.3 V operation, +5 V I/O compatible *Operating temperature (ambient) -40C to +85C *Available in 100 pin LQFP package * Meets Holdover requirements, lowest bandwidth 0.1 Hz. Block Diagram Figure 1. Simple Block Diagram 2 x AMI 10 x TTL 2 x PECL/LVDS Programmable; 64/8kHz 2kHz 4kHz N x 8kHz 1.544/2.048MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz Input Ports TOUT4 selector Divider Digital Loop Filter PFD DTO DPLL/Freq. Synthesis 14xSEC 9xSEC Monitors TOUT0 selector PFD Divider IEEE 1149.1 JTAG Digital Loop Filter DTO DPLL/Freq. Synthesis MFrSync TCK TDI TMS TRST TDO Output Ports Chip Clock Generator Priority Table Register Set APLL Frequency Dividers FrSync MFrSync 1 x AMI 6 x TTL 2 x PECL/LVDS Programmable: 64/8kHz 1.544/2.048MHz 3.088/4.096MHz 6.176/8.182MHz 12.352/16.384MHz 6.48MHz 19.44MHz 25.92MHz 38.88MHz 51.84MHz 77.76MHz 155.52MHz 311.04MHz 2kHz MFrSync 8kHz FrSync Microprocessor Port TCXO (*OCXO) Revision 2.00/September 2003 Semtech Corp. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS TTable able of Cont ents Contents List of Sections Description ................................................................................................................................................................................................ 1 Block Diagram ........................................................................................................................................................................................... 1 Features ..................................................................................................................................................................................................... 1 Table of Contents ...................................................................................................................................................................................... 2 Pin Diagram ............................................................................................................................................................................................... 5 Pin Descriptions ........................................................................................................................................................................................ 6 Functional Description ............................................................................................................................................................................. 9 Local Oscillator Clock ................................................................................................................................................................................... 10 ITU and ETSI Specification ............................................................................................................................................................. 10 Telcordia GR-1244 CORE Specification ....................................................................................................................................... 10 Crystal Frequency Calibration ...................................................................................................................................................... 10 Input Interfaces ............................................................................................................................................................................................. 10 Over-Voltage Protection .............................................................................................................................................................................. 10 Input Reference Clock Ports ....................................................................................................................................................................... 11 Input Wander and Jitter Tolerance .............................................................................................................................................................. 9 Output Clock Ports ........................................................................................................................................................................................ 12 Low Speed Output Clock (DPLL2) ................................................................................................................................................. 12 High Speed Output Clock (DPLL1) ............................................................................................................................................... 12 Frame Sync and Multi-Frame Sync Clocks (Part of DPLL1) ................................................................................................... 13 Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 13 Output Wander and Jitter ............................................................................................................................................................................ 13 Phase Variation ............................................................................................................................................................................................. 18 Phase Build Out ............................................................................................................................................................................................. 21 Microprocessor Interface ............................................................................................................................................................................. 21 Motorola Mode ................................................................................................................................................................................ 21 Intel Mode ........................................................................................................................................................................................ 21 Multiplexed Mode ........................................................................................................................................................................... 21 Serial Mode ...................................................................................................................................................................................... 21 EPROM Mode ................................................................................................................................................................................... 21 Register Set ..................................................................................................................................................................................... 22 Configuration Registers ................................................................................................................................................................. 22 Status Registers .............................................................................................................................................................................. 22 Register Access ............................................................................................................................................................................... 22 Interrupt Enable and Clear ......................................................................................................................................................................... 22 Register Map .................................................................................................................................................................................................. 23 Register Map Description ........................................................................................................................................................................... 27 Selection of Input Reference Clock Source ............................................................................................................................................. 36 Forced Control Selection ............................................................................................................................................................... 37 Automatic Control Selection ........................................................................................................................................................ 37 Ultra Fast Switching ....................................................................................................................................................................... 37 External Protection Switching ..................................................................................................................................................... 38 Clock Quality Monitoring ............................................................................................................................................................................. 38 Activity Monitoring ....................................................................................................................................................................................... 39 Frequency Monitoring .................................................................................................................................................................................. 39 Modes of Operation ...................................................................................................................................................................................... 41 Free-run mode ................................................................................................................................................................................. 41 Pre-Locked mode ............................................................................................................................................................................ 41 Locked mode .................................................................................................................................................................................... 41 Lost_Phase mode ........................................................................................................................................................................... 41 Holdover mode ................................................................................................................................................................................ 42 Pre-Locked(2) mode ........................................................................................................................................................................ 42 Protection Facility ........................................................................................................................................................................................ 43 Alignment of Priority Tables in Master and Slave ACS8510 ................................................................................................. 44 Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 ........... 45 Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 ....................................... 45 JTAG .................................................................................................................................................................................................................. 45 PORB ................................................................................................................................................................................................................ 45 Electrical Specification .......................................................................................................................................................................... 48 Revision 2.00/September 2003 Semtech Corp. 2 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS DC Characteristics: AMI Input/Output Port ........................................................................................................................................... 54 Microprocessor Interface Timing .......................................................................................................................................................... 63 Motorola Mode .............................................................................................................................................................................................. 63 Intel Mode ....................................................................................................................................................................................................... 65 Multiplexed Mode ......................................................................................................................................................................................... 67 Serial Mode .................................................................................................................................................................................................... 69 EPROM Mode ................................................................................................................................................................................................. 71 Package Information .............................................................................................................................................................................. 72 Thermal Conditions ....................................................................................................................................................................................... 73 Application Information .......................................................................................................................................................................... 74 Revision History ...................................................................................................................................................................................... 75 Ordering Information .............................................................................................................................................................................. 76 Disclaimers ..................................................................................................................................................................................................... 76 List of Figures Figure 1. Simple Block Diagram ............................................................................................................................................................. 1 Figure 2. ACS8510 Pin Diagram ............................................................................................................................................................ 5 Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) ................................................................................................................... 15 Figure 4. Minimum Input Jitter Tolerance (DS1/E1) .......................................................................................................................... 16 Figure 5. Wander and Jitter Measured Transfer Characteristics ....................................................................................................... 18 Figure 6. Maximum Time Interval Error of TOUT0 output port ........................................................................................................... 20 Figure 7. Time Deviation of TOUT0 output port ................................................................................................................................... 20 Figure 8. Phase error accumulation of TOUT0 output port in Holdover mode .................................................................................. 20 Figure 9. Inactivity and Irregularity Monitoring ................................................................................................................................... 38 Figure 10. Master-Slave Schematic ..................................................................................................................................................... 46 Figure 11. Automatic Mode Control State Diagram ........................................................................................................................... 47 Figure 12. Recommended Line Termination for PECL Input/Output Ports ...................................................................................... 51 Figure 13. Recommended Line Termination for LVDS Input/Output Ports ...................................................................................... 53 Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface ............................................................................................ 55 Figure 15. AMI Input and Output Signal Levels .................................................................................................................................. 55 Figure 16. Recommended Line Termination for AMI Output/Output Ports ..................................................................................... 56 Figure 17. JTAG Timing ............................................................................................................................................................................ 61 Figure 18. Input/Output Timing ............................................................................................................................................................ 62 Figure 19. Read Access Timing in MOTOROLA Mode ........................................................................................................................ 63 Figure 20. Write Access Timing in MOTOROLA Mode ....................................................................................................................... 64 Figure 21. Read Access Timing in INTEL Mode ................................................................................................................................... 65 Figure 22. Write Access Timing in INTEL Mode .................................................................................................................................. 66 Figure 23. Read Access Timing in MULTIPLEXED Mode .................................................................................................................... 67 Figure 24. Write Access Timing in MULTIPLEXED Mode ................................................................................................................... 68 Figure 25. Read Access Timing in SERIAL Mode ................................................................................................................................ 69 Figure 26. Write Access Timing in SERIAL Mode ............................................................................................................................... 70 Figure 27. Access Timing in EPROM Mode ......................................................................................................................................... 71 Figure 28. LQFP Package ...................................................................................................................................................................... 72 Figure 29. Typical 100 Pin LQFP Footprint ......................................................................................................................................... 73 Figure 30. Simplified Application Schematic ...................................................................................................................................... 74 Revision 2.00/September 2003 Semtech Corp. 3 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS List of TTables ables Table 1. Power Pins .................................................................................................................................................................................... 6 Table 2. No Connections ............................................................................................................................................................................ 6 Table 3. Other Pins ..................................................................................................................................................................................... 7 Table 4. Input Reference Source Selection and Priority Table .......................................................................................................... 12 Table 5. Input ReferenceSource Jitter Tolerance ................................................................................................................................. 14 Table 6. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 15 Table 7. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 16 Table 8. Output Reference Source Selection Table ............................................................................................................................. 17 Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 17 Table 10. Microprocessor Interface Mode Selection ......................................................................................................................... 21 Table 11. Register Map .......................................................................................................................................................................... 23 Table 12. Register Map Description ..................................................................................................................................................... 27 Table 13. Master-Slave Relationship .................................................................................................................................................... 46 Table 14. Absolute Maximum Ratings .................................................................................................................................................. 48 Table 15. Operating Conditions ............................................................................................................................................................. 48 Table 16. DC Characteristics: TTL Input Port ....................................................................................................................................... 48 Table 17. DC Characteristics: TTL Input Port with Internal Pull-up .................................................................................................... 49 Table 18. DC Characteristics: TTL Input Port with Internal Pull-down ............................................................................................... 49 Table 18. DC Characteristics: TTL Output Port .................................................................................................................................... 49 Table 20. DC Characteristics: PECL Input/Output Port ...................................................................................................................... 50 Table 21. DC Characteristics: LVDS Input/Output Port ...................................................................................................................... 52 Table 22. DC Characteristics: AMI Input/Output Port ........................................................................................................................ 54 Table 23. DC Characteristics: Ouput Jitter Generation (Test Definition G.813) ............................................................................. 57 Table 24. DC Characteristics: Ouput Jitter Generation (Test Definition G.812) ............................................................................. 57 Table 25. DC Characteristics: Ouput Jitter Generation (Test Definition ETS-300-462-3) .............................................................. 58 Table 26. DC Characteristics: Ouput Jitter Generation (Test Definition GR-253-CORE) ............................................................... 58 Table 27. DC Characteristics: Ouput Jitter Generation (Test Definition AT&T 62411) ................................................................... 59 Table 28. DC Characteristics: Ouput Jitter Generation (Test Definition G.742) .............................................................................. 59 Table 29. DC Characteristics: Ouput Jitter Generation (Test Definition TR-NWT-000499) ........................................................... 59 Table 30. DC Characteristics: Ouput Jitter Generation (Test Definition GR-1244-CORE) ............................................................. 60 Table 31. JTAG Timing (for use with Figure 17) ................................................................................................................................... 61 Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) ................................................................................. 63 Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) ................................................................................ 64 Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) ............................................................................................ 65 Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) ........................................................................................... 66 Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) ............................................................................. 67 Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) ............................................................................. 68 Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) ......................................................................................... 70 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70 Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71 Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73 Revision 2.00/September 2003 Semtech Corp. 4 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Pin Diagram Figure 2. ACS8510 Pin Diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AGND TRST IC NC AGND VA1+ TMS INTREQ TCK REFCLK DGND VD+ VD+ DGND DGND VD+ NC SRCSW VA2+ AGND TDO IC TDI I1 I2 VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFF VDD_DIFF TO6POS TO6NEG TO7POS TO7NEG GND_DIFF VDD_DIFF I5POS I5NEG I6POS I6NEG VDD5 SYNC2K I3 I4 I7 DGND VDD 1 ACS8510 SDH/SONET SETS Rev 2.1 NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float. Revision 2.00/September 2003 Semtech Corp. 5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SONSDHB MSTSLVB IC IC IC TO9 TO5 TO4 DGND VDD TO3 TO2 TO1 DGND VDD VDD DGND AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 RDY PORB ALE RDB WRB CSB A0 A1 A2 A3 A4 A5 A6 DGND VDD UPSEL0 UPSEL1 UPSEL2 I14 I13 I12 I11 I10 I9 I8 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Pin Descriptions Table 1. Power Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 12, 13, 16 VD+ P - S u p p l y v o l t a g e : Digital supply to gates in analog section, +3.3 Volts. +/- 10% 26 VAMI+ P - S u p p l y v o l t a g e : Digital supply to AMI output, +3.3 Volts. +/- 10% 33, 39 VDD_DIFF P - S u p p l y v o l t a g e : Digital supply for differential por ts, +3.3 Volts. +/- 10% 44 VDD5 P - V D D 5 : Digital supply for +5 Volts tolerance to input pins. Connect to +5 Volts (+/- 10%) for clamping to +5 Volts. Connect to VDD for clamping to +3.3 Volts. Leave floating for no clamping, input pins tolerant up to +5.5 Volts. 50, 61, 85, 86, 91 VDD P - S u p p l y v o l t a g e : Digital supply to logic, +3.3 Volts. +/- 10% 6 VA1+ P - S u p p l y v o l t a g e : Analog supply to clock multipying PLL, +3.3 Volts. +/- 10% 19 VA2+ P - S u p p l y v o l t a g e : Analog supply to output PLL, +3.3 Volts. +/- 10% 11, 14, 15, 49, 62, 84, 87, 92 DGN D P - S u p p l y G r o u n d : Digital ground for logic 29 GN D_AMI P - S u p p l y G r o u n d : Digital ground for AMI output 32, 38 GN D_DIFF P - S u p p l y G r o u n d : Digital ground for differential por ts 1, 5, 20 AGN D P - S u p p l y G r o u n d : Analog ground Table 2. No Connections PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 4, 17 NC - - N o t C o n n e c t e d : Leave to Float 3, 22, 96, 97,98 IC - - I n t e r n a l l y C o n n e c t e d : Leave to Float Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor Revision 2.00/September 2003 Semtech Corp. 6 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 2 TRST I T T LD J TA G C o n t r o l R e s e t I n p u t : TRST = 1 to enable JTAG Boundary Scan mode. TRST = 0 for normal device op eration (JTAG logic transp arent). If not used connect to GN D or leave floating. 7 T MS I T T LU J TA G Te s t M o d e S e l e c t : Boundary Scan enable. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. 8 IN T R E Q O TTL CMOS I n t e r r u p t R e q u e s t : Active high software Interrup t outp ut 9 TCK I T T LD J TA G C l o c k : Boundary Scan clock inp ut. If not used connect to GN D or leave floating. This p in may require a cap acitor p laced between the p in and the nearest GN D, to reduce noise p ickup . A value of 10 p F should be adequate, but the value is dep endent on PCB layout. 10 REFCLK I TTL R e f e r e n c e C l o c k : 12.8 MHz (refer to section headed Local Oscillator Clock) 18 SRCSW I T T LD S o u r c e S w i t c h i n g : Force Fast Source Switching 21 TDO O TTL CMOS 23 TDI I T T LU J TA G I n p u t : Serial test data Inp ut. Samp led on rising edge of TCK. If not used connect to VDD or leave floating. 24 I1 I A MI I n p u t r e f e r e n c e 1 : comp osite clock 64 kHz + 8 kHz 25 I2 I A MI I n p u t r e f e r e n c e 2 : comp osite clock 64 kHz + 8 kHz 27 TO8N EG O A MI O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz negative p ulse 28 TO8POS O A MI O u t p u t r e f e r e n c e 8 : comp osite clock, 64 kHz + 8 kHz p ositive p ulse 30 FrSync O TTL CMOS O u t p u t r e f e r e n c e 10 : 8 kHz Frame Sync clock outp ut (square wave) 31 MFrSync O TTL CMOS O u t p u t r e f e r e n c e 1 1 : 2 kHz Multi-Frame Sync clock outp ut (square wave) 34 35 TO6POS TO6N EG O LVDS PECL O u t p u t r e f e r e n c e 6 : default 38.88 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04 MHz. Default typ e LVDS. 36 37 TO7POS TO7N EG O PECL LVDS O u t p u t r e f e r e n c e 7 : default 19.44 MHz. Also 51.84 MHz, 77.76 MHz, 155.52 MHz. Default typ e PECL. 40 41 I5POS I5N EG I LVDS PECL I n p u t r e f e r e n c e 5 : default 19.44 MHz, default typ e LVDS 42 43 I6POS I6N EG I PECL LVDS I n p u t r e f e r e n c e 6 : default 19.44 MHz, default typ e PECL Revision 2.00/September 2003 Semtech Corp. J TA G O u t p u t : Serial test data outp ut. Up dated on falling edge of TCK. If not used leave floating. 7 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN SYMB OL IO IO T YPE N A M E /DE S CR I P T I O N 45 SYN C2K I T T LD S y n c h r o n i s e 2 k H z : Connect to 2 kHz Multi-Frame Sync outp ut of p ar tner ACS8510 in redundancy system 46 I3 I T T LD I n p u t r e f e r e n c e 3 : p rogrammable, default 8 kHz 47 I4 I T T LD I n p u t r e f e r e n c e 4 : p rogrammable, default 8 kHz 48 I7 I T T LD I n p u t r e f e r e n c e 7 : p rogrammable, default 19.44 MHz 51 I8 I T T LD I n p u t r e f e r e n c e 8 : p rogrammable, default 19.44 MHz 52 I9 I T T LD I n p u t r e f e r e n c e 9 : p rogrammable, default 19.44 MHz 53 I10 I T T LD I n p u t r e f e r e n c e 10 : p rogrammable, default 19.44 MHz. 54 I11 I T T LD I n p u t r e f e r e n c e 1 1 : p rogrammable, default (master mode)1.544/2.048 MHz, default (slave mode) 6.48 MHz 55 I12 I T T LD I n p u t r e f e r e n c e 1 2 : p rogrammable, default 1.544/2.048 MHz. 56 I13 I T T LD I n p u t r e f e r e n c e 1 3 : p rogrammable, default 1.544/2.048 MHz. 57 I14 I T T LD I n p u t r e f e r e n c e 14 : p rogrammable, default 1.544/2.048 MHz. 58 - 60 UPSEL(2:0) I T T LD M i c r o p r o c e s s o r s e l e c t : Configures the inter face for a p ar ticular microp rocessor typ e. 63 - 69 A(6:0) I T T LD M i c r o p r o c e s s o r I n t e r f a c e A d d r e s s : Address bus for the microp rocessor inter face registers. A(0) is SDI in Serial mode. 70 CSB I T T LU C h i p S e l e c t ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to enable the microp rocessor inter face. 71 WRB I T T LU W r i t e ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a write cycle. In Motorola mode, WRB = 1 for Read. 72 RDB I T T LU R e a d ( A c t i v e L o w ) : This p in is asser ted Low by the microp rocessor to initiate a read cycle. 73 A LE I T T LD A d d r e s s L a t c h E n a b l e : This p in becomes the address latch enable from the microp rocessor. When this p in transitions from Low to High, the address bus inp uts are latched into the internal registers. ALE = SCLK in Serial mode. 74 PORB I T T LU P o w e r O n R e s e t : Master reset. If PORB is forced Low, all internal states are reset back to default values. 75 RDY O TTL CMOS R e a d y / D a t a a c k n o w l e d g e : This p in is asser ted High to indicate the device has comp leted a read or write op eration. 76 - 83 AD(7:0) IO T T LD A d d r e s s / D a t a : Multip lexed data/address bus dep ending on the microp rocessor mode selection. AD(0) is SDO in Serial mode. Revision 2.00/September 2003 Semtech Corp. 8 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 3. Other Pins (continued) PIN SYMB OL IO IO T YPE 88 TO1 O TTL CMOS O u t p u t r e f e r e n c e 1 : default 6.48 MHz. Also Dig1 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 25.92 MHz 89 TO2 O TTL CMOS O u t p u t r e f e r e n c e 2 : default 38.88 MHz. Also Dig2 (1.544 MHz/2.048 MHz and 2, 4, 8 x), 25.92 MHz, 51.84 MHz 90 TO3 O TTL CMOS O u t p u t r e f e r e n c e 3 : 19.44 MHz - fixed. 93 TO4 O TTL CMOS O u t p u t r e f e r e n c e 4 : 38.88 MHz - fixed. 94 TO5 O TTL CMOS O u t p u t r e f e r e n c e 5 : 77.76 MHz - fixed. 95 TO9 O TTL CMOS O u t p u t r e f e r e n c e 9 : 1.544/2.048 MHz. (T4 BITS) 99 100 MSTSLVB SON SDHB I I N A M E /DE S CR I P T I O N T T LU M A S T E R S L AV E B : Master slave select: sets the initial p ower up state (or state after a PORB) of the Master/Slave selection register, addr 34, bit 1. The register state can be changed after p ower up by software. T T LD S O N E T S D H B : SON ET or SDH frequency select: sets the initial p ower up state (or state after a PORB) of the SON ET/SDH frequency selection registers, addr 34h, bit 2 and addr 38, bits 5 and 6. The register states can be changed after p ower up by software. FFunctional unctional Description The ACS8510 is a highly integrated, single-chip solution for the SETS function in a SONET/SDH Network Element, for the generation of SEC and frame synchronization pulses. In Free-run mode, the ACS8510 generates a stable, lownoise clock signal from an internal oscillator. In Locked mode, the ACS8510 selects the most appropriate input reference source and generates a stable, low-noise clock signal locked to the selected reference. In Holdover mode, the ACS8510 generates a stable, low-noise clock signal from the internal oscillator, adjusted to match the last known good frequency of the last selected reference source. In all modes, the frequency accuracy, jitter and drift performance of the clock meet the requirements of ITU G.812, G.813, G.823, and GR-1244-CORE. Revision 2.00/September 2003 Semtech Corp. 9 The ACS8510 supports all three types of reference clock source: recovered line clock (TIN1), PDH network synchronization timing (TIN2) and node synchronization (TIN3). The ACS8510 generates independent TOUT0 and TOUT4 clocks, an 8 kHz Frame Synchronization clock and a 2 kHz Multi-Frame Synchronization clock. The ACS8510 has a high tolerance to input jitter and wander. The jitter/wander transfer is programmable (0.1 Hz up to 20 Hz cut-off points). The ACS8510 supports protection. Two ACS8510 devices can be configured to provide protection against a single ACS8510 failure. The protection maintains alignment of the two ACS8510 devices (Master and Slave) and ensures that both ACS8510 devices maintain the same priority table, choose the same www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS reference input and generate the TOUT0 clock, the 8 kHz Frame Synchronization clock and the 2 kHz Multi-Frame Synchronization clock with the same phase. The ACS8510 includes a microprocessor port, providing access to the configuration and status registers for device setup and monitoring. Local Oscillator Clock The Master system clock on the ACS8510 should be provided by an external clock oscillator of frequency 12.80 MHz. The clock specification is important for meeting the ITU/ETSI and Telcordia performance requirements for Holdover mode. ITU and ETSI specifications permit a combined drift characteristic, at constant temperature, of all non-temperaturerelated parameters, of up to 10 ppb per day. The same specifications allow a drift of 1 ppm over a temperature range of 0 to +70 C. Telcordia specifications are somewhat tighter, requiring a non-temperature-related drift of less than 40 ppb per day and a drift of 280 ppb over the temperature range 0 to +50 C. ITU and ETSI Specification Crystal Frequency Calibration The absolute crystal frequency accuracy is less important than the stability since any frequency offset can be compensated by adjustment of register values in the IC. This allows for calibration and compensation of any crystal frequency variation away from its nominal value. +/- 50 ppm adjustment would be sufficient to cope with most crystals, in fact the range is an order of magnitude larger due to the use of two 8 bit register locations. The setting of the conf_nominal_frequency register allows for this adjustment. An increase in the register value increases the output frequencies by 0.02 ppm for each LSB step. The default value (in decimal) is 39321. The minimum being 0 and the maximum 65535, gives a -700 ppm to +500 ppm adjustment range of the output frequencies. For example, if the crystal was oscillating at 12.8 MHz + 5 ppm, then the calibration value in the register to give a -5 ppm adjustment in output frequencies to compensate for the crystal inaccuracy, would be : 39321 - (5 / 0.02) = 39071 (decimal) Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. Input Interfaces +/- 0.01 ppm/day @ constant temp. The ACS8510 supports up to fourteen input reference clock sources from input types TIN1, TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and AMI buffer I/O technologies. These interface technologies support +3.3 V and +5 V operation. +/- 1 ppm over temp. range 0 to +70 C *Frequency drift over supply range of +2.7V to +3.3V. Telcordia GR-1244 CORE Specification Tolerance: +/- 4.6 ppm over 20 year life time. Drift*: +/- 0.05 ppm/15 seconds @ constant temp. Over-Voltage Protection +/- 0.04 ppm/day @ constant temp. +/- 0.28 ppm over temp. range 0 to +50 C *Frequency drift over supply range of +2.7V to +3.3V. Please contact Semtech for information on crystal oscillator suppliers. Revision 2.00/September 2003 Semtech Corp. 10 The ACS8510 may require Over-Voltage Protection on input reference clock ports according to ITU Recommendation K.41. Semtech protection devices are recommended for this purpose (see separate Semtech data book). www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Input Reference Clock Ports Table 4 gives details of the input reference ports, showing the input technologies and the range of frequencies supported on each port; the default spot frequencies and default priorities assigned to each port on power-up or by reset are also shown. Note that SDH and SONET networks use different default frequencies; the network type is pin-selectable (using the SONSDHB pin). Specific frequencies and priorities are set by configuration. Although each input port is shown as belonging to one of the types, TIN1, TIN2 or TIN3, they are fully interchangeable as long as the selected speed is within the maximum operating speed of the input port technology. SDH and SONET networks use different default frequencies; the network type is selectable using the config_mode register 34 Hex, bit 2. For SONET, config_mode register 34 Hex, bit 2 = 1, for SDH config_mode register 34 Hex, bit 2 = 0. On power-up or by reset, the default will be set by the state of the SONSDHB pin (pin 100). Specific frequencies and priorities are set by configuration. TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies supported are: * 2 kHz * 4 kHz * 8 kHz (and N x 8 kHz) * 1.544 MHz (SONET)/2.048 MHz (SDH) * 6.48 MHz, * 19.44 MHz, * 25.92 MHz, * 38.88 MHz, * 51.84 MHz, * 77.76 MHz. Revision 2.00/September 2003 Semtech Corp. 11 The frequency selection is programmed via the cnfg_ref_source_frequency register. The internal DPLL will normally lock to the selected input at the frequency of the input, eg. 19.44 MHz will lock the DPLL phase comparisons at 19.44 MHz. It is, however, possible to utilise an internal pre-divider to the DPLL to divide the input frequency before it is used for phase comparisons in the DPLL. This pre-divider can be used in one of 2 ways: 1. Any of the supported spot frequencies can be divided to 8 kHz by setting the `lock8K' bit (bit 6) in the appropriate cnfg_ref_source_frequency register location. For good jitter tolerance for all frequencies and for operation at 19.44 MHz and above, use lock8K. It is possible to choose which edge of the 8kHz input to lock to, by setting the appropriate bit of the cnfg_control1 register. 2. Any multiple of 8 kHz between 1544 kHz to 100 MHz can be supported by using the `DivN' feature (bit 7 of the cnfg_ref_source_frequency register). Any reference input can be set to use DivN independently of the frequencies and configurations of the other inputs. Any reference input with the DivN bit set in the cnfg_ref_source_frequency register will employ the internal pre-divider prior to the DPLL locking. The cnfg_freq_divn register contains the divider ratio N where the reference input will get divided by (N+1) where 0<N<2 14 -1. The cnfg_ref_source_frequency register must be set to the closest supported spot frequency to the input frequency, but must be lower than the input frequency. When using the DivN feature the post-divider frequency must be 8 kHz, which is indicated by setting the `lock8k' bit high (bit 6 in cnfg_ref_source_frequency register). Any input set to DivN must have the frequency monitors disabled (If the frequency monitors are disabled, they are disabled for all inputs regardless of the input configurations, in this case only activity monitoring will take place). Whilst any number of inputs can be set to use the DivN feature, only one N can be programmed, hence all inputs using the DivN feature must require the same division to get to 8 kHz. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 4. Input Reference Source Selection and Priority Table P or t N u m b er C h an n el N u m b er P or t Ty p e I n p u t P or t Te c h n o l o g y I_1 0001 T IN 3 A MI 64/8kHz (composite clock, 64kHz + 8kHz) Default (SON ET): 64/8kHz Default (SDH): 64/8kHz 2 I _2 0010 T IN 3 A MI 64/8kHz (composite clock, 64kHz + 8kHz) Default (SON ET): 64/8kHz Default (SDH): 64/8kHz 3 I _3 0011 T IN 3 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 8kHz Default (SDH): 8kHz 4 I_4 0100 T IN 3 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 8kHz Default (SDH): 8kHz 5 I_5 0101 T IN 1 LVDS/PECL LVDS default Up to 155.52MHz (see N ote 2) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 6 I_6 0110 T IN 1 PECL/LVDS PECL default Up to 155.52MHz (see N ote 2) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 7 I _7 0111 T IN 1 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 8 I_8 1000 T IN 1 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 9 I_9 1001 T IN 1 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 10 I_10 1010 T IN 1 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 19.44MHz Default (SDH): 19.44MHz 11 12/1 (N ote 3) Fr e q u e n c i e s S u p p o r t e d Def au l t P ri ori t y I_11 1011 T IN 2 TTL/CMOS Up to 100MHz (see N ote 1) Default (Master) (SON ET): 1.544MHz Default (Master) (SDH): 2.048MHz Default (Slave) 6.48MHz I_12 1100 T IN 2 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 1.544MHz Default (SDH): 2.048MHz 13 I_13 1101 T IN 2 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 1.544MHz Default (SDH): 2.048MHz 14 I_14 1110 T IN 2 TTL/CMOS Up to 100MHz (see N ote 1) Default (SON ET): 1.544MHz Default (SDH): 2.048MHz 15 Revision 2.00/September 2003 Semtech Corp. 12 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Notes for Table 4. Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH is selected using the SONSDHB pin. When the SONSDHB pin is High SONET is selected, when the SONSDHB pin is Low SDH is selected. Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz. Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin. DivN examples To lock to 2.000 MHz. (1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the frequency to E1/DS1. (XX = `leaky bucket' ID for this input). (2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1). (3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. (4) The DivN register is set to F9 Hex (249 decimal). To lock to 10.000 MHz. (1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the frequency to 6.48 MHz. (XX = `leaky bucket' ID for this input). (2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1. (3) The DivN register is set to 4E1 Hex (1249 decimal). PECL and LVDS ports support the spot clock frequencies listed plus 155.52 MHz and 311.04 MHz. The choice of PECL or LVDS compatibility is programmed via the cnfg_differential_inputs register. Unused PECL/ LVDS differential inputs should be fixed with one input high (VDD) and the other input low (GND), or set in LVDS mode and left floating, in which case one input is internally pulled high and the other low. An AMI port supports a composite clock, consisting of a 64 kHz AMI clock with 8 kHz boundaries marked by deliberate violations of the AMI coding rules, as specified in ITU recommendation G.703. Departures from the nominal pattern are detected within the Revision 2.00/September 2003 Semtech Corp. 13 ACS8510, and may cause reference-switching if too frequent. See section DC Characteristics: AMI Input/Output Port, for more details. If the AMI port is unused, the pins (I1 and I2) should be tied to GND and the VAMI+ supply pin (pin 26) disconnected. Input Wander and Jitter Tolerance The ACS8510 is compliant to the requirements of all relevant standards, principally ITU Recommendation G.825, ANSI DS1.101-1994 and ETS 300 462-5 (1997). All reference clock inputs have a tight frequency tolerance but a generous jitter tolerance. Pullin, hold-in and pull-out ranges are specified for each input port in Table 5. Minimum jitter www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS tolerance masks are specified in Figures 3 and 4, and Tables 6 and 7, respectively. The ACS8510 will tolerate wander and jitter components greater than those shown in Figure 3 and Figure 4, up to a limit determined by a combination of the apparent long-term frequency offset caused by wander and the eye-closure caused by jitter (the input source will be rejected if the offset pushes the frequency outside the hold-in range for long enough to be detected, whilst the signal will also be rejected if the eye closes sufficiently to affect the signal purity). The `8klocking' mode should be engaged for high jitter tolerance according to these masks. All reference clock ports are monitored for quality, including frequency offset and general activity. Single short-term interruptions in selected reference clocks may not cause rearrangements, whilst longer interruptions, or multiple, short-term interruptions, will cause rearrangements, as will frequency offsets which are sufficiently large or sufficiently long to cause loss-of-lock in the phase-locked loop. The failed reference source will be removed from the priority table and declared as unserviceable, until its perceived quality has been restored to an acceptable level. The registers sts_curr_inc_offset (address 0C, 0D, 07) report the frequency of the DPLL with respect to the external TCXO frequency. This is a 19 bit signed number with one LSB representing 0.0003 ppm (range of +/- 80 ppm). Reading this regularly can show how the currently locked source is varying in value e.g. due to wander on its input. The ACS8510 performs automatic frequency monitoring with an acceptable input frequency offset range of +/- 16.6 ppm. The ACS8510 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. Table 5. Input Reference Source Jitter Tolerance J i t t er To l e r a n c e Fr e q u e n c y M o n i t o r A ccep t an ce R an g e G.703 G.783 G.823 Fr e q u e n c y A ccep t an ce R an g e ( Pu l l -i n ) Fr e q u e n c y A ccep t an ce R an g e ( H ol d - i n ) Fr e q u e n c y A ccep t an ce R an g e ( P u l l - ou t ) +/- 4.6 ppm (see N ote 1) +/- 4.6 ppm (see N ote 1) +/- 4.6 ppm (see N ote 1) +/- 9.2 ppm (see N ote 2) +/- 9.2 ppm (see N ote 2) +/- 9.2 ppm (see N ote 2) +/- 16.6 ppm GR-1244-CORE Notes for Table 5. Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm. Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal frequency of 12.8 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08 ppm steps. Revision 2.00/September 2003 Semtech Corp. 14 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) (for inputs supporting G.783 compliant sources) A0 A1 A2 A3 A4 Jitter and wander frequency (log scale) f0 f1 f2 f3 f4 f5 f6 f8 f9 Table 6. Amplitude and Frequency Values for Jitter Tolerance P eak t o p eak am p l i t u d e ( u n i t I n t er v al ) ST M l evel STM-1 Fr e q u e n c y ( H z ) A0 A0 A1 A1 A2 A2 A3 A3 A4 A4 F0 F0 F1 F1 F2 F2 F3 F3 F4 F4 F5 F5 F6 F6 F7 F7 F8 F8 F9 F9 2800 311 39 1.5 0.15 12u 178u 1.6m 15.6m 0.125 19.3 500 6.5k 65k 1.3m Output Clock Ports The device supports a set of main output clocks, TOUT0 and TOUT4, and a pair of secondary output clocks, 'Frame-Sync' and 'Multi-Frame-Sync'. The two main output clocks, TOUT0 and TOUT4, are independent of each other and are individually selectable. The two secondary output clocks, 'Frame-Sync' and 'Multi-Frame-Sync', are derived from TOUT0. The frequencies of the output clocks are selectable from a range of pre-defined spot frequencies and a variety of output technologies are supported, as defined in Table 8. Low-speed Output Clock (T OUT4 ) The TOUT4 clock is supplied on two output ports, TO8 and TO9. The former port will provide an AMI signal carrying a composite clock of 64 kHz and 8 kHz, according to ITU Recommendation Revision 2.00/September 2003 Semtech Corp. 15 G.703. The latter port will provide a TTL/CMOS signal at either 1.544 MHz or 2.048 MHz, depending on the setting of the SONSDHB pin. High-speed Output Clock (Part of T OUT0 ) The TOUT0 port has multiple outputs. Outputs TO1 and TO2 are TTL/CMOS output with a choice of 11 different frequencies up to 51.84 MHz. Outputs TO3 to TO5 are all TTL/CMOS outputs with fixed frequencies of 19.44 MHz, 38.88 MHz and 77.76 MHz respectively. Output TO6 is differential and can support clocks up to 155.52 MHz. Output TO7 is also differential and can support clocks up to 155.52 MHz. Each output is individually configured to operate at the frequencies shown in Table 8 (configuration must be consistent between ACS8510 devices for protection-switching to be effective - output clocks will be phase-aligned www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 4. Minimum Input Jitter Tolerance (DS1/E1) (for inputs supporting G.783 compliant sources) Peak-to-peak jitter and wander amplitude (log scale) A1 A2 Jitter and wander frequency (log scale) f1 f2 f3 f4 Table 7. Amplitude and Frequency Values for Jitter Tolerance Ty p e S p ec. A mp l i tu d e ( U I p k-p k) Fr e q u e n c y ( Hz ) A1 A1 A2 A2 F1 F1 F2 F2 F3 F3 F4 F4 DS 1 G R - 1 24 4 - C O R E 5 0.1 10 500 8k 40k E1 E1 I T U G. 823 1.5 0.2 20 2.4k 18k 100k between devices). Using the cnfg_differential_outputs register, outputs TO6 and T O7 can be made to be LVDS or PECL compatible. Frame Sync and Multi-Frame Sync Clocks (Part of T OUT0) Frame Sync (8 kHz) and Multi-Frame Sync (2 kHz) clocks are provided on outputs TO10 (FrSync) and TO11 (MFrSync). The FrSync and MFrSync clocks have a 50:50 mark space ratio. These are driven from the TOUT0 clock. They are synchronized with their counterparts in a second ACS8510 device (if used), using the technique described later. Revision 2.00/September 2003 Semtech Corp. 16 Low Jitter Multiple E1/DS1 Outputs This feature added to Rev2.1 is activated using the cnfg_control1 register. This sends a frequency of twice the Dig2 rate (see reg addr 39h, bits 7:6) to the APLL instead of the normal 77.76MHz. For this feature to be used, the Dig2 rate must only be set to 12352kHz/16384kHz using the cnfg_T0_output_frequencies register. The normal OC3 rate outputs are then replaced with E1/DS1 multiple rates. The E1(SONET)/ DS1(SDH) selection is made in the same way as for Dig2 using the cnfg_T0_output_enable register. Table 9 shows the relationship between primary output frequencies and the corresponding output in E1/DS1 mode, and which output they are available from. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Output Wander and Jitter Wander and jitter present on the output clocks are dependent on: 1. The magnitude of wander and jitter on the selected input reference clock (in Locked mode) 2. The internal wander and jitter transfer characteristic (in Locked mode) 3. The jitter on the local oscillator clock 4. The wander on the local oscillator clock (in Holdover mode) Wander and jitter are treated in different ways to reflect their differing impacts on network design. Jitter is always strongly attenuated, whilst wander attenuation can be varied to suit the application and operating state. Wander and jitter attenuation is performed using a digital phase locked loop (DPLL) with a programmable bandwidth. This gives a transfer characteristic of a low pass filter, with a programmable pole. It is sometimes necessary to change the filter dynamics to suit particular circumstances - one example being when locking to a new source, Table 8. Output Reference Source Selection Table P or t N am e O u t p u t P or t Te c h n o l o g y T01 TTL/CMOS 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 6.48 MHz (default), 12.352 MHz/16.384 MHz, 19.44 MHz, 25.92 MHz T02 TTL/CMOS 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 12.352 MHz/16.384 MHz, 25.92 MHz, 38.88 MHz (default), 51.84 MHz T03 TTL/CMOS 19.44 MHz - fixed T04 TTL/CMOS 38.88 MHz - fixed T05 TTL/CMOS 77.76 MHz - fixed T06 LVDS/PECL (LVDS default) 1.544 MHz/2.048 MHz, 3.088 MHz/4.096 MHz, 6.176 MHz/8.192 MHz, 12.352 MHz/16.384 MHz, 19.44 MHz, 38.88 MHz (default), 155.52 MHz, 311.04 MHz T07 PECL/LVDS (PECL default) 19.44 MHz (default), 51.84 MHz, 77.76 MHz, 155.52 MHz T08 A MI T09 TTL/CMOS 1.544 MHz/2.048 MHz T010 TTL/CMOS FrSync, 8 kHz - with a 50:50 MSR T011 TTL/CMOS MFrSync, 2 kHz - with a 50:50 MSR Fr e q u e n c i e s S u p p o r t e d 64/8 kHz (composite clock, 64 kHz + 8 kHz) Note for Table 8. Where 1.544 MHz/2.048 MHz is shown, 1.544 MHz is SONET, and 2.048 MHz is SDH. Pin SONSDHB controls the default frequency output. Where the SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default. Revision 2.00/September 2003 Semtech Corp. 17 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs M od e Default Fr e q t o A PLL A PLL M u l t i p l i er 77.76 4 A PLL Fr e q cl k _ f i l t cl k _ f i l t /2 cl k _ f i l t /4 cl k _ f i l t /6 cl k _ f i l t /8 cl k _ f i l t /12 cl k _ f i l t / 16 cl k _ f i l t /48 DP L L Fr e q 311.04 311.04 155.52 77.76 51.84 38.88 25.92 19.44 6.48 77.76 n value 16 16 8 4 n x E1 32.768 4 131.072 131.072 65.536 3 2 . 76 8 21.84533 16 . 3 8 4 10.92267 8 .1 9 2 2.730667 77.76 n x T1 24.704 4 98.816 49.408 24 . 7 0 4 16.46933 1 2 . 3 5 2 8.234667 6 .176 2.058667 77.76 98.816 Frequencies Available by Outp ut T01 T02 T03 T04 T05 T06 T06 T07 the filter can be opened up to reduce locking time and can then be gradually tightened again to remove wander. Since wander represents a relatively long-term deviation from the nominal operating frequency, it affects the rate of supply of data to the network element. Strong wander attenuation limits the rate of consumption of data to within a smaller range, so a larger buffer store is required to prevent data loss. But, since any buffer store potentially increases latency, wander may often only need to be removed at specific points within a network where buffer stores are acceptable, such as at digital cross connects. Otherwise, wander is sometimes not required to be attenuated and can be passed through transparently. The ACS8510 has programmable wander transfer characteristics in a range from 0.1 Hz to 20 Hz. The wander and jitter transfer characteristic is shown in Figure 5. Wander on the local oscillator clock will not have significant effect on the output clock whilst in Locked mode, so long as the DPLL bandwidth is set high enough so that the DPLL can compensate quickly enough for any frequency changes in the crystal. In Free-run or Holdover mode wander on the crystal is more significant. Revision 2.00/September 2003 Semtech Corp. 18 T06 T07 Variation in crystal temperature or supply voltage both cause drifts in operating frequency, as does ageing. These effects must be limited by careful selection of a suitable component for the local oscillator, as specified in the section `Local Oscillator Clock'. Phase Variation There will be a phase shift across the ACS8510 between the selected input reference source and the output clock. This phase shift may vary over time but will be constrained to lie within specified limits. The phase shift is characterised using two parameters, MTIE (Maximum Time Interval Error), and TDEV (Time Deviation), which, although being specified in all relevent specifications, differ in acceptable limits in each one. Typical measurements for the ACS8510 are shown in Figures 6 and 7, for Locked mode operation. Figure 8 shows a typical measurement of Phase Error accumulation in Holdover mode operation. The required performance for phase variation during Holdover is specified in several ways depending upon the particular circumstances pertaining: www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 5. Wander and Jitter Measured Transfer Characteristics 5 0 -3 Gain (dB) -5 -10 0.1 Hz 0.3 Hz -15 0.5 Hz 1.0 Hz -20 2.0 Hz 4.0 Hz 8.0 Hz -25 -30 17 Hz 0.01 0.1 10 1 100 1000 Frequency (Hz) 1. ETSI 300 462-5, Section 9.1, requires that the shortterm phase error during switchover (i.e., Locked to Holdover to Locked) be limited to an accumulation rate no greater than 0.05 ppm during a 15 second interval. 2. ETSI 300 462-5, Section 9.2, requires that the longterm phase error in the Holdover mode should not exceed 3. ANSI Tin1.101-1994, Section 8.2.2, requires that the phase variation be limited so that no more than 255 slips (of 125 s each) occur during the first day of Holdover. This requires a frequency accuracy better than: ((24x60x60)+(255x125s))/(24x60x60) = 0.37 ppm Temperature variation is not restricted, except to within the normal bounds of 0 to 50 C. {(a1+a2)S+0.5bS2+c} 4. Telcordia GR.1244.CORE, Section 5.2., Table 4, shows that an initial frequency offset of 50 ppb is permitted on entering Holdover, whilst a drift over temperature of 280 ppb is allowed; an allowance of 40 ppb is permitted for all other effects. where a1 = 50 ns/s (allowance for initial frequency offset) a2 = 2000 ns/s (allowance for temperature variation) 5. ITU G.822, Section 2.6, requires that the slip rate during category(b) operation (interpreted as being applicable to Holdover mode operation) be limited to less than 30 slips (of 125 s each) per hour b = 1.16x10-4 ns/s2 (allowance for ageing) c = 120 ns (allowance for entry into Holdover mode). ((((60 x 60)/30)+125s)/(60x60)) = 1.042 ppm Revision 2.00/September 2003 Semtech Corp. 19 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 6. Maximum Time Interval Error of T OUT0 output port 1 00 G .81 3 op tio n 1, co n sta nt te m pe rature w and er lim it T im e (ns) 10 1 M T IE m e as urem e nt o n 15 5 M H z o utpu t, 1 9.4 4 M H z i/p (8 kH z locking), V ectro n 6 664 xtal 0 .1 0 .0 1 0 .0 1 1 0 .1 10 1 00 0 1 00 00 O b se rv ation in terva l (s) 1 00 Figure 7. Time Deviation of T OUT0 output port 10 G .813 op tion 1 co nsta nt tem pe rature w ander lim it T im e (n s) 1 0.1 T D E V m easurem en t on 15 5 M H z o utput, 19 .4 4 M H z i/p (8kH z locking), V ectron 66 64 xtal 0.01 0.01 0.1 1 10 10 0 10 00 10 000 O bservation interval (s) Figure 8. Phase error accumulation of T OUT0 output port in Holdover mode P h a s e E rro r (n s ) 10000000 1000000 P e rm itte d P h a s e E rro r L im it 100000 10000 1000 100 Revision 2.00/September 2003 Semtech Corp. T y p ic a l m e a s u re m e n t, 2 5 C c o n s ta n t te m p e ra tu re 10000 1000 20 100000 O b s e rv a tio n in te rv a l (s ) www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Phase Build Out Phase Build Out (PBO) is the function to minimise phase transients on the output SEC clock during input reference switching. If the currently selected input reference clock source is lost (due to a short interruption, out of frequency detection, or complete loss of reference), the second, next highest priority reference source will be selected. During this transition, the Lost_Phase mode is entered. The typical phase disturbance on clock reference source switching will be less than 12 ns on the ACS8510. For clock reference switching caused by the main input failing or being disconnected, then the phase disturbance on the output will still be less than the 120 ns allowed for in the G.813 spec. The actual value is dependent on the frequency being locked to. ITU-T G.813 states that the max allowable short term phase transient response, resulting from a switch from one clock source to another, with Holdover mode entered in between, should be a maximum of 1 s over a 15 second interval. The maximum phase transient or jump should be less than 120 ns at a rate of change of less than 7.5 ppm and the Holdover performance should be better than 0.05 ppm. On the ACS8510, PBO can be enabled, disabled or frozen using the P interface. By default, it is enabled. When PBO is enabled, it can also be frozen, which will disable the PBO operation on the next input reference switch, but will remain with the current offset. If PBO is disabled while the device is in the Locked mode, there will be a phase jump on the output SEC clocks as the DPLL locks back to 0 degree phase error. Table 10. Microprocessor Interface Mode Selection UPSEL(2:0) Mode Description 111 110 101 100 011 010 001 000 OFF OFF SERIAL MOTOROLA INTEL MULTIPLEXED EPROM OFF Interface disabled Interface disabled Serial uP bus interface Motorola interface Intel compatible bus interface Multiplexed bus interface EPROM read mode Interface disabled (7) (6) (5) (4) (3) (2) (1) (0) Motorola Mode Parallel data + address: this mode is suitable for use with Motorola's 68x0 type bus. Intel Mode Parallel data + address: this mode is suitable for use with Intel's 80x86 type bus. Multiplexed Mode Data/address: this mode is suitable for use with microprocessors which share bus signals between address and data (e.g., Intel's 80x86 family). Serial Mode This mode is suitable for use with microprocessor which use a serial interface. EPROM Mode This mode is suitable for simple standalone applications where it is required to change the default loading of the register values to suit different applications. Microprocessor Interface This can be done by loading values from an external ROM. The data is read from the ROM automatically after power up when the UPSEL(2:0) pins are set to `001'. Each register value is stored sequentially, with ROM address 0 corresponding to register address 0 and so on. The ACS8510 incorporates a microprocessor interface, which can be configured for the following modes via the bus interface mode control pins UPSEL(2:0) as defined in Table 10. The value in the `chip_id' location (address 00 & 01) is checked to see if it matches the ID number of the ACS8510 V2 (value 213E). Upon a successful number match, the remaining data Revision 2.00/September 2003 Semtech Corp. 21 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS from the ROM is used to set the internal register values. Only 64 locations in the ROM are required. Register Set All registers are 8-bits wide, organised with the most-significant bit positioned in the left-most bit, with bit significance decreasing towards the right most bit. Some registers carry several individual data fields of various sizes, from single-bit values (e.g. flags) upwards. Several data fields are spread across multiple registers; their organisation is shown in the register map, Table 11. Configuration Registers Each configuration register reverts to a default value on power-up or following a reset. Most default values are fixed, but some will be pinsettable. All configuration registers can be read out over the microprocessor port. Status Registers The Status Registers contain readable registers. They may all be read from outside the chip but are not writeable from outside the chip (except for a clearing operation). All status registers are read via shadow registers to avoid data hits due to dynamic operation. Each individual status register has a unique location. Register Access Most registers are of one of two types, configuration registers or status registers, the exceptions being the chip_ID and chip_revision registers. Configuration registers may be written to or read from at any time (the complete 8-bit register must be written, even if only one bit is being modified). All status registers may be read at any time and, in some status registers (such as the sts_interrupts register), any individual data field may be cleared by writing a `1' into each bit of the field (writing a `0' value into a bit will not affect the value of the bit). A description of each register is given in the Register Map, and Register Map Description. Revision 2.00/September 2003 Semtech Corp. 22 Interrupt Enable and Clear Interrupt requests are flagged on pin INTREQ (active High). Bits in the interrupt status register are set (high) by the following conditions: 1. Any reference source becoming valid or going invalid 2. A change in the operating state (eg. Locked, Holdover etc.) 3. A brief loss of the currently selected reference source 4. An AMI input error All interrupt sources are maskable via the mask register, each one being enabled by writing a '1' to the appropriate bit. Any unmasked bit set in the interrupt status register will cause the interrupt request pin to be asserted (high). All interrupts are cleared by writing a '1' to the bit(s) to be cleared in the status register. When all pending unmasked interrupts are cleared the interrupt pin will go inactive (low). The loss of the currently selected reference source will eventually cause the input to be considered invalid, triggering an interrupt. The time taken to raise this interrupt is dependant on the leaky bucket configuration of the activity monitors. The fastest leaky bucket setting will still take up to 128 ms to trigger the interrupt. The interrupt caused by the brief loss of the currently selected reference source is provided to facilitate very fast source failure detection if desired. It is triggered after missing just a couple of cycles of the reference source. Some applications require the facility to switch downstream devices based on the status of the reference sources. In order to provide extra flexibility, it is possible to flag the `main reference failed' interrupt (addr 06, bit 6) on the pin TDO. This is simply a copy of the status bit in the interrupt register and is independent of the mask register settings. The bit is reset by writing to the interrupt status register in the normal way. This feature can be enabled and disabled by writing to bit 6 of register 48Hex. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Register Map Shaded areas in the map are `don't care' and writing either 0 or 1 will not affect any function of the device. Bits labelled `Set to 0' or `Set to 1' must be set as stated during initialisation of the device, either following power up, or after a power on reset (POR). Failure to correctly set these bits may result in the device operating in an unexpected way. Some registers do not appear in this list. These are either not used, or have test functionality. Do not write to any undefined registers as this may cause the device to operate in a test mode. If an undefined register has been inadvertently addressed, the device should be reset to ensure the undefined registers are at default values. Table 11. Register Map A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 00 6 5 4 chip_id (read only) 1 0 ( l sb ) 8k Edge Polarity Set to '0' Set to '0' Set to '0' Set to '1' Set to '0' Device p ar t number (15:8) 02 chip _revision (read only) 03 cnfg_control1 (read/write) 04 cnfg_control2 (read/write) 05 sts_interrupts (read/write) 06 08 sts_T4_inputs (read/write) 09 sts_op erating_mode (read only) 0A sts_p riority_table (read only) Chip revision number (7:0) Mu l t i p l e E1/T1 O/P Analog div sync Set to '0' Phase loss flag limit <I_8> valid change <I_7> valid change <I_6> valid change <I_5> valid change <I_4> valid change <I_3> valid change <I_2> valid change <I_1> valid change Operating mode Main ref. failed <I_14> valid change <I_13> valid change <I_12> valid change <I_11> valid change <I_10> valid change <I_9> valid change T4 ref failed Ami2 Violation Ami2 L.O.S. Ami1 Violation Ami1 L.O.S. Op erating mode (2:0) 0B Highest priority valid source Currently selected reference source 3rd highest priority valid source 2nd highest p riority valid source sts_curr_inc_offset (read only) Current increment offset (7:0) 0D Current increment offset (15:8) 07 0E 2 Device par t number (7:0) 01 0C 3 Current increment offset (18:16) sts_sources_valid (read only) <I_8> <I_7> 0F Revision 2.00/September 2003 Semtech Corp. <I_6> <I_5> <I_4> <I_3> <I_2> <I_1> <I_14> <I_13> <I_12> <I_11> <I_10> <I_9> 23 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 11. Register Map (continued). A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 10 6 sts_reference_sources (read/write) 5 4 3 2 1 status <I_2> status <I_1> 11 status <I_4> status <I_3> 12 status <I_6> status <I_5> 13 status <I_8> status <I_7> 14 status <I_10> status <I_9> 15 status <I_12> status <I_11> 16 status <I_14> status <I_13> p rogrammed_p riority <I_2> p rogrammed_p riority <I_1> 19 p rogrammed_p riority <I_4> p rogrammed_p riority <I_3> 1A p rogrammed_p riority <I_6> p rogrammed_p riority <I_5> 1B p rogrammed_p riority <I_8> p rogrammed_p riority <I_7> 1C p rogrammed_p riority <I_10> p rogrammed_p riority <I_9> 1D p rogrammed_p riority <I_12> p rogrammed_p riority <I_11> 1E p rogrammed_p riority <I_14> p rogrammed_p riority <I_13> 18 20 cnfg_ref_selection_p riority (read/write) cnfg_ref_source_frequency (read/write) 0 ( l sb ) divn lock8k bucket_id <I_1>(1:0) reference_source_frequency <I_1>(3:0) 21 divn lock8k bucket_id <I_2>(1:0) reference_source_frequency <I_2>(3:0) 22 divn lock8k bucket_id <I_3>(1:0) reference_source_frequency <I_3>(3:0) 23 divn lock8k bucket_id <I_4>(1:0) reference_source_frequency <I_4>(3:0) 24 divn lock8k bucket_id <I_5>(1:0) reference_source_frequency <I_5>(3:0) 25 divn lock8k bucket_id <I_6>(1:0) reference_source_frequency <I_6>(3:0) 26 divn lock8k bucket_id <I_7>(1:0) reference_source_frequency <I_7>(3:0) 27 divn lock8k bucket_id <I_8>(1:0) reference_source_frequency <I_8>(3:0) 28 divn lock8k bucket_id <I_9>(1:0) reference_source_frequency <I_9>(3:0) 29 divn lock8k bucket_id <I_10>(1:0) reference_source_frequency <I_10>(3:0) 2A divn lock8k bucket_id <I_11>(1:0) reference_source_frequency <I_11>(3:0) 2B divn lock8k bucket_id <I_12>(1:0) reference_source_frequency <I_12>(3:0) 2C divn lock8k bucket_id <I_13>(1:0) reference_source_frequency <I_13>(3:0) 2D divn lock8k bucket_id <I_14>(1:0) reference_source_frequency <I_14>(3:0) Revision 2.00/September 2003 Semtech Corp. 24 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 11. Register Map (continued). A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 30 31 5 4 cnfg_sts_remote_sources_ valid (read/write) 32 cnfg_op erating_mode (read/write) 33 cnfg_ref_selection (read/write) 34 cnfg_mode (read/write) 35 cnfg_T4 (read/write) 36 cnfg_differential_inp uts (read/write) 37 cnfg_uPsel_p ins (read only) 38 cnfg_T0_outp ut_enable (read/write) 39 cnfg_T0_outp ut_frequencies (read/write) 3A cnfg_differential_outp uts (read/write) 3B cnfg_bandwidth (read/write) 3C 6 1 Forced op erating mode force_select_reference_source A u to external 2K enable Phase alarm timeout enable Clock edge Holdover Offset enable Squelch Select T0/T1 SON ET/ SDH I/P External 2K Sync enable Master/ Slave Force T1 inp ut source selection (only valid for inp uts I_5 to I_10) <I_5> PECL Micro-p rocessor typ e 311.04MHz on T06 1=SON ET 0=SDH for Dig2 1=SON ET 0=SDH for Dig1 T01 Digital2 Digital1 T07 Frequency selection T06 Frequency selection Auto b/w switch Acq/lock T03 19.44MHz T02 T04 38.88MHz T02 Acquisition bandwidth T07 LVDS enable T07 PECL enable Set to '0' T05 77.76MHz T01 T06 LVDS enable T06 PECL enable N ormal/locked bandwidth N ominal frequency (7:0) N ominal frequency (15:8) cnfg_holdover_offset (read/write) Holdover offset (7:0) Holdover offset (15:8) A u to Holdover Averaging Holdover offset (18:16) cnfg_freq_limit (read/write) DPLL Frequency offset limit (7:0) 42 DPLL Frequency offset limit (9:8) cnfg_interrup t_mask (read/write) 44 <I_8> valid change <I_7> valid change <I_6> valid change <I_5> valid change <I_4> valid change <I_3> valid change <I_2> valid change <I_1> valid change Op erating mode Main ref. failed <I_14> valid change <I_13> valid change <I_12> valid change <I_11> valid change <I_10> valid change <I_9> valid change T4 ref Ami2 Violation A mi 2 L.O.S A mi 1 Violation A mi 1 L.O.S 45 46 Reversion mode <I_6> PECL cnfg_nominal_frequency (read/write) 40 43 0 ( l sb ) Remote status, channels <14:9> 3F 41 2 Remote status, channels <8:1> 3D 3E 3 cnfg_freq_divn (read/write) Divide-inp ut-by-n ratio (7:0) 47 Revision 2.00/September 2003 Semtech Corp. Divide-inp ut-by-n ratio (13:8) 25 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 11. Register Map (continued). A d d r. P a r a m e t e r N a m e ( Hex ) Dat a B i t 7 ( m sb ) 48 cnfg_monitors (read/write) 6 5 4 3 2 Flag ref lost on TDO Ultra-fast switching External source switch enable Freeze phase buildout Phase buildout enable 50 cnfg_activ_upper_threshold0 (read/write) Configuration 0: Activity alarm set threshold (7:0) 51 cnfg_activ_lower_threshold0 (read/write) Configuration 0: Activity alarm reset threshold (7:0) 52 cnfg_bucket_size0 (read/write) 53 cnfg_decay_rate0 (read/write) 54 cnfg_activ_upper_threshold1 (read/write) Configuration 1: Activity alarm set threshold (7:0) 55 cnfg_activ_lower_threshold1 (read/write) Configuration 1: Activity alarm reset threshold (7:0) 56 cnfg_bucket_size1 (read/write) 57 cnfg_decay_rate1 (read/write) 58 cnfg_activ_upper_threshold2 (read/write) Configuration 2: Activity alarm set threshold (7:0) 59 cnfg_activ_lower_threshold2 (read/write) Configuration 2: Activity alarm reset threshold (7:0) 5A cnfg_bucket_size2 (read/write) 5B cnfg_decay_rate2 (read/write) 5C cnfg_activ_upper_threshold3 (read/write) Configuration 3: Activity alarm set threshold (7:0) 5D cnfg_activ_lower_threshold3 (read/write) Configuration 3: Activity alarm reset threshold (7:0) 5E cnfg_bucket_size3 (read/write) 5F cnfg_decay_rate3 (read/write) 7F cnfg_uPsel (read/write) Revision 2.00/September 2003 Semtech Corp. 1 0 ( l sb ) Frequency monitors configuration (1:0) Configuration 0: Activity alarm bucket size (7:0) Cfg 0:decay_rate (1:0) Configuration 1: Activity alarm bucket size (7:0) Cfg 1:decay_rate (1:0) Configuration 2: Activity alarm bucket size (7:0) Cfg 2:decay_rate (1:0) Configuration 3: Activity alarm bucket size (7:0) Cfg 3:decay_rate (1:0) Micro-processor type 26 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Register Map Description Table 12. Register Map Description Addr. Parameter Name (Hex) chip_id 00 01 chip_revision 02 cnfg_control1 Description Default Value (bin) This register contains the chip ID = 8510 (decimal) Bits (7:0) Chip ID bits (7:0) 00111110 Bits (7:0) Chip ID bits (15:8) 00100001 This read only register contains the chip revision number This revision = 1 Last revision (engineering samples) = 0 Bits (7:6) 00000001 Unused Bi t 5 =1 32/24MHz to APLL: Feeds 2x Dig2 frequency to the APLL instead of the normal 77.76Mhz. Thus the normal OC3/STM1 outputs are replaced with multiple E1/T1 rates. Note: Dig2 set bits (Reg. 39h Bits (7:6)) must be set to 11 for this mode. =0 77.76MHz to APLL Bi t 4 =1 Synchronizes the dividers in the output APLL section to the dividers in the DPLL section such that their phases align. This is necessary in order to have phase alignment between inputs and output clocks at OC3 derived rates (6.48 MHz to 77.76 MHz). Keeping this bit high may be necessary to avoid the dividers getting out of synchronization when quick changes in frequency occur such as a force into Free-Run. =0 The dividers may get out of phase following step changes in frequency, but in this mode the correct number of high frequency edges is guarenteed within any synchronization period. The output will frequency lock (default). The device will always remain in synchronization 2 seconds from a reset, before the default setting applies. 03 Bits 3 X X 000000 Test control - leave unchanged, or set to '0' Bi t 2 =1 When in 8k locking mode the system will lock to the rising input clock edge. =0 When in 8k locking mode the system will lock to the falling input clock edge. cnfg_control2 Bits (1:0) Test controls - leave unchanged, or set to '00' Bits (7:6) Unused Bits (5:3) define the phase loss flag limit. By default set to 4 (100) which corresponds to approximately 140. A lower value sets a corresponding lower phase limit. The flag limit determines the value at which the DPLL indicates phase lost as a result of input jitter, a phase jump, or a frequency jump on the input 04 Bits (2:0) sts_interrupts X X 100010 Test controls - leave unchanged, or set to '010' This register contains one bit for each bit of sts_sources_valid, one for loss of reference the device was locked to, and another for the operating mode. All bits are active high. All bits except the main_ref_failed bit (bit 14) are set on a 'change' in the state of the relevent status bit, i.e. if a source becomes valid, or goes invalid it will trigger an interrupt. If the Operating Mode (register 9) changes state the interrupt will be generated. Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to more quickly than the activity monitors can support. If bit 6 of the cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO pin of the device. All bits are maskable by the bits in the cnfg_interrupt_mask register. Each bit may be cleared individually by writing a '1' to that bit, thus resetting the interrupt. Any number of bits can be cleared with a single write operation. Writing '0's will have no effect. 05 Bits (7:0) <I_8> to <I_1> 00000000 06 Bits (7:0) Operating mode, main ref failed, <I_14> to <I_9> 00000000 Revision 2.00/September 2003 Semtech Corp. 27 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) Description sts_T4_inputs This register holds the status flags of the AMI inputs and the TOUT4 reference. The alarms once set will hold their state until reset. Each bit may be cleared individually by writing a '1' to that bit, thus resetting the interrupt. Writing '0's will have no effect. These bits can also generate interrupts. Bits (7:5) Bi t 4 =1 =0 Bi t 3 =1 =0 Bi t 2 =1 =0 Bi t 1 =1 =0 Bi t 0 =1 =0 08 sts_operating_mode 09 sts_priority_table Default Value (bin) Unused. T4 reference failed - no valid TIN1 input (<I_10>:<I_5>), T4 DPLL cannot lock to source (default) T4 reference good - valid TIN1 input available. X X X 10000 Ami2 Violation detected Ami2 clear (default) Ami2 Loss of signal Ami2 clear (default) Ami1 Violation detected Ami1 clear (default) Ami1 Loss of signal Ami1 clear (default) This read-only register holds the current operating state of the main state machine. Figure 11 shows how the values of the 'operating state' variable match with the individual states. Bits (7:3) Unused. Bits (2:0) 001 010 100 110 101 111 State Free-Run (default) Holdover L o cke d Pre-locked Pre-locked2 Phase lost X X X X X 001 This is a 16-bit read-only register. Bits (15:12) Third highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the second-highest-priority valid source. Bits (11:8) Second highest priority valid source: this is the channel number of the input reference source which is valid and has the next-highest priority to the highest-priority valid source. Bits (7:4) Highest priority valid source: this is the channel number of the input reference source which is valid and has the highest priority - it may not be the same as the currently selected reference source (due to failure history or changes in programmed priority). Bits (3:0) Currently selected reference source: this is the channel number of the input reference source which is currently input to DPLL. Note that these registers are updated by the state machine in response to the contents of the cnfg_ref_selection_priority register and the ongoing status of individual channels; channel number '0000', appearing in any of these registers, indicates that no channel is available for that priority. 0A Bits (7:4) Bits (3:0) Highest priority valid source (sts_priority_table bits (7:4)) Currently selected reference source (sts_priority_table bits (3:0)) 00000000 0B Bits (7:4) Bits (3:0) 3rd-highest priority valid source (sts_priority_table bits (15:12)) 2nd-highest priority valid source (sts_priority_table bits (11:8)) 00000000 Revision 2.00/September 2003 Semtech Corp. 28 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) sts_curr_inc_offset Description Default Value (bin) This read-only register contains a signed-integer value representing the 19 significant bits of the current increment offset of the digital PLL. The register may be read periodically to build up a historical database for later use during holdover periods (this would only be necessary if an external oscillator which did not meet the stability criteria described in Local Oscillator Clock section is used). The register will read 00000000 immediately after reset. 0C Bits (7:0) sts_curr_inc_offset bits (7:0) 00000000 0D Bits (7:0) sts_curr_inc_offset bits (15:8) 00000000 07 Bits (7:3) Bits (2:0) Unused sts_curr_inc_offset bits (18:16) X X X X X 000 sts_sources_valid This register contains a bit to show validity for every reference source. =1 Valid source =0 Invalid source (default) 0E Bits (7:0) <I_8> to <I_1> 00000000 0F Bits (7:6) Bits (5:0) Unused <I_14> to <I_9> X X 000000 sts_reference_sources This is a 7-byte register which holds the status of each of the 14 input reference sources. The status of each reference source is shown in a 4-bit field. Each bit is active high.To aid status checking, a copy of each status bit 3 is provided in the sts_sources_valid register. The status is reported as follows: (Each bit may be cleared individually) Status bit 3 Status bit 2 Status bit 1 Status bit 0 = Source valid (no alarms) (bit 3 is combination of bits (2:0)) (default 0) = out-of-band alarm (default 1) = no activity alarm (default 1) = phase lock alarm (default 0) 10 Bits (7:4) Bits (3:0) Status of input reference source <I_2> Status of input reference source <I_1> 01100110 11 Bits (7:4) Bits (3:0) Status of input reference source <I_4> Status of input reference source <I_3> 01100110 Bits (7:4) Bits (3:0) Status of input reference source <I_6> Status of input reference source <I_5> 01100110 13 Bits (7:4) Bits (3:0) Status of input reference source <I_8> Status of input reference source <I_7> 01100110 14 Bits (7:4) Bits (3:0) Status of input reference source <I_10> Status of input reference source <I_9> 01100110 15 Bits (7:4) Bits (3:0) Status of input reference source <I_12> Status of input reference source <I_11> 01100110 16 Bits (7:4) Bits (3:0) Status of input reference source <I_14> Status of input reference source <I_13> 01100110 12 sts_reference_sources (continued) cnfg_ref_selection_priority This register holds the priority of each of the 14 input reference sources. The priority values are all relative to each other, with lower-valued numbers taking higher priorities. Only the values '1' to '15' (dec) are valid - '0' disables the reference source. Each reference source should be given a unique number, however two sources given the same priority number will be assigned on a first in first out basis. It is recommended to reserve the priority value '1' as this is used when forcing reference selection via the cnfg_ref_selection register. If the user does not intend to use the cnfg_ref_selection register then the priority value '1' need not be reserved. Bits (7:4) Programmed priority of input reference source <I_2> Bits (3:0) Programmed priority of input reference source <I_1> Bits (7:4) Programmed priority of input reference source <I_4> Bits (3:0) Programmed priority of input reference source <I_3> Bits (7:4) Programmed priority of input reference source <I_6> Bits (3:0) Programmed priority of input reference source <I_5> Bits (7:4) Programmed priority of input reference source <I_8> Bits (3:0) Programmed priority of input reference source <I_7> 18 00110010 19 01010100 1A 01110110 1B 10011000 Revision 2.00/September 2003 Semtech Corp. 29 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) 1C cnfg_ref_selection_priority (continued) Description Bits (7:4) Programmed priority of input reference source <I_10> Bits (3:0) Programmed priority of input reference source <I_9> Bits (7:4) Programmed priority of input reference source <I_12> Bits (3:0) Programmed priority of input reference source <I_11> Bits (7:4) Programmed priority of input reference source <I_14> Bits (3:0) Programmed priority of input reference source <I_13> Default Value (bin) 10111010 11010001 (MSTSLVB=0) 11011100 (MSTSLVB=1) 1D 1E 11111110 cnfg_ref_source_frequency This register is used to set up each of the 14 input reference sources. Bits (7:6) of each byte defines the operation undertaken on the input frequency, in accordance with the following key: 00 01 10 11 The input frequency is fed directly into the DPLL. (default). The input frequency is internally divided down to 8 kHz, before being fed into the DPLL. (For high jitter tolerance). Unsupported configuration - do not use. Uses the division coefficient stored in registers 46 and 47 (cnfg_freq_divn) to divide the input by this value prior to being fed into the DPLL. The frequency monitors must be disabled. The divided down frequency should equal 8 kHz. The frequency (3:0) should be set to the nearest spot frequency just below the actual input frequency. The DivN feature works for input frequencies between 1.544 MHz and 100 MHz. Bits (5:4) define which leaky bucket group (0-3) is used, as defined in registers 50 to 5F. (default 00). Bits (3:0) defines the frequency of the reference source in accordance with the following: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 8 kHz (fixed <I_1>, <I_2>, default <I_3>, <I_4>) 1.544 MHz (SONET)/2.048 MHz (SDH) (as defined by register 34, bit 2) (default <I_12>, <I_13>, <I_14>) 6.48 MHz (default <I_11> when MSTSLVB = 1) 19.44 MHz (default <I_11> when MSTSLVB=0, and <I_5>, <I_6>, <I_7>, <I_8>, <I_9>, <I_10>) 25.92 MHz 38.88 MHz 51.84 MHz 77.76 MHz 155.52 MHz 2 kHz 4 kHz 20 Frequency of reference source <I_1> - fixed at 00000000 for 8kHz only 00000000 21 Frequency of reference source <I_2> - fixed at 00000000 for 8kHz only 00000000 22 Frequency of reference source <I_3> 00000000 23 Frequency of reference source <I_4> 00000000 24 Frequency of reference source <I_5> 00000011 25 Frequency of reference source <I_6> 00000011 26 Frequency of reference source <I_7> 00000011 27 Frequency of reference source <I_8> 00000011 28 Frequency of reference source <I_9> 00000011 29 Frequency of reference source <I_10> 00000011 Frequency of reference source <I_11> 00000010 (MSTSLVB=0) 00000011 (MSTSLVB=1) 2A Revision 2.00/September 2003 Semtech Corp. 30 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) 2B cnfg_ref_source_frequency (continued) Description Default Value (bin) Frequency of reference source <I_12> 00000001 2C Frequency of reference source <I_13> 00000001 2D Frequency of reference source <I_14> 00000001 cnfg_sts_remote_sources_ valid This register holds the status of the reference sources supplied to the other device in a master/slave configuration. It is a copy of the other device's sts_sources_valid register. The register is part of the protection mechanism. 30 Bits (7:0) Reference sources <I_8>:<I_1> 11111111 31 Bits (7:6) Bits (5:0) Unused Reference sources <I_14>:<I_9> XX111111 cnfg_operating_mode 32 This register is used to force the device into a desired operating state, represented by the binary values shown in Figure 11. Value 0 (hex) allows the control state machine to operate automatically. Bits (7:3) Bits (2:0) cnfg_ref_selection X X X X X 000 Unused Desired operating state (as per Figure 11) This register is used to force the device to select a particular input reference source, irrespective of its priority. Writing to this register temporarily raises the selected input to priority '1'. Provided no other input is already programmed with priority '1', and revertive mode is on, this source will be selected. 33 XXXX1111 cnfg_mode Bits (7:4) Unused Bits (3:0) allows Desired reference source (0000 and 1111 disables the force selection, and automatic selection of all sources, default is 1111) This register contains several individual configuration fields, as detailed below: Bi t 7 =1 Auto 2 kHz Sync enable: External 2 kHz Sync will be enabled only when the source is locked to 6.48 MHz. Otherwise it will be disabled (default) =0 Auto 2 kHz Sync disable: The user controls this function using bit 3 of this register, as described below Bi t 6 =1 Phase Alarm Timeout enable: The phase alarm will timeout after 100 seconds (default) =0 Phase Alarm Timeout disable: The phase alarm will not timeout and must be reset by software 34 Bi t 5 =1 Rising Clock Edge selected: The device will reference to the rising edge of the external 12.8 MHz crystal oscillator signal =0 Falling edge Edge selected: The device will reference to the falling edge of the external 12.8 MHz crystal oscillator signal (default) Bi t 4 =1 Holdover offset enable: The device will adopt the Holdover offset value stored in the cnfg_holdover_offset register, in order to set the frequency in Holdover =0 Holdover offset disable: The device will ignore the value and Holdover will freeze the frequency of the DPLL on entering Holdover mode (default) 11001000 (MSTSLVB=0) (SONSDHB=0) 11001100 (MSTSLVB=0) (SONSDHB=1) 11000010 (MSTSLVB=1) (SONSDHB=0) 11000110 (MSTSLVB=1) (SONSDHB=1) Bi t 3 = 1 External 2 kHz Sync Enable: The device will align the phase of its internally generated Frame Sync signal (8 kHz) and Multi-Frame Sync signal (2 kHz) with that of the signal supplied to the Sync2K pin. The device should be locked to a 6.48 MHz output from another A C S 8510. = 0 External 2 kHz Sync Disable: The device will ignore the Sync2k pin. Revision 2.00/September 2003 Semtech Corp. 31 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) cnfg_mode (continued) Description Default Value (bin) This register contains several individual configuration fields, as detailed below: Bi t 2 = 1 SONET Mode: The device expects the input frequency of any input channel given the value '0001' in the cnfg_ref_source_frequency register to be 1544 kHz = 0 SDH Mode: The device expects the input frequency of any input channel given the value '0001' in the cnfg_ref_source_frequency register to be 2048 kHz. At start up or reset the bit value will be defaulted to the setting of pin SONSDHB. This setting can subsequently be altered by changing this bit value 11001000 (MSTSLVB=0) (SONSDHB=0) 11001100 (MSTSLVB=0) (SONSDHB=1) Bi t 1 = 1 Master Mode: The device will adopt the master mode and make the active decisions of 11000010 which source to select, etc. This bit is writeable, but its default value is determined by the pin, (MSTSLVB=1) MSTSLVB (SONSDHB=0) = 0 Slave Mode: The device will adopt the slave mode and will follow the master device. At start up or reset the bit value will be defaulted to the setting of pin MSTSLVB. This setting 11000110 can subsequently be altered by changing this bit value (MSTSLVB=1) (SONSDHB=1) Bi t 0 = 1 Revertive Mode: The device will switch to the highest priority source available shown in the sts_priority_table register, bits (7:4) = 0 Non Revertive Mode: The device will retain the presently selected source (default) 34 cnfg_T4 35 This controls DPLL _T4 (output on TO8/TO9) and input source selection: Bits (7:6) Unused Bi t 5 =1 =0 DPLL_T4 is turned off (squelched) DPLL_T4 is on (default) Bi t 4 =1 =0 Selects which DPLL (T4 or T0) source feeds outputs TO8/TO9: DPLL_T0 output is fed to outputs TO8 and TO9 DPLL_T4 output is fed to outputs TO8 and TO9 X X 000000 Bits (3:0) Input source selection. The device will switch to the source shown in this field for the generation of the TOUT4 signal. If '0' it will select the highest priority active TIN1. cnfg_differential_inputs 36 cnfg_uPsel_pins 37 This register contains two individual configuration fields, as follows: Bits (7:2) Unused Bi t 1 =1 =0 Input <I_6> is PECL-compatible (Default) Input <I_6> is LVDS-compatible Bi t 0 =1 =0 Input <I_5> is PECL-compatible Input <I_5> is LVDS-compatible (Default) X X X X X X 10 This read only register returns a value indicating the microprocessor type selected at power up or reset. This is set by the configuration of the UPSEL pins (pins 58 - 60). If the UPSEL pin configuration is changed while the device is operating no effect will take place, but this register will reflect that change, so indicating the configuration that will be implemented at the next power up or reset. The microprocessor type can be changed with the device operational, though register 7F. Bits (7:3) Unused. Bit (2:0) 000 001 010 011 100 101 110 111 Microprocessor type OFF (interface disabled) EPROM MULTIPLEXED INTEL MOTOROLA SERIAL OFF (interface disabled) OFF (interface disabled) Revision 2.00/September 2003 Semtech Corp. 32 Bits(7:3)= XXXXX Bits(2:0)= UPSEL pi n configuration www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) cnfg_T0_output_enable Description This register contains several individual configuration fields, as follows: Bi t 7 =1 =0 Bi t 6 =1 =0 Bi t 5 =1 =0 Bi t 4 =1 =0 38 Default Value (bin) Bi t 3 =1 =0 T06 output frequency set to 311.04 MHz * T06 output frequency set by Address 3A (5:4) (default) SONET mode selected for Dig2 SDH mode selected for Dig2 (default) - see register cnfg_T0_output_frequencies SONET mode selected for Dig1 SDH mode selected for Dig1 (default) - see register cnfg_T0_output_frequencies Output port T01 enabled (default) Output port T01 disabled** - see register cnfg_T0_output_frequencies 00011111 Output port T02 enabled (default) Output port T02 disabled** - see register cnfg_T0_output_frequencies Bi t 2 =1 =0 Output port T03 enabled (19.44 MHz*) (default) Output port T03 disabled** Bi t 1 =1 =0 Output port T04 enabled (38.88 MHz*) (default) Output port T04 disabled** Bi t 0 =1 =0 Output port T05 enabled (77.76 MHz*) (default) Output port T05 disabled** Notes: * Defaults frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 8. ** "Disabled" means that the output port holds a static logic value (the port is not Tri-stated). cnfg_T0_output_frequencies 39 This register holds the frequency selections for each output port, as detailed below.* Bits (7:6) 00 01 10 11 D i g2 1544 kHz/2048 kHz (default) 3088 kHz/4096 kHz 6176 kHz/8192 kHz 12352 kHz/16384 kHz Bits (5:4) 00 01 10 11 D i g1 1544 kHz/2048 kHz (default) 3088 kHz/4096 kHz 6176 kHz/8192 kHz 12352 kHz/16384 kHz Bits (3:2) 00 01 10 11 T02 25.92 MHz 51.84 MHz 38.88 MHz (default) D i g2 Bits (1:0) 00 01 10 11 T01 6.48 MHz (default) 25.92 MHz 19.44 MHz D i g1 00001000 For Dig1/Dig2 the frequency values are shown for SONET/SDH. They are selected via the SONET/SDH bits in register cnfg_T0_output_enable. Note: * The above frequencies are changed to multiples of E1/T1 if the appropriate bit of the cnfg_control1 register is set to 1. For details, see Table 8. Revision 2.00/September 2003 Semtech Corp. 33 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) cnfg_differential_outputs 3A cnfg_bandwidth 3B cnfg_nominal_frequency Description Default Value (bin) This register holds the frequency selections and the port-technology type for the differential outputs, T06 and T07, as detailed below. Bits (7:6) 00 01 10 11 T07 155.52 MHz 51.84 MHz 77.76 MHz 19.44 MHz (default) Bits (5:4) 00 01 10 11 T06 38.88 MHz (default) 19.44 MHz 155.52 MHz D i g1 Bits (3:2) 00 01 10 11 T07 Port disabled PECL-compatible (default) LVDS-compatible Unused (1:0) 00 01 10 11 T06 Port disabled PECL-compatible LVDS-compatible (default) Unused 11000110 This register contains information used to control the operation of the digital PLL. When bandwidth selection is set to automatic, the DPLL will use the acquisition bandwidth setting when out of lock, and the normal/locked bandwidth setting when in lock. When set to manual, the DPLL will alway use the normal/locked bandwidth setting. Bi t 7 =1 =0 Automatic operation Manual operation (default) Bits (6:4) 000 001 010 011 100 101 110 111 Acquisition bandwidth 0.1 Hz 0.3 Hz 0.5Hz 1.0 Hz 2.0 Hz 4.0 Hz 8.0 Hz 17 Hz (default) Bi t 3 Unused Bit (2:0) 000 001 010 011 100 101 110 111 Loop bandwidth 0.1 Hz 0.3 Hz 0.5 Hz 1.0 Hz 2.0 Hz 4.0 Hz (default) 8.0 Hz 17 Hz 0111X101 This register holds a 16 bit unsigned integer allowing compensation for offset of the crystal oscillator from the nominal 12.8 MHz. See section Crystal Frequency Calibration. Default results in 0 ppm adjustment. 3C Bits (7:0) cnfg_nominal_frequency bits (7:0) 10011001 3D Bits (7:0) cnfg_nominal_frequency bits (15:8) 10011001 cnfg_holdover_offset This register holds a 19 bit signed integer, representing the holdover offset value, which can be used to set the holdover mode frequency when enabled via the holdover offset enabled bit in the cnfg_mode register. 3E Bits (7:0) cnfg_holdover_offset bits (7:0) 00000000 3F Bits (7:0) cnfg_holdover_offset bits (15:8) 00000000 Bi t 7 =1 Auto Holdover Averaging enable. This enables the frequency average to be taken from 32 samples. One sample taken every 32 seconds, after the frequency has been confirmed to be in-band by the frequency monitors. This gives a 17 minute history of the currently locked to reference source for use in Holdover. (default). =0 Auto Holdover Averaging disabled. 40 cnfg_freq_limit Bits (6:3) Unused Bits (2:0) cnfg_holdover_offset bits (18:16) 1X X X X 000 This register holds a 10 bit unsigned integer representing the pull-in range of the DPLL. It should be set according to the accuracy of crystal implemented in the application, using the following formula: Frequency range +/- (ppm) = (cnfg_freq_limit x 0.0785)+0.01647 or cnfg_freq_limit = (Frequency range +/- (ppm) - 0.01647) / 0.0785 Default value when SRCSW is left unconnected or tied low is 9.3 ppm. Default value when SRCSW is high is the full range of around 80 ppm. Revision 2.00/September 2003 Semtech Corp. 34 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) 41 cnfg_freq_limit (continued) Description Bits (7:0) cnfg_freq_limit bits (7:0) Bits (7:2) Unused Bits (1:0) cnfg_freq_limit bits (9:8) Default Value (bin) 01110101 (SRCSW low) 11111111 (SRCSW high) X X X X X X 00 (SRCSW low) XXXXXX11 (SRCSW high) 42 cnfg_interrupt-mask Each bit, if set to '0' will disable the appropriate interrupt source in either the interrupt status register or the sts_T4_inputs register. 43 Bits (7:0) cnfg_interrupt_mask bits (7:0) 11111111 44 Bits (7:0) cnfg_interrupt_mask bits (15:8) 11111111 45 Bits (7:5) Bits (4:0) Unused cnfg_interrupt_mask bits (20:16) XXX11111 cnfg_freq_divn This 14 bit integer is used as the divisor for any input applied to <I_14>:<I_1> to get the phase locking frequency desired. Only active for inputs with the DivN bit set to `1'. This will cause the input frequency to be divided by (N+1) prior to phase comparison, e.g. program N to: ((input freq)/ 8 kHz) -1 The reference_source_frequency bits should be set to reflect the closest spot frequency to the input frequency, but must be lower than the input frequency. 46 Bits (7:0) cnfg_freq_divn bits (7:0) 00000000 47 Bits (7:6) Bits (5:0) Unused cnfg_freq_divn bits (13:8) X X 000000 cnfg_monitors This 7 bit register allows global configuration of monitors and control of phase build out. Bit 7 Unused Bi t 6 =1 Enables value of the main_ref_failed interrupt to be driven out of pin TDO =0 Disables value of the main_ref_failed interrupt from being driven out of pin TDO (default) Bi t 5 =1 Enables ultra fast switching: Allows the DPLLto raise an inactivity alarm on the currently selected source after missing only a few cycles. See section on Ultra Fast Switching =0 Normal operation (default) 48 Bi t 4 =1 Forces locking to <I_3> if pin SRCSW high, or <I_4> if SRCSW low =0 Pin SRCSW ignored , and automatic control enabled X 0000101 (SRCSW low) X 0010101 (SRCSW high) Bi t 3 =1 Will freeze the output phase relationship with the current input to output phase offset =0 Allows changes in input to output phase offset (Normal phasebuild out mode) (default) Bi t 2 =1 Enables phase build out (default) =0 DPLL will always lock to 0 Bits (1:0) are for configuring frequency monitors- 00 = off, 01 = 15 ppm (default), others are reserved for future use. 50 cnfg_activ_upper_threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be raised 00000110 51 cnfg_activ_lower_threshold0 Bits (7:0) set the value in the leaky bucket that causes the activity alarm to be cleared 00000100 52 cnfg_bucket_size0 Bits (7:0) set the maximum value that the leaky bucket can reach given an inactive input 00001000 cnfg_decay_rate0 Bits (7:2) 53 Unused Bits (1:0) control the leak rate of the leaky bucket. The fill-rate of the bucket is +1 for every 128 ms interval that has experienced some level of inactivity. The decay rate is programmable in ratios of the fill rate. The ratio can be set to 1:1, 2:1, 4:1, 8:1 by using values of 00, 01, 10, 11 respectively. However, these buckets are not `true' leaky buckets in nature. The bucket stops `leaking' when it is being filled. This means that the fill and decay rates can be the same (00 = 1:1) with the net effect that an active input can be recognised at the same rate as an inactive one. Revision 2.00/September 2003 Semtech Corp. 35 X X X X X X 01 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 12. Register Map Description (continued). Addr. Parameter Name (Hex) Description Default Value (bin) 54 cnfg_activ_upper_threshold1 As for register 50 but for bucket 1 00000110 55 cnfg_activ_lower_threshold1 As for register 51 but for bucket 1 00000100 56 cnfg_bucket_size1 As for register 52 but for bucket 1 00001000 57 cnfg_decay_rate1 As for register 53 but for bucket 1 X X X X X X 01 58 cnfg_activ_upper_threshold2 As for register 50 but for bucket 2 00000110 59 cnfg_activ_lower_threshold2 As for register 51 but for bucket 2 00000100 5A cnfg_bucket_size2 As for register 52 but for bucket 2 00001000 5B cnfg_decay_rate2 As for register 53 but for bucket 2 X X X X X X 01 5C cnfg_activ_upper_threshold3 As for register 50 but for bucket 3 00000110 5D cnfg_activ_lower_threshold3 As for register 51 but for bucket 3 00000100 5E cnfg_bucket_size3 As for register 52 but for bucket 3 00001000 5F cnfg_decay_rate3 As for register 53 but for bucket 3 X X X X X X 01 cnfg_uPsel Bits (7:3) 7F Unused Bits (2:0) can be used to change the mode of the microprocessor interface. The interface will initially be set as the pins UPSEL (pins 58 - 60) - the pin set up can be read via register 37 (cnfg_uPsel_pins). At power up or reset the device will default to this setting. This register can be used to change the microprocessor mode after start up, supporting booting from EPROM and subsequently communicating via another mode. At start up the EPROM will down load the pre-programmed settings for all the registers, and as the last operation, action the change of interface with this last register. It is recommended that this function is only used for EPROM start up applications, as subsequent versions of this device may only allow operation in this way. The bits are defined in Table 9 or as given in register 37 of the register map description. Selection of Input Reference Clock Source Under normal operation, the input reference sources are selected automatically by an order of priority. But, for special circumstances, such as chip or board testing, the selection may be forced by configuration. Automatic operation selects a reference source based on its pre-defined priority and its current availability. A table is maintained which lists all reference sources in the order of priority. This is initially downloaded into the ACS8510 via the microprocessor interface by the Network Manager, and is subsequently modified by the results of the ongoing quality monitoring. In this way, when all the defined sources are active and valid, the source with the highest programmed priority is selected but, if this source fails, the next-highest source is selected, and so on. Restoration of repaired reference sources is handled carefully to avoid inadvertent disturbance of the output clock. The ACS8510 has two modes of operation; Revertive and Revision 2.00/September 2003 Semtech Corp. 36 Bits(7:3)= XXXXX Bits(2:0)= Pin dependent Non-Revertive. In Revertive mode, if a revalidated (or newly validated) source has a higher priority than the reference source which is currently selected, a switch over will take place. Many applications prefer to minimise the clock switching events and choose NonRevertive mode. In Non-Revertive mode , when a re-validated (or newly validated) source has a higher priority then the selected source will be maintained. The re-validation of the reference source will be flagged in the sts_sources_valid register and, if not masked, will generate an interrupt. Selection of the re-validated source can only take place under software control the software should briefly enable Revertive mode to affect a switch-over to the higher priority source. If the selected source fails under these conditions the device will indicate that it is still locked to the failed reference. It will not select the higher priority source until instructed to do so by the software; by briefly setting the Revertive mode bit. When there is a reference available with higher priority than the selected reference, there will be NO change of reference source as long as the Non-Revertive mode remains on AND the device will remain indicating www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS a locked state on the failed reference. This is the case even if there are lower priority references available or the currently selected reference fails. When the ONLY valid reference sources that are available have a lower priority than the selected reference, a failure of the selected reference will always trigger a switchover, regardless of whether Revertive or NonRevertive mode has been chosen. Also, in a Master/Slave redundancy-protection scheme, the Slave device(s) must follow the Master device. The alignment of the Master and Slave devices is part of the protection mechanism. The availability of each source is determined by a combination of local and remote monitoring of each source. Each input reference source supplied to each ACS8510 device is monitored locally and the results are made available to other devices. Forced Control Selection A configuration register, cnfg_ref_selection, controls both the choice of automatic or forced selection and the selection itself (when forced selection is required). The forced selection of an input reference source occurs when the cnfg_ref_selection variable contains a non-zero value, the value then representing the input port required to be selected. This is not the normal mode of operation, and the cnfg_ref_selection variable is defaulted to the all-one value on reset, thereby adopting the automatic selection of the reference source. Automatic Control Selection When an automatic selection is required, the cnfg_ref_selection register must be set to all zero or all one. The configuration registers, cnfg_ref_selection_priority, held in the P port block, consists of seven, 8 bit registers organised as one 4 bit register per input reference port. Each register holds a 4-bit value which represents the desired priority of that particular port. Unused ports should be given the value, '0000' or '1111', in the relevant register to indicate they are not to be included Revision 2.00/September 2003 Semtech Corp. 37 in the priority table. On power-up, or following a reset, the whole of the configuration file will be defaulted to the values defined by Table 4. The selection priority values are all relative to each other, with lower-valued numbers taking higher priorities. Each reference source should be given a unique number, the valid values are 1 to 15 (dec). A value of 0 disables the reference source. However if two or more inputs are given the same priority number those inputs will be selected on a first in, first out basis. If the first of two same priority number sources goes invalid the second will be switched in. If the first then becomes valid again, it becomes the second source on the first in, first out basis, and there will not be a switch. If a third source with the same priority number as the other two becomes valid, it joins the priority list on the same first in, first out basis. There is no implied priority based on the channel numbers. The input port <I_11> is for the connection of the synchronous clock of the TOUT0 output of the Master device (or the active-Slave device), to be used to align the TOUT0 output with the Master (or active-Slave) device if this device is acting in a subordinate-Slave or subordinateMaster role. Ultra Fast Switching A reference source is normally disqualified after the leaky bucket monitor thresholds have been crossed. An option for a faster disqualification has been implemented, whereby if register 48H, bit 5 (Ultra Fast Switching), is set then a loss of activity of just a few reference clock cycles will set the `no activity alarm' and cause a reference switch. This can be chosen to cause an interrupt to occur instead of or as well as causing the reference switch. The sts_interrupts register 05 Hex Bit 14 (main_ref_failed) of the interrupt status register is used to flag inactivity on the reference that the device is locked to much faster than the activity monitors can support. If bit 6 of the cnfg_monitors register (flag ref loss on TDO) is set, then the state of this bit is driven onto the TDO pin of the device. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS The flagging of the loss of the main reference failure on TDO is simply allowing the status of the sts_interrupt bit 14 to be reflected in the state of the TDO output pin. The pin will, therefore remain High until the interrupt is cleared. This functionality is not enabled by default so the usual JTAG functions can be used. When JTAG is normally used straight out of power-up, then this feature will have no bearing on the functionality. The TDO flagging feature will need to be disabled if JTAG is not enabled on power-up and the feature has since been enabled. When the TDO output from the ACS8510 is connected to the TDI pin of the next device in the JTAG scan chain, the implementation should be such that a logic change caused by the action of the interrupt on the TDI input should not effect the operation when JTAG is not active. External Protection Switching Fast external switching between inputs <I_3> and <I_4> can also be triggered directly from a dedicated pin (SRCSW). This mode can be activated either by holding this pin high during reset, or by writing to bit 4 of register address 48Hex. Once external protection switching is enabled, then the value of this pin directly selects either <I_3> (SRCSW high) or <I_4> (SRCSW low). If this mode is activated at reset by pulling the SRCSW pin high, then it configures the default frequency tolerance of <I_3> and <I_4> to +/- 80 ppm (register address 41Hex and 42Hex). Any of these registers can be subsequently set by external software if required. When external protection switching is enabled, the device will operate as a simple switch. All clock monitoring is disabled and the DPLL will simply be forced to try to lock on to the indicated reference source. Clock Quality Monitoring Clock quality is monitored and used to modify the priority tables of the local and remote ACS8510 devices. The following parameters are monitored: 1. Activity (toggling) 2. Frequency (This monitoring is only performed when there is no irregular operation of the clock or loss of clock condition) In addition, input ports <I_1> and <I_2> carry AMI-encoded composite clocks which are Figure 9. Inactivity and Irregularity Monitoring inactivities/irregularities reference source bucket_size leaky bucket response upper_threshold lower_threshold programmable fall slopes (all programmable) alarm Revision 2.00/September 2003 Semtech Corp. 38 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS monitored by the AMI-decoder blocks. Loss of signal is declared by the decoders when either the signal amplitude falls below +0.3 V or there is no activity for 1 ms. Any reference source which suffers a loss-ofsignal, loss-of-activity, loss-of-regularity or clockout-of-band condition will be declared as unavailable. Clock quality monitoring is a continuous process which is used to identify clock problems. There is a difference in dynamics between the selected clock and the other reference clocks. Anomalies occurring on non-selected reference sources affect only that source's suitability for selection, whereas anomalies occurring on the selected clock could have a detrimental impact on the accuracy of the output clock. Anomalies, whether affecting signal purity or signal frequency, could induce jitter or frequency offsets in the output clock, leading to anomalous behaviour. Anomalies on the selected clock, therefore, have to be detected as they occur and the phase locked loop must be temporarily isolated until the clock is once again pure. The clock monitoring process cannot be used for this because the high degree of accuracy required dictates that the process be slow. To achieve the immediacy required by the phase locked loop requires an alternative mechanism. The phase locked loop itself contains appropriate circuitry, based around the phase detector, and isolates itself from the selected reference source as soon as a signal impurity is detected. It can likewise respond to frequency offsets outside the permitted range since these result in saturation of the phase detector. When the phase locked loop is isolated from the reference source, it is essentially operating in a Holdover state; this is preferable to feeding the loop with a standby source, either temporarily or permanently, since excessive phase excursions on the output clock are avoided. Anomalies detected by the phase detector are integrated in a leaky bucket accumulator. Leaky bucket timing The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky bucket empty) will be: (cnfg_activ_upper_threshold N) secs 8 where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is 0.75 s. The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated as: (cnfg_decay_rate N) 2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N)) secs 8 where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown in the following: 1 2 x (8-4) = 1.0 s 8 Revision 2.00/September 2003 Semtech Corp. 39 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Occasional anomalies do not cause the accumulator to cross the alarm setting threshold, so the selected reference source is retained. Persistent anomalies cause the alarm setting threshold to be crossed and result in the selected reference source being rejected. Activity Monitoring The ACS8510 has a combined inactivity and irregularity monitor. The ACS8510 uses a `leaky bucket' accumulator, which is a digital circuit which mimics the operation of an analog integrator, in which input pulses increase the output amplitude but die away over time. Such integrators are used when alarms have to be triggered either by fairly regular defect events, which occur sufficiently close together, or by defect events which occur in bursts. Events which are sufficiently spread out should not trigger the alarm. By adjusting the alarm setting threshold, the point at which the alarm is triggered can be controlled. The point at which the alarm is cleared depends upon the decay rate and the alarm clearing threshold. On the alarm setting side, if several events occur close together, each event adds to the amplitude and the alarm will be triggered quickly; if events occur a little more spread out, but still sufficiently close together to overcome the decay, the alarm will be triggered eventually. If events occur at a rate which is not sufficient to overcome the decay, the alarm will not be triggered. On the alarm clearing side, if no defect events occur for a sufficient time, the amplitude will decay gradually and the alarm will be cleared when the amplitude falls below the alarm clearing threshold. The ability to decay the amplitude over time allows the importance of defect events to be reduced as time passes by. This means that, in the case of isolated events, the alarm will not be set, whereas, once the alarm becomes set, it will be held on until normal operation has persisted for a suitable time (but if the operation is still erratic, the alarm will remain set). See Figure 9. Revision 2.00/September 2003 Semtech Corp. 40 The `leaky bucket' accumulators are programmable for size, alarm set & reset thresholds and decay rate. Each source is monitored over a 128 ms period. If, within a 128 ms period, an irregularity occurs that is not deemed to be due to allowable jitter/wander, then the accumulator is incremented. The accumulator will continue to increment up to the point that it reaches the programmed bucket size. The `fill rate' of the leaky bucket is, therefore, 8 units/second. The `leak rate' of the leaky bucket is programmable to be in multiples of the fill rate (x1, x0.5, x0.25 and x0.125) to give a programmable leak rate from 8 units/sec down to 1 unit/sec. A conflict between trying to `leak' at the same time as a `fill' is avoided by preventing a `leak' when a `fill' event occurs. Disqualification of a non-selected reference source is based on inactivity, or on an out of band result from the frequency monitors. The currently selected reference source can be disqualified for phase, frequency, inactivity or if the source is outside the DPLL lock range. If the currently selected reference source is disqualified, the next highest priority, active reference source is selected. Frequency Monitoring The ACS8510 performs frequency monitoring to identify reference sources which have drifted outside the acceptable frequency range of +/- 16.6 ppm (measured with respect to the output clock). The sts_reference_sources outof-band alarm for a particular reference source is raised when the reference source is outside the acceptable frequency range. The ACS8510 DPLL has a programmable frequency limit of +/- 80 ppm. If the range is programmed to be > 16.6 ppm, the frequency monitors should be disabled so the input reference source is not automatically rejected as out of frequency range. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Modes of Operation Locked mode The ACS8510 has three primary modes of operation (Free-run, Locked and Holdover) supported by three secondary, temporary modes (Pre-Locked, Lost_Phase and PreLocked2). These are shown in the State Transition Diagram, Figure 11. The Locked mode is used when an input reference source has been selected and the PLL has had time to lock. When the Locked mode is achieved, the output signal is in phase and locked to the selected input reference source. The selected input reference source is determined by the priority table. When the ACS8510 is in Locked mode, the output frequency and phase follows that of the selected input reference source. Variations of the external crystal frequency have a minimal effect on the output frequency. Only the minimum to maximum frequency range is affected. Note that the term, 'in phase', is not applied in the conventional sense when the ACS8510 is used as a frequency translator (e.g., when the input frequency is 2.048 MHz and the output frequency is 19.44 MHz) as the input and output cycles will be constantly moving past each other; however, this variation will itself be cyclical over time unless the input and output are not locked. The ACS8510 can operate in Forced or Automatic control. On reset, the ACS8510 reverts to Automatic Control, where transitions between states are controlled completely automatically. Forced Control can be invoked by configuration, allowing transitions to be performed under external control. This is not the normal mode of operation, but is provided for special occasions such as testing, or where a high degree of hands-on control is required. Free-run mode The Free-run mode is typically used following a power-on-reset or a device reset before network synchronization has been achieved. In the Free-run mode, the timing and synchronization signals generated from the ACS8510 are based on the Master clock frequency provided from the external oscillator and are not synchronized to an input reference source. The frequency of the output clock is a fixed multiple of the frequency of the external oscillator, and the accuracy of the output clock is equal to the accuracy of the Master clock. The transition from Free-run to Pre-locked occurs when the ACS8510 selects a reference source. Pre-Locked mode The ACS8510 will enter the Locked state in a maximum of 100 seconds, as defined by GR1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Free-run mode and another reference source is selected. Revision 2.00/September 2003 Semtech Corp. 41 Lost_Phase mode Lost-phase mode is entered when the current phase error, as measured within the DPLL, is larger than a preset limit (see register 04, bits 5:3), as a result of a frequency or phase transient on the selected reference source. This mode is similar in behavior to the Pre-locked or Pre-locked(2) modes, although in this mode the DPLL is attempting to regain lock to the same reference rather than attempt lock to a new reference. If the DPLL cannot regain lock within 100 s, the source is disqualified, and one of the following transitions takes place: 1. Go to Pre-Locked(2); - If a known-good standby source is available. 2. Go to Holdover; - If no standby sources are available. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Holdover mode The Holdover mode is used when the ACS8510 has been in Locked mode for long enough to acquire stable frequency data, but the final selected reference source has become unavailable and a replacement has not yet been qualified for selection. In Holdover mode, the ACS8510 provides the timing and synchronisation signals to maintain the Network Element (NE), but they are not phase locked to any input reference source. The timing is based on a stored value of the frequency ratio obtained during the last Locked mode period. To allow for further development of the way the internal algorithm operates, and to allow for customised switching behaviour, the switch to and from Holdover state may be controlled by external software. The device must be set in either `manual' mode or `automatic' mode: 1. Register cnfg_mode bit `holdover offset en' set high (manual mode). The Holdover frequency is determined by the value in register cnfg_holdover_offset. This is a 19 bit signed number, with a LSB resolution of 0.0003 ppm, which gives an adjustment range of 80 ppm. This value can be derived from a reading of the register sts_curr_inc_offset (addr 0D, 0C and 07) which gives, in the same format, an indication of the current output frequency deviation, which would be read when the device is locked. If required, this value could be read by an external microcontroller and averaged over the time required. The averaged value could then be fed to the cnfg_holdover_offset register ready for setting of the averaged frequency value when the device enters Holdover mode. The sts_curr_inc_offset value is internally derived from the Digital Phase Locked Loop (DPLL) integral path value, which already represents a well averaged measure of the current frequency, depending on the loop bandwidth selected. 2. Register cnfg_mode bit `holdover offset en' set low (automatic mode). In automatic control, the device can be run in one of two ways: 2.1 Register cnfg_holdover_offset register 40 bit 7 `auto holdover averaging' is set high. The value is averaged Revision 2.00/September 2003 Semtech Corp. 42 internally over 32 samples at 32 seconds apart, giving the average frequency over approximatley the last 20 minutes. The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. If the device has been previously correctly locked, missing pulses in the input clock stream fed to the SETS IC are ignored, hence also avoiding any frequency disturbances to the output frequency value when an input clock source fails. 2.2 Register cnfg_holdover_offset register 40 bit 7 `auto holdover averaging' is set low. This simply freezes the DPLL at the current frequency (as reported by the sts_curr_inc_offset register). The proportional DPLL path is ignored so that recent signal disturbances do not affect the Holdover frequency value. Automatic control with internal averaging (option 2.1) is the default condition. If the TCXO frequency is varying due to temperature fluctuations in the room, then the instantaneous value can be different from the average value, and then it may be possible to exceed the 0.05 ppm limit (depending on how extreme the temperature flucuations are). It is advantageous to shield the TCXO to slow down frequency changes due to drift and external temperature fluctuations. The frequency accuracy of Holdover mode has to meet the ITU-T, ETSI and Telcordia performance requirements. The performance of the external oscillator clock is critical in this mode, although only the frequency stability is important - the stability of the output clock in Holdover is directly related to the stability of the external oscillator. Pre-Locked(2) mode This state is very similar to the Pre-Locked state. It is entered from the Holdover state when a reference source has been selected and applied to the phase locked loop. It is also entered if the device is operating in Revertive mode and a higher-priority reference source is restored. Upon applying a reference source to the phase locked loop, the ACS8510 will enter the Locked state in a maximum of 100 seconds, as defined www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS by GR-1244-CORE specification, if the selected reference source is of good quality. If the device cannot achieve lock within 100 seconds, it reverts to Holdover mode and another reference source is selected. Protection Facility The ACS8510 supports redundancy protection. The primary functions of this include: - Alignment of the priority tables of both Master and Slave ACS8510 devices so as to align the selection of reference sources of both Master and Slave ACS8510 devices. - Alignment of the phases of the 8 kHz and 2 kHz clocks in both Master and Slave ACS8510 devices to within one cycle of the 77.76 MHz internal clock. When two ACS8510 devices are to be used in a redundancy-protection scheme within an NE, one will be designated as the Master and the other as the Slave. It is expected that an NE will use the T OUT0 output for its internal operations because the TOUT4 output is intended to feed an SSU/BITS system. An SSU/BITS will not be bothered by phase differences between signals arriving from different sources because it typically incorporates line build-out functions to absorb phase differences on reference inputs. This means that the phasing of the composite clocks between two ACS8510 devices do not have to be mutually-aligned. The same is not true, however, of the TOUT0 output signals (T01 - T07, Frame clock and Multi-Frame clock). It is usually important to align the phases of all equivalent TOUT0 signals generated by different sources so that switch-over from one device to another does not affect the internal operations of the NE. Both ACS8510 devices will produce the same signals, which will be routed around the NE to the various consumers (clock sinks). With the possible exception of a Revision 2.00/September 2003 Semtech Corp. 43 through-timing mode, the signals from the Master device will be used by all consumers, unless the Master device fails, when each consumer will switch over to the signals generated by the Slave device. Switchover to a new TOUT0 clock should be as hitless as possible. This requires the signals of both ACS8510 devices to be phase aligned at each consumer. Phase alignment requires frequency alignment. To ensure that both devices can generate output clocks locked to the same source, both devices are supplied with the same reference sources on the same input ports and will have identical priority tables. Failures of selected reference sources will result in both ACS8510 devices making the same updates to their priority tables as availability information will be updated in both devices. Although, in principle, the priority tables will be the same if the same reference sources are used on the same input port on each device, in practice, this is only true if the reference sources actually arrive at each device - failures of a source seen only by one device and not by the other, such as could be caused, for example, by a backplane connector failure, would result in the priority tables becoming misaligned. It is thus necessary to force the priority tables to be aligned under normal operating conditions so that the devices can make the same decisions - this can be achieved by loading the availability seen by one device (via the sts_reference_sources register) into the cnfg_sts_remote_sources_valid register of the other device. Another factor which could affect hit-less switching is the frequency of the local oscillator clock used by each ACS8510 device: these clocks are not mutually aligned and, whilst this has no impact on the frequency of the output clocks during locked mode, it could cause the output frequencies to diverge during Holdover mode if no action were taken to avoid it. In order to maintain alignment of the output frequencies of each ACS8510 device even www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS during Holdover, the Master device's 6.48 MHz output is fed into the Slave device on its <I_11> pin, whilst the Multi-Frame Sync (2 kHz) output is fed to the Sync2k input of the Slave. In this way, the Slave locks to the master's output and remains locked whilst the Master moves between operating states. Only when the Master fails does the Slave use its own reference inputs - should the Master have been in the Holdover state, the Slave device will see the same lack of reference sources and also enter the Holdover state. This scheme also provides a convenient way to phase-align all TOUT0 output clocks in Master and Slave devices, and also to detect the failure of the Master device. If a Master device fails, the Slave has to take over responsibility for the generation of the output clocks, including the 8 kHz and 2 kHz Frame and Multi-Frame clocks. The Slave device is also given responsibility for building the priority table and performing the reference switching operations. The Slave device, therefore, adopts a more active role when the Master has failed. The cnfg_mode register 34 (Hex) Bit 1 contains the `Master/Slave' control bit to determine the designation of the device. To restore redundancy protection, the Master has to be repaired and replaced. When this occurs, the new Master cannot immediately adopt its normal role because it must not cause phase hits on the output clocks. It has, therefore, to adopt a subordinate role to the active Slave device, at least until such time as it has acquired alignment to the 8 kHz and 2 kHz frame and Multi-Frame clocks and the priority table of the Slave device; then, when a switch-back (restoration) is ordered, the Master can take over responsibility. These activities, in Master or Slave operation, are summarized in Table 12 and described in detail in Application Note AN-SETS-2. Revision 2.00/September 2003 Semtech Corp. 44 Alignment of Priority Tables in Master and Slave ACS8510 Correct protection will only be achieved by connecting individual reference sources to the same input ports on each device and priority tables in each device must be aligned to each other. The Master device must take account of the availability of each reference source seen by another device and a Slave device must adopt the same order of priority as the Master device (except that the Slave's highest-priority input is <I_11>). Both devices monitor the reference sources and decide the availability of each source; if the failure of a reference source is seen by both devices, they will both update their priority tables - however, if the reference source failure is only seen by one device and not by both, the priority tables could get out of step: this could be catastrophic if it resulted in two devices choosing different reference sources since any slight differences in frequency variation over time (e.g. wander) would mis-align the phase of the 8 kHz Frame and 2 kHz MultiFrame clocks produced by the individual devices, resulting in phase hits on switch-over. It is therefore important that the same priority table be built by each device, using the reference source availability seen by each device. The monitoring of the reference sources performed by a Master ACS8510 results in a list of available sources being placed in a sts_valid_sources register. This information is used within the device as one of the masks used to build the device's priority table. The information is passed to the Slave device and used to configure the cnfg_sts_remote_ sources_valid register so that it can use it as a mask in building its own priority tables. The information is passed between devices using the microprocessor port. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Alignment of the Selection of Reference Sources for T OUT4 Generation in the Master and Slave ACS8510 As stated previously, there is no need to align the phases of the TOUT4 outputs in Master and Slave devices. There is a need, however, to ensure that all devices select the same reference source. But, since there is no Holdover mode required for the generation of the TOUT4 clock, and every reference source is continuously monitored within each device, it is permissible to rely on external intelligence to command a switch-over to an alternative source should the selected one fail. The time delay involved in detecting the failure, indicating it to the outside and selecting a new source, will result only in the SSU/BITS entering its Holdover mode for a short time. Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 In addition to aligning the edges of the TOUT0 outputs of Master and Slave devices, it is necessary to align the edges of the Frame and Multi-Frame clocks. If this is not performed, frame alignment may be lost in distant equipment on switch-over to an alternative device, resulting in anomalous network operation of a very serious nature. In accordance with the alignment mechanism used with the main TOUT0 clock (described in the opening paragraphs of this section), whereby the 6.48 MHz output of the Master device is supplied to the Slave device, the alignment of both the 8 kHz and 2 kHz clocks is accomplished (they are already synchronous to the TOUT0 clocks) by feeding the 2 kHz clock of the Master device into the Slave device. The Multi-Frame Sync clock output of the Slave device is also fed to the Sync2K input of the Master device. Alignment of the Multi-Frame Sync input occurs only when cnfg_mode register, bit 3, address 34Hex External 2 kHz Sync Enable is set to 1. Revision 2.00/September 2003 Semtech Corp. 45 JTAG The JTAG connections on the ACS8510 allow a full boundary scan to be made. The JTAG implementation is fully compliant to IEEE 1149.1, with the following minor exceptions, and the user should refer to the standard for further information. 1. The output boundary scan cells do not capture data from the core, and so do not support EXTEST. However this does not affect board testing. 2. In common with some other manufacturers, pin TRST is internally pulled low to disable JTAG by default. The standard is to pull high. The polarity of TRST is as the standard: TRST high to enable JTAG boundary scan mode, TRST low for normal operation. 3. The device does not support the optional tri-state capability (HIGHZ). This will be supported on the next revision of the device. The JTAG timing diagram is shown in Figure 17. PORB The Power On Reset (PORB) pin resets the device if forced Low for a power on reset to be initiated. The reset is asynchronous, the minimum Low pulse width is 5 ns. Reset is needed to initialize all of the register values to their defaults. Asserting Reset is required at power on, and may be re-asserted at any time to restore defaults. This is implemented most simplistically by an external capacitor to GND along with the internal pull-up resistor. The ACS8510 is held in a reset state for 250 ms after the PORB pin has been pulled High. In normal operation PORB should be held High. www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 10. Master-Slave Schematic TCXO V DD MASTER MSTSLVB T 01 SEC1 I_1 T 02 SEC2 I_2 T 03 SEC3 I_3 . . . T 04 . . . I_11 . . . I_14 T 07 . . . T 011 SEC14 6.48 MHz MFr S ync SYNC2K 6.48 MHz TCXO SLAVE GND MSTSLVB T 01 SEC1 I_1 T 02 SEC2 I_2 T 03 SEC3 I_3 . . . T 04 . . . I_11 . . . I_14 T 07 . . . T 011 SEC13 MFr S ync SYNC2K SYNC2K_EN=1 34Bit3 Table 13. Master-Slave Relationship R ef _ sou r ces t o M a s t e r A C S 8 510 R ef _ sou r ces t o S l a v e A C S 8 510 M a s t e r A C S 8 510 st at u s S l a v e A C S 8 510 st at u s M a s t e r A C S 8 510 S l a v e A C S 8 510 ou t p u t Com m en t s All good All good Good Good Locked (ref_x) Locked to master N ote 1 Some failed Some others failed Good Good Locked (ref_y) Locked to master N ote 1 Good Good Good Failed Locked (ref_x) Dead Good Good Failed Good Dead Locked (ref_x) Good Good Failed Failed Dead Dead Failed Failed Failed Good Holdover Locked to master Failed Failed Good Failed Holdover Dead Failed Failed Failed Good Dead Holdover Failed Failed Failed Failed Dead Dead N ote 2 N ote 3 Notes to Table 13 Note 1: Both ACS8510 must build a common priority table so that the Slave ACS8510 can select the same input reference source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output). Note 2: Slave ACS8510 uses common priority table, built before Master ACS8510 failed - priority table can be modified as status of the input reference sources changes Note 3: Slave ACS8510 outputs must remain in phase with those of Master ACS8510 Revision 2.00/September 2003 Semtech Corp. 46 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 11. Automatic Mode Control State Diagram (1)Reset free-run select ref (state 001) (2) all refs evaluated & at least one ref valid (3) no valid standby ref & (main ref invalid or out of lock >100s) Reference sources are flagged as 'valid' when active, 'in-band' and have no phase alarm set. (4) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] pre-locked w ait for up to 100s (state 110) (5) selected ref phase locked All sources are continuously checked for activity and frequency. Only the main source is checked for phase. A phase lock alarm is only raised on a reference when that reference has lost phase whilst being used as the main reference. The micro-processor can reset the phase lock alarm. A source is considered to have phase locked when it has been continuously in phase lock for between 1 and 2 seconds locked keep ref (state 100) (10) selected source phase locked (9) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) ] pre-locked2 w ait for up to 100s (state 101) (12) valid standby ref & (main ref invalid or out of lock >100s) (15) valid standby ref & [ main ref invalid or (higher-priority ref valid & in revertive mode) or out of lock >100s] Revision 2.00/September 2003 Semtech Corp. (8) phase regained within 100s (6) no valid standby ref & main ref invalid (7) phase lost on main ref Lost phase w ait for up to 100s (state 111) (11) no valid standby ref & (main ref invalid or out of lock >100s) holdover select ref (state 010) (13) no valid standby ref & (main ref invalid or out of lock >100s) (14) all refs evaluated & at least one ref valid 47 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Electrical Specification Important Note Note: The `Absolute Maximum Ratings' are stress ratings only, and functional operation of the device at conditions other than those indicated in the `Operating Conditions' sections of this specification are not implied. Exposure to the absolute maximum ratings for an extended period may reduce the reliability or useful lifetime of the product. Table 14. Absolute Maximum Ratings PA RA METER SYMB OL M IN IN M AX AX U N ITS Sup p ly Voltage VDD, VD+, VA1+,VA2+ VDD -0.5 3.6 V Inp ut Voltage (non-sup p ly p ins) Vin - 5.5 V Outp ut Voltage (non-sup p ly p ins) Vout - 5.5 V TA -40 +85 C Tstor -50 +150 C Ambient Op erating Temp erature Range Storage Temp erature Table 15. Operating Conditions PA RA METER SYMB OL MIN T YP MA X U N ITS Power Sup p ly (dc voltage) VDD, VD+,VA1+, VA2+, VAMI+, VDD_DIFF VDD 3.0 3.3 3.6 V Power Sup p ly (dc voltage) VDD5 VDD5 3.0 3.3/5.0 5.5 V Ambient temp erature Range TA -40 - +85 C Sup p ly current IDD - 110 200 mA PTOT - 360 720 mW (Typ ical - one 19 MHz outp ut) Total p ower dissip ation Table 16. DC Characteristics: TTL Input Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Inp ut current Ii n - - 10 A Revision 2.00/September 2003 Semtech Corp. 48 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 17. DC Characteristics: TTL Input Port with Internal Pull-up Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-up resistor PU 30 - 80 k Inp ut current Ii n - - 120 A Table 18. DC Characteristics: TTL Input Port with Internal Pull-down Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vin High V ih 2.0 - - V Vin Low V il - - 0.8 V Pull-down resistor PD 30 - 80 k Inp ut current Ii n - - 120 A Table 19. DC Characteristics: TTL Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Vout Low Iol = 4mA Vol 0 - 0.4 V Vout High Ioh = 4mA Voh 2.4 - Drive current ID - - Revision 2.00/September 2003 Semtech Corp. 49 V 4 mA www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 20. DC Characteristics: PECL Input/Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VILPECL VDD-2.5 - VDD-0.5 V Differential inp uts (N ote 1) VIHPECL VDD-2.4 - VDD-0.4 V Inp ut Differential voltage VIDPECL 0.1 - 1.4 V VILPECL_S VDD-2.4 - VDD-1.5 V VIHPECL_S VDD-1.3 - VDD-0.5 V IIHPECL -10 - +10 A IILPECL -10 - +10 A VOLPECL VDD-2.10 - VDD-1.62 V VOHPECL VDD-1.25 - VDD-0.88 V VODPECL 580 - 900 mV PECL Inp ut Low voltage Differential inp uts (N ote 1) PECL Inp ut High voltage PECL Inp ut Low voltage Single ended inp ut (N ote 2) PECL Inp ut High voltage Single ended inp ut (N ote 2) Inp ut High current Inp ut differential voltage VID = 1.4v Inp ut Low current Inp ut differential voltage VID = 1.4v PECL Outp ut Low voltage (N ote 3) PECL Outp ut High voltage (N ote 3) PECL Outp ut Differential voltage (N ote 1) Notes to Table 20 Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied to VDD and GND respectively. Note 1. Assuming a differential input voltage of at least 100 mV. Note 2. Unused differential input terminated to VDD-1.4 V. Note 3. With 50 load on each pin to VDD-2 V. i.e. 82 to GND and 130 to VDD. Revision 2.00/September 2003 Semtech Corp. 50 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 12. Recommended Line Termination for PECL Input/Output Ports V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 V DD 130R ZO=50 I5POS ZO=50 130R 82R 130R T06POS ZO=50 I5NEG 130R 82R T06NEG 82R 82R GND GND V DD 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 V DD 130R ZO=50 I6POS ZO=50 130R T07POS 130R 82R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 ZO=50 I6NEG 130R 82R 19.44, 51.84, 77.76, 155.52 MHz T07NEG 82R 82R GND GND VDD = +3.3 V Revision 2.00/September 2003 Semtech Corp. 51 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 21. DC Characteristics: LVDS Input/Output Port Across all operating conditions, unless otherwise stated PA R A M E T E R SYMB OL MIN T YP MA X U N ITS VVRLVDS 0 - 2.40 V VDITH -100 - +100 mV VIDLVDS 0.1 - 1.4 V R TERM 95 100 105 VOHLVDS - - 1.585 V VOLLVDS 0.885 - - V (N ote 1) VODLVDS 250 - 450 mV LVDS Change in magnitude of differential outp ut voltage for comp limentary states VDOSLVDS - - 25 mV VOSLVDS 1.125 - 1.275 V LVDS Inp ut voltage range Differential inp ut voltage = 100 mV LVDS Differential inp ut threshold LVDS Inp ut Differential voltage LVDS Inp ut termination resistance Must be p laced externally across the LVDS+/- inp ut p ins of ACS8510. Resistor should be 100 with 5% tolerance LVDS Outp ut high voltage (N ote 1) LVDS Outp ut low voltage (N ote 1) LVDS Differential outp ut voltage (N ote 1) LVDS outp ut offset voltage Temp erature = 25C (N ote 1) Note to Table 21 Note 1. With 100 load between the differential outputs. Revision 2.00/September 2003 Semtech Corp. 52 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 13. Recommended Line Termination for LVDS Input/Output Ports 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz 8kHz, 1.544/2.048, 6.48, 19.44, 38.88, 51.84, 77.76 or 155.52 MHz ZO=50 ZO=50 I5POS ZO=50 T06POS 100R ZO=50 I5NEG T06NEG I6POS T07POS ZO=50 ZO=50 100R 19.44, 38.88, 155.52, 311.04 MHz & DIG1 ZO=50 100R ZO=50 I6NEG Revision 2.00/September 2003 Semtech Corp. 100R 19.44, 51.84, 77.76, 155.52 MHz T07NEG 53 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS DC Characteristics: AMI Input/Output Port Across all operating conditions, unless otherwise stated The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative pulses with a peak to peak voltage of 2.0 +/- 0.2 V. The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64 kbit/s centralized clock interface, from ITU G.703. Table 22. DC Characteristics: AMI Input/Output Port PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Inp ut Pulse width t PW 1.56 7.8 14.04 us Inp ut Pulse rise/fall time tR/F - - 5 us AMI Inp ut voltage high V IH A M I 2.5 - VDD + 0.3 V AMI Inp ut voltage middle V V IM A M I 1.5 1.65 1.8 V AMI Inp ut voltage low V V IL A M I 0 - 1.4 V AMI Outp ut current drive IAMIOUT - - 20 mA VOH AMI VDD - 0.16 - - V Outp ut current = 20mA VOLAMI - - 0.16 V N ominal test load imp edence RTEST - 110 - "Mark" amp litude after transformer V MA R K 0.9 1.0 1.1 V "Sp ace" amp litude after transformer VSPACE -0.1 0 0.1 V AMI Outp ut high voltage Outp ut current = 20mA AMI Outp ut low voltage The electrical characteristics of 64 kbits/s interface are as follows; Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability. There should be a symmetrical pair carrying the composite timing signal (64 kHz and 8 kHz). The use of transformers is recommended. Over-voltage protection requirement; refer to Recommendation K.41. Code conversion rules; The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals convey the 64 kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the 8 kHz octet phase information by introducing violations in the code rule. The structure of the signals and voltage levels are shown in Figures 14 and 15. Revision 2.00/September 2003 Semtech Corp. 54 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface after suitable input/output transformer (also see Figure 6/G.703) 15.6us 7.8us + 1.0V IH 1V 2V p -p 0V IM 1V -1.0V IL Figure 15. AMI Input and Output Signal Levels 15.6us Signal structure of 64 kHz/ 8 kHz central clock interface after suitable transformer. 7.8us +V D D 15.6us 7.8us 0V + 1.0V IH I_1 1V 2V p -p TO8POS C1 0V IM C2 15.6us 1V I_2 -1.0V IL TO8NEG 7.8us +V D D C1 0V Revision 2.00/September 2003 Semtech Corp. 55 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 16. Recommended Line Termination for AMI Output/Output Ports AMI input signal Turns ratio 1:1 <I_1> C1 C2 AMI input signal <I_2> AMI output signal to external devices TO8POS TO8NEG R load C3 GND C1 Notes The AMI inputs <I_1> and <I_2> should be connected to the external AMI clock source by 470 nF coupling capacitor C1. The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1. Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses. Revision 2.00/September 2003 Semtech Corp. 56 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.813 for 155.52 MHz op tion 1 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 2) G.813 for 155.52 MHz op tion 1 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 3) 0.048 (N ote 2) 0.053 (N ote 4) 0.053 (N ote 5) 0.058 (N ote 6) 0.053 (N ote 7) G.813 for 155.52 MHz op tion 2 12 kHz to 1.3 MHz UIpp = 0.1 0.053 (N ote 2) 0.058 (N ote 3) 0.057 (N ote 8) 0.055 (N ote 9) 0.057 (N ote 10) 0.057 (N ote 11) 0.057 (N ote 12) 0.053 (N ote 13) G.813 & G.812 for 2.048 MHz op tion 1 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.812 for 1.544 MHz 10 Hz to 40 kHz UIpp = 0.05 0.036 (N ote 14) G.812 for 155.52 MHz electrical 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 15) G.812 for 2.048 MHz electrical 65 kHz to 1.3 MHz U Ip p = 0.075 0.048 (N ote 15) Revision 2.00/September 2003 Semtech Corp. 57 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 ETS-300-462-3 for 2.048 MHz SEC 20 Hz to 100 kHz UIpp = 0.5 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SEC (Filter sp ec 49 Hz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.2 0.046 (N ote 14) ETS-300-462-3 for 2.048 MHz SSU 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) ETS-300-462-3 for 155.52 MHz 500 Hz to 1.3 MHz UIpp = 0.5 0.058 (N ote 15) ETS-300-462-3 for 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.1 0.048 (N ote 15) Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 GR-253-CORE net i/f, 51.84 MHz 100 Hz to 400 kHz UIpp = 1.5 0.022 (N ote 15) GR-253-CORE net i/f, 51.84 MHz (Filter sp ec 20 kHz to 400 kHz) 18 kHz to 400 kHz UIpp = 0.15 0.019 (N ote 15) GR-253-CORE net i/f, 155.52 MHz 500 Hz to 1.3 MHz UIpp = 1.5 0.058 (N ote 15) GR-253-CORE net i/f, 155.52 MHz 65 kHz to 1.3 MHz UIpp = 0.15 0.048 (N ote 15) GR-253-CORE cat II elect i/f, 155.52 MHz UIpp = 0.1 0.057 (N ote 15) 12 kHz to 400 kHz UIrms = 0.01 0.006 (N ote 15) GR-253-CORE cat II elect i/f, 51.84 MHz UIpp = 0.1 0.017 (N ote 15) 12 kHz to 1.3 MHz UIrms = 0.01 0.003 (N ote 15) GR-253-CORE DS1 i/f, 1.544 MHz UIpp = 0.1 0.036 (N ote 14) 10 Hz to 40 kHz UIrms = 0.01 0.0055 (N ote 14) Revision 2.00/September 2003 Semtech Corp. 58 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 AT&T 62411 for 1.544 MHz (Filter sp ec 10 Hz to 8 kHz) 10 Hz to 40 kHz UIrms = 0.02 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz 10 Hz to 40 kHz UIrms = 0.025 0.0055 (N ote 14) AT&T 62411 for 1.544 MHz Broadband UIrms = 0.05 0.0055 (N ote 14) Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 G.742 for 2.048 MHz DC to 100 kHz UIpp = 0.25 0.047 (N ote 14) G.742 for 2.048 MHz (Filter spec 18 kHz to 100 kHz) 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) G.742 for 2.048 MHz 20 Hz to 100 kHz UIpp = 0.05 0.046 (N ote 14) Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 TR-N WT-000499 & G824 for 1.544 MHz 10 Hz to 40 kHz UIpp = 5.0 0.036 (N ote 14) TR-N WT-000499 & G824 for 1.544 MHz (Filter spec 8 kHz to 40 kHz) 10 Hz to 40 kHz UIpp = 0.1 0.036 (N ote 14) Revision 2.00/September 2003 Semtech Corp. 59 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE) Across all operating conditions, unless otherwise stated Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905. Te s t d e f i n i t i o n F i l t er u sed U I sp ec U I m e a s u r e m e n t o n A C S 8 510 R ev 2 GR-1244-CORE for 1.544 MHz >10 Hz UIpp = 0.05 0.036 (N ote 14) Notes for Tables 23 - 30 Note 1. Filter used is that defined by test definition unless otherwise stated Note 2. 5 Hz bandwidth, 19.44 MHz direct lock Note 3. 5 Hz bandwidth, 8 kHz lock Note 4. 20 Hz bandwidth, 19.44 MHz direct lock Note 5. 20 Hz bandwidth, 8 kHz lock Note 6. 10 Hz bandwidth, 19.44 MHz direct lock Note 7. 10 Hz bandwidth, 8 kHz lock Note 8. 2.5 Hz bandwidth, 19.44 MHz direct lock Note 9. 2.5 Hz bandwidth, 8 kHz lock Note 10. 1.2 Hz bandwidth, 19.44 MHz direct lock Note 11. 1.2 Hz bandwidth, 8 kHz lock Note 12. 0.6 Hz bandwidth, 19.44 MHz direct lock Note 13. 0.6 Hz bandwidth, 8 kHz lock Note 14. 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input Note 15. 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input Revision 2.00/September 2003 Semtech Corp. 60 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 17. JTAG Timing t CYC TCK t SU R t HT TM S TDI t DO D TDO Table 31. JTAG Timing (for use with Figure 17) PA R A M E T E R SYMB OL MIN T YP MA X U N ITS Cycle time tCYC 50 - - ns TMS/TDI to TCK rising edge time tSUR 3 - - ns TCK rising to TMS/TDI hold time tHT 23 - - ns TCK falling to TDO valid tDOD - - 5 ns Revision 2.00/September 2003 Semtech Corp. 61 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 18. Input/Output Timing Typical Delay Input/Output 8 kHz input Output 1.5 ns Typical Phase Alignment 8 kHz output 8 kHz 6.48 MHz input 2 kHz < 1 ns +6.5 to +8.5 ns 6.48 MHz output 19.44 MHz input +5.5 to +7.5 ns T1 +3.5 to +5.5 ns (Multiples have the same offset) E1 +3.5 to +5.5 ns (Multiples have the same offset) 19.44 MHz output 25.92 MHz input 6.48 MHz +3.0 to +5.0 ns 19.44 MHz +2.5 to +4.5 ns 25.92 MHz +3.0 to +5.0 ns 38.88 MHz +3.0 to +4.5 ns 51.84 MHz +6.0 to +8.0 ns (Additional delay for this output) 77.76 MHz +2.0 to +4.0 ns +6.5 to +8.5 ns 25.92 MHz output 38.88 MHz input +4.0 to +6.0 ns 38.88 MHz output 51.84 MHz input +6.0 to +8.0 ns 51.84 MHz output 77.76 MHz input +5.5 to +7.5 ns 155.52 MHz < 1 ns 311.04 MHz < 0.5 ns 77.76 MHz output Revision 2.00/September 2003 Semtech Corp. 62 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Microprocessor Interface Timing Motorola Mode In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 19. Read Access Timing in MOTOROLA Mode t pw1 CSB t su2 WRB t h2 X X t h1 t su1 A X address X t d3 t d1 AD Z t d2 RDY (DTACK) Z data t pw2 t h3 t d4 Z Z Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup WRB valid to CSBfalling edge MIN T YP MA X 0 ns - - 0 ns - - td 1 Delay CSBfalling edge to AD valid - - 177 ns td 2 Delay CSBfalling edge to DTACKrising edge - - 13 ns td 3 Delay CSBrising edge to AD high-Z - - 0 ns td 4 Delay CSBrising edge to RDY high-Z - - 7 ns tp w 1 CSB low time 485 ns(1) - - tp w 2 RDY high time 310 ns - 472 ns th 1 Hold A valid after CSBrising edge 0 ns - - th 2 Hold WRB high after CSBrising edge 0 ns - - th 3 Hold CSB low after RDYfalling edge 0 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 320 ns - - Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 63 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 20. Write Access Timing in MOTOROLA Mode t pw1 CSB t su2 WRB t h2 X X t h1 t su1 A X address X t h4 t su3 AD X data t d2 RDY (DTACK) t pw2 X t h3 t d4 Z Z Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) S y m b ol tsu1 P ar am et er Setup A valid to CSBfalling edge MIN T YP MA X 0 ns - - tsu2 Setup WRB valid to CSBfalling edge 0 ns - - tsu3 Setup AD valid before CSBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDYrising edge - - 13 ns td 4 Delay CSBrising edge to RDY high-Z - - 7 ns tp w 1 CSB low time 485 ns(1) - - tp w 2 RDY high time 310 ns - 472 ns th 1 Hold A valid after CSBrising edge 3 ns - - th 2 Hold WRB low after CSBrising edge 0 ns - - th 3 Hold CSB low after RDYfalling edge 0 ns - - th 4 Hold AD valid after CSBrising edge 4 ns tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) - - 320 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns. Revision 2.00/September 2003 Semtech Corp. 64 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Intel Mode In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 21. Read Access Timing in INTEL Mode CSB WRB t su2 t pw 1 t h2 RDB t su1 t h1 A a dd re ss t d1 AD Z d ata t d2 RDY t d4 Z t d3 t pw 2 t h3 t d5 Z Z Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup CSBfalling edge to RDBfalling edge MIN T YP MA X 0 ns - - 0 ns - - td 1 Delay RDBfalling edge to AD valid - - 177 ns td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay RDBfalling edge to RDYfalling edge - - 14 ns td 4 Delay RDBrising edge to AD high-Z - - 10 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 RDB low time 486 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns th 1 Hold A valid after RDBrising edge 0 ns - - th 2 Hold CSB low after RDBrising edge 0 ns - - th 3 Hold RDB low after RDYrising edge 0 ns - - tp Time between consecutive accesses (RDBrising edge to RDBfalling edge , or RDBrising edge to WRBfalling edge) 320 ns - - 9 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 65 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 22. Write Access Timing in INTEL Mode CSB t su2 t pw1 t h2 WRB RDB t su1 t h1 A address t su3 AD data t d2 RDY t h4 t d3 t pw2 t h3 t d5 Z Z Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) S y m b ol tsu1 tsu2 P ar am et er Setup A valid to CSBfalling edge Setup CSBfalling edge to WRBfalling edge MIN T YP MA X 0 ns - - 0 ns - - tsu3 Setup AD valid to WRBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay WRBfalling edge to RDYfalling edge - - 14 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 WRB low time 486 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns th 1 Hold A valid after WRBrising edge 170 ns(2) - - th 2 Hold CSB low after WRBrising edge 0 ns - - th 3 Hold WRB low after RDYrising edge 0 ns - - th 4 Hold AD valid after WRBrising edge 4 ns tp Time between consecutive accesses (WRBrising edge to WRBfalling edge , or WRBrising edge to RDBfalling edge) - - 9 ns 320 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge. Revision 2.00/September 2003 Semtech Corp. 66 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Multiplexed Mode In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/ data bus. The following figures show the timing diagrams of write and read accesses for this mode. Figure 23. Read Access Timing in MULTIPLEXED Mode t t pw 3 p1 ALE t su1 t h1 CSB t su2 W RB t t pw 1 h2 RDB t AD X a d d re s s t RDY t d1 d4 X d a ta t d2 d3 t pw 2 t t h3 d5 Z Z Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) S y m b ol tsu1 P ar am et er Setup A D address valid to A LEfalling edge MIN T YP MA X 2 ns - - tsu2 Setup CSBfalling edge to RDBfalling edge 0 ns - - td 1 Delay RDBfalling edge to A D data valid - - 177 ns td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay RDBfalling edge to RDYfalling edge - - 15 ns td 4 Delay RDBrising edge to A D data high-Z - - 9 ns td 5 Delay CSBrising edge to RDY high-Z - - 10 ns tp w 1 RDB low time - - tp w 2 RDY low time 310 ns - 472 ns tp w 3 A LE high time 2 ns th 1 Hold A D address valid after A LEfalling edge 3 ns - - th 2 Hold CSB low after RDBrising edge 0 ns - - th 3 Hold RDB low after RDYrising edge 0 ns - - tp 1 Time b etween A LEfalling edge and RDBfalling edge 0 ns - - tp 2 Time b etween consecutive accesses (RDBrising edge to A LErising edge) 320 ns - - 487 ns (1) Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 67 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Figure 24. Write Access Timing in MULTIPLEXED Mode t t pw 3 p1 ALE t t su1 h1 CSB t t su2 t pw 1 h2 W RB RDB t AD a d d re s s RDY h4 d a ta X t t su3 t d2 d3 t X pw 2 t h3 t d5 Z Z Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) S y m b ol tsu1 P ar am et er Setup AD address valid to ALEfalling edge MIN T YP MA X 2 ns - - tsu2 Setup CSBfalling edge to WRBfalling edge 0 ns - - tsu3 Setup AD data valid to WRBrising edge 3 ns - - td 2 Delay CSBfalling edge to RDY active - - 13 ns td 3 Delay WRBfalling edge to RDYfalling edge - - 15 ns td 5 Delay CSBrising edge to RDY high-Z tp w 1 WRB low time 487 ns(1) - - tp w 2 RDY low time 310 ns - 472 ns tp w 3 ALE high time 2 ns - - th 1 Hold AD address valid after ALEfalling edge 3 ns - - th 2 Hold CSB low after WRBrising edge 0 ns - - th 3 Hold WRB low after RDYrising edge 0 ns - - th 4 AD data hold valid after WRBrising edge 4 ns tp 1 Time between ALEfalling edge and WRBfalling edge 0 ns - - tp 2 Time between consecutive accesses (WRBrising edge to ALErising edge) 320 ns - - 9 ns Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns. Revision 2.00/September 2003 Semtech Corp. 68 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Serial Mode In Serial mode, the device is configured to interface with a serial microprocessor bus.The combined minimum High and Low times for SCLK define the maximum clock rate. For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us). This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock out the SDO. A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz. SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing diagrams for Write and Read access for this mode. Figure 25. Read Access Timing in Serial Mode CLKE = 0; SDO data is clocked out on the rising edge of SCLK CSB tsu2 tpw2 th2 SCLK th1 tsu1 _ SDI R/W tpw1 A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 CLKE = 1; SDO data is clocked out on the falling edge of SCLK CSB th2 SCLK _ SDI R/W A0 A1 A2 A3 A4 A5 A6 td1 SDO Output not driven, pulled low by internal resistor td2 D0 D1 D2 D3 D4 D5 D6 D7 F8525D_013ReadAccSerial_01 Revision 2.00/September 2003 Semtech Corp. 69 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) S y m b ol P ar am et er Setup SDI valid to SCLKrising edge tsu1 Setup CSBfalling edge to SCLKrising edge tsu2 MIN T YP MA X 0 ns - - 160 ns - - td 1 Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid - - 17 ns td 2 Delay CSBrising edge to SDO high-Z - - 10 ns tp w 1 SCLK low time CLKE = 0 CLKE = 1 250ns 500ns - - tp w 2 SCLK high time CLKE = 0 CLKE = 1 250ns 500ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge, for CLKE = 0 Hold CSB low after SCLKfalling edge, for CLKE = 1 5 ns - - tp Time b etween consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Figure 26. Write Access Timing in SERIAL Mode CSB tsu2 tpw2 th2 ALE=SCLK th1 tsu1 _ A(0)=SDI AD(0)=SDO R/W tpw1 A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7 Output not driven, pulled low by internal resistor F8110D_014WriteAccSerial_02 Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) S y m b ol P ar am et er MIN T YP MA X 0 ns - - tsu1 Setup SDI valid to SCLKrising edge tsu2 Setup CSBfalling edge to SCLKrising edge 160 ns - - tp w 1 SCLK low time 180 ns - - tp w 2 SCLK high time 180 ns - - th 1 Hold SDI valid after SCLKrising edge 170 ns - - th 2 Hold CSB low after SCLKrising edge 5 ns - - tp Time between consecutive accesses (CSBrising edge to CSBfalling edge) 160 ns - - Revision 2.00/September 2003 Semtech Corp. 70 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS EPROM Mode In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state machine in the up interface sequences the accesses. Further details can be found in the AMD AM27C64 data sheet. Figure 27. Access Timing in EPROM Mode CSB (=OEB) A address t acc AD Z Z data Table 40. Access Timing in EPROM Mode (for use with Figure 27) S y m b ol tacc P ar am et er Delay CSBfalling edge or A change to AD valid Revision 2.00/September 2003 Semtech Corp. 71 MIN T YP MA X - - 920 ns www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Package Information Figure 28. LQFP Package D 2 D1 1 3 AN2 AN3 1 Section A-A R1 S E 2 R2 B AN1 E1 1 A A B 3 AN4 L 4 L1 5 1 2 3 b A Section B-B 7 e A2 7 c c1 7 Seating plane A1 6 b1 7 b 8 Notes 1 The top package body may be smaller than the bottom package body by as much as 0.15 mm. 2 To be determined at seating plane. 3 Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4 Details of pin 1 identifier are optional but will be located within the zone indicated. 5 Exact shape of corners can vary. 6 A1 is defined as the distance from the seating plane to the lowest point of the package body. 7 These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8 Shows plating. Revision 2.00/September 2003 Semtech Corp. 72 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) 10 0 L Q F P P ack ag e Di m en si on s i n mm D/E D1/E 1 Mi n N om Max 16.00 14.00 A A1 A1 A2 A2 1.40 0.05 1.35 1.50 0.10 1.40 1.60 0.15 1.45 e 0.50 AN1 AN2 AN3 AN4 R1 R1 R2 R2 L 11 11 0 0 0.08 0.08 0.45 12 12 - 3.5 - - 0.60 13 13 - 7 - 0.20 0.75 L1 L1 1.00 (ref) S b b1 b1 c c1 c1 0.20 0.17 0.17 0.09 0.09 - 0.22 0.20 - - - 0.27 0.23 0.20 0.16 Thermal Conditions The device is rated for full temperature range when this package is used with a 4 layer or more PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum operating temperature must be reduced when the device is used with a PCB with less than these requirements. Figure 29. Typical 100 Pin LQFP Footprint 18.3 mm 17.0 mm (1) 14.6 mm 1.85 mm Pitch 0.5 mm Width 0.3 mm Notes (1) Solderable to this limit. Square package - dimensions apply in both X and Y directions. Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc. Revision 2.00/September 2003 Semtech Corp. 73 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Application Information Figure 30. Simplified Application Schematic Revision 2.00/September 2003 Semtech Corp. 74 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Revision History Table 42. Changes from Revision 1.06 to 2.00 September 2003 Item 1 Section Non-Revertive Mode Page 36-37 Description Updated description of Non-Revertive Mode Operation Revision 2.00/September 2003 Semtech Corp. 75 www.semtech.com ACS8510 Rev2.1 SETS FINAL ADVANCED COMMUNICATIONS Ordering Information PA R T N U M B E R DE S CR I P T I O N ACS8510 Rev2.1 SON ET/SDH Synchronisation, 100 p in LQFP Disclaimers Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or other critical applications. This product is not authorized or warranted by Semtech Corporation for such use. Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product. Customers are advised to obtain the latest version of the relevant information before placing orders. Compliance to relevant standards - Operation of this device is subject to the user's implementation, and design practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards. For additional information, contact the following: Semtech Corporation Advanced Communications Products E-Mail: sales@semtech.com acsupport@semtech.com Internet: http://www.semtech.com USA: Mailing Address: P.O. Box 6097, Camarillo, CA 93011-6097 Street Address: 200 Flynn Road, Camarillo, CA 93012-8790 Tel: +1 805 498 2111, Fax: +1 805 498 3804 FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C. Tel: +886 2 2748 3380, Fax: +886 2 2748 3390 EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate, Romsey, Hampshire, SO51 9DN, UK Tel: +44 1794 527 600, Fax: +44 1794 527 601 ISO9001 CERTIFIED Revision 2.00/September 2003 Semtech Corp. 76 www.semtech.com