ACS8510REV2.1 - Semtech - Datasheet.Live

Synchronous EE

Equipment TT

Timing SS

Source

for SONET or SDH Network Elements

ACS8510 Rev2.1 SETS

Description Description

Description Features Features

Features Features

Features

Block Diagram Block Diagram

Block Diagram

The ACS8510 is a highly integrated, single-chip

solution for the Synchronous Equipment Timing

Source (SETS) function in a SONET or SDH Net-

work Element. The device generates SONET or

SDH Equipment Clocks (SEC) and frame synchro-

nization clocks. The ACS8510 is fully compliant

with the required specifications and standards.

The device supports Free-run, Locked and

Holdover modes. It also supports all three types

of reference clock source: recovered line clock,

PDH network, and node synchronization. The

ACS8510 generates independent SEC and BITS

clocks, an 8 kHz Frame Synchronization clock

and a 2 kHz Multi-Frame Synchronization clock.

Two ACS8510 devices can be used together in a

Master/Slave configuration mode allowing sys-

tem protection against a single ACS8510 failure.

A microprocessor port is incorporated, providing

access to the configuration and status registers

for device setup and monitoring. The ACS8510

supports IEEE 1149.1 JTAG boundary scan.

Rev2.1 adds choice of edge alignment for 8kHz

input, as well as a low jitter n x E1/DS1 output

mode. Other minor changes are made, with all

described in Appendix A.

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp. www.semtech.com

•Suitable for Stratum 3E*, 3, 4E and 4 SONET

or SDH Equipment Clock (SEC) applications

•Meets AT&T, ITU-T, ETSI and Telcordia

specifications

•Accepts 14 individual input reference clocks

•Generates 11 output clocks

•Supports Free-run, Locked and Holdover

modes of operation

•Robust input clock source quality monitoring on

all inputs

•Automatic ‘hit-less’ source switchover on loss

of input

•Phase build out for output clock phase

continuity during input switchover and mode

transitions

•Microprocessor interface - Intel, Motorola,

Serial, Multiplexed, EPROM

•Programmable wander and jitter tracking

attenuation 0.1 Hz to 20 Hz

•Support for Master/Slave device configuration

alignment and hot/standby redundancy

•IEEE 1149.1 JTAG Boundary Scan

•Single +3.3 V operation, +5 V I/O compatible

•Operating temperature (ambient) -40°C to

+85°C

•Available in 100 pin LQFP package

* Meets Holdover requirements, lowest bandwidth 0.1 Hz.

Figure 1. Simple Block DiagramFigure 1. Simple Block Diagram

Figure 1. Simple Block Diagram

DPLL/Freq. Synthesis

TOUT0

selector

TOUT4

selector

Chip Clock

Generator

Divider

PFD

DPLL/Freq. Synthesis

Divider

Monitors

Digital

Loop

Filter

APLL

Frequency

Dividers

Microprocessor

Port

2 x AMI

10 x TTL

2 x PECL/LVDS

Programmable;

64/8kHz

2kHz

4kHz

N x 8kHz

1.544/2.048MHz

6.48MHz

19.44MHz

25.92MHz

38.88MHz

51.84MHz

77.76MHz

155.52MHz

DTO

Digital

Loop

Filter

PFD

1 x AMI

6 x TTL

2 x PECL/LVDS

Programmable:

64/8kHz

1.544/2.048MHz

3.088/4.096MHz

6.176/8.182MHz

12.352/16.384MHz

6.48MHz

19.44MHz

25.92MHz

38.88MHz

51.84MHz

77.76MHz

155.52MHz

311.04MHz

2kHz MFrSync

8kHz FrSync

Input

Ports

14xSEC

MFrSync

Output

Ports

TCXO (*OCXO)

IEEE

1149.1

JTAG

TCK

TDI

TMS

TRST

TDO

Priority

Table

Set

DTO

9xSEC

FrSync

MFrSync

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

T T

able of Contable of Cont

able of Contentsents

entsents

ents

List of SectionsList of Sections

List of Sections

Description ................................................................................................................................................................................................ 1

Block Diagram ........................................................................................................................................................................................... 1

Features ..................................................................................................................................................................................................... 1

Table of Contents ...................................................................................................................................................................................... 2

Pin Diagram ............................................................................................................................................................................................... 5

Pin Descriptions ........................................................................................................................................................................................ 6

Functional Description ............................................................................................................................................................................. 9

Local Oscillator Clock ................................................................................................................................................................................... 10

ITU and ETSI Specification ............................................................................................................................................................. 10

Telcordia GR-1244 CORE Specification ....................................................................................................................................... 10

Crystal Frequency Calibration ...................................................................................................................................................... 10

Input Interfaces ............................................................................................................................................................................................. 10

Over-Voltage Protection .............................................................................................................................................................................. 10

Input Reference Clock Ports ....................................................................................................................................................................... 11

Input Wander and Jitter Tolerance .............................................................................................................................................................. 9

Output Clock Ports ........................................................................................................................................................................................ 12

Low Speed Output Clock (DPLL2) ................................................................................................................................................. 12

High Speed Output Clock (DPLL1) ............................................................................................................................................... 12

Frame Sync and Multi-Frame Sync Clocks (Part of DPLL1) ................................................................................................... 13

Low Jitter Multiple E1/DS1 Outputs ........................................................................................................................................... 13

Output Wander and Jitter ............................................................................................................................................................................ 13

Phase Variation ............................................................................................................................................................................................. 18

Phase Build Out ............................................................................................................................................................................................. 21

Microprocessor Interface ............................................................................................................................................................................. 21

Motorola Mode ................................................................................................................................................................................ 21

Intel Mode ........................................................................................................................................................................................ 21

Multiplexed Mode ........................................................................................................................................................................... 21

Serial Mode ...................................................................................................................................................................................... 21

EPROM Mode ................................................................................................................................................................................... 21

Register Set ..................................................................................................................................................................................... 22

Configuration Registers ................................................................................................................................................................. 22

Status Registers .............................................................................................................................................................................. 22

Register Access ............................................................................................................................................................................... 22

Interrupt Enable and Clear ......................................................................................................................................................................... 22

Register Map .................................................................................................................................................................................................. 23

Register Map Description ........................................................................................................................................................................... 27

Selection of Input Reference Clock Source ............................................................................................................................................. 36

Forced Control Selection ............................................................................................................................................................... 37

Automatic Control Selection ........................................................................................................................................................ 37

Ultra Fast Switching ....................................................................................................................................................................... 37

External Protection Switching ..................................................................................................................................................... 38

Clock Quality Monitoring ............................................................................................................................................................................. 38

Activity Monitoring ....................................................................................................................................................................................... 39

Frequency Monitoring .................................................................................................................................................................................. 39

Modes of Operation ...................................................................................................................................................................................... 41

Free-run mode ................................................................................................................................................................................. 41

Pre-Locked mode ............................................................................................................................................................................ 41

Locked mode .................................................................................................................................................................................... 41

Lost_Phase mode ........................................................................................................................................................................... 41

Holdover mode ................................................................................................................................................................................ 42

Pre-Locked(2) mode ........................................................................................................................................................................ 42

Protection Facility ........................................................................................................................................................................................ 43

Alignment of Priority Tables in Master and Slave ACS8510 ................................................................................................. 44

Alignment of the Selection of Reference Sources for TOUT4 Generation in the Master and Slave ACS8510 ........... 45

Alignment of the Phases of the 8kHz and 2kHz Clocks in both Master and Slave ACS8510 ....................................... 45

JTAG .................................................................................................................................................................................................................. 45

PORB ................................................................................................................................................................................................................ 45

Electrical Specification .......................................................................................................................................................................... 48

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

List of FiguresList of Figures

List of Figures

Figure 1. Simple Block Diagram ............................................................................................................................................................. 1

Figure 2. ACS8510 Pin Diagram ............................................................................................................................................................ 5

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) ................................................................................................................... 15

Figure 4. Minimum Input Jitter Tolerance (DS1/E1) .......................................................................................................................... 16

Figure 5. Wander and Jitter Measured Transfer Characteristics ....................................................................................................... 18

Figure 6. Maximum Time Interval Error of TOUT0 output port ........................................................................................................... 20

Figure 7. Time Deviation of TOUT0 output port ................................................................................................................................... 20

Figure 8. Phase error accumulation of TOUT0 output port in Holdover mode .................................................................................. 20

Figure 9. Inactivity and Irregularity Monitoring ................................................................................................................................... 38

Figure 10. Master-Slave Schematic ..................................................................................................................................................... 46

Figure 11. Automatic Mode Control State Diagram ........................................................................................................................... 47

Figure 12. Recommended Line Termination for PECL Input/Output Ports ...................................................................................... 51

Figure 13. Recommended Line Termination for LVDS Input/Output Ports ...................................................................................... 53

Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface ............................................................................................ 55

Figure 15. AMI Input and Output Signal Levels .................................................................................................................................. 55

Figure 16. Recommended Line Termination for AMI Output/Output Ports ..................................................................................... 56

Figure 17. JTAG Timing ............................................................................................................................................................................ 61

Figure 18. Input/Output Timing ............................................................................................................................................................ 62

Figure 19. Read Access Timing in MOTOROLA Mode ........................................................................................................................ 63

Figure 20. Write Access Timing in MOTOROLA Mode ....................................................................................................................... 64

Figure 21. Read Access Timing in INTEL Mode ................................................................................................................................... 65

Figure 22. Write Access Timing in INTEL Mode .................................................................................................................................. 66

Figure 23. Read Access Timing in MULTIPLEXED Mode .................................................................................................................... 67

Figure 24. Write Access Timing in MULTIPLEXED Mode ................................................................................................................... 68

Figure 25. Read Access Timing in SERIAL Mode ................................................................................................................................ 69

Figure 26. Write Access Timing in SERIAL Mode ............................................................................................................................... 70

Figure 27. Access Timing in EPROM Mode ......................................................................................................................................... 71

Figure 28. LQFP Package ...................................................................................................................................................................... 72

Figure 29. Typical 100 Pin LQFP Footprint ......................................................................................................................................... 73

Figure 30. Simplified Application Schematic ...................................................................................................................................... 74

DC Characteristics: AMI Input/Output Port ........................................................................................................................................... 54

Microprocessor Interface Timing .......................................................................................................................................................... 63

Motorola Mode .............................................................................................................................................................................................. 63

Intel Mode ....................................................................................................................................................................................................... 65

Multiplexed Mode ......................................................................................................................................................................................... 67

Serial Mode .................................................................................................................................................................................................... 69

EPROM Mode ................................................................................................................................................................................................. 71

Package Information .............................................................................................................................................................................. 72

Thermal Conditions ....................................................................................................................................................................................... 73

Application Information .......................................................................................................................................................................... 74

Revision History ...................................................................................................................................................................................... 75

Ordering Information .............................................................................................................................................................................. 76

Disclaimers ..................................................................................................................................................................................................... 76

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

List of TList of T

List of Tablesables

ablesables

ables

Table 1. Power Pins .................................................................................................................................................................................... 6

Table 2. No Connections ............................................................................................................................................................................ 6

Table 3. Other Pins ..................................................................................................................................................................................... 7

Table 4. Input Reference Source Selection and Priority Table .......................................................................................................... 12

Table 5. Input ReferenceSource Jitter Tolerance ................................................................................................................................. 14

Table 6. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 15

Table 7. Amplitude and Frequency Values for Jitter Tolerance ............................................................................................................ 16

Table 8. Output Reference Source Selection Table ............................................................................................................................. 17

Table 9. Multiple E1/DS1 Output in Relation to Normal Outputs ..................................................................................................... 17

Table 10. Microprocessor Interface Mode Selection ......................................................................................................................... 21

Table 11. Register Map .......................................................................................................................................................................... 23

Table 12. Register Map Description ..................................................................................................................................................... 27

Table 13. Master-Slave Relationship .................................................................................................................................................... 46

Table 14. Absolute Maximum Ratings .................................................................................................................................................. 48

Table 15. Operating Conditions ............................................................................................................................................................. 48

Table 16. DC Characteristics: TTL Input Port ....................................................................................................................................... 48

Table 17. DC Characteristics: TTL Input Port with Internal Pull-up .................................................................................................... 49

Table 18. DC Characteristics: TTL Input Port with Internal Pull-down ............................................................................................... 49

Table 18. DC Characteristics: TTL Output Port .................................................................................................................................... 49

Table 20. DC Characteristics: PECL Input/Output Port ...................................................................................................................... 50

Table 21. DC Characteristics: LVDS Input/Output Port...................................................................................................................... 52

Table 22. DC Characteristics: AMI Input/Output Port ........................................................................................................................ 54

Table 23. DC Characteristics: Ouput Jitter Generation (Test Definition G.813) ............................................................................. 57

Table 24. DC Characteristics: Ouput Jitter Generation (Test Definition G.812) ............................................................................. 57

Table 25. DC Characteristics: Ouput Jitter Generation (Test Definition ETS-300-462-3) .............................................................. 58

Table 26. DC Characteristics: Ouput Jitter Generation (Test Definition GR-253-CORE) ............................................................... 58

Table 27. DC Characteristics: Ouput Jitter Generation (Test Definition AT&T 62411) ................................................................... 59

Table 28. DC Characteristics: Ouput Jitter Generation (Test Definition G.742) .............................................................................. 59

Table 29. DC Characteristics: Ouput Jitter Generation (Test Definition TR-NWT-000499) ........................................................... 59

Table 30. DC Characteristics: Ouput Jitter Generation (Test Definition GR-1244-CORE) ............................................................. 60

Table 31. JTAG Timing (for use with Figure 17) ................................................................................................................................... 61

Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19) ................................................................................. 63

Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20) ................................................................................ 64

Table 34. Read Access Timing in INTEL Mode (for use with Figure 21) ............................................................................................ 65

Table 35. Write Access Timing in INTEL Mode (for use with Figure 22) ........................................................................................... 66

Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23) ............................................................................. 67

Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24) ............................................................................. 68

Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25) ......................................................................................... 70

Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26) ........................................................................................ 70

Table 40. Access Timing in EPROM Mode (for use with Figure 27) .................................................................................................. 71

Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28) ................................................................................... 73

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

NC - Not Connected; leave to Float. IC - Internally Connected; leave to Float.

100 SONSDHB

99 MSTSLVB

98 IC

97 IC

96 IC

95 TO9

94 TO5

93 TO4

92 DGND

91 VDD

90 TO3

89 TO2

88 TO1

87 DGND

86 VDD

85 VDD

84 DGND

83 AD0

82 AD1

81 AD2

80 AD3

79 AD4

78 AD5

77 AD6

76 AD7

75 RDY

74 PORB

73 ALE

72 RDB

71 WRB

70 CSB

69 A0

68 A1

67 A2

66 A3

65 A4

64 A5

63 A6

62 DGND

61 VDD

60 UPSEL0

59 UPSEL1

58 UPSEL2

57 I14

56 I13

55 I12

54 I11

53 I10

52 I9

51 I8

ACS8510

SDH/SONET SETS

Rev 2.1

1 AGND

2 TRST

3IC

4NC

5 AGND

6 VA1+

7 TMS

8 INTREQ

9 TCK

10 REFCLK

11 DGND

12 VD+

13 VD+

14 DGND

15 DGND

16 VD+

17 NC

18 SRCSW

19 VA2+

20 AGND

21 TD O

22 IC

23 TDI

24 I1

25 I2

26 VAMI+

27 TO8NEG

28 TO8POS

29 GND_AMI

30 FrSync

31 MFrSync

32 GND_DIFF

33 VDD_DIFF

34 TO6POS

35 TO6NEG

36 TO7POS

37 TO7NEG

38 GND_DIFF

39 VDD_DIFF

40 I5POS

41 I5NEG

42 I6POS

43 I6NEG

44 VDD5

45 SYNC2K

46 I3

47 I4

48 I7

49 DGND

50 VDD

Pin Diagram Pin Diagram

Pin Diagram

Figure 2. ACS8510 Pin DiagramFigure 2. ACS8510 Pin Diagram

Figure 2. ACS8510 Pin Diagram

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

71,4CN-- detcennoCtoNdetcennoCtoN detcennoCtoN detcennoCtoNdetcennoCtoNtaolFotevaeL:

,69,22,3

89,79 CI-- detcennoCyllanretnIdetcennoCyllanretnI detcennoCyllanretnI detcennoCyllanretnIdetcennoCyllanretnItaolFotevaeL:

Pin Descriptions Pin Descriptions

Pin Descriptions

Table 1. Power PinsTable 1. Power Pins

Table 1. Power Pins

Table 2. No ConnectionsTable 2. No Connections

Table 2. No Connections

Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

61,31,21+DVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS3.3+,noitcesgolananisetagotylppuslatigiD

%01-/+.stloV

62+IMAVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS%01-/+.stloV3.3+,tuptuoIMAotylppuslatigiD

93,33FFID_DDVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS.stloV3.3+,stroplaitnereffidrofylppuslatigiD

%01-/+

445DDVP-

5DDV5DDV 5DDV 5DDV5DDVtcennoC.sniptupniotecnarelotstloV5+rofylppuslatigiD:

rofDDVottcennoC.stloV5+otgnipmalcrof)%01-/+(stloV5+ot

sniptupni,gnipmalconrofgnitaolfevaeL.stloV3.3+otgnipmalc

.stloV5.5+otputnarelot

,58,16,05

19,68 DDVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS%01-/+.stloV3.3+,cigolotylppuslatigiD

6+1AVP- :egatlovylppuS:egatlovylppuS :egatlovylppuS :egatlovylppuS:egatlovylppuS.stloV3.3+,LLPgniypitlumkcolcotylppusgolanA

%01-/+

91+2AVP- egatlovylppuSegatlovylppuS egatlovylppuS egatlovylppuSegatlovylppuS%01-/+.stloV3.3+,LLPtuptuootylppusgolanA:

,51,41,11

,48,26,94

29,78

DNGDP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuScigolrofdnuorglatigiD:

92IMA_DNGP

dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuStuptuoIMArofdnuorglatigiD:

83,23FFID_DNGP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuSstroplaitnereffidrofdnuorglatigiD:

02,5,1DNGAP- dnuorGylppuSdnuorGylppuS dnuorGylppuS dnuorGylppuSdnuorGylppuSdnuorggolanA:

www.semtech.com7

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 3. Other PinsTable 3. Other Pins

Table 3. Other Pins

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

2TSRTILTT

tupnIteseRlortnoCGATJtupnIteseRlortnoCGATJ tupnIteseRlortnoCGATJ tupnIteseRlortnoCGATJtupnIteseRlortnoCGATJyradnuoBGATJelbaneot1=TSRT:

cigolGATJ(noitarepoecivedlamronrof0=TSRT.edomnacS

.gnitaolfevaelroDNGottcennocdesutonfI.)tnerapsnart

7SMTILTT

tceleSedoMtseTGATJtceleSedoMtseTGATJ tceleSedoMtseTGATJ tceleSedoMtseTGATJtceleSedoMtseTGATJnodelpmaS.elbanenacSyradnuoB:

.gnitaolfevaelroDDVottcennocdesutonfI.KCTfoegdegnisir

8QERTNIO

LTT

SOMC tseuqeRtpurretnItseuqeRtpurretnI tseuqeRtpurretnI tseuqeRtpurretnItseuqeRtpurretnItuptuotpurretnIerawtfoshgihevitcA:

9KCTILTT

kcolCGATJkcolCGATJ kcolCGATJ kcolCGATJkcolCGATJottcennocdesutonfI.tupnikcolcnacSyradnuoB:

decalproticapacaeriuqeryamnipsihT.gnitaolfevaelroDNG

A.pukcipesionecuderot,DNGtseraenehtdnanipehtneewteb

notnednepedsieulavehttub,etauqedaebdluohsFp01foeulav

.tuoyalBCP

01KLCFERILTT kcolCecnerefeRkcolCecnerefeR kcolCecnerefeR kcolCecnerefeRkcolCecnerefeRlacoLdedaehnoitcesotrefer(zHM8.21:

)kcolCrotallicsO

81WSCRSILTT

gnihctiwSecruoSgnihctiwSecruoS gnihctiwSecruoS gnihctiwSecruoSgnihctiwSecruoSgnihctiwSecruoStsaFecroF:

12ODTO

LTT

SOMC

tuptuOGATJtuptuOGATJ tuptuOGATJ tuptuOGATJtuptuOGATJfoegdegnillafnodetadpU.tuptuoatadtsetlaireS:

.gnitaolfevaeldesutonfI.KCT

32IDTILTT

tupnIGATJtupnIGATJ tupnIGATJ tupnIGATJtupnIGATJ.KCTfoegdegnisirnodelpmaS.tupnIatadtsetlaireS:

.gnitaolfevaelroDDVottcennocdesutonfI

421IIIMA1ecnerefertupnI1ecnerefertupnI 1ecnerefertupnI 1ecnerefertupnI1ecnerefertupnIzHk8+zHk46kcolcetisopmoc:

522IIIMA2ecnerefertupnI2ecnerefertupnI 2ecnerefertupnI 2ecnerefertupnI2ecnerefertupnIzHk8+zHk46kcolcetisopmoc:

72GEN8OTOIMA 8ecnerefertuptuO8ecnerefertuptuO 8ecnerefertuptuO 8ecnerefertuptuO8ecnerefertuptuOevitagenzHk8+zHk46,kcolcetisopmoc:

eslup

82SOP8OTOIMA 8ecnerefertuptuO8ecnerefertuptuO 8ecnerefertuptuO 8ecnerefertuptuO8ecnerefertuptuOevitisopzHk8+zHk46,kcolcetisopmoc:

eslup

03cnySrFO

LTT

SOMC

01ecnerefertuptuO01ecnerefertuptuO 01ecnerefertuptuO 01ecnerefertuptuO01ecnerefertuptuOerauqs(tuptuokcolccnySemarFzHk8:

)evaw

13cnySrFMO

LTT

SOMC

11ecnerefertuptuO11ecnerefertuptuO 11ecnerefertuptuO 11ecnerefertuptuO11ecnerefertuptuOtuptuokcolccnySemarF-itluMzHk2:

)evawerauqs(

SOP6OT

GEN6OT OSDVL

LCEP

6ecnerefertuptuO6ecnerefertuptuO 6ecnerefertuptuO 6ecnerefertuptuO6ecnerefertuptuO445.1(1giDoslA.zHM88.83tluafed:

40.113,zHM25.551,zHM44.91,)x8,4,2dnazHM840.2/zHM

.SDVLepyttluafeD.zHM

SOP7OT

GEN7OT OLCEP

SDVL

7ecnerefertuptuO7ecnerefertuptuO 7ecnerefertuptuO 7ecnerefertuptuO7ecnerefertuptuO67.77,zHM48.15oslA.zHM44.91tluafed:

.LCEPepyttluafeD.zHM25.551,zHM

SOP5I

GEN5I ISDVL

LCEP 5ecnerefertupnI5ecnerefertupnI 5ecnerefertupnI 5ecnerefertupnI5ecnerefertupnISDVLepyttluafed,zHM44.91tluafed:

SOP6I

GEN6I ILCEP

SDVL 6ecnerefertupnI6ecnerefertupnI 6ecnerefertupnI 6ecnerefertupnI6ecnerefertupnILCEPepyttluafed,zHM44.91tluafed:

www.semtech.com8

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 3. Other Pins (continued)Table 3. Other Pins (continued)

Table 3. Other Pins (continued)

NIPNIP NIP NIPNIPLOBMYSLOBMYS LOBMYS LOBMYSLOBMYSOIOIOIOIOIEPYTEPYT EPYT EPYTEPYTNOITPIRCSED/EMANNOITPIRCSED/EMAN NOITPIRCSED/EMAN NOITPIRCSED/EMANNOITPIRCSED/EMAN

54K2CNYSILTT

zHk2esinorhcnySzHk2esinorhcnyS zHk2esinorhcnyS zHk2esinorhcnySzHk2esinorhcnySfotuptuocnySemarF-itluMzHk2ottcennoC:

metsysycnadnuderni0158SCArentrap

643IILTT

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www.semtech.com9

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

F F

unctional Descriptionunctional Description

unctional Description

The ACS8510 is a highly integrated, single-chip

solution for the SETS function in a SONET/SDH

Network Element, for the generation of SEC

and frame synchronization pulses. In Free-run

mode, the ACS8510 generates a stable, low-

noise clock signal from an internal oscillator.

In Locked mode, the ACS8510 selects the most

appropriate input reference source and

generates a stable, low-noise clock signal locked

to the selected reference. In Holdover mode,

the ACS8510 generates a stable, low-noise

clock signal from the internal oscillator,

adjusted to match the last known good

frequency of the last selected reference source.

In all modes, the frequency accuracy, jitter and

drift performance of the clock meet the

requirements of ITU G.812, G.813, G.823, and

GR-1244-CORE.

The ACS8510 supports all three types of

reference clock source: recovered line clock

(TIN1), PDH network synchronization timing (TIN2)

and node synchronization (TIN3). The ACS8510

generates independent TOUT0 and TOUT4 clocks,

an 8 kHz Frame Synchronization clock and a

2 kHz Multi-Frame Synchronization clock.

The ACS8510 has a high tolerance to input

jitter and wander. The jitter/wander transfer is

programmable (0.1 Hz up to 20 Hz cut-off

points).

The ACS8510 supports protection. Two

ACS8510 devices can be configured to provide

protection against a single ACS8510 failure.

The protection maintains alignment of the two

ACS8510 devices (Master and Slave) and

ensures that both ACS8510 devices maintain

the same priority table, choose the same

Table 3. Other Pins (continued)Table 3. Other Pins (continued)

Table 3. Other Pins (continued)

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www.semtech.com10

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

reference input and generate the TOUT0 clock,

the 8 kHz Frame Synchronization clock and the

2 kHz Multi-Frame Synchronization clock with

the same phase. The ACS8510 includes a

microprocessor port, providing access to the

configuration and status registers for device

setup and monitoring.

Local Oscillator ClockLocal Oscillator Clock

Local Oscillator Clock

The Master system clock on the ACS8510

should be provided by an external clock oscillator

of frequency 12.80 MHz. The clock specification

is important for meeting the ITU/ETSI and

Telcordia performance requirements for

Holdover mode. ITU and ETSI specifications

permit a combined drift characteristic, at

constant temperature, of all non-temperature-

related parameters, of up to 10 ppb per day.

The same specifications allow a drift of 1 ppm

over a temperature range of 0 to +70 °C.

Telcordia specifications are somewhat tighter,

requiring a non-temperature-related drift of less

than 40 ppb per day and a drift of 280 ppb

over the temperature range 0 to +50 °C.

ITU and ETSI SpecificationITU and ETSI Specification

ITU and ETSI Specification

Tolerance: +/- 4.6 ppm over 20 year life time.

Drift*: +/- 0.05 ppm/15 seconds @ constant temp.

+/- 0.01 ppm/day @ constant temp.

+/- 1 ppm over temp. range 0 to +70 °C

*Frequency drift over supply range of +2.7V to +3.3V.

Telcordia GR-1244 CORE SpecificationTelcordia GR-1244 CORE Specification

Telcordia GR-1244 CORE Specification

Tolerance: +/- 4.6 ppm over 20 year life time.

Drift*: +/- 0.05 ppm/15 seconds @ constant temp.

+/- 0.04 ppm/day @ constant temp.

+/- 0.28 ppm over temp. range 0 to +50 °C

*Frequency drift over supply range of +2.7V to +3.3V.

Please contact Semtech for information on

crystal oscillator suppliers.

Crystal Frequency CalibrationCrystal Frequency Calibration

Crystal Frequency Calibration

The absolute crystal frequency accuracy is less

important than the stability since any frequency

offset can be compensated by adjustment of

calibration and compensation of any crystal

frequency variation away from its nominal value.

+/- 50 ppm adjustment would be sufficient to

cope with most crystals, in fact the range is an

order of magnitude larger due to the use of

two 8 bit register locations. The setting of the

conf_nominal_frequency register allows for this

adjustment. An increase in the register value

increases the output frequencies by 0.02 ppm

for each LSB step. The default value (in decimal)

is 39321. The minimum being 0 and the

maximum 65535, gives a -700 ppm to

+500 ppm adjustment range of the output

frequencies.

For example, if the crystal was oscillating at

12.8 MHz + 5 ppm, then the calibration value

in the register to give a -5 ppm adjustment in

output frequencies to compensate for the

crystal inaccuracy, would be :

39321 - (5 / 0.02) = 39071 (decimal)

Input InterfacesInput Interfaces

Input Interfaces

The ACS8510 supports up to fourteen input

reference clock sources from input types TIN1,

TIN2 and TIN3 using TTL, CMOS, PECL, LVDS and

AMI buffer I/O technologies. These interface

technologies support +3.3 V and +5 V

operation.

Over-Voltage ProtectionOver-Voltage Protection

Over-Voltage Protection

The ACS8510 may require Over-Voltage

Protection on input reference clock ports

according to ITU Recommendation K.41.

Semtech protection devices are recommended

for this purpose (see separate Semtech data

book).

www.semtech.com11

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Input Reference Clock PortsInput Reference Clock Ports

Input Reference Clock Ports

Table 4 gives details of the input reference

ports, showing the input technologies and the

range of frequencies supported on each port;

the default spot frequencies and default

priorities assigned to each port on power-up or

by reset are also shown. Note that SDH and

SONET networks use different default

frequencies; the network type is pin-selectable

(using the SONSDHB pin). Specific frequencies

and priorities are set by configuration.

Although each input port is shown as belonging

to one of the types, TIN1, TIN2 or TIN3, they are

fully interchangeable as long as the selected

speed is within the maximum operating speed

of the input port technology.

SDH and SONET networks use different default

frequencies; the network type is selectable

using the config_mode register 34 Hex, bit 2.

For SONET, config_mode register 34 Hex, bit 2

= 1, for SDH config_mode register 34 Hex, bit

2 = 0. On power-up or by reset, the default will

be set by the state of the SONSDHB pin (pin

100). Specific frequencies and priorities are set

by configuration.

TTL ports (compatible also with CMOS signals)

support clock speeds up to 100 MHz, with the

highest spot frequency being 77.76 MHz. The

actual spot frequencies supported are:

• 2 kHz

• 4 kHz

• 8 kHz (and N x 8 kHz)

• 1.544 MHz (SONET)/2.048 MHz (SDH)

• 6.48 MHz,

• 19.44 MHz,

• 25.92 MHz,

• 38.88 MHz,

• 51.84 MHz,

• 77.76 MHz.

The frequency selection is programmed via the

cnfg_ref_source_frequency register. The

internal DPLL will normally lock to the selected

input at the frequency of the input, eg. 19.44

MHz will lock the DPLL phase comparisons at

19.44 MHz. It is, however, possible to utilise

an internal pre-divider to the DPLL to divide the

input frequency before it is used for phase

comparisons in the DPLL. This pre-divider can

be used in one of 2 ways:

1. Any of the supported spot frequencies can be divided to

8 kHz by setting the ‘lock8K’ bit (bit 6) in the appropriate

cnfg_ref_source_frequency register location. For good jitter

tolerance for all frequencies and for operation at

19.44 MHz and above, use lock8K. It is possible to choose

which edge of the 8kHz input to lock to, by setting the

appropriate bit of the cnfg_control1 register.

2. Any multiple of 8 kHz between 1544 kHz to 100 MHz

can be supported by using the ‘DivN’ feature (bit 7 of the

cnfg_ref_source_frequency register). Any reference input

can be set to use DivN independently of the frequencies

and configurations of the other inputs.

Any reference input with the DivN bit set in the

cnfg_ref_source_frequency register will employ

the internal pre-divider prior to the DPLL locking.

The cnfg_freq_divn register contains the divider

ratio N where the reference input will get divided

by (N+1) where 0<N<214-1. The

cnfg_ref_source_frequency register must be set

to the closest supported spot frequency to the

input frequency, but must be lower than the

input frequency. When using the DivN feature

the post-divider frequency must be 8 kHz, which

is indicated by setting the ‘lock8k’ bit high (bit

6 in cnfg_ref_source_frequency register). Any

input set to DivN must have the frequency

monitors disabled (If the frequency monitors

are disabled, they are disabled for all inputs

regardless of the input configurations, in this

case only activity monitoring will take place).

Whilst any number of inputs can be set to use

the DivN feature, only one N can be

programmed, hence all inputs using the DivN

feature must require the same division to get

to 8 kHz.

www.semtech.com12

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 4. Input Reference Source Selection and Priority TableTable 4. Input Reference Source Selection and Priority Table

Table 4. Input Reference Source Selection and Priority Table

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www.semtech.com13

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Notes for Table 4.Notes for Table 4.

Notes for Table 4.

Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot

frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz

(SONET)/2.048 MHz (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH

is selected using the SONSDHB pin. When the SONSDHB pin is High SONET is selected, when the SONSDHB pin is

Low SDH is selected.

Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz.

Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or

PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin.

PECL and LVDS ports support the spot clock

frequencies listed plus 155.52 MHz and

311.04 MHz. The choice of PECL or LVDS

compatibility is programmed via the

cnfg_differential_inputs register. Unused PECL/

LVDS differential inputs should be fixed with

one input high (VDD) and the other input low

(GND), or set in LVDS mode and left floating, in

which case one input is internally pulled high

and the other low.

An AMI port supports a composite clock,

consisting of a 64 kHz AMI clock with 8 kHz

boundaries marked by deliberate violations of

the AMI coding rules, as specified in ITU

recommendation G.703. Departures from the

nominal pattern are detected within the

ACS8510, and may cause reference-switching

if too frequent. See section DC Characteristics:

AMI Input/Output Port, for more details. If the

AMI port is unused, the pins (I1 and I2) should

be tied to GND and the VAMI+ supply pin (pin

26) disconnected.

Input Wander and Jitter ToleranceInput Wander and Jitter Tolerance

Input Wander and Jitter Tolerance

The ACS8510 is compliant to the requirements

of all relevant standards, principally ITU

Recommendation G.825, ANSI DS1.101-1994

and ETS 300 462-5 (1997).

All reference clock inputs have a tight frequency

tolerance but a generous jitter tolerance. Pull-

in, hold-in and pull-out ranges are specified for

each input port in Table 5. Minimum jitter

DivN examplesDivN examples

DivN examples

To lock to 2.000 MHz.

(1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the

frequency to E1/DS1. (XX = ‘leaky bucket’ ID for this input).

(2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (DS1).

(3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.

(4) The DivN register is set to F9 Hex (249 decimal).

To lock to 10.000 MHz.

(1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the

frequency to 6.48 MHz. (XX = ‘leaky bucket’ ID for this input).

(2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.

(3) The DivN register is set to 4E1 Hex (1249 decimal).

www.semtech.com14

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

tolerance masks are specified in Figures 3 and

4, and Tables 6 and 7, respectively. The

ACS8510 will tolerate wander and jitter

components greater than those shown in Figure

3 and Figure 4, up to a limit determined by a

combination of the apparent long-term

frequency offset caused by wander and the

eye-closure caused by jitter (the input source

will be rejected if the offset pushes the

frequency outside the hold-in range for long

enough to be detected, whilst the signal will

also be rejected if the eye closes sufficiently to

affect the signal purity). The ‘8klocking’ mode

should be engaged for high jitter tolerance

according to these masks. All reference clock

ports are monitored for quality, including

frequency offset and general activity. Single

short-term interruptions in selected reference

clocks may not cause rearrangements, whilst

longer interruptions, or multiple, short-term

interruptions, will cause rearrangements, as will

frequency offsets which are sufficiently large

or sufficiently long to cause loss-of-lock in the

phase-locked loop. The failed reference source

will be removed from the priority table and

declared as unserviceable, until its perceived

quality has been restored to an acceptable

level.

The registers sts_curr_inc_offset (address 0C,

0D, 07) report the frequency of the DPLL with

respect to the external TCXO frequency. This is

a 19 bit signed number with one LSB

representing 0.0003 ppm (range of +/- 80

ppm). Reading this regularly can show how the

currently locked source is varying in value e.g.

due to wander on its input.

The ACS8510 performs automatic frequency

monitoring with an acceptable input frequency

offset range of +/- 16.6 ppm. The ACS8510

DPLL has a programmable frequency limit of

+/- 80 ppm. If the range is programmed to be

> 16.6 ppm, the frequency monitors should be

disabled so the input reference source is not

automatically rejected as out of frequency

range.

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)ni-lluP()ni-lluP( )ni-lluP( )ni-lluP()ni-lluP(

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF

ecnatpeccAecnatpeccA ecnatpeccA ecnatpeccAecnatpeccA

)ni-dloH(egnaR)ni-dloH(egnaR )ni-dloH(egnaR )ni-dloH(egnaR)ni-dloH(egnaR

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF

egnaRecnatpeccAegnaRecnatpeccA egnaRecnatpeccA egnaRecnatpeccAegnaRecnatpeccA

)tuo-lluP()tuo-lluP( )tuo-lluP( )tuo-lluP()tuo-lluP(

307.G

mpp6.61-/+

mpp6.4-/+

)1etoNees(

mpp2.9-/+

)2etoNees(

mpp6.4-/+

)1etoNees(

mpp2.9-/+

)2etoNees(

mpp6.4-/+

)1etoNees(

mpp2.9-/+

)2etoNees(

387.G

328.G

EROC-4421-RG

Table 5. Input Reference Source Jitter ToleranceTable 5. Input Reference Source Jitter Tolerance

Table 5. Input Reference Source Jitter Tolerance

Notes for Table 5.Notes for Table 5.

Notes for Table 5.

Note 1. The frequency acceptance and generation range will be +/-4.6 ppm around the required frequency when the

external crystal frequency accuracy is within a tolerance of +/- 4.6 ppm.

Note 2. The fundamental acceptance range and generation range is +/- 9.2 ppm with an exact external crystal

frequency of 12.8 MHz. This is the default DPLL range, the range is also programmable from 0 to 80 ppm in 0.08

ppm steps.

www.semtech.com15

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

f0 f1 f2 f3 f4 f5 f6

Jitter and wander frequency (log scale)

f8 f9

f0 f1 f2 f3 f4 f5 f6

Jitter and wander frequency (log scale)

f8 f9

(for inputs supporting G.783 compliant sources)

Table 6. Amplitude and Frequency Values for Jitter ToleranceTable 6. Amplitude and Frequency Values for Jitter Tolerance

Table 6. Amplitude and Frequency Values for Jitter Tolerance

MTSMTS MTS MTSMTS

levellevel level levellevel

edutilpmakaepotkaePedutilpmakaepotkaeP edutilpmakaepotkaeP edutilpmakaepotkaePedutilpmakaepotkaeP

)lavretnItinu()lavretnItinu( )lavretnItinu( )lavretnItinu()lavretnItinu( )zH(ycneuqerF)zH(ycneuqerF )zH(ycneuqerF )zH(ycneuqerF)zH(ycneuqerF

0A0A0A0A0A1A1A1A1A1A2A2A2A2A2A3A3A3A3A3A4A4A4A4A4A0F0F0F0F0F1F1F1F1F1F2F2F2F2F2F3F3F3F3F3F4F4F4F4F4F5F5F5F5F5F6F6F6F6F6F7F7F7F7F7F8F8F8F8F8F9F9F9F9F9F

1-MTS0082113935.151.0u21u871m6.1m6.51521.03.91005k5.6k56m3.1

Output Clock PortsOutput Clock Ports

Output Clock Ports

The device supports a set of main output clocks,

TOUT0 and TOUT4, and a pair of secondary output

clocks, 'Frame-Sync' and 'Multi-Frame-Sync'. The

two main output clocks, TOUT0 and TOUT4, are

independent of each other and are individually

selectable. The two secondary output clocks,

'Frame-Sync' and 'Multi-Frame-Sync', are derived

from TOUT0. The frequencies of the output clocks

are selectable from a range of pre-defined spot

frequencies and a variety of output technologies

are supported, as defined in Table 8.

Low-speed Output Clock (TLow-speed Output Clock (T

Low-speed Output Clock (TOUT4OUT4

OUT4OUT4

OUT4))

))

)

The TOUT4 clock is supplied on two output ports,

TO8 and TO9. The former port will provide an AMI

signal carrying a composite clock of 64 kHz

and 8 kHz, according to ITU Recommendation

G.703. The latter port will provide a TTL/CMOS

signal at either 1.544 MHz or 2.048 MHz,

depending on the setting of the SONSDHB pin.

High-speed Output Clock (Part of THigh-speed Output Clock (Part of T

High-speed Output Clock (Part of TOUT0OUT0

OUT0OUT0

OUT0))

))

)

The TOUT0 port has multiple outputs. Outputs TO1

and TO2 are TTL/CMOS output with a choice of

11 different frequencies up to 51.84 MHz.

Outputs TO3 to TO5 are all TTL/CMOS outputs

with fixed frequencies of 19.44 MHz,

38.88 MHz and 77.76 MHz respectively. Output

TO6 is differential and can support clocks up to

155.52 MHz. Output TO7 is also differential

and can support clocks up to 155.52 MHz.

Each output is individually configured to operate

at the frequencies shown in Table 8

(configuration must be consistent between

ACS8510 devices for protection-switching to be

effective - output clocks will be phase-aligned

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1) Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)

Figure 3. Minimum Input Jitter Tolerance (OC-3/STM-1)

www.semtech.com16

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

between devices). Using the

cnfg_differential_outputs register, outputs TO6

and TO7 can be made to be LVDS or PECL

compatible.

Frame Sync and Multi-Frame Sync Clocks (Part ofFrame Sync and Multi-Frame Sync Clocks (Part of

Frame Sync and Multi-Frame Sync Clocks (Part of

TOUT0OUT0

OUT0OUT0

OUT0))

))

)

Frame Sync (8 kHz) and Multi-Frame Sync

(2 kHz) clocks are provided on outputs TO10

(FrSync) and TO11 (MFrSync). The FrSync and

MFrSync clocks have a 50:50 mark space ratio.

These are driven from the TOUT0 clock. They are

synchronized with their counterparts in a second

ACS8510 device (if used), using the technique

described later.

Low Jitter Multiple E1/DS1 OutputsLow Jitter Multiple E1/DS1 Outputs

Low Jitter Multiple E1/DS1 Outputs

This feature added to Rev2.1 is activated using

the cnfg_control1 register. This sends a fre-

quency of twice the Dig2 rate (see reg addr 39h,

bits 7:6) to the APLL instead of the normal

77.76MHz. For this feature to be used, the Dig2

rate must only be set to 12352kHz/16384kHz

using the cnfg_T0_output_frequencies register.

The normal OC3 rate outputs are then replaced

with E1/DS1 multiple rates. The E1(SONET)/

DS1(SDH) selection is made in the same way as

for Dig2 using the cnfg_T0_output_enable reg-

ister. Table 9 shows the relationship between

primary output frequencies and the correspond-

ing output in E1/DS1 mode, and which output

they are available from.

epyTepyT epyT epyTepyT.cepS.cepS .cepS .cepS.cepS edutilpmAedutilpmA edutilpmA edutilpmAedutilpmA

)kp-kpIU()kp-kpIU( )kp-kpIU( )kp-kpIU()kp-kpIU(

ycneuqerFycneuqerF ycneuqerF ycneuqerFycneuqerF

)zH()zH( )zH( )zH()zH(

1A1A1A 1A1A2A2A2A 2A2A1F1F1F1F1F2F2F2F2F2F3F3F3F3F3F4F4F4F4F4F

1SD1SD 1SD 1SD1SDEROC-4421-RGEROC-4421-RG EROC-4421-RG EROC-4421-RGEROC-4421-RG51.001005k8k04

1E1E1E1E1E328.GUTI328.GUTI 328.GUTI 328.GUTI328.GUTI5.12.002k4.2k81k001

f1 f2 f3 f4

Peak-to-peak jitter and wander amplitude (log

scale)

Jitter and wander frequency (log scale)

f1 f2 f3 f4

Peak-to-peak jitter and wander amplitude (log

scale)

Jitter and wander frequency (log scale)

(for inputs supporting G.783 compliant sources)

Figure 4. Minimum Input Jitter Tolerance (DS1/E1) Figure 4. Minimum Input Jitter Tolerance (DS1/E1)

Figure 4. Minimum Input Jitter Tolerance (DS1/E1)

Table 7. Amplitude and Frequency Values for Jitter ToleranceTable 7. Amplitude and Frequency Values for Jitter Tolerance

Table 7. Amplitude and Frequency Values for Jitter Tolerance

www.semtech.com17

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Output Wander and JitterOutput Wander and Jitter

Output Wander and Jitter

Wander and jitter present on the output clocks

are dependent on:

1. The magnitude of wander and jitter on the selected

input reference clock (in Locked mode)

2. The internal wander and jitter transfer characteristic

(in Locked mode)

3. The jitter on the local oscillator clock

4. The wander on the local oscillator clock (in Holdover

mode)

Wander and jitter are treated in different ways

to reflect their differing impacts on network

design. Jitter is always strongly attenuated,

whilst wander attenuation can be varied to suit

the application and operating state. Wander and

jitter attenuation is performed using a digital

phase locked loop (DPLL) with a programmable

bandwidth. This gives a transfer characteristic

of a low pass filter, with a programmable pole.

It is sometimes necessary to change the filter

dynamics to suit particular circumstances - one

example being when locking to a new source,

Note for Table 8.Note for Table 8.

Note for Table 8.

Where 1.544 MHz/2.048 MHz is shown, 1.544 MHz is SONET, and 2.048 MHz is SDH. Pin SONSDHB controls the default

frequency output. Where the SONSDHB pin is High SONET is default, and when SONSDHB pin is Low SDH is default.

troPtroP troP troPtroP

emaNemaN emaN emaNemaN

troPtuptuOtroPtuptuO troPtuptuO troPtuptuOtroPtuptuO

ygolonhceTygolonhceT ygolonhceT ygolonhceTygolonhceT detroppuSseicneuqerFdetroppuSseicneuqerF detroppuSseicneuqerF detroppuSseicneuqerFdetroppuSseicneuqerF

SOMC/LTT ,zHM291.8/zHM671.6,zHM690.4/zHM880.3,zHM840.2/zHM445.1

zHM29.52,zHM44.91,zHM483.61/zHM253.21,)tluafed(zHM84.6

SOMC/LTT ,zHM291.8/zHM671.6,zHM690.4/zHM880.3,zHM840.2/zHM445.1

zHM48.15,)tluafed(zHM88.83,zHM29.52,zHM483.61/zHM253.21

SOMC/LTTdexif-zHM44.91

SOMC/LTTdexif-zHM88.83

SOMC/LTTdexif-zHM67.77

LSDVLCEP/

SDVL()tluafed

,zHM291.8/zHM671.6,zHM690.4/zHM880.3,zHM840.2/zHM445.1

,zHM25.551,)tluafed(zHM88.83,zHM44.91,zHM483.61/zHM253.21

zHM40.113

SDVL/LCEP

LCEP()tluafed zHM25.551,zHM67.77,zHM48.15,)tluafed(zHM44.91

IMA)zHk8+zHk46,kcolcetisopmoc(zHk8/46

SOMC/LTTzHM840.2/zHM445.1

010

SOMC/LTTRSM05:05ahtiw-zHk8,cnySrF

110

SOMC/LTTRSM05:05ahtiw-zHk2,cnySrFM

Table 8. Output Reference Source Selection TableTable 8. Output Reference Source Selection Table

Table 8. Output Reference Source Selection Table

www.semtech.com18

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

the filter can be opened up to reduce locking

time and can then be gradually tightened again

to remove wander. Since wander represents a

relatively long-term deviation from the nominal

operating frequency, it affects the rate of supply

of data to the network element. Strong wander

attenuation limits the rate of consumption of

data to within a smaller range, so a larger buffer

store is required to prevent data loss. But, since

any buffer store potentially increases latency,

wander may often only need to be removed at

specific points within a network where buffer

stores are acceptable, such as at digital cross

connects. Otherwise, wander is sometimes not

required to be attenuated and can be passed

through transparently. The ACS8510 has

programmable wander transfer characteristics

in a range from 0.1 Hz to 20 Hz. The wander

and jitter transfer characteristic is shown in

Figure 5.

Wander on the local oscillator clock will not

have significant effect on the output clock whilst

in Locked mode, so long as the DPLL bandwidth

is set high enough so that the DPLL can

compensate quickly enough for any frequency

changes in the crystal. In Free-run or Holdover

mode wander on the crystal is more significant.

Variation in crystal temperature or supply

voltage both cause drifts in operating frequency,

as does ageing. These effects must be limited

by careful selection of a suitable component

for the local oscillator, as specified in the section

‘Local Oscillator Clock’.

Phase VariationPhase Variation

Phase Variation

There will be a phase shift across the ACS8510

between the selected input reference source

and the output clock. This phase shift may vary

over time but will be constrained to lie within

specified limits. The phase shift is characterised

using two parameters, MTIE (Maximum Time

Interval Error), and TDEV (Time Deviation), which,

although being specified in all relevent

specifications, differ in acceptable limits in each

one. Typical measurements for the ACS8510

are shown in Figures 6 and 7, for Locked mode

operation. Figure 8 shows a typical

measurement of Phase Error accumulation in

Holdover mode operation.

The required performance for phase variation

during Holdover is specified in several ways

depending upon the particular circumstances

pertaining:

edoMedoM edoM edoMedoMotqerFotqerF otqerF otqerFotqerF

LLPALLPA LLPA LLPALLPA

reilpitluMreilpitluM reilpitluM reilpitluMreilpitluM

LLPALLPA LLPA LLPALLPA

qerFqerF qerF qerFqerF

tlif_klctlif_klc tlif_klc tlif_klctlif_klc_klc_klc _klc _klc_klc

2/tlif2/tlif 2/tlif 2/tlif2/tlif

_klc_klc _klc _klc_klc

4/tlif4/tlif 4/tlif 4/tlif4/tlif

_klc_klc _klc _klc_klc

6/tlif6/tlif 6/tlif 6/tlif6/tlif

_klc_klc _klc _klc_klc

8/tlif8/tlif 8/tlif 8/tlif8/tlif

_klc_klc _klc _klc_klc

21/tlif21/tlif 21/tlif 21/tlif21/tlif

_klc_klc _klc _klc_klc

61/tlif61/tlif 61/tlif 61/tlif61/tlif

_klc_klc _klc _klc_klc

84/tlif84/tlif 84/tlif 84/tlif84/tlif

LLPDLLPD LLPD LLPDLLPD

qerFqerF qerF qerFqerF

tluafeD67.774 40.11340.11325.55167.7748.1588.8329.5244.9184.667.77

eulavn616161616188

8844

1Exn867.234 270.131270.131635.56867.23867.23 867.23 867.23867.2333548.12483.61483.61 483.61 483.61483.6176229.01291.8291.8 291.8 291.8291.8766037.267.77

1Txn407.424618.89618.89804.94407.42407.42 407.42 407.42407.4233964.61253.21253.21 253.21 253.21253.21766432.8671.6671.6 671.6 671.6671.6766850.267.77

tuptuOybelbaliavAseicneuqerF

10T

20T

30T

40T

50T

60T 60T 60T

70T 70T

Table 9. Multiple E1/DS1 Ouputs in relation to Standard OutputsTable 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs

Table 9. Multiple E1/DS1 Ouputs in relation to Standard Outputs

www.semtech.com19

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

1. ETSI 300 462-5, Section 9.1, requires that the short-

term phase error during switchover (i.e., Locked to Holdover

to Locked) be limited to an accumulation rate no greater

than 0.05 ppm during a 15 second interval.

2. ETSI 300 462-5, Section 9.2, requires that the long-

term phase error in the Holdover mode should not

exceed

{(a1+a2)S+0.5bS2+c}

where

a1 = 50 ns/s (allowance for initial frequency offset)

a2 = 2000 ns/s (allowance for temperature variation)

b = 1.16x10-4 ns/s2 (allowance for ageing)

c = 120 ns (allowance for entry into Holdover mode).

3. ANSI Tin1.101-1994, Section 8.2.2, requires that the

phase variation be limited so that no more than 255 slips

(of 125 µs each) occur during the first day of Holdover.

This requires a frequency accuracy better than:

((24x60x60)+(255x125µs))/(24x60x60) = 0.37 ppm

Temperature variation is not restricted, except to within

the normal bounds of 0 to 50 °C.

4. Telcordia GR.1244.CORE, Section 5.2., Table 4, shows

that an initial frequency offset of 50 ppb is permitted on

entering Holdover, whilst a drift over temperature of

280 ppb is allowed; an allowance of 40 ppb is permitted

for all other effects.

5. ITU G.822, Section 2.6, requires that the slip rate during

category(b) operation (interpreted as being applicable to

Holdover mode operation) be limited to less than 30 slips

(of 125 µs each) per hour

((((60 x 60)/30)+125µs)/(60x60)) = 1.042 ppm

-3

-5

-10

-15

-20

-25

-30

Gain (dB)

0.01 0.1 110 100 1000

Frequency (Hz)

0.1 Hz

0.3 Hz

0.5 Hz

1.0 Hz

2.0 Hz

4.0 Hz

8.0 Hz

17 Hz

Figure 5. Wander and Jitter Measured Transfer CharacteristicsFigure 5. Wander and Jitter Measured Transfer Characteristics

Figure 5. Wander and Jitter Measured Transfer Characteristics

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

0.1

0.01

Time

(ns)

0.01 0.1 110 100 1000 10000

Observation interval (s)

G.813 option 1 constant temperature wander limit

TDEV measurement on 155 MHz output, 19.44 MHz i/p (8kHz locking),

Vectron 6664 xtal

100

0.1

0.01

0.01 0.1 110 100 1000 10000

Observation interval (s)

Time

(ns)

G.813 option 1, constant temperature wander limit

MTIE measurement on 155 MHz output, 19.44 MHz i/p (8kHz locking),

Vectron 6664 xtal

10000000

1000000

100000

10000

1000

100 1000 10000 100000

Observation interval (s)

Phase Error (ns)

Permitted Phase Error Limit

Typical measurement, 25°C constant temperature

Figure 8. Phase error accumulation of TFigure 8. Phase error accumulation of T

Figure 8. Phase error accumulation of TOUT0OUT0

OUT0OUT0

OUT0 output port in Holdover mode output port in Holdover mode

output port in Holdover mode output port in Holdover mode

output port in Holdover mode

Figure 6. Maximum Time Interval Error of TFigure 6. Maximum Time Interval Error of T

Figure 6. Maximum Time Interval Error of TOUT0OUT0

OUT0OUT0

OUT0 output port output port

output port output port

output port

Figure 7. Time Deviation of TFigure 7. Time Deviation of T

Figure 7. Time Deviation of TOUT0OUT0

OUT0OUT0

OUT0 output port output port

output port output port

output port

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Phase Build OutPhase Build Out

Phase Build Out

Phase Build Out (PBO) is the function to minimise

phase transients on the output SEC clock during

input reference switching. If the currently

selected input reference clock source is lost

(due to a short interruption, out of frequency

detection, or complete loss of reference), the

second, next highest priority reference source

will be selected. During this transition, the

Lost_Phase mode is entered.

The typical phase disturbance on clock

reference source switching will be less than

12 ns on the ACS8510. For clock reference

switching caused by the main input failing or

being disconnected, then the phase disturbance

on the output will still be less than the 120 ns

allowed for in the G.813 spec. The actual value

is dependent on the frequency being locked to.

ITU-T G.813 states that the max allowable short

term phase transient response, resulting from

a switch from one clock source to another,

with Holdover mode entered in between, should

be a maximum of 1 µs over a 15 second

interval. The maximum phase transient or jump

should be less than 120 ns at a rate of change

of less than 7.5 ppm and the Holdover

performance should be better than 0.05 ppm.

On the ACS8510, PBO can be enabled, disabled

or frozen using the µP interface. By default, it

is enabled. When PBO is enabled, it can also

be frozen, which will disable the PBO operation

on the next input reference switch, but will

remain with the current offset. If PBO is disabled

while the device is in the Locked mode, there

will be a phase jump on the output SEC clocks

as the DPLL locks back to 0 degree phase

error.

Microprocessor InterfaceMicroprocessor Interface

Microprocessor Interface

The ACS8510 incorporates a microprocessor

interface, which can be configured for the

following modes via the bus interface mode

control pins UPSEL(2:0) as defined in Table 10.

Table 10. Microprocessor InterfaceTable 10. Microprocessor Interface

Table 10. Microprocessor Interface

Mode SelectionMode Selection

Mode Selection

Motorola ModeMotorola Mode

Motorola Mode

Parallel data + address: this mode is suitable

for use with Motorola's 68x0 type bus.

Intel ModeIntel Mode

Intel Mode

Parallel data + address: this mode is suitable

for use with Intel's 80x86 type bus.

Multiplexed ModeMultiplexed Mode

Multiplexed Mode

Data/address: this mode is suitable for use

with microprocessors which share bus signals

between address and data (e.g., Intel's 80x86

family).

Serial ModeSerial Mode

Serial Mode

This mode is suitable for use with micro-

processor which use a serial interface.

EPROM ModeEPROM Mode

EPROM Mode

This mode is suitable for simple standalone

applications where it is required to change the

default loading of the register values to suit

different applications.

This can be done by loading values from an

external ROM. The data is read from the ROM

automatically after power up when the

UPSEL(2:0) pins are set to ‘001’. Each register

value is stored sequentially, with ROM address

0 corresponding to register address 0 and so

on.

The value in the ‘chip_id’ location (address 00

& 01) is checked to see if it matches the ID

number of the ACS8510 V2 (value 213E). Upon

a successful number match, the remaining data

UPSEL(2:0)UPSEL(2:0)

UPSEL(2:0) ModeMode

ModeMode

Mode DescriptionDescription

DescriptionDescription

Description

111 (7) OFF Interface disabled

110 (6) OFF Interface disabled

101 (5) SERIAL Serial uP bus interface

100 (4) MOTOROLA Motorola interface

011 (3) INTEL Intel compatible bus interface

010 (2) MULTIPLEXED Multiplexed bus interface

001 (1) EPROM EPROM read mode

000 (0) OFF Interface disabled

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Interrupt Enable and ClearInterrupt Enable and Clear

Interrupt Enable and Clear

Interrupt requests are flagged on pin INTREQ

(active High). Bits in the interrupt status register

are set (high) by the following conditions:

1. Any reference source becoming valid or going invalid

2. A change in the operating state (eg. Locked, Holdover

etc.)

3. A brief loss of the currently selected reference source

4. An AMI input error

All interrupt sources are maskable via the mask

'1' to the appropriate bit. Any unmasked bit set

in the interrupt status register will cause the

interrupt request pin to be asserted (high). All

interrupts are cleared by writing a '1' to the

bit(s) to be cleared in the status register. When

all pending unmasked interrupts are cleared

the interrupt pin will go inactive (low).

The loss of the currently selected reference

source will eventually cause the input to be

considered invalid, triggering an interrupt. The

time taken to raise this interrupt is dependant

on the leaky bucket configuration of the activity

monitors. The fastest leaky bucket setting will

still take up to 128 ms to trigger the interrupt.

The interrupt caused by the brief loss of the

currently selected reference source is provided

to facilitate very fast source failure detection if

desired. It is triggered after missing just a

couple of cycles of the reference source. Some

applications require the facility to switch

downstream devices based on the status of

the reference sources. In order to provide extra

flexibility, it is possible to flag the ‘main

reference failed’ interrupt (addr 06, bit 6) on

the pin TDO. This is simply a copy of the status

bit in the interrupt register and is independent

of the mask register settings. The bit is reset

by writing to the interrupt status register in the

normal way. This feature can be enabled and

disabled by writing to bit 6 of register 48Hex.

from the ROM is used to set the internal register

values. Only 64 locations in the ROM are

required.

All registers are 8-bits wide, organised with the

most-significant bit positioned in the left-most

bit, with bit significance decreasing towards the

right most bit. Some registers carry several

individual data fields of various sizes, from

single-bit values (e.g. flags) upwards. Several

data fields are spread across multiple registers;

their organisation is shown in the register map,

Table 11.

Configuration RegistersConfiguration Registers

Configuration Registers

Each configuration register reverts to a default

value on power-up or following a reset. Most

default values are fixed, but some will be pin-

settable. All configuration registers can be read

out over the microprocessor port.

Status RegistersStatus Registers

Status Registers

The Status Registers contain readable registers.

They may all be read from outside the chip but

are not writeable from outside the chip (except

for a clearing operation). All status registers

are read via shadow registers to avoid data

hits due to dynamic operation. Each individual

status register has a unique location.

Most registers are of one of two types,

configuration registers or status registers, the

exceptions being the chip_ID and chip_revision

registers. Configuration registers may be written

to or read from at any time (the complete 8-bit

being modified). All status registers may be read

at any time and, in some status registers (such

as the sts_interrupts register), any individual

data field may be cleared by writing a ‘1’ into

each bit of the field (writing a ‘0’ value into a

bit will not affect the value of the bit). A

description of each register is given in the

www.semtech.com23

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA.rddA .rddA .rddA.rddA

)xeH()xeH( )xeH( )xeH()xeH(

emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6655

5544

4433

3322

2211

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

00di_pihc

)ylnodaer(

)0:7(rebmuntrapeciveD

10 )8:51(rebmuntrapeciveD

20noisiver_pihc

)ylnodaer( )0:7(rebmunnoisiverpihC

301lortnoc_gfnc

)etirw/daer(

elpitluM

P/O1T/1E

golanA

cnysvid '0'otteS egdEk8

ytiraloP '0'otteS'0'otteS

402lortnoc_gfnc

)etirw/daer( timilgalfssolesahP'0'otteS'1'otteS'0'otteS

50stpurretni_sts

)etirw/daer(

dilav>8_I<

egnahc

dilav>7_I<

egnahc

dilav>6_I<

egnahc

dilav>5_I<

egnahc

dilav>4_I<

egnahc

dilav>3_I<

egnahc

dilav>2_I<

egnahc

dilav>1_I<

egnahc

60gnitarepO

edom

.ferniaM

deliaf

dilav>41_I<

egnahc

dilav>31_I<

egnahc

dilav>21_I<

egnahc

dilav>11_I<

egnahc

dilav>01_I<

egnahc

dilav>9_I<

egnahc

80stupni_4T_sts

)etirw/daer( deliaffer4T 2imA

noitaloiV

2imA

.S.O.L

1imA

noitaloiV

1imA

.S.O.L

90edom_gnitarepo_sts

)ylnodaer( )0:2(edomgnitarepO

A0elbat_ytiroirp_sts

)ylnodaer(

ecruosdilavytiroirptsehgiH ecruosecnereferdetcelesyltnerruC

B0 3

ecruosdilavytiroirptsehgih2

ecruosdilavytiroirptsehgih

C0tesffo_cni_rruc_sts

)ylnodaer(

)0:7(tesffotnemercnitnerruC

D0 )8:51(tesffotnemercnitnerruC

70 )61:81(tesffotnemercnitnerruC

E0dilav_secruos_sts

)ylnodaer(

>8_I<>7_I<>6_I<>5_I<>4_I<>3_I<>2_I<>1_I<

F0 >41_I<>31_I<>21_I<>11_I<>01_I<>9_I<

Shaded areas in the map are ‘don’t care’ and writing either 0 or 1 will not affect any function of

the device.

Bits labelled ‘Set to 0’ or ‘Set to 1’ must be set as stated during initialisation of the device,

either following power up, or after a power on reset (POR). Failure to correctly set these bits may

result in the device operating in an unexpected way.

Some registers do not appear in this list. These are either not used, or have test functionality. Do

not write to any undefined registers as this may cause the device to operate in a test mode. If an

undefined register has been inadvertently addressed, the device should be reset to ensure the

undefined registers are at default values.

Table 11. Register MapTable 11. Register Map

Table 11. Register Map

www.semtech.com24

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA.rddA .rddA .rddA.rddA

)xeH()xeH( )xeH( )xeH()xeH(

emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6655

5544

4433

3322

2211

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

01secruos_ecnerefer_sts

)etirw/daer(

>2_I<sutats>1_I<sutats

11 >4_I<sutats>3_I<sutats

21 >6_I<sutats>5_I<sutats

31 >8_I<sutats>7_I<sutats

41 >01_I<sutats>9_I<sutats

51 >21_I<sutats>11_I<sutats

61 >41_I<sutats>31_I<sutats

81ytiroirp_noitceles_fer_gfnc

)etirw/daer(

>2_I<ytiroirp_demmargorp >1_I<ytiroirp_demmargorp

91 >4_I<ytiroirp_demmargorp >3_I<ytiroirp_demmargorp

A1 >6_I<ytiroirp_demmargorp >5_I<ytiroirp_demmargorp

B1 >8_I<ytiroirp_demmargorp >7_I<ytiroirp_demmargorp

C1 >01_I<ytiroirp_demmargorp >9_I<ytiroirp_demmargorp

D1 >21_I<ytiroirp_demmargorp >11_I<ytiroirp_demmargorp

E1 >41_I<ytiroirp_demmargorp >31_I<ytiroirp_demmargorp

02ycneuqerf_ecruos_fer_gfnc

)etirw/daer(

nvidk8kcol)0:1(>1_I<di_tekcub)0:3(>1_I<ycneuqerf_ecruos_ecnerefer

12 nvidk8kcol)0:1(>2_I<di_tekcub)0:3(>2_I<ycneuqerf_ecruos_ecnerefer

22 nvidk8kcol)0:1(>3_I<di_tekcub)0:3(>3_I<ycneuqerf_ecruos_ecnerefer

32 nvidk8kcol)0:1(>4_I<di_tekcub)0:3(>4_I<ycneuqerf_ecruos_ecnerefer

42 nvidk8kcol)0:1(>5_I<di_tekcub)0:3(>5_I<ycneuqerf_ecruos_ecnerefer

52 nvidk8kcol)0:1(>6_I<di_tekcub)0:3(>6_I<ycneuqerf_ecruos_ecnerefer

62 nvidk8kcol)0:1(>7_I<di_tekcub)0:3(>7_I<ycneuqerf_ecruos_ecnerefer

72 nvidk8kcol)0:1(>8_I<di_tekcub)0:3(>8_I<ycneuqerf_ecruos_ecnerefer

82 nvidk8kcol)0:1(>9_I<di_tekcub)0:3(>9_I<ycneuqerf_ecruos_ecnerefer

92 nvidk8kcol)0:1(>01_I<di_tekcub)0:3(>01_I<ycneuqerf_ecruos_ecnerefer

A2 nvidk8kcol)0:1(>11_I<di_tekcub)0:3(>11_I<ycneuqerf_ecruos_ecnerefer

B2 nvidk8kcol)0:1(>21_I<di_tekcub)0:3(>21_I<ycneuqerf_ecruos_ecnerefer

C2 nvidk8kcol)0:1(>31_I<di_tekcub)0:3(>31_I<ycneuqerf_ecruos_ecnerefer

D2 nvidk8kcol)0:1(>41_I<di_tekcub)0:3(>41_I<ycneuqerf_ecruos_ecnerefer

Table 11. Register Map (continued).Table 11. Register Map (continued).

Table 11. Register Map (continued).

www.semtech.com25

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA.rddA .rddA .rddA.rddA

)xeH()xeH( )xeH( )xeH()xeH(

emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6655

5544

4433

3322

2211

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

03_secruos_etomer_sts_gfnc

dilav

)etirw/daer(

>1:8<slennahc,sutatsetomeR

13 >9:41<slennahc,sutatsetomeR

23edom_gnitarepo_gfnc

)etirw/daer( edomgnitarepodecroF

33noitceles_fer_gfnc

)etirw/daer( ecruos_ecnerefer_tceles_ecrof

43edom_gfnc

)etirw/daer( otuA

lanretxe

elbaneK2

esahP

mrala

tuoemit

elbane

egdekcolC

revodloH

tesffO

elbane

K2lanretxE

elbanecnyS

/TENOS

HDS

P/I

/retsaM

evalS

noisreveR

edom

534T_gfnc

)etirw/daer( hcleuqS tceleS

1T/0T

noitcelesecruostupni1TecroF

)01_Iot5_Istupnirofdilavylno(

63stupni_laitnereffid_gfnc

)etirw/daer(

>6_I<

LCEP

>5_I<

LCEP

73snip_lesPu_gfnc

)ylnodaer( epytrossecorp-orciM

83elbane_tuptuo_0T_gfnc

)etirw/daer( zHM40.113

60Tno

TENOS=1

HDS=0

2giDrof

TENOS=1

HDS=0

1giDrof

10T20T 30T

zHM44.91

40T

zHM88.83

50T

zHM67.77

93seicneuqerf_tuptuo_0T_gfnc

)etirw/daer( 2latigiD1latigiD20T10T

A3stuptuo_laitnereffid_gfnc

)etirw/daer(

ycneuqerF70T

noitceles

ycneuqerF60T

noitceles

SDVL70T

elbane

LCEP70T

elbane

SDVL60T

elbane

LCEP60T

elbane

B3htdiwdnab_gfnc

)etirw/daer(

w/botuA

hctiws

kcol/qcA

htdiwdnabnoitisiuqcA'0'otteShtdiwdnabdekcol/lamroN

C3ycneuqerf_lanimon_gfnc

)etirw/daer(

)0:7(ycneuqerflanimoN

D3 )8:51(ycneuqerflanimoN

E3tesffo_revodloh_gfnc

)etirw/daer(

)0:7(tesfforevodloH

F3 )8:51(tesfforevodloH

04otuA

revodloH

gnigarevA

)61:81(tesfforevodloH

14timil_qerf_gfnc

)etirw/daer(

)0:7(timiltesffoycneuqerFLLPD

24 tesffoycneuqerFLLPD

)8:9(timil

34ksam_tpurretni_gfnc

)etirw/daer(

dilav>8_I<

egnahc

dilav>7_I<

egnahc

dilav>6_I<

egnahc

dilav>5_I<

egnahc

dilav>4_I<

egnahc

dilav>3_I<

egnahc

dilav>2_I<

egnahc

dilav>1_I<

egnahc

44gnitarepO

edom

.ferniaM

deliaf

dilav>41_I<

egnahc

dilav>31_I<

egnahc

dilav>21_I<

egnahc

dilav>11_I<

egnahc

dilav>01_I<

egnahc

dilav>9_I<

egnahc

54 fer4T 2imA

noitaloiV

2imA

S.O.L

1imA

noitaloiV

1imA

S.O.L

64nvid_qerf_gfnc

)etirw/daer(

)0:7(oitarn-yb-tupni-ediviD

74 )8:31(oitarn-yb-tupni-ediviD

Table 11. Register Map (continued).Table 11. Register Map (continued).

Table 11. Register Map (continued).

www.semtech.com26

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA.rddA .rddA .rddA.rddA

)xeH()xeH( )xeH( )xeH()xeH(

emaNretemaraPemaNretemaraP emaNretemaraP emaNretemaraPemaNretemaraPtiBataDtiBataD tiBataD tiBataDtiBataD

)bsm(7)bsm(7 )bsm(7 )bsm(7)bsm(766

6655

5544

4433

3322

2211

11)bsl(0)bsl(0 )bsl(0 )bsl(0)bsl(0

84srotinom_gfnc

)etirw/daer( tsolfergalF

ODTno

tsaf-artlU

gnihctiws

lanretxE

ecruos

hctiws

elbane

esahpezeerF

tuodliub

esahP

tuodliub

elbane

srotinomycneuqerF

)0:1(noitarugifnoc

050dlohserht_reppu_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesmralaytivitcA:0noitarugifnoC

150dlohserht_rewol_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesermralaytivitcA:0noitarugifnoC

250ezis_tekcub_gfnc

)etirw/daer( )0:7(ezistekcubmralaytivitcA:0noitarugifnoC

350etar_yaced_gfnc

)etirw/daer( )0:1(etar_yaced:0gfC

451dlohserht_reppu_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesmralaytivitcA:1noitarugifnoC

551dlohserht_rewol_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesermralaytivitcA:1noitarugifnoC

651ezis_tekcub_gfnc

)etirw/daer( )0:7(ezistekcubmralaytivitcA:1noitarugifnoC

751etar_yaced_gfnc

)etirw/daer( )0:1(etar_yaced:1gfC

852dlohserht_reppu_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesmralaytivitcA:2noitarugifnoC

952dlohserht_rewol_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesermralaytivitcA:2noitarugifnoC

A52ezis_tekcub_gfnc

)etirw/daer( )0:7(ezistekcubmralaytivitcA:2noitarugifnoC

B52etar_yaced_gfnc

)etirw/daer( )0:1(etar_yaced:2gfC

C53dlohserht_reppu_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesmralaytivitcA:3noitarugifnoC

D53dlohserht_rewol_vitca_gfnc

)etirw/daer( )0:7(dlohserhttesermralaytivitcA:3noitarugifnoC

E53ezis_tekcub_gfnc

)etirw/daer( )0:7(ezistekcubmralaytivitcA:3noitarugifnoC

F53etar_yaced_gfnc

)etirw/daer( )0:1(etar_yaced:3gfC

F7lesPu_gfnc

)etirw/daer( epytrossecorp-orciM

Table 11. Register Map (continued).Table 11. Register Map (continued).

Table 11. Register Map (continued).

www.semtech.com27

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 12. Register Map DescriptionTable 12. Register Map Description

Table 12. Register Map Description

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

di_pihc )lamiced(0158=DIpihcehtsniatnocretsigersihT

00)0:7(stibDIpihC)0:7(stiB 01111100

10)8:51(stibDIpihC)0:7(stiB 10000100

noisiver_pihc rebmunnoisiverpihcehtsniatnocretsigerylnodaersihT

1=noisiversihT

0=)selpmasgnireenigne(noisivertsaL

10000000

1lortnoc_gfncdesunU)6:7(stiB

5tiB

.zhM67.77lamronehtfodaetsniLLPAehtotycneuqerf2giDx2sdeeF:LLPAotzHM42/231=

stibtes2giD:etoN.setar1T/1Eelpitlumhtiwdecalpererastuptuo1MTS/3COlamronehtsuhT

.edomsihtrof11ottesebtsum))6:7(stiBh93.geR(

LLPAotzHM67.770=

4tiB

noitcesLLPDehtnisredividehtotnoitcesLLPAtuptuoehtnisredividehtsezinorhcnyS1=

stupnineewtebtnemngilaesahpevahotredroniyrassecensisihT.ngilasesahpriehttahthcus

ebyamhgihtibsihtgnipeeK.)zHM67.77otzHM84.6(setardevired3COtaskcolctuptuodna

ycneuqerfnisegnahckciuqnehwnoitazinorhcnysfotuognittegsredividehtdiovaotyrassecen

.nuR-eerFotniecrofasahcusrucco

ehtedomsihtnitub,ycneuqerfnisegnahcpetsgniwollofesahpfotuotegyamsredividehT0=

ehT.doirepnoitazinorhcnysynanihtiwdeetneraugsisegdeycneuqerfhgihforebmuntcerroc

.)tluafed(kcolycneuqerflliwtuptuo

tluafedehterofeb,teseramorfsdnoces2noitazinorhcnysniniamersyawlalliwecivedehT

.seilppagnittes

'0'ottesro,degnahcnuevael-lortnoctseT3stiB

2tiB

.egdekcolctupnignisirehtotkcollliwmetsysehtedomgnikcolk8ninehW1=

.egdekcolctupnignillafehtotkcollliwmetsysehtedomgnikcolk8ninehW0=

'00'ottesro,degnahcnuevael-slortnoctseT)0:1(stiB

000000XX

2lortnoc_gfncdesunU)6:7(stiB

otsdnopserrochcihw)001(4ottestluafedyB.timilgalfssolesahpehtenifed)3:5(stiB

timilgalfehT.timilesahprewolgnidnopserrocasteseulavrewolA.°041yletamixorppa

esahpa,rettijtupnifotluserasatsolesahpsetacidniLLPDehthcihwtaeulavehtsenimreted

tupniehtnopmujycneuqerfaro,pmuj

'010'ottesro,degnahcnuevael-slortnoctseT)0:2(stiB

010001XX

stpurretni_sts ehtecnereferfossolrofeno,dilav_secruos_stsfotibhcaeroftibenosniatnocretsigersihT

.hgihevitcaerastibllA.edomgnitarepoehtrofrehtonadna,otdekcolsawecived

tnevelerehtfoetatsehtni'egnahc'anotesera)41tib(tibdeliaf_fer_niamehttpecxestibllA

ehtfI.tpurretninareggirtlliwtidilavniseogro,dilavsemocebecruosafi.e.i,tibsutats

.detarenegeblliwtpurretniehtetatssegnahc)9retsiger(edoMgnitarepO

ecnereferehtnoytivitcanigalfotdesusiretsigersutatstpurretniehtfo)deliaf_fer_niam(41tiB

ehtfo6tibfI.troppusnacsrotinomytivitcaehtnahtylkciuqeromotdekcolsiecivedehttaht

ehtotnonevirdsitibsihtfoetatsehtneht,tessi)ODTnossolfergalf(retsigersrotinom_gfnc

.ecivedehtfonipODT

deraelcebyamtibhcaE.retsigerksam_tpurretni_gfncehtnistibehtybelbaksamerastibllA

ebnacstibforebmunynA.tpurretniehtgnittesersuht,tibtahtot'1'agnitirwybyllaudividni

.tceffeonevahlliws'0'gnitirW.noitarepoetirwelgnisahtiwderaelc

50>1_I<ot>8_I<)0:7(stiB 00000000

60 >9_I<ot>41_I<,deliafferniam,edomgnitarepO)0:7(stiB 00000000

www.semtech.com28

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

stupni_4T_sts ecnosmralaehT.ecnerefer4TUOTehtdnastupniIMAehtfosgalfsutatsehtsdlohretsigersihT

,tibtahtot'1'agnitirwybyllaudividnideraelcebyamtibhcaE.teserlitnuetatsriehtdlohlliwtes

etarenegoslanacstibesehT.tceffeonevahlliws'0'gnitirW.tpurretniehtgnittesersuht

.stpurretni

.desunU)5:7(stiB

4tiB

Tdilavon-deliafecnerefer4T1=

1NI

kcoltonnacLLPD4T,)>5_I<:>01_I<(tupni

)tluafed(ecruosot

Tdilav-doogecnerefer4T0=

1NI

.elbaliavatupni

3tiB

detcetednoitaloiV2imA1=

)tluafed(raelc2imA0=

2tiB

langisfossoL2imA1=

)tluafed(raelc2imA0=

1tiB

detcetednoitaloiV1imA1=

)tluafed(raelc1imA0=

0tiB

langisfossoL1imA1=

)tluafed(raelc1imA0=

00001XXX

edom_gnitarepo_sts 11erugiF.enihcametatsniamehtfoetatsgnitarepotnerrucehtsdlohretsigerylno-daersihT

.setatslaudividniehthtiwhctamelbairav'etatsgnitarepo'ehtfoseulavehtwohswohs

.desunU)3:7(stiB

etatS)0:2(stiB

)tluafed(nuR-eerF100

revodloH010

dekcoL001

dekcol-erP011

2dekcol-erP101

tsolesahP111

100XXXXX

elbat_ytiroirp_sts.retsigerylno-daertib-61asisihT

ecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgihdrihT)21:51(stiB

dilavytiroirp-tsehgih-dnocesehtotytiroirptsehgih-txenehtsahdnadilavsihcihwecruos

.ecruos

tupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgihdnoceS)8:11(stiB

dilavytiroirp-tsehgihehtotytiroirptsehgih-txenehtsahdnadilavsihcihwecruosecnerefer

.ecruos

ecruosecnerefertupniehtforebmunlennahcehtsisiht:ecruosdilavytiroirptsehgiH)4:7(stiB

detcelesyltnerrucehtsaemasehtebtonyamti-ytiroirptsehgihehtsahdnadilavsihcihw

.)ytiroirpdemmargorpnisegnahcroyrotsiheruliafoteud(ecruosecnerefer

ecnerefertupniehtforebmunlennahcehtsisiht:ecruosecnereferdetcelesyltnerruC)0:3(stiB

.LLPDottupniyltnerrucsihcihwecruos

ehtfostnetnocehtotesnopsernienihcametatsehtybdetadpuerasretsigeresehttahtetoN

lennahc;slennahclaudividnifosutatsgniognoehtdnaretsigerytiroirp_noitceles_fer_gfnc

rofelbaliavasilennahcontahtsetacidni,sretsigeresehtfoynanigniraeppa,'0000'rebmun

.ytiroirptaht

A0 ))4:7(stibelbat_ytiroirp_sts(ecruosdilavytiroirptsehgiH)4:7(stiB

))0:3(stibelbat_ytiroirp_sts(ecruosecnereferdetcelesyltnerruC)0:3(stiB 00000000

B0 3)4:7(stiB

))21:51(stibelbat_ytiroirp_sts(ecruosdilavytiroirptsehgih-

2)0:3(stiB

))8:11(stibelbat_ytiroirp_sts(ecruosdilavytiroirptsehgih- 00000000

www.semtech.com29

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

tesffo_cni_rruc_sts fostibtnacifingis91ehtgnitneserpereulavregetni-dengisasniatnocretsigerylno-daersihT

dliubotyllacidoirepdaerebyamretsigerehT.LLPlatigidehtfotesffotnemercnitnerruceht

fiyrassecenebylnodluowsiht(sdoireprevodlohgnirudesuretalrofesabatadlacirotsihapu

rotallicsOlacoLnidebircsedairetircytilibatsehtteemtondidhcihwrotallicsolanretxena

.teserretfayletaidemmi00000000daerlliwretsigerehT.)desusinoitceskcolC

C0 )0:7(stibtesffo_cni_rruc_sts)0:7(stiB 00000000

D0 )8:51(stibtesffo_cni_rruc_sts)0:7(stiB 00000000

70 desunU)3:7(stiB

)61:81(stibtesffo_cni_rruc_sts)0:2(stiB 000XXXXX

dilav_secruos_sts .ecruosecnereferyreverofytidilavwohsottibasniatnocretsigersihT

ecruosdilaV1=

)tluafed(ecruosdilavnI0=

E0>1_I<ot>8_I<)0:7(stiB 00000000

F0 desunU)6:7(stiB

>9_I<ot>41_I<)0:5(stiB 000000XX

secruos_ecnerefer_sts ehT.secruosecnerefertupni41ehtfohcaefosutatsehtsdlohhcihwretsigeretyb-7asisihT

sutatsdiaoT.hgihevitcasitibhcaE.dleiftib-4aninwohssiecruosecnereferhcaefosutats

sutatsehT.retsigerdilav_secruos_stsehtnidedivorpsi3tibsutatshcaefoypoca,gnikcehc

)yllaudividnideraelcebyamtibhcaE(:swollofsadetropersi

)0tluafed())0:2(stibfonoitanibmocsi3tib()smralaon(dilavecruoS=3tibsutatS

)1tluafed(mraladnab-fo-tuo=2tibsutatS

)1tluafed(mralaytivitcaon=1tibsutatS

)0tluafed(mralakcolesahp=0tibsutatS

01 >2_I<ecruosecnerefertupnifosutatS)4:7(stiB

>1_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

11 >4_I<ecruosecnerefertupnifosutatS)4:7(stiB

>3_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

21 secruos_ecnerefer_sts

)deunitnoc(

>6_I<ecruosecnerefertupnifosutatS)4:7(stiB

>5_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

31 >8_I<ecruosecnerefertupnifosutatS)4:7(stiB

>7_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

41 >01_I<ecruosecnerefertupnifosutatS)4:7(stiB

>9_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

51 >21_I<ecruosecnerefertupnifosutatS)4:7(stiB

>11_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

61 >41_I<ecruosecnerefertupnifosutatS)4:7(stiB

>31_I<ecruosecnerefertupnifosutatS)0:3(stiB 01100110

ytiroirp_noitceles_fer_gfnc eraseulavytiroirpehT.secruosecnerefertupni41ehtfohcaefoytiroirpehtsdlohretsigersihT

'1'seulavehtylnO.seitiroirprehgihgnikatsrebmundeulav-rewolhtiw,rehtohcaeotevitalerlla

ebdluohsecruosecnereferhcaE.ecruosecnereferehtselbasid'0'-dilavera)ced('51'ot

dengissaeblliwrebmunytiroirpemasehtnevigsecruosowtrevewoh,rebmuneuqinuanevig

.sisabtuotsrifnitsrifano

ecnerefergnicrofnehwdesusisihtsa'1'eulavytiroirpehtevreserotdednemmocersitI

ehtesuotdnetnitonseodresuehtfI.retsigernoitceles_fer_gfncehtaivnoitceles

.devreserebtondeen'1'eulavytiroirpehtnehtretsigernoitceles_fer_gfnc

>2_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>1_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

01001100

>4_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>3_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

00101010

>6_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>5_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

01101110

>8_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>7_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

00011001

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com30

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

ytiroirp_noitceles_fer_gfnc

)deunitnoc(

>01_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>9_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

01011101

>21_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>11_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

10001011

)0=BVLSTSM(

00111011

)1=BVLSTSM(

>41_I<ecruosecnerefertupnifoytiroirpdemmargorP)4:7(stiB

>31_I<ecruosecnerefertupnifoytiroirpdemmargorP)0:3(stiB

01111111

ycneuqerf_ecruos_fer_gfnc .secruosecnerefertupni41ehtfohcaeputesotdesusiretsigersihT

ecnadroccani,ycneuqerftupniehtnonekatrednunoitarepoehtsenifedetybhcaefo)6:7(stiB

:yekgniwollofehthtiw

.)tluafed(.LLPDehtotniyltceriddefsiycneuqerftupniehT00

ehtotnidefgnieberofeb,zHk8otnwoddedividyllanretnisiycneuqerftupniehT10

.)ecnarelotrettijhgihroF(.LLPD

.esutonod-noitarugifnocdetroppusnU01

ot)nvid_qerf_gfnc(74dna64sretsigerniderotstneiciffeocnoisividehtsesU11

ycneuqerfehT.LLPDehtotnidefgniebotroirpeulavsihtybtupniehtedivid

ehT.zHk8lauqedluohsycneuqerfnwoddedividehT.delbasidebtsumsrotinom

lautcaehtwolebtsujycneuqerftopstseraenehtottesebdluohs)0:3(ycneuqerf

zHM445.1neewtebseicneuqerftupnirofskrowerutaefNviDehT.ycneuqerftupni

.zHM001dna

.F5ot05sretsigernidenifedsa,desusi)3-0(puorgtekcubykaelhcihwenifed)4:5(stiB

.)00tluafed(

:gniwollofehthtiwecnadroccaniecruosecnereferehtfoycneuqerfehtsenifed)0:3(stiB

)>4_I<,>3_I<tluafed,>2_I<,>1_I<dexif(zHk80000

)2tib,43retsigerybdenifedsa()HDS(zHM840.2/)TENOS(zHM445.11000

)>41_I<,>31_I<,>21_I<tluafed(

)1=BVLSTSMnehw>11_I<tluafed(zHM84.60100

,>8_I<,>7_I<,>6_I<,>5_I<dna,0=BVLSTSMnehw>11_I<tluafed(zHM44.911100

)>01_I<,>9_I<

zHM29.520010

zHM88.831010

zHM48.150110

zHM67.771110

zHM25.5510001

zHk21001

zHk40101

02 ylnozHk8rof00000000tadexif->1_I<ecruosecnereferfoycneuqerF 00000000

12 ylnozHk8rof00000000tadexif->2_I<ecruosecnereferfoycneuqerF 00000000

22>3_I<ecruosecnereferfoycneuqerF 00000000

32>4_I<ecruosecnereferfoycneuqerF 00000000

42>5_I<ecruosecnereferfoycneuqerF 11000000

52>6_I<ecruosecnereferfoycneuqerF 11000000

62>7_I<ecruosecnereferfoycneuqerF 11000000

72>8_I<ecruosecnereferfoycneuqerF 11000000

82>9_I<ecruosecnereferfoycneuqerF 11000000

92>01_I<ecruosecnereferfoycneuqerF 11000000

A2>11_I<ecruosecnereferfoycneuqerF

01000000

)0=BVLSTSM(

11000000

)1=BVLSTSM(

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com31

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

ycneuqerf_ecruos_fer_gfnc

)deunitnoc( >21_I<ecruosecnereferfoycneuqerF 10000000

C2 >31_I<ecruosecnereferfoycneuqerF 10000000

D2 >41_I<ecruosecnereferfoycneuqerF 10000000

_secruos_etomer_sts_gfnc

dilav

aniecivedrehtoehtotdeilppussecruosecnereferehtfosutatsehtsdlohretsigersihT

ehT.retsigerdilav_secruos_stss'ecivedrehtoehtfoypocasitI.noitarugifnocevals/retsam

.msinahcemnoitcetorpehtfotrapsiretsiger

03 >1_I<:>8_I<secruosecnerefeR)0:7(stiB 11111111

13 desunU)6:7(stiB

>9_I<:>41_I<secruosecnerefeR)0:5(stiB 111111XX

edom_gnitarepo_gfnc ehtybdetneserper,etatsgnitarepoderisedaotniecivedehtecrofotdesusiretsigersihT

etarepootenihcametatslortnocehtswolla)xeh(0eulaV.11erugiFninwohsseulavyranib

.yllacitamotua

desunU)3:7(stiB

)11erugiFrepsa(etatsgnitarepoderiseD)0:2(stiB

000XXXXX

noitceles_fer_gfnc ,ecruosecnerefertupniralucitrapatcelesotecivedehtecrofotdesusiretsigersihT

ottupnidetcelesehtsesiaryliraropmetretsigersihtotgnitirW.ytiroirpstifoevitcepserri

edomevitreverdna,'1'ytiroirphtiwdemmargorpydaerlasitupnirehtoondedivorP.'1'ytiroirp

.detceleseblliwecruossiht,nosi

desunU)4:7(stiB

dna,noitcelesecrofehtselbasid1111dna0000(ecruosecnereferderiseD)0:3(stiB

)1111sitluafed,secruosllafonoitcelescitamotuaswolla

1111XXXX

edom_gfnc :wolebdeliatedsa,sdleifnoitarugifnoclaudividnilarevessniatnocretsigersihT

7tiB

siecruosehtnehwylnodelbaneeblliwcnySzHk2lanretxE:elbanecnySzHk2otuA1=

)tluafed(delbasideblliwtiesiwrehtO.zHM84.6otdekcol

sa,retsigersihtfo3tibgnisunoitcnufsihtslortnocresuehT:elbasidcnySzHk2otuA0=

wolebdebircsed

6tiB

)tluafed(sdnoces001retfatuoemitlliwmralaesahpehT:elbanetuoemiTmralAesahP1=

ybteserebtsumdnatuoemittonlliwmralaesahpehT:elbasidtuoemiTmralAesahP0=

erawtfos

5tiB

lanretxeehtfoegdegnisirehtotecnereferlliwecivedehT:detcelesegdEkcolCgnisiR1=

langisrotallicsolatsyrczHM8.21

lanretxeehtfoegdegnillafehtotecnereferlliwecivedehT:detcelesegdEegdegnillaF0=

)tluafed(langisrotallicsolatsyrczHM8.21

4tiB

ehtniderotseulavtesfforevodloHehttpodalliwecivedehT:elbanetesfforevodloH1=

revodloHniycneuqerfehttesotredroni,retsigertesffo_revodloh_gfnc

ehtezeerflliwrevodloHdnaeulavehterongilliwecivedehT:elbasidtesfforevodloH0=

)tluafed(edomrevodloHgniretnenoLLPDehtfoycneuqerf

3tiB

detarenegyllanretnistifoesahpehtngilalliwecivedehT:elbanEcnySzHk2lanretxE1=

langisehtfotahthtiw)zHk2(langiscnySemarF-itluMdna)zHk8(langiscnySemarF

rehtonamorftuptuozHM84.6aotdekcolebdluohsecivedehT.nipK2cnySehtotdeilppus

.0158SCA

.nipk2cnySehterongilliwecivedehT:elbasiDcnySzHk2lanretxE0=

00010011

)0=BVLSTSM(

)0=BHDSNOS(

00110011

)0=BVLSTSM(

)1=BHDSNOS(

01000011

)1=BVLSTSM(

)0=BHDSNOS(

01100011

)1=BVLSTSM(

)1=BHDSNOS(

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com32

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

edom_gfnc

)deunitnoc(

:wolebdeliatedsa,sdleifnoitarugifnoclaudividnilarevessniatnocretsigersihT

2tiB

ehtneviglennahctupniynafoycneuqerftupniehtstcepxeecivedehT:edoMTENOS1=

zHk4451ebotretsigerycneuqerf_ecruos_fer_gfncehtni'1000'eulav

eulavehtneviglennahctupniynafoycneuqerftupniehtstcepxeecivedehT:edoMHDS0=

.zHk8402ebotretsigerycneuqerf_ecruos_fer_gfncehtni'1000'

gnittessihT.BHDSNOSnipfognittesehtotdetluafedeblliweulavtibehtteserroputratstA

eulavtibsihtgnignahcybderetlaebyltneuqesbusnac

1tiB

fosnoisicedevitcaehtekamdnaedomretsamehttpodalliwecivedehT:edoMretsaM1=

,nipehtybdenimretedsieulavtluafedstitub,elbaetirwsitibsihT.cte,tcelesotecruoshcihw

BVLSTSM

.ecivedretsamehtwolloflliwdnaedomevalsehttpodalliwecivedehT:edoMevalS0=

gnittessihT.BVLSTSMnipfognittesehtotdetluafedeblliweulavtibehtteserroputratstA

eulavtibsihtgnignahcybderetlaebyltneuqesbusnac

0tiB

ninwohselbaliavaecruosytiroirptsehgihehtothctiwslliwecivedehT:edoMevitreveR1=

)4:7(stib,retsigerelbat_ytiroirp_stseht

)tluafed(ecruosdetcelesyltneserpehtniaterlliwecivedehT:edoMevitreveRnoN0=

00010011

)0=BVLSTSM(

)0=BHDSNOS(

00110011

)0=BVLSTSM(

)1=BHDSNOS(

01000011

)1=BVLSTSM(

)0=BHDSNOS(

01100011

)1=BVLSTSM(

)1=BHDSNOS(

4T_gfnc :noitcelesecruostupnidna)9OT/8OTnotuptuo(4T_LLPDslortnocsihT

desunU)6:7(stiB

5tiB

)dehcleuqs(ffodenrutsi4T_LLPD1=

)tluafed(nosi4T_LLPD0=

:9OT/8OTstuptuosdeefecruos)0Tro4T(LLPDhcihwstceleS4tiB

9OTdna8OTstuptuootdefsituptuo0T_LLPD1=

9OTdna8OTstuptuootdefsituptuo4T_LLPD0=

rofdleifsihtninwohsecruosehtothctiwslliwecivedehT.noitcelesecruostupnI)0:3(stiB

Tehtfonoitarenegeht

4TUO

Tevitcaytiroirptsehgihehttceleslliwti'0'fI.langis

1NI

000000XX

stupni_laitnereffid_gfnc :swollofsa,sdleifnoitarugifnoclaudividniowtsniatnocretsigersihT

desunU)2:7(stiB

1tiB

)tluafeD(elbitapmoc-LCEPsi>6_I<tupnI1=

elbitapmoc-SDVLsi>6_I<tupnI0=

0tiB

elbitapmoc-LCEPsi>5_I<tupnI1=

)tluafeD(elbitapmoc-SDVLsi>5_I<tupnI0=

01XXXXXX

snip_lesPu_gfnc rewoptadetcelesepytrossecorporcimehtgnitacidnieulavasnruterretsigerylnodaersihT

LESPUehtfI.)06-85snip(snipLESPUehtfonoitarugifnocehtybtessisihT.teserropu

sihttub,ecalpekatlliwtceffeongnitareposiecivedehtelihwdegnahcsinoitarugifnocnip

ehttadetnemelpmieblliwtahtnoitarugifnocehtgnitacidnios,egnahctahttcelferlliwretsiger

.teserropurewoptxen

.F7retsigerhguoht,lanoitarepoecivedehthtiwdegnahcebnacepytrossecorporcimehT

.desunU)3:7(stiB

epytrossecorporciM)0:2(tiB

)delbasidecafretni(FFO000

MORPE100

DEXELPITLUM010

LETNI110

ALOROTOM001

LAIRES101

)delbasidecafretni(FFO011

)delbasidecafretni(FFO111

=)3:7(stiB

XXXXX

=)0:2(stiB

LESPU

nip

noitarugifnoc

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com33

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

elbane_tuptuo_0T_gfnc :swollofsa,sdleifnoitarugifnoclaudividnilarevessniatnocretsigersihT

7tiB

*zHM40.113ottesycneuqerftuptuo60T1=

)tluafed()4:5(A3sserddAybtesycneuqerftuptuo60T0=

6tiB

2giDrofdetcelesedomTENOS1=

)tluafed(2giDrofdetcelesedomHDS0=

seicneuqerf_tuptuo_0T_gfncretsigerees-

5tiB

1giDrofdetcelesedomTENOS1=

)tluafed(1giDrofdetcelesedomHDS0=

seicneuqerf_tuptuo_0T_gfncretsigerees-

4tiB

)tluafed(delbane10TtroptuptuO1=

**delbasid10TtroptuptuO0=

seicneuqerf_tuptuo_0T_gfncretsigerees-

3tiB

)tluafed(delbane20TtroptuptuO1=

**delbasid20TtroptuptuO0=

seicneuqerf_tuptuo_0T_gfncretsigerees-

2tiB

)tluafed()*zHM44.91(delbane30TtroptuptuO1=

**delbasid30TtroptuptuO0=

1tiB

)tluafed()*zHM88.83(delbane40TtroptuptuO1=

**delbasid40TtroptuptuO0=

0tiB

)tluafed()*zHM67.77(delbane50TtroptuptuO1=

**delbasid50TtroptuptuO0=

:setoN

ehtfotibetairporppaehtfi1T/1EfoselpitlumotdegnahceraseicneuqerfstluafeD*

1lortnoc_gfnc .8elbaTees,sliatedroF.1ottessiretsiger

.)detats-irTtonsitropeht(eulavcigolcitatsasdlohtroptuptuoehttahtsnaem"delbasiD"**

11111000

seicneuqerf_tuptuo_0T_gfnc *.wolebdeliatedsa,troptuptuohcaerofsnoitcelesycneuqerfehtsdlohretsigersihT

1giD)4:5(stiB2giD)6:7(stiB

)tluafed(zHk8402/zHk445100)tluafed(zHk8402/zHk445100

zHk6904/zHk880310zHk6904/zHk880310

zHk2918/zHk671601zHk2918/zHk671601

zHk48361/zHk2532111zHk48361/zHk2532111

10T)0:1(stiB20T)2:3(stiB

)tluafed(zHM84.600zHM29.5200

zHM29.5210zHM48.1510

zHM44.9101)tluafed(zHM88.8301

1giD112giD11

ehtaivdetceleserayehT.HDS/TENOSrofnwohseraseulavycneuqerfeht2giD/1giDroF

.elbane_tuptuo_0T_gfncretsigernistibHDS/TENOS

:etoN

ehtfotibetairporppaehtfi1T/1EfoselpitlumotdegnahceraseicneuqerfevobaehT*

1lortnoc_gfnc .8elbaTees,sliatedroF.1ottessiretsiger

00010000

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com34

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

stuptuo_laitnereffid_gfnc laitnereffidehtrofepytygolonhcet-tropehtdnasnoitcelesycneuqerfehtsdlohretsigersihT

.wolebdeliatedsa,70Tdna60T,stuptuo

60T)4:5(stiB70T)6:7(stiB

)tluafed(zHM88.8300zHM25.55100

zHM44.9110zHM48.1510

zHM25.55101zHM67.7701

1giD11)tluafed(zHM44.9111

60T)0:1(70T)2:3(stiB

delbasidtroP00delbasidtroP00

elbitapmoc-LCEP10)tluafed(elbitapmoc-LCEP10

)tluafed(elbitapmoc-SDVL01elbitapmoc-SDVL01

desunU11desunU11

01100011

htdiwdnab_gfnc nehW.LLPlatigidehtfonoitarepoehtlortnocotdesunoitamrofnisniatnocretsigersihT

gnitteshtdiwdnabnoitisiuqcaehtesulliwLLPDeht,citamotuaottessinoitceleshtdiwdnab

,launamottesnehW.kcolninehwgnitteshtdiwdnabdekcol/lamronehtdna,kcolfotuonehw

.gnitteshtdiwdnabdekcol/lamronehtesuyawlalliwLLPDeht

7tiB

noitarepocitamotuA1=

)tluafed(noitarepolaunaM0=

htdiwdnabpooL)0:2(tiBhtdiwdnabnoitisiuqcA)4:6(stiB

zH1.0000zH1.0000

zH3.0100zH3.0100

zH5.0010zH5.0010

zH0.1110zH0.1110

zH0.2001zH0.2001

)tluafed(zH0.4101zH0.4101

zH0.8011zH0.8011

zH71111)tluafed(zH71111

desunU3tiB

101X1110

ycneuqerf_lanimon_gfnc latsyrcehtfotesfforofnoitasnepmocgniwollaregetnidengisnutib61asdlohretsigersihT

tluafeD.noitarbilaCycneuqerFlatsyrCnoitceseeS.zHM8.21lanimonehtmorfrotallicso

.tnemtsujdampp0nistluser

C3 )0:7(stibycneuqerf_lanimon_gfnc)0:7(stiB 10011001

D3 )8:51(stibycneuqerf_lanimon_gfnc)0:7(stiB 10011001

tesffo_revodloh_gfnc nachcihw,eulavtesfforevodlohehtgnitneserper,regetnidengistib91asdlohretsigersihT

tibdelbanetesfforevodlohehtaivdelbanenehwycneuqerfedomrevodlohehttesotdesueb

.retsigeredom_gfncehtni

E3 )0:7(stibtesffo_revodloh_gfnc)0:7(stiB 00000000

F3 )8:51(stibtesffo_revodloh_gfnc)0:7(stiB 00000000

7tiB

23morfnekatebotegarevaycneuqerfehtselbanesihT.elbanegnigarevArevodloHotuA1=

ebotdemrifnocneebsahycneuqerfehtretfa,sdnoces23yrevenekatelpmasenO.selpmas

otdekcolyltnerrucehtfoyrotsihetunim71asevigsihT.srotinomycneuqerfehtybdnab-ni

.)tluafed(.revodloHniesurofecruosecnerefer

.delbasidgnigarevArevodloHotuA0=

desunU)3:6(stiB

)61:81(stibtesffo_revodloh_gfnc)0:2(stiB

000XXXX1

timil_qerf_gfnc tI.LLPDehtfoegnarni-llupehtgnitneserperregetnidengisnutib01asdlohretsigersihT

ehtgnisu,noitacilppaehtnidetnemelpmilatsyrcfoycaruccaehtotgnidroccatesebdluohs

:alumrofgniwollof

ro74610.0+)5870.0xtimil_qerf_gfnc(=)mpp(-/+egnarycneuqerF

5870.0/)74610.0-)mpp(-/+egnarycneuqerF(=timil_qerf_gfnc

nehweulavtluafeD.mpp3.9±siwoldeitrodetcennocnutfelsiWSCRSnehweulavtluafeD

.mpp08±dnuorafoegnarllufehtsihgihsiWSCRS

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com35

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

timil_qerf_gfnc

)deunitnoc( )0:7(stibtimil_qerf_gfnc)0:7(stiB

10101110

)wolWSCRS(

11111111

)hgihWSCRS(

desunU)2:7(stiB

)8:9(stibtimil_qerf_gfnc)0:1(stiB

00XXXXXX

)wolWSCRS(

11XXXXXX

)hgihWSCRS(

ksam-tpurretni_gfnc sutatstpurretniehtrehtieniecruostpurretnietairporppaehtelbasidlliw'0'ottesfi,tibhcaE

.retsigerstupni_4T_stsehtroretsiger

34 )0:7(stibksam_tpurretni_gfnc)0:7(stiB 11111111

44 )8:51(stibksam_tpurretni_gfnc)0:7(stiB 11111111

54 desunU)5:7(stiB

)61:02(stibksam_tpurretni_gfnc)0:4(stiB 11111XXX

nvid_qerf_gfnc esahpehttegot>1_I<:>41_I<otdeilppatupniynarofrosividehtsadesusiregetnitib41sihT

esuaclliwsihT.’1‘ottestibNviDehthtiwstupnirofevitcaylnO.derisedycneuqerfgnikcol

:otNmargorp.g.e,nosirapmocesahpotroirp)1+N(ybdedividebotycneuqerftupnieht

1-)zHk8/)qerftupni((

ehtotycneuqerftopstsesolcehttcelferottesebdluohsstibycneuqerf_ecruos_ecnereferehT

.ycneuqerftupniehtnahtrewolebtsumtub,ycneuqerftupni

64)0:7(stibnvid_qerf_gfnc)0:7(stiB 00000000

74 desunU)6:7(stiB

)8:31(stibnvid_qerf_gfnc)0:5(stiB 000000XX

srotinom_gfnc .tuodliubesahpfolortnocdnasrotinomfonoitarugifnoclabolgswollaretsigertib7sihT

desunU7tiB

6tiB

ODTnipfotuonevirdebottpurretnideliaf_fer_niamehtfoeulavselbanE1=

)tluafed(ODTnipfotuonevirdgniebmorftpurretnideliaf_fer_niamehtfoeulavselbasiD0=

5tiB

yltnerrucehtnomralaytivitcaninaesiarotLLPDehtswollA:gnihctiwstsafartluselbanE1=

gnihctiwStsaFartlUnonoitceseeS.selcycwefaylnognissimretfaecruosdetceles

)tluafed(noitarepolamroN0=

4tiB

wolWSCRSfi>4_I<ro,hgihWSCRSnipfi>3_I<otgnikcolsecroF1=

delbanelortnoccitamotuadna,derongiWSCRSniP0=

3tiB

tesffoesahptuptuoottupnitnerrucehthtiwpihsnoitaleresahptuptuoehtezeerflliW1=

)tluafed()edomtuodliubesahplamroN(tesffoesahptuptuoottupninisegnahcswollA0=

2tiB

)tluafed(tuodliubesahpselbanE1=

°0otkcolsyawlalliwLLPD0=

erasrehto,)tluafed(mpp51=10,ffo=00-srotinomycneuqerfgnirugifnocrofera)0:1(stiB

.esuerutufrofdevreser

1010000X

)wolWSCRS(

1010100X

)hgihWSCRS(

05 0dlohserht_reppu_vitca_gfnc desiarebotmralaytivitcaehtsesuactahttekcubykaelehtnieulavehttes)0:7(stiB 01100000

15 0dlohserht_rewol_vitca_gfnc deraelcebotmralaytivitcaehtsesuactahttekcubykaelehtnieulavehttes)0:7(stiB 00100000

25 0ezis_tekcub_gfnc tupnievitcaninanevighcaernactekcubykaelehttahteulavmumixamehttes)0:7(stiB 00010000

0etar_yaced_gfncdesunU)2:7(stiB

yreverof1+sitekcubehtfoetar-llifehT.tekcubykaelehtfoetarkaelehtlortnoc)0:1(stiB

elbammargorpsietaryacedehT.ytivitcanifolevelemosdecneirepxesahtahtlavretnism821

,01,10,00foseulavgnisuyb1:8,1:4,1:2,1:1ottesebnacoitarehT.etarllifehtfosoitarni

tekcubehT.erutannistekcubykael’eurt‘tonerastekcubeseht,revewoH.ylevitcepser11

ehtebnacsetaryaceddnallifehttahtsnaemsihT.dellifgniebsitinehw’gnikael‘spots

saetaremasehttadesingocerebnactupnievitcanatahttceffetenehthtiw)1:1=00(emas

.enoevitcanina

10XXXXXX

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com36

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Selection of Input Reference ClockSelection of Input Reference Clock

Selection of Input Reference Clock

SourceSource

Source

Under normal operation, the input reference

sources are selected automatically by an order

of priority. But, for special circumstances, such

as chip or board testing, the selection may be

forced by configuration.

Automatic operation selects a reference source

based on its pre-defined priority and its current

availability. A table is maintained which lists all

reference sources in the order of priority. This

is initially downloaded into the ACS8510 via

the microprocessor interface by the Network

Manager, and is subsequently modified by the

results of the ongoing quality monitoring. In this

way, when all the defined sources are active

and valid, the source with the highest

programmed priority is selected but, if this

source fails, the next-highest source is selected,

and so on.

Restoration of repaired reference sources is

handled carefully to avoid inadvertent

disturbance of the output clock. The ACS8510

has two modes of operation; Revertive and

Non-Revertive. In Revertive mode, if a re-

validated (or newly validated) source has a

higher priority than the reference source which

is currently selected, a switch over will take

place. Many applications prefer to minimise the

clock switching events and choose Non-

Revertive mode. In Non-Revertive mode , when

a re-validated (or newly validated) source has a

higher priority then the selected source will be

maintained. The re-validation of the reference

source will be flagged in the sts_sources_valid

interrupt. Selection of the re-validated source

can only take place under software control -

the software should briefly enable Revertive

mode to affect a switch-over to the higher

priority source. If the selected source fails under

these conditions the device will indicate that it

is still locked to the failed reference. It will not

select the higher priority source until instructed

to do so by the software; by briefly setting the

Revertive mode bit. When there is a reference

available with higher priority than the selected

reference, there will be NO change of reference

source as long as the Non-Revertive mode

remains on AND the device will remain indicating

.rddA

)xeH(

emaNretemaraPnoitpircseDtluafeD

)nib(eulaV

451dlohserht_reppu_vitca_gfnc1tekcubroftub05retsigerrofsA 01100000

551dlohserht_rewol_vitca_gfnc1tekcubroftub15retsigerrofsA 00100000

651ezis_tekcub_gfnc1tekcubroftub25retsigerrofsA 00010000

751etar_yaced_gfnc1tekcubroftub35retsigerrofsA 10XXXXXX

852dlohserht_reppu_vitca_gfnc2tekcubroftub05retsigerrofsA 01100000

952dlohserht_rewol_vitca_gfnc2tekcubroftub15retsigerrofsA 00100000

A52ezis_tekcub_gfnc2tekcubroftub25retsigerrofsA 00010000

B52etar_yaced_gfnc2tekcubroftub35retsigerrofsA 10XXXXXX

C53dlohserht_reppu_vitca_gfnc3tekcubroftub05retsigerrofsA 01100000

D53dlohserht_rewol_vitca_gfnc3tekcubroftub15retsigerrofsA 00100000

E53ezis_tekcub_gfnc3tekcubroftub25retsigerrofsA 00010000

F53etar_yaced_gfnc3tekcubroftub35retsigerrofsA 10XXXXXX

lesPu_gfncdesunU)3:7(stiB

lliwecafretniehT.ecafretnirossecorporcimehtfoedomehtegnahcotdesuebnac)0:2(stiB

73retsigeraivdaerebnacputesnipeht-)06-85snip(LESPUsnipehtsatesebyllaitini

.gnittessihtottluafedlliwecivedehtteserropurewoptA.)snip_lesPu_gfnc(

gnitroppus,putratsretfaedomrossecorporcimehtegnahcotdesuebnacretsigersihT

ehtputratstA.edomrehtonaaivgnitacinummocyltneuqesbusdnaMORPEmorfgnitoob

tsalehtsadna,sretsigerehtllarofsgnittesdemmargorp-erpehtdaolnwodlliwMORPE

sihttahtdednemmocersitI.retsigertsalsihthtiwecafretnifoegnahcehtnoitca,noitarepo

ecivedsihtfosnoisrevtneuqesbussa,snoitacilppaputratsMORPErofdesuylnosinoitcnuf

73retsigerninevigsaro9elbaTnidenifederastibehT.yawsihtninoitarepowollaylnoyam

.noitpircsedpamretsigerehtfo

=)3:7(stiB

XXXXX

=)0:2(stiB

tnednepedniP

Table 12. Register Map Description (continued).Table 12. Register Map Description (continued).

Table 12. Register Map Description (continued).

www.semtech.com37

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

a locked state on the failed reference. This is

the case even if there are lower priority

references available or the currently selected

reference fails. When the ONLY valid reference

sources that are available have a lower priority

than the selected reference, a failure of the

selected reference will always trigger a switch-

over, regardless of whether Revertive or Non-

Revertive mode has been chosen.

Also, in a Master/Slave redundancy-protection

scheme, the Slave device(s) must follow the

Master device. The alignment of the Master

and Slave devices is part of the protection

mechanism. The availability of each source is

determined by a combination of local and

remote monitoring of each source. Each input

reference source supplied to each ACS8510

device is monitored locally and the results are

made available to other devices.

Forced Control SelectionForced Control Selection

Forced Control Selection

A configuration register, cnfg_ref_selection,

controls both the choice of automatic or forced

selection and the selection itself (when forced

selection is required). The forced selection of

an input reference source occurs when the

cnfg_ref_selection variable contains a non-zero

value, the value then representing the input

port required to be selected. This is not the

normal mode of operation, and the

cnfg_ref_selection variable is defaulted to the

all-one value on reset, thereby adopting the

automatic selection of the reference source.

Automatic Control SelectionAutomatic Control Selection

Automatic Control Selection

When an automatic selection is required, the

cnfg_ref_selection register must be set to all

zero or all one. The configuration registers,

cnfg_ref_selection_priority, held in the µP port

block, consists of seven, 8 bit registers

organised as one 4 bit register per input

reference port. Each register holds a 4-bit value

which represents the desired priority of that

particular port. Unused ports should be given

the value, '0000' or '1111', in the relevant

in the priority table. On power-up, or following a

reset, the whole of the configuration file will be

defaulted to the values defined by Table 4. The

selection priority values are all relative to each

other, with lower-valued numbers taking higher

priorities. Each reference source should be given

a unique number, the valid values are 1 to 15

(dec). A value of 0 disables the reference

source. However if two or more inputs are given

the same priority number those inputs will be

selected on a first in, first out basis. If the first

of two same priority number sources goes

invalid the second will be switched in. If the

first then becomes valid again, it becomes the

second source on the first in, first out basis,

and there will not be a switch. If a third source

with the same priority number as the other two

becomes valid, it joins the priority list on the

same first in, first out basis. There is no implied

priority based on the channel numbers.

The input port <I_11> is for the connection of

the synchronous clock of the TOUT0 output of

the Master device (or the active-Slave device),

to be used to align the TOUT0 output with the

Master (or active-Slave) device if this device is

acting in a subordinate-Slave or subordinate-

Master role.

Ultra Fast SwitchingUltra Fast Switching

Ultra Fast Switching

A reference source is normally disqualified after

the leaky bucket monitor thresholds have been

crossed. An option for a faster disqualification

has been implemented, whereby if register 48H,

bit 5 (Ultra Fast Switching), is set then a loss of

activity of just a few reference clock cycles will

set the ‘no activity alarm’ and cause a

reference switch. This can be chosen to cause

an interrupt to occur instead of or as well as

causing the reference switch. The sts_interrupts

interrupt status register is used to flag inactivity

on the reference that the device is locked to

much faster than the activity monitors can

support. If bit 6 of the cnfg_monitors register

(flag ref loss on TDO) is set, then the state of

this bit is driven onto the TDO pin of the device.

www.semtech.com38

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

The flagging of the loss of the main reference

failure on TDO is simply allowing the status of

the sts_interrupt bit 14 to be reflected in the

state of the TDO output pin. The pin will,

therefore remain High until the interrupt is

cleared. This functionality is not enabled by

default so the usual JTAG functions can be

used. When JTAG is normally used straight out

of power-up, then this feature will have no

bearing on the functionality. The TDO flagging

feature will need to be disabled if JTAG is not

enabled on power-up and the feature has since

been enabled.

When the TDO output from the ACS8510 is

connected to the TDI pin of the next device in

the JTAG scan chain, the implementation should

be such that a logic change caused by the

action of the interrupt on the TDI input should

not effect the operation when JTAG is not

active.

External Protection SwitchingExternal Protection Switching

External Protection Switching

Fast external switching between inputs <I_3>

and <I_4> can also be triggered directly from a

dedicated pin (SRCSW). This mode can be

activated either by holding this pin high during

reset, or by writing to bit 4 of register address

48Hex. Once external protection switching is

enabled, then the value of this pin directly

selects either <I_3> (SRCSW high) or <I_4>

(SRCSW low). If this mode is activated at reset

by pulling the SRCSW pin high, then it configures

the default frequency tolerance of <I_3> and

<I_4> to +/- 80 ppm (register address 41Hex

and 42Hex). Any of these registers can be

subsequently set by external software if

required.

When external protection switching is enabled,

the device will operate as a simple switch. All

clock monitoring is disabled and the DPLL will

simply be forced to try to lock on to the

indicated reference source.

Clock Quality MonitoringClock Quality Monitoring

Clock Quality Monitoring

Clock quality is monitored and used to modify

the priority tables of the local and remote

ACS8510 devices. The following parameters are

monitored:

1. Activity (toggling)

2. Frequency (This monitoring is only performed when

there is no irregular operation of the clock or loss of clock

condition)

In addition, input ports <I_1> and <I_2> carry

AMI-encoded composite clocks which are

reference

leaky bucket

source

response

alarm

bucket_size

upper_threshold

lower_threshold

(all programmable)programmable fall slopes

inactivities/irregularities

Figure 9. Inactivity and Irregularity MonitoringFigure 9. Inactivity and Irregularity Monitoring

Figure 9. Inactivity and Irregularity Monitoring

www.semtech.com39

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

monitored by the AMI-decoder blocks. Loss of

signal is declared by the decoders when either

the signal amplitude falls below +0.3 V or there

is no activity for 1 ms.

Any reference source which suffers a loss-of-

signal, loss-of-activity, loss-of-regularity or clock-

out-of-band condition will be declared as

unavailable.

Clock quality monitoring is a continuous process

which is used to identify clock problems. There

is a difference in dynamics between the

selected clock and the other reference clocks.

Anomalies occurring on non-selected reference

sources affect only that source's suitability for

selection, whereas anomalies occurring on the

selected clock could have a detrimental impact

on the accuracy of the output clock.

Anomalies, whether affecting signal purity or

signal frequency, could induce jitter or frequency

offsets in the output clock, leading to

anomalous behaviour. Anomalies on the

selected clock, therefore, have to be detected

as they occur and the phase locked loop must

be temporarily isolated until the clock is once

again pure. The clock monitoring process cannot

be used for this because the high degree of

accuracy required dictates that the process be

slow. To achieve the immediacy required by the

phase locked loop requires an alternative

mechanism. The phase locked loop itself

contains appropriate circuitry, based around the

phase detector, and isolates itself from the

selected reference source as soon as a signal

impurity is detected. It can likewise respond to

frequency offsets outside the permitted range

since these result in saturation of the phase

detector. When the phase locked loop is isolated

from the reference source, it is essentially

operating in a Holdover state; this is preferable

to feeding the loop with a standby source, either

temporarily or permanently, since excessive

phase excursions on the output clock are

avoided.

Anomalies detected by the phase detector are

integrated in a leaky bucket accumulator.

The time taken to raise an inactivity alarm on a reference source that has previously been fully active (leaky

bucket empty) will be:

(cnfg_activ_upper_threshold N)

where N is the number of the relevent leaky bucket configuration. If an input is intermittently inactive then

this time can be longer. The default setting of cnfg_activ_upper_threshold is 6, therefore the default time is

0.75 s.

The time taken to cancel the activity alarm on a previously completely inactive reference source is calculated

as:

2 x ((cnfg_bucket_size N) - (cnfg_activ_lower_thrshold N))

where N is the number of the relevent leaky bucket configuration in each case. The default setting are shown

in the following:

2 x (8-4) = 1.0 s

secs

(cnfg_decay_rate N)

Leaky bucket timing Leaky bucket timing

Leaky bucket timing

www.semtech.com40

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

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Occasional anomalies do not cause the

accumulator to cross the alarm setting

threshold, so the selected reference source is

retained. Persistent anomalies cause the alarm

setting threshold to be crossed and result in

the selected reference source being rejected.

Activity MonitoringActivity Monitoring

Activity Monitoring

The ACS8510 has a combined inactivity and

irregularity monitor. The ACS8510 uses a ‘leaky

bucket’ accumulator, which is a digital circuit

which mimics the operation of an analog

integrator, in which input pulses increase the

output amplitude but die away over time. Such

integrators are used when alarms have to be

triggered either by fairly regular defect events,

which occur sufficiently close together, or by

defect events which occur in bursts. Events

which are sufficiently spread out should not

trigger the alarm. By adjusting the alarm setting

threshold, the point at which the alarm is

triggered can be controlled. The point at which

the alarm is cleared depends upon the decay

rate and the alarm clearing threshold. On the

alarm setting side, if several events occur close

together, each event adds to the amplitude

and the alarm will be triggered quickly; if events

occur a little more spread out, but still

sufficiently close together to overcome the

decay, the alarm will be triggered eventually. If

events occur at a rate which is not sufficient to

overcome the decay, the alarm will not be

triggered. On the alarm clearing side, if no defect

events occur for a sufficient time, the amplitude

will decay gradually and the alarm will be cleared

when the amplitude falls below the alarm

clearing threshold. The ability to decay the

amplitude over time allows the importance of

defect events to be reduced as time passes

by. This means that, in the case of isolated

events, the alarm will not be set, whereas, once

the alarm becomes set, it will be held on until

normal operation has persisted for a suitable

time (but if the operation is still erratic, the

alarm will remain set). See Figure 9.

The ‘leaky bucket’ accumulators are

programmable for size, alarm set & reset

thresholds and decay rate. Each source is

monitored over a 128 ms period. If, within a

128 ms period, an irregularity occurs that is

not deemed to be due to allowable jitter/wander,

then the accumulator is incremented. The

accumulator will continue to increment up to

the point that it reaches the programmed

bucket size. The ‘fill rate’ of the leaky bucket

is, therefore, 8 units/second. The ‘leak rate’

of the leaky bucket is programmable to be in

multiples of the fill rate (x1, x0.5, x0.25 and

x0.125) to give a programmable leak rate from

8 units/sec down to 1 unit/sec. A conflict

between trying to ‘leak’ at the same time as a

‘fill’ is avoided by preventing a ‘leak’ when a

‘fill’ event occurs.

Disqualification of a non-selected reference

source is based on inactivity, or on an out of

band result from the frequency monitors. The

currently selected reference source can be

disqualified for phase, frequency, inactivity or if

the source is outside the DPLL lock range. If

the currently selected reference source is

disqualified, the next highest priority, active

reference source is selected.

Frequency MonitoringFrequency Monitoring

Frequency Monitoring

The ACS8510 performs frequency monitoring

to identify reference sources which have drifted

outside the acceptable frequency range of

+/- 16.6 ppm (measured with respect to the

output clock). The sts_reference_sources out-

of-band alarm for a particular reference source

is raised when the reference source is outside

the acceptable frequency range. The ACS8510

DPLL has a programmable frequency limit of

+/- 80 ppm. If the range is programmed to be

> 16.6 ppm, the frequency monitors should be

disabled so the input reference source is not

automatically rejected as out of frequency

range.

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Modes of OperationModes of Operation

Modes of Operation

The ACS8510 has three primary modes of

operation (Free-run, Locked and Holdover)

supported by three secondary, temporary

modes (Pre-Locked, Lost_Phase and Pre-

Locked2). These are shown in the State

Transition Diagram, Figure 11.

The ACS8510 can operate in Forced or

Automatic control. On reset, the ACS8510

reverts to Automatic Control, where transitions

between states are controlled completely

automatically. Forced Control can be invoked

by configuration, allowing transitions to be

performed under external control. This is not

the normal mode of operation, but is provided

for special occasions such as testing, or where

a high degree of hands-on control is required.

Free-run modeFree-run mode

Free-run mode

The Free-run mode is typically used following a

power-on-reset or a device reset before

network synchronization has been achieved. In

the Free-run mode, the timing and

synchronization signals generated from the

ACS8510 are based on the Master clock

frequency provided from the external oscillator

and are not synchronized to an input reference

source. The frequency of the output clock is a

fixed multiple of the frequency of the external

oscillator, and the accuracy of the output clock

is equal to the accuracy of the Master clock.

The transition from Free-run to Pre-locked

occurs when the ACS8510 selects a reference

source.

Pre-Locked modePre-Locked mode

Pre-Locked mode

The ACS8510 will enter the Locked state in a

maximum of 100 seconds, as defined by GR-

1244-CORE specification, if the selected

reference source is of good quality. If the

device cannot achieve lock within 100 seconds,

it reverts to Free-run mode and another

reference source is selected.

Locked modeLocked mode

Locked mode

The Locked mode is used when an input

reference source has been selected and the

PLL has had time to lock. When the Locked

mode is achieved, the output signal is in phase

and locked to the selected input reference

source. The selected input reference source is

determined by the priority table. When the

ACS8510 is in Locked mode, the output

frequency and phase follows that of the

selected input reference source. Variations of

the external crystal frequency have a minimal

effect on the output frequency. Only the

minimum to maximum frequency range is

affected. Note that the term, 'in phase', is not

applied in the conventional sense when the

ACS8510 is used as a frequency translator (e.g.,

when the input frequency is 2.048 MHz and

the output frequency is 19.44 MHz) as the input

and output cycles will be constantly moving past

each other; however, this variation will itself be

cyclical over time unless the input and output

are not locked.

Lost_Phase modeLost_Phase mode

Lost_Phase mode

Lost-phase mode is entered when the current

phase error, as measured within the DPLL, is

larger than a preset limit (see register 04, bits

5:3), as a result of a frequency or phase

transient on the selected reference source.

This mode is similar in behavior to the Pre-locked

or Pre-locked(2) modes, although in this mode

the DPLL is attempting to regain lock to the same

reference rather than attempt lock to a new

reference.

If the DPLL cannot regain lock within 100 s, the

source is disqualified, and one of the following

transitions takes place:

1. Go to Pre-Locked(2);

- If a known-good standby source is available.

2. Go to Holdover;

- If no standby sources are available.

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Holdover modeHoldover mode

Holdover mode

The Holdover mode is used when the ACS8510

has been in Locked mode for long enough to

acquire stable frequency data, but the final

selected reference source has become

unavailable and a replacement has not yet been

qualified for selection.

In Holdover mode, the ACS8510 provides the

timing and synchronisation signals to maintain

the Network Element (NE), but they are not

phase locked to any input reference source.

The timing is based on a stored value of the

frequency ratio obtained during the last Locked

mode period.

To allow for further development of the way

the internal algorithm operates, and to allow

for customised switching behaviour, the switch

to and from Holdover state may be controlled

by external software.

The device must be set in either ‘manual’ mode

or ‘automatic’ mode:

1. Register cnfg_mode bit ‘holdover offset en’ set high

(manual mode).

The Holdover frequency is determined by the value in

number, with a LSB resolution of 0.0003 ppm, which gives

an adjustment range of ± 80 ppm. This value can be derived

from a reading of the register sts_curr_inc_offset (addr

0D, 0C and 07) which gives, in the same format, an

indication of the current output frequency deviation, which

would be read when the device is locked. If required, this

value could be read by an external microcontroller and

averaged over the time required. The averaged value could

then be fed to the cnfg_holdover_offset register ready for

setting of the averaged frequency value when the device

enters Holdover mode. The sts_curr_inc_offset value is

internally derived from the Digital Phase Locked Loop

(DPLL) integral path value, which already represents a well

averaged measure of the current frequency, depending on

the loop bandwidth selected.

2. Register cnfg_mode bit ‘holdover offset en’ set low

(automatic mode).

In automatic control, the device can be run in one of two

ways:

2.1 Register cnfg_holdover_offset register 40 bit 7 ‘auto

holdover averaging’ is set high. The value is averaged

internally over 32 samples at 32 seconds apart, giving the

average frequency over approximatley the last 20 minutes.

The proportional DPLL path is ignored so that recent signal

disturbances do not affect the Holdover frequency value.

If the device has been previously correctly locked, missing

pulses in the input clock stream fed to the SETS IC are

ignored, hence also avoiding any frequency disturbances

to the output frequency value when an input clock source

fails.

2.2 Register cnfg_holdover_offset register 40 bit 7 ‘auto

holdover averaging’ is set low. This simply freezes the DPLL

at the current frequency (as reported by the

sts_curr_inc_offset register). The proportional DPLL path

is ignored so that recent signal disturbances do not affect

the Holdover frequency value.

Automatic control with internal averaging (option

2.1) is the default condition.

If the TCXO frequency is varying due to

temperature fluctuations in the room, then the

instantaneous value can be different from the

average value, and then it may be possible to

exceed the 0.05 ppm limit (depending on how

extreme the temperature flucuations are). It is

advantageous to shield the TCXO to slow down

frequency changes due to drift and external

temperature fluctuations.

The frequency accuracy of Holdover mode has

to meet the ITU-T, ETSI and Telcordia

performance requirements. The performance

of the external oscillator clock is critical in this

mode, although only the frequency stability is

important - the stability of the output clock in

Holdover is directly related to the stability of

the external oscillator.

Pre-Locked(2) modePre-Locked(2) mode

Pre-Locked(2) mode

This state is very similar to the Pre-Locked state.

It is entered from the Holdover state when a

reference source has been selected and applied

to the phase locked loop. It is also entered if

the device is operating in Revertive mode and

a higher-priority reference source is restored.

Upon applying a reference source to the phase

locked loop, the ACS8510 will enter the Locked

state in a maximum of 100 seconds, as defined

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

by GR-1244-CORE specification, if the selected

reference source is of good quality.

If the device cannot achieve lock within 100

seconds, it reverts to Holdover mode and

another reference source is selected.

Protection FacilityProtection Facility

Protection Facility

The ACS8510 supports redundancy protection.

The primary functions of this include:

- Alignment of the priority tables of both Master

and Slave ACS8510 devices so as to align the

selection of reference sources of both Master

and Slave ACS8510 devices.

- Alignment of the phases of the 8 kHz and

2 kHz clocks in both Master and Slave

ACS8510 devices to within one cycle of the

77.76 MHz internal clock.

When two ACS8510 devices are to be used in

a redundancy-protection scheme within an NE,

one will be designated as the Master and the

other as the Slave. It is expected that an NE

will use the TOUT0 output for its internal

operations because the TOUT4 output is intended

to feed an SSU/BITS system. An SSU/BITS will

not be bothered by phase differences between

signals arriving from different sources because

it typically incorporates line build-out functions

to absorb phase differences on reference

inputs. This means that the phasing of the

composite clocks between two ACS8510

devices do not have to be mutually-aligned. The

same is not true, however, of the TOUT0 output

signals (T01 - T07, Frame clock and Multi-Frame

clock). It is usually important to align the phases

of all equivalent TOUT0 signals generated by

different sources so that switch-over from one

device to another does not affect the internal

operations of the NE. Both ACS8510 devices

will produce the same signals, which will be

routed around the NE to the various consumers

(clock sinks). With the possible exception of a

through-timing mode, the signals from the

Master device will be used by all consumers,

unless the Master device fails, when each

consumer will switch over to the signals

generated by the Slave device.

Switchover to a new TOUT0 clock should be as

hitless as possible. This requires the signals of

both ACS8510 devices to be phase aligned at

each consumer. Phase alignment requires

frequency alignment. To ensure that both

devices can generate output clocks locked to

the same source, both devices are supplied

with the same reference sources on the same

input ports and will have identical priority tables.

Failures of selected reference sources will result

in both ACS8510 devices making the same

updates to their priority tables as availability

information will be updated in both devices.

Although, in principle, the priority tables will be

the same if the same reference sources are

used on the same input port on each device, in

practice, this is only true if the reference

sources actually arrive at each device - failures

of a source seen only by one device and not by

the other, such as could be caused, for example,

by a backplane connector failure, would result

in the priority tables becoming misaligned. It is

thus necessary to force the priority tables to

be aligned under normal operating conditions

so that the devices can make the same

decisions - this can be achieved by loading the

availability seen by one device (via the

sts_reference_sources register) into the

cnfg_sts_remote_sources_valid register of the

other device. Another factor which could affect

hit-less switching is the frequency of the local

oscillator clock used by each ACS8510 device:

these clocks are not mutually aligned and,

whilst this has no impact on the frequency of

the output clocks during locked mode, it could

cause the output frequencies to diverge during

Holdover mode if no action were taken to avoid

it. In order to maintain alignment of the output

frequencies of each ACS8510 device even

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

during Holdover, the Master device's 6.48 MHz

output is fed into the Slave device on its <I_11>

pin, whilst the Multi-Frame Sync (2 kHz) output

is fed to the Sync2k input of the Slave. In this

way, the Slave locks to the master's output

and remains locked whilst the Master moves

between operating states. Only when the

Master fails does the Slave use its own

reference inputs - should the Master have been

in the Holdover state, the Slave device will see

the same lack of reference sources and also

enter the Holdover state. This scheme also

provides a convenient way to phase-align all

TOUT0 output clocks in Master and Slave devices,

and also to detect the failure of the Master

device.

If a Master device fails, the Slave has to take

over responsibility for the generation of the

output clocks, including the 8 kHz and 2 kHz

Frame and Multi-Frame clocks. The Slave device

is also given responsibility for building the priority

table and performing the reference switching

operations. The Slave device, therefore, adopts

a more active role when the Master has failed.

The cnfg_mode register 34 (Hex) Bit 1 contains

the ‘Master/Slave’ control bit to determine the

designation of the device.

To restore redundancy protection, the Master

has to be repaired and replaced. When this

occurs, the new Master cannot immediately

adopt its normal role because it must not cause

phase hits on the output clocks. It has,

therefore, to adopt a subordinate role to the

active Slave device, at least until such time as

it has acquired alignment to the 8 kHz and

2 kHz frame and Multi-Frame clocks and the

priority table of the Slave device; then, when a

switch-back (restoration) is ordered, the Master

can take over responsibility. These activities, in

Master or Slave operation, are summarized in

Table 12 and described in detail in Application

Note AN-SETS-2.

Alignment of Priority Tables in Master and SlaveAlignment of Priority Tables in Master and Slave

Alignment of Priority Tables in Master and Slave

ACS8510ACS8510

ACS8510

Correct protection will only be achieved by

connecting individual reference sources to the

same input ports on each device and priority

tables in each device must be aligned to each

other.

The Master device must take account of the

availability of each reference source seen by

another device and a Slave device must adopt

the same order of priority as the Master device

(except that the Slave's highest-priority input is

<I_11>). Both devices monitor the reference

sources and decide the availability of each

source; if the failure of a reference source is

seen by both devices, they will both update

their priority tables - however, if the reference

source failure is only seen by one device and

not by both, the priority tables could get out of

step: this could be catastrophic if it resulted in

two devices choosing different reference

sources since any slight differences in frequency

variation over time (e.g. wander) would mis-align

the phase of the 8 kHz Frame and 2 kHz Multi-

Frame clocks produced by the individual

devices, resulting in phase hits on switch-over.

It is therefore important that the same priority

table be built by each device, using the

reference source availability seen by each

device.

The monitoring of the reference sources

performed by a Master ACS8510 results in a

list of available sources being placed in a

sts_valid_sources register. This information is

used within the device as one of the masks

used to build the device's priority table. The

information is passed to the Slave device and

used to configure the cnfg_sts_remote_

sources_valid register so that it can use it as a

mask in building its own priority tables. The

information is passed between devices using

the microprocessor port.

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ACS8510 Rev2.1 SETS

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Revision 2.00/September 2003 Semtech Corp.

Alignment of the Selection of Reference SourcesAlignment of the Selection of Reference Sources

Alignment of the Selection of Reference Sources

for Tfor T

for TOUT4OUT4

OUT4OUT4

OUT4 Generation in the Master and Slave Generation in the Master and Slave

Generation in the Master and Slave Generation in the Master and Slave

Generation in the Master and Slave

ACS8510ACS8510

ACS8510

As stated previously, there is no need to align

the phases of the TOUT4 outputs in Master and

Slave devices. There is a need, however, to

ensure that all devices select the same

reference source. But, since there is no

Holdover mode required for the generation of

the TOUT4 clock, and every reference source is

continuously monitored within each device, it is

permissible to rely on external intelligence to

command a switch-over to an alternative source

should the selected one fail. The time delay

involved in detecting the failure, indicating it to

the outside and selecting a new source, will

result only in the SSU/BITS entering its Holdover

mode for a short time.

Alignment of the Phases of the 8kHz and 2kHzAlignment of the Phases of the 8kHz and 2kHz

Alignment of the Phases of the 8kHz and 2kHz

Clocks in both Master and Slave ACS8510Clocks in both Master and Slave ACS8510

Clocks in both Master and Slave ACS8510

In addition to aligning the edges of the TOUT0

outputs of Master and Slave devices, it is

necessary to align the edges of the Frame and

Multi-Frame clocks. If this is not performed,

frame alignment may be lost in distant

equipment on switch-over to an alternative

device, resulting in anomalous network

operation of a very serious nature.

In accordance with the alignment mechanism

used with the main TOUT0 clock (described in the

opening paragraphs of this section), whereby

the 6.48 MHz output of the Master device is

supplied to the Slave device, the alignment of

both the 8 kHz and 2 kHz clocks is

accomplished (they are already synchronous to

the TOUT0 clocks) by feeding the 2 kHz clock of

the Master device into the Slave device. The

Multi-Frame Sync clock output of the Slave

device is also fed to the Sync2K input of the

Master device. Alignment of the Multi-Frame

Sync input occurs only when cnfg_mode

Sync Enable is set to 1.

JTAGJTAG

JTAG

The JTAG connections on the ACS8510 allow a

full boundary scan to be made. The JTAG

implementation is fully compliant to IEEE

1149.1, with the following minor exceptions,

and the user should refer to the standard for

further information.

1. The output boundary scan cells do not capture data

from the core, and so do not support EXTEST. However

this does not affect board testing.

2. In common with some other manufacturers, pin TRST

is internally pulled low to disable JTAG by default. The

standard is to pull high. The polarity of TRST is as the

standard: TRST high to enable JTAG boundary scan mode,

TRST low for normal operation.

3. The device does not support the optional tri-state

capability (HIGHZ). This will be supported on the next

revision of the device.

The JTAG timing diagram is shown in Figure 17.

PORBPORB

PORB

The Power On Reset (PORB) pin resets the

device if forced Low for a power on reset to be

initiated. The reset is asynchronous, the

minimum Low pulse width is 5 ns. Reset is

needed to initialize all of the register values to

their defaults. Asserting Reset is required at

power on, and may be re-asserted at any time

to restore defaults. This is implemented most

simplistically by an external capacitor to GND

along with the internal pull-up resistor. The

ACS8510 is held in a reset state for 250 ms

after the PORB pin has been pulled High. In

normal operation PORB should be held High.

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

otsecruos_feRotsecruos_feR otsecruos_feR otsecruos_feRotsecruos_feR

0158SCAretsaM0158SCAretsaM 0158SCAretsaM 0158SCAretsaM0158SCAretsaM

otsecruos_feRotsecruos_feR otsecruos_feR otsecruos_feRotsecruos_feR

0158SCAevalS0158SCAevalS 0158SCAevalS 0158SCAevalS0158SCAevalS

0158SCAretsaM0158SCAretsaM 0158SCAretsaM 0158SCAretsaM0158SCAretsaM

sutatssutats sutats sutatssutats

0158SCAevalS0158SCAevalS 0158SCAevalS 0158SCAevalS0158SCAevalS

sutatssutats sutats sutatssutats 0158SCAretsaM0158SCAretsaM 0158SCAretsaM 0158SCAretsaM0158SCAretsaM 0158SCAevalS0158SCAevalS 0158SCAevalS 0158SCAevalS0158SCAevalS

tuptuotuptuo tuptuo tuptuotuptuo stnemmoCstnemmoC stnemmoC stnemmoCstnemmoC

doogllAdoogllAdooGdooG)x_fer(dekcoLretsamotdekcoL1etoN

deliafemoSdeliafsrehtoemoSdooGdooG)y_fer(dekcoLretsamotdekcoL1etoN

dooGdooGdooGdeliaF)x_fer(dekcoLdaeD

dooGdooGdeliaFdooGdaeD)x_fer(dekcoL2etoN

dooGdooGdeliaFdeliaFdaeDdaeD

deliaFdeliaFdeliaFdooGrevodloHretsamotdekcoL3etoN

deliaFdeliaFdooGdeliaFrevodloHdaeD

deliaFdeliaFdeliaFdooGdaeDrevodloH

deliaFdeliaFdeliaFdeliaFdaeDdaeD

MASTER

MSTSLVB

I_1

I_2

I_3

I_11

I_14

SYNC2K

011

MF Sync

I_11

SYNC2K

I_14

T011

ync

MSTSLVB

I_3

I_2

I_1

TCXO

SLAVE

T01

TCXO

SEC1

SEC2

SEC3

SEC13

SEC14

SEC1

SEC2

SEC3

GND

6.48 MHz

SYNC2K_EN=1

34Bit3

Notes to Table 13Notes to Table 13

Notes to Table 13

Note 1: Both ACS8510 must build a common priority table so that the Slave ACS8510 can select the same input reference

source as the Master ACS8510 if the Master fails (when the Master is OK, the Slave locks to the Master's output).

Note 2: Slave ACS8510 uses common priority table, built before Master ACS8510 failed - priority table can be modified as

status of the input reference sources changes

Note 3: Slave ACS8510 outputs must remain in phase with those of Master ACS8510

Figure 10. Master-Slave SchematicFigure 10. Master-Slave Schematic

Figure 10. Master-Slave Schematic

Table 13. Master-Slave RelationshipTable 13. Master-Slave Relationship

Table 13. Master-Slave Relationship

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

pre-locked

w ait for up to 100s

(state 110)

locked

keep ref

(state 100)

holdover

select ref

(state 010)

(2) all refs evaluated

at least one ref valid

(5) selected ref

phase l ocked

(3) no valid standby ref

(main ref invalid

or out of lock > 100s)

(14) al l r efs evaluated

at least one ref valid

pre-locked2

w ait for up to 100s

(state 101)

(10) selected source phase

locked

(6) no valid standby ref

main ref invalid

free-run

select ref

(state 001)

(1)Reset

Reference sources are flagged as 'valid' when

active, 'in-band' and have no phase alarm set.

All sources are continuously checked for

activity and frequency.

Only the main source is checked for phase.

A phase lock alarm is only raised on a

reference when that reference has lost phase

whilst being used as the main reference. The

micro-processor can reset the phase lock

alarm.

A source is considered to have phase locked

when it has been continuously in phase lock

for between 1 and 2 seconds

Lost phase

w ait for up to 100s

(state 111)

(7) phase lost

on m ain r ef

(8) phase

regained within

100s

(12) valid standby r ef

(main ref invalid

or out of lock > 100s)

(13) no valid standby ref

(main ref invalid

or out of lock > 100s)

(11) no valid standby ref

(main ref invalid

or out of lock > 100s)

(9) valid standby ref

[ main ref invalid or

(higher-priority ref valid

& in revertive mode) ]

(15) valid standby r ef

[ main ref invalid or

(higher-priority ref valid

& in revertive mode) or

out of lock >100s]

(4) valid standby ref

[ main ref invalid or

(higher-priority ref valid

& in revertive mode) or

out of lock >100s]

Figure 11. Automatic Mode Control State DiagramFigure 11. Automatic Mode Control State Diagram

Figure 11. Automatic Mode Control State Diagram

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Electrical Specification Electrical Specification

Electrical Specification

Important NoteImportant Note

Important Note: The ‘Absolute Maximum Ratings’ are stress ratings only, and functional operation

of the device at conditions other than those indicated in the ‘Operating Conditions’ sections of

this specification are not implied. Exposure to the absolute maximum ratings for an extended

period may reduce the reliability or useful lifetime of the product.

Table 14. Absolute Maximum RatingsTable 14. Absolute Maximum Ratings

Table 14. Absolute Maximum Ratings

Table 15. Operating ConditionsTable 15. Operating Conditions

Table 15. Operating Conditions

PPRETEMARARETEMARA RETEMARA RETEMARARETEMARA SS

SSLOBMYLOBMY LOBMY LOBMYLOBMY MM

MMNININININI MM

MMXAXAXAXAXA UU

UUSTINSTIN STIN STINSTIN

ppuSegatloVyl

V,+

,+1V

+2 V

5.0-6.3V

egatloVtupnI

)snipylppus-non( niV- 5.5V

egatloVtuptuO

)snipylppus-non( tuoV- 5.5V

erutarepmeTgnitarepOtneibmA

egnaR T

04-+58°C

erutarepmeTegarotST

rots

05-+051°C

Table 16. DC Characteristics: TTL Input PortTable 16. DC Characteristics: TTL Input Port

Table 16. DC Characteristics: TTL Input Port

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

hgiHV

0.2--V

woLV

-- 8.0V

tnerructupnII

-- 01Aµ

Across all operating conditions, unless otherwise stated

PPRETEMARARETEMARA RETEMARA RETEMARARETEMARA SS

SSLOBMYLOBMY LOBMY LOBMYLOBMY NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

)egatlovcd(ylppuSrewoP

VDD+2AV,+1AV,+DV,,+IMAV,

FFID_DDV

DDV0.33.36.3V

)egatlovcd(ylppuSrewoP

5DDV 5DDV0.30.5/3.35.5V

egnaRerutarepmettneibmAT

04--+58°C

tnerrucylppuS

)tuptuozHM91eno-lacipyT(

DDI-011002Am

noitapissidrewoplatoTP

TOT

-063027Wm

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Revision 2.00/September 2003 Semtech Corp.

Table 17. DC Characteristics: TTL Input Port with Internal Pull-upTable 17. DC Characteristics: TTL Input Port with Internal Pull-up

Table 17. DC Characteristics: TTL Input Port with Internal Pull-up

Table 18. DC Characteristics: TTL Input Port with Internal Pull-downTable 18. DC Characteristics: TTL Input Port with Internal Pull-down

Table 18. DC Characteristics: TTL Input Port with Internal Pull-down

Table 19. DC Characteristics: TTL Output PortTable 19. DC Characteristics: TTL Output Port

Table 19. DC Characteristics: TTL Output Port

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

woLtuoV

Am4=loI loV0- 4.0V

hgiHtuoV

Am4=hoI hoV4.2- V

tnerrucevirDDI--4Am

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

hgiHV

0.2--V

woLV

-- 8.0V

rotsiserpu-lluPUP03-08kΩ

tnerructupnII

-- 021Aµ

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

hgiHV

0.2--V

woLV

-- 8.0V

rotsisernwod-lluPDP03-08kΩ

tnerructupnII

-- 021Aµ

Across all operating conditions, unless otherwise stated

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Revision 2.00/September 2003 Semtech Corp.

Table 20. DC Characteristics: PECL Input/Output PortTable 20. DC Characteristics: PECL Input/Output Port

Table 20. DC Characteristics: PECL Input/Output Port

Notes to Table 20Notes to Table 20

Notes to Table 20

Unused differential input ports should be left floating and set in LVDS mode, or the positive and negative inputs tied

to VDD and GND respectively.

Note 1. Assuming a differential input voltage of at least 100 mV.

Note 2. Unused differential input terminated to VDD-1.4 V.

Note 3. With 50  load on each pin to VDD-2 V. i.e. 82  to GND and 130  to VDD.

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

egatlovwoLtupnILCEP

stupnilaitnereffiD)1etoN(

LCEPLI

-DDV5.2- 5.0-DDVV

egatlovhgiHtupnILCEP

stupnilaitnereffiD)1etoN(

LCEPHI

-DDV4.2- 4.0-DDVV

egatlovlaitnereffiDtupnIV

LCEPDI

1.0-4.1V

egatlovwoLtupnILCEP

tupnidedneelgniS)2etoN(

S_LCEPLI

-DDV4.2- 5.1-DDVV

egatlovhgiHtupnILCEP

tupnidedneelgniS)2etoN(

S_LCEPHI

1-DDV3.- 5.0-DDVV

tnerruchgiHtupnI

egatlovlaitnereffidtupnI

v4.1=

LCEPHI

01--01+Aµ

tnerrucwoLtupnI

egatlovlaitnereffidtupnI

v4.1=

LCEPLI

01--01+Aµ

egatlovwoLtuptuOLCEP

)3etoN(

LCEPLO

-DDV01.2- 26.1-DDVV

egatlovhgiHtuptuOLCEP

)3etoN(

LCEPHO

52.1-DDV-88.0-DDVV

egatlovlaitnereffiDtuptuOLCEP

)1etoN(

LCEPDO

085-009Vm

Across all operating conditions, unless otherwise stated

www.semtech.com51

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

130R

I6POS

I6NEG

I5NEG

I5POS T06POS

T06NEG

T07POS

T07NEG

ZO=50Ω

82R

130R

ZO=50Ω

130R

82R

130R

82R

130R

82R

130R

82R

130R

GND

GND GND

GND

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

51.84, 77.76 or

155.52 MHz

51.84, 77.76 or

155.52 MHz

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

19.44, 38.88, 155.52,

311.04 MHz & DIG1

19.44, 51.84, 77.76,

155.52 MHz

VDD = +3.3 V

Figure 12. Recommended Line Termination for PECL Input/Output PortsFigure 12. Recommended Line Termination for PECL Input/Output Ports

Figure 12. Recommended Line Termination for PECL Input/Output Ports

www.semtech.com52

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Table 21. DC Characteristics: LVDS Input/Output PortTable 21. DC Characteristics: LVDS Input/Output Port

Table 21. DC Characteristics: LVDS Input/Output Port

Note to Table 21Note to Table 21

Note to Table 21

Note 1. With 100  load between the differential outputs.

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

LSDVegnaregatlovtupnI

Vm001=egatlovtupnilaitnereffiD

SDVLRV

0- 04.2V

dlohserhttupnilaitnereffiDSDVLV

HTID

001--001+mV

egatlovlaitnereffiDtupnISDVLV

SDVLDI

1.0-4.1V

ecnatsisernoitanimrettupnISDVL

ehtssorcayllanretxedecalpebtsuM

.0158SCAfosniptupni-/+SDVL

001ebdluohsrotsiseR Ω%5htiw

ecnarelot

MRET

59001501 Ω

egatlovhgihtuptuOSDVL

)1etoN(

SDVLHO

-- 585.1V

egatlovwoltuptuOSDVL

)1etoN(

SDVLLO

588.0--V

egatlovtuptuolaitnereffiDSDVL

)1etoN(

SDVLDO

052-054Vm

LSDVfoedutingamniegnahC

rofegatlovtuptuolaitnereffid

setatsyratnemilpmoc

)1etoN(

SDVLSOD

-- 52Vm

LSDVegatlovtesffotuptuo

C°52=erutarepmeT

)1etoN(

SDVLSO

521.1-572.1V

Across all operating conditions, unless otherwise stated

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

I6POS

I6NEG

I5NEG

I5POS T06POS

T06NEG

T07POS

T07NEG

ZO=50Ω

100R

ZO=50Ω

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

51.84, 77.76 or

155.52 MHz

51.84, 77.76 or

155.52 MHz

8kHz, 1.544/2.048,

6.48, 19.44, 38.88,

19.44, 38.88, 155.52,

311.04 MHz & DIG1

19.44, 51.84, 77.76,

155.52 MHz

100R

Figure 13. Recommended Line Termination for LVDS Input/Output PortsFigure 13. Recommended Line Termination for LVDS Input/Output Ports

Figure 13. Recommended Line Termination for LVDS Input/Output Ports

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

The Alternate Mark Inversion (AMI) signal is DC balanced and consists of positive and negative

pulses with a peak to peak voltage of 2.0 +/- 0.2 V.

The electrical specifications are taken from option a) of Table 2/G.703 - Digital 64 kbit/s

centralized clock interface, from ITU G.703.

The electrical characteristics of 64 kbits/s interface are as follows;

Nominal bit rate: 64 kbit/s. The tolerance is determined by the network clock stability.

There should be a symmetrical pair carrying the composite timing signal (64 kHz and 8 kHz). The

use of transformers is recommended.

Over-voltage protection requirement; refer to Recommendation K.41.

Code conversion rules;

The data signals are coded in AMI code with 100% duty cycle. The composite clock timing signals

convey the 64 kHz bit-timing information using AMI coding with a 50% to 70% duty ratio and the

8 kHz octet phase information by introducing violations in the code rule. The structure of the

signals and voltage levels are shown in Figures 14 and 15.

Table 22. DC Characteristics: AMI Input/Output PortTable 22. DC Characteristics: AMI Input/Output Port

Table 22. DC Characteristics: AMI Input/Output Port

DC Characteristics: AMI Input/Output Port DC Characteristics: AMI Input/Output Port

DC Characteristics: AMI Input/Output Port

Across all operating conditions, unless otherwise stated

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

htdiwesluPtupnIt

65.18.740.41su

emitllaf/esiresluPtupnIt

F/R

--5su

IMAhgihegatlovtupnIV

IMAHI

5.2-V

3.0+V

IMAegatlovtupnIelddimV

IMAMIV

5.156.18.1V

IMAegatlovtupnIwolV

IMALIV

0- 4.1V

evirdtnerructuptuOIMAI

TUOIMA

-- 02Am

egatlovhgihtuptuOIMA

Am02=tnerructuptuO

IMAHO

61.0---V

IMAegatlovwoltuptuO

Am02=tnerructuptuO

IMALO

-- 61.0V

ecnedepmidaoltsetlanimoNR

TSET

-011-Ω

retfaedutilpma"kraM"

remrofsnart V

KRAM

9.00.11.1V

retfaedutilpma"ecapS"

remrofsnart V

ECAPS

1.0-01.0V

www.semtech.com55

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

after suitable input/output transformer (also see Figure 6/G.703)

15.6us

7.8us

2V p-p 1V

+1.0V

-1 .0 V

15.6us

7.8us

2V p-p 1V

+1.0V

-1 .0 V

15.6us

7.8us

2V p-p 1V

+1.0V

-1 .0 V

15.6us

7.8us

2V p-p 1V

+1.0V

-1 .0 V

TO8POS

TO8NEG

I_1

I_2

15.6us

7.8us

+VDD

15.6us

7.8us

+VDD

Signal structure of 64 kHz/

8 kHz central clock interface

after suitable transformer.

15.6us

7.8us

+VDD

15.6us

7.8us

+VDD

Figure 14. Signal Structure of 64 kHz/8kHz Central Clock InterfaceFigure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface

Figure 14. Signal Structure of 64 kHz/8kHz Central Clock Interface

Figure 15. AMI Input and Output Signal LevelsFigure 15. AMI Input and Output Signal Levels

Figure 15. AMI Input and Output Signal Levels

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Figure 16. Recommended Line Termination for AMI Output/Output Ports Figure 16. Recommended Line Termination for AMI Output/Output Ports

Figure 16. Recommended Line Termination for AMI Output/Output Ports

Notes

The AMI inputs <I_1> and <I_2> should be connected to the external AMI clock source by 470 nF coupling capacitor

C1.

The AMI differential output TO8POS/TO8NEG should be coupled to a line transformer with a turns ration of 3:1.

Components C2 = 470 pF and C3 = 2 nF. If a transformer with a turns ratio of 1:1 is used, a 3:1 ratio potential

divider Rload must be used to achieve the required 1 V pp voltage level for the positive and negative pulses.

C2 C3

TO8POS

TO8NEG

<I_1>

<I_2>

AMI input

GND

AMI output signal

to external devices

Turns

ratio

1:1

signal

AMI input

signal

load

www.semtech.com57

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Across all operating conditions, unless otherwise stated

Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813)Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813)

Table 23. DC Characteristics: Output Jitter Generation (Test Definition G.813)

Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812)Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812)

Table 24. DC Characteristics: Output Jitter Generation (Test Definition G.812)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

noitinifedtseTnoitinifedtseT noitinifedtseT noitinifedtseTnoitinifedtseTdesuretliFdesuretliF desuretliF desuretliFdesuretliFcepsIUcepsIU cepsIU cepsIUcepsIU 0158SCAnotnemerusaemIU0158SCAnotnemerusaemIU 0158SCAnotnemerusaemIU 0158SCAnotnemerusaemIU0158SCAnotnemerusaemIU

2veR2veR 2veR 2veR2veR

1noitpozHM25.551rof318.GzHM3.1otzH005IU

5.0=)2etoN(850.0

1noitpozHM25.551rof318.GzHM3.1otzHk56IU

1.0= )3etoN(840.0

)2etoN(840.0

2noitpozHM25.551rof318.GzHM3.1otzHk21IU

1.0=

)4etoN(350.0

)5etoN(350.0

)6etoN(850.0

)7etoN(350.0

)2etoN(350.0

)3etoN(850.0

)8etoN(750.0

)9etoN(550.0

)01etoN(750.0

)11etoN(750.0

)21etoN(750.0

)31etoN(350.0

zHM840.2rof218.G&318.G

1noitpo zHk001otzH02IU

50.0=)41etoN(640.0

2veR2veR 2veR 2veR2veR

zHM445.1rof218.GzHk04otzH01IU

50.0=)41etoN(630.0

lacirtcelezHM25.551rof218.GzHM3.1otzH005IU

5.0=)51etoN(850.0

lacirtcelezHM840.2rof218.GzHM3.1otzHk56 IU

570.0 )51etoN(840.0

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

2veR2veR 2veR 2veR2veR

zHM840.2rof3-264-003-STE

CES zHk001otzH02IU

5.0=)41etoN(640.0

zHM840.2rof3-264-003-STE

CES

)zHk001otzH94cepsretliF(

zHk001otzH02IU

2.0=)41etoN(640.0

zHM840.2rof3-264-003-STE

USS zHk001otzH02IU

50.0=)41etoN(640.0

zHM25.551rof3-264-003-STEzHM3.1otzH005IU

5.0=)51etoN(850.0

zHM25.551rof3-264-003-STEzHM3.1otzHk56IU

1.0=)51etoN(840.0

2veR2veR 2veR 2veR2veR

48.15,f/itenEROC-352-RG

zHM zHk004otzH001IU

5.1=)51etoN(220.0

48.15,f/itenEROC-352-RG

zHM

)zHk004otzHk02cepsretliF(

zHk004otzHk81IU

51.0=)51etoN(910.0

25.551,f/itenEROC-352-RG

zHM zHM3.1otzH005IU

5.1=)51etoN(850.0

25.551,f/itenEROC-352-RG

zHM zHM3.1otzHk56IU

51.0=)51etoN(840.0

,f/itceleIItacEROC-352-RG

zHM25.551 zHk004otzHk21

1.0=)51etoN(750.0

smr

10.0=)51etoN(600.0

,f/itceleIItacEROC-352-RG

zHM48.15 zHM3.1otzHk21

1.0=)51etoN(710.0

smr

10.0=)51etoN(300.0

445.1,f/i1SDEROC-352-RG

zHM zHk04otzH01

1.0=)41etoN(630.0

smr

10.0=)41etoN(5500.0

Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3)Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3)

Table 25. DC Characteristics: Output Jitter Generation (Test Definition ETS-300-462-3)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE)Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE)

Table 26. DC Characteristics: Output Jitter Generation (Test Definition GR-253-CORE)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

2veR2veR 2veR 2veR2veR

zHM445.1rof11426T&TA

)zHk8otzH01cepsretliF( zHk04otzH01IU

smr

20.0=)41etoN(5500.0

zHM445.1rof11426T&TAzHk04otzH01 IU

smr

520.0 )41etoN(5500.0

zHM445.1rof11426T&TAzHk04otzH01 IU

smr

520.0 )41etoN(5500.0

zHM445.1rof11426T&TAdnabdaorBIU

smr

50.0=)41etoN(5500.0

2veR2veR 2veR 2veR2veR

rof428G&994000-TWN-RT

zHM445.1 zHk04otzH01IU

0.5=)41etoN(630.0

rof428G&994000-TWN-RT

zHM445.1

)zHk04otzHk8cepsretliF(

zHk04otzH01IU

1.0=)41etoN(630.0

Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411)Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411)

Table 27. DC Characteristics: Output Jitter Generation (Test Definition AT&T 62411)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742)Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742)

Table 28. DC Characteristics: Output Jitter Generation (Test Definition G.742)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499)Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499)

Table 29. DC Characteristics: Output Jitter Generation (Test Definition TR-NWT-000499)

Across all operating conditions, unless otherwise stated

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

2veR2veR 2veR 2veR2veR

zHM840.2rof247.GzHk001otCDIU

52.0=)41etoN(740.0

zHM840.2rof247.G

)zHk001otzHk81cepsretliF( zHk001otzH02IU

50.0=)41etoN(640.0

zHM840.2rof247.GzHk001otzH02IU

50.0=)41etoN(640.0

www.semtech.com60

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Notes for Tables 23 - 30Notes for Tables 23 - 30

Notes for Tables 23 - 30

Note 1. Filter used is that defined by test definition unless otherwise stated

Note 2. 5 Hz bandwidth, 19.44 MHz direct lock

Note 3. 5 Hz bandwidth, 8 kHz lock

Note 4. 20 Hz bandwidth, 19.44 MHz direct lock

Note 5. 20 Hz bandwidth, 8 kHz lock

Note 6. 10 Hz bandwidth, 19.44 MHz direct lock

Note 7. 10 Hz bandwidth, 8 kHz lock

Note 8. 2.5 Hz bandwidth, 19.44 MHz direct lock

Note 9. 2.5 Hz bandwidth, 8 kHz lock

Note 10. 1.2 Hz bandwidth, 19.44 MHz direct lock

Note 11. 1.2 Hz bandwidth, 8 kHz lock

Note 12. 0.6 Hz bandwidth, 19.44 MHz direct lock

Note 13. 0.6 Hz bandwidth, 8 kHz lock

Note 14. 5 Hz bandwidth, 8 kHz lock, 2.048 MHz input

Note 15. 5 Hz bandwidth, 8 kHz lock, 19.44 MHz input

2veR2veR 2veR 2veR2veR

zHM445.1rofEROC-4421-RGzH01>IU

50.0=)41etoN(630.0

Output jitter generation measured over 60 seconds interval, UI pp max measured using Vectron 6664 12.8 MHz

TCXO on ICT Flexacom + 10 MHz reference from Wavetek 905.

Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE)Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE)

Table 30. DC Characteristics: Output Jitter Generation (Test Definition GR-1244-CORE)

Across all operating conditions, unless otherwise stated

www.semtech.com61

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

tSUR tHT

tDOD

tCYC

TCK

TMS

TDO

TDI

RETEMARAPRETEMARAP RETEMARAP RETEMARAPRETEMARAP LOBMYSLOBMYS LOBMYS LOBMYSLOBMYS NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM STINUSTINU STINU STINUSTINU

emitelcyCt

CYC

05--sn

egdegnisirKCTotIDT/SMT

emit t

RUS

3- -sn

dlohIDT/SMTotgnisirKCT

emit t

32--sn

dilavODTotgnillafKCTt

DOD

--5sn

Table 31. JTAG Timing (for use with Figure 17)Table 31. JTAG Timing (for use with Figure 17)

Table 31. JTAG Timing (for use with Figure 17)

Figure 17. JTAG TimingFigure 17. JTAG Timing

Figure 17. JTAG Timing

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

(Multiples have the

< ± 0.5 ns

311.04 MHz

< ± 1 ns

+2.0 to +4.0 ns

+6.0 to +8.0 ns

+3.0 to +4.5 ns

+3.0 to +5.0 ns

+2.5 to +4.5 ns

+3.0 to +5.0 ns

155.52 MHz

77.76 MHz

51.84 MHz

38.88 MHz

19.44 MHz

25.92 MHz

6.48 MHz

for this output)

(Additional delay

same offset)

+3.5 to +5.5 ns

< ±1 ns

Alignment

Phase

8 kHz

2 kHz

Output

same offset)

(Multiples have the

8 kHz input

8 kHz output

6.48 MHz input

6.48 MHz output

19.44 MHz input

19.44 MHz output

25.92 MHz input

25.92 MHz output

38.88 MHz input

38.88 MHz output

51.84 MHz input

51.84 MHz output

77.76 MHz input

77.76 MHz output

Input/Output Delay

± 1.5 ns

+6.5 to +8.5 ns

+5.5 to +7.5 ns

+6.5 to +8.5 ns

+4.0 to +6.0 ns

+6.0 to +8.0 ns

+5.5 to +7.5 ns

Typical

Figure 18. Input/Output TimingFigure 18. Input/Output Timing

Figure 18. Input/Output Timing

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Motorola ModeMotorola Mode

Motorola Mode

In MOTOROLA mode, the device is configured to interface with a microprocessor using a 680x0 type bus. The

following figures show the timing diagrams of write and read accesses for this mode.

address

data

Z Z

X X

td1

td2 tpw2 th3 td4

td3

tsu1 th1

tsu2 th2

tpw1

CSB

WRB

RDY

(DTACK)

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.

Microprocessor Interface Timing Microprocessor Interface Timing

Microprocessor Interface Timing

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

BSCotdilavAputeS

egdegnillaf

0sn- -

2us

BSCotdilavBRWputeS

egdegnillaf

sn0--

BSCyaleD

egdegnillaf

dilavDAot--sn771

BSCyaleD

egdegnillaf

KCATDot

egdegnisir

-- sn31

BSCyaleD

egdegnisir

Z-hgihDAot--sn0

BSCyaleD

egdegnisir

Z-hgihYDRot--sn7

1wp

emitwolBSC sn584

)1(

2wp

emithgihYDR sn013- sn274

BSCretfadilavAdloH

egdegnisir

sn0--

BSCretfahgihBRWdloH

egdegnisir

sn0--

YDRretfawolBSCdloH

egdegnillaf

sn0--

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn023--

Figure 19. Read Access Timing in MOTOROLA ModeFigure 19. Read Access Timing in MOTOROLA Mode

Figure 19. Read Access Timing in MOTOROLA Mode

Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19)Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19)

Table 32. Read Access Timing in MOTOROLA Mode (for use with Figure 19)

www.semtech.com64

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 178 ns.

address

data

X X

tsu3

td2 tpw2 th3 td4

th4

tsu1 th1

tsu2 th2

tpw1

CSB

WRB

RDY

(DTACK)

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

BSCotdilavAputeS

egdegnillaf

0sn- -

2us

BSCotdilavBRWputeS

egdegnillaf

sn0--

3us

BSCerofebdilavDAputeS

egdegnisir

sn3--

BSCyaleD

egdegnillaf

YDRot

egdegnisir

-- sn31

BSCyaleD

egdegnisir

Z-hgihYDRot--sn7

1wp

emitwolBSC sn584

)1(

2wp

emithgihYDR sn013- sn274

BSCretfadilavAdloH

egdegnisir

sn3--

BSCretfawolBRWdloH

egdegnisir

sn0--

YDRretfawolBSCdloH

egdegnillaf

sn0--

BSCretfadilavDAdloH

egdegnisir

sn4

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn023--

Figure 20. Write Access Timing in MOTOROLA ModeFigure 20. Write Access Timing in MOTOROLA Mode

Figure 20. Write Access Timing in MOTOROLA Mode

Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20)Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20)

Table 33. Write Access Timing in MOTOROLA Mode (for use with Figure 20)

www.semtech.com65

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Intel ModeIntel Mode

Intel Mode

In INTEL mode, the device is configured to interface with a microprocessor using a 80x86 type bus. The following

figures show the timing diagrams of write and read accesses for this mode.

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.

address

data

Z Z

td1

td2 tpw2 th3

td3

td4

tsu1 th1

tsu2 th2

tpw1

CSB

WRB

RDY

RDB

td5

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

BSCotdilavAputeS

egdegnillaf

0sn- -

2us

BSCputeS

egdegnillaf

BDRot

egdegnillaf

sn0--

BDRyaleD

egdegnillaf

dilavDAot--sn771

BSCyaleD

egdegnillaf

evitcaYDRot--sn31

BDRyaleD

egdegnillaf

YDRot

egdegnillaf

-- sn41

BDRyaleD

egdegnisir

Z-hgihDAot--sn01

BSCyaleD

egdegnisir

Z-hgihYDRot sn9

1wp

emitwolBDR sn684

)1(

2wp

emitwolYDR sn013- sn274

BDRretfadilavAdloH

egdegnisir

sn0--

BDRretfawolBSCdloH

egdegnisir

sn0--

YDRretfawolBDRdloH

egdegnisir

sn0--

BDR(sesseccaevitucesnocneewtebemiT

egdegnisir

BDRot

egdegnillaf

ro,

BDR

egdegnisir

BRWot

egdegnillaf

)sn023--

Figure 21. Read Access Timing in INTEL ModeFigure 21. Read Access Timing in INTEL Mode

Figure 21. Read Access Timing in INTEL Mode

Table 34. Read Access Timing in INTEL Mode (for use with Figure 21)Table 34. Read Access Timing in INTEL Mode (for use with Figure 21)

Table 34. Read Access Timing in INTEL Mode (for use with Figure 21)

www.semtech.com66

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.

Note 2: Timing if th2 is greater than 170 ns, otherwise 5 ns after CSB rising edge.

address

data

Z Z

td2 tpw2 th3

td3

th4

tsu1 th1

tsu2 th2

tpw1

CSB

WRB

RDY

RDB

td5

su3

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

BSCotdilavAputeS

egdegnillaf

0sn- -

2us

BSCputeS

egdegnillaf

BRWot

egdegnillaf

sn0--

3us

BRWotdilavDAputeS

egdegnisir

sn3--

BSCyaleD

egdegnillaf

evitcaYDRot--sn31

BRWyaleD

egdegnillaf

YDRot

egdegnillaf

-- sn41

BSCyaleD

egdegnisir

Z-hgihYDRot sn9

1wp

emitwolBRW sn684

)1(

2wp

emitwolYDR sn013- sn274

BRWretfadilavAdloH

egdegnisir

sn071

)2(

BRWretfawolBSCdloH

egdegnisir

sn0--

YDRretfawolBRWdloH

egdegnisir

sn0--

BRWretfadilavDAdloH

egdegnisir

sn4

BRW(sesseccaevitucesnocneewtebemiT

egdegnisir

BRWot

egdegnillaf

ro,

BRW

egdegnisir

BDRot

egdegnillaf

)sn023--

Figure 22. Write Access Timing in INTEL ModeFigure 22. Write Access Timing in INTEL Mode

Figure 22. Write Access Timing in INTEL Mode

Table 35. Write Access Timing in INTEL Mode (for use with Figure 22)Table 35. Write Access Timing in INTEL Mode (for use with Figure 22)

Table 35. Write Access Timing in INTEL Mode (for use with Figure 22)

www.semtech.com67

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Multiplexed ModeMultiplexed Mode

Multiplexed Mode

In MULTIPLEXED mode, the device is configured to interface with a microprocessor using a multiplexed address/

data bus. The following figures show the timing diagrams of write and read accesses for this mode.

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.

address data

Z Z

td1

td2 tpw2 th3

td3

td4

th1

th2

tpw1

CSB

WRB

RDY

RDB

td5

ALE

pw3

su1

X X

tp1

su2

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

ELAotdilavsserddaDAputeS

egdegnillaf

sn2--

2us

BSCputeS

egdegnillaf

BDRot

egdegnillaf

sn0--

BDRyaleD

egdegnillaf

dilavatadDAot--sn771

BSCyaleD

egdegnillaf

evitcaYDRot--sn31

BDRyaleD

egdegnillaf

YDRot

egdegnillaf

-- sn51

BDRyaleD

egdegnisir

Z-hgihatadDAot--sn9

BSCyaleD

egdegnisir

Z-hgihYDRot--sn01

1wp

emitwolBDR sn784

)1(

2wp

emitwolYDR sn013- sn274

3wp

emithgihELA sn2

ELAretfadilavsserddaDAdloH

egdegnillaf

sn3--

BDRretfawolBSCdloH

egdegnisir

sn0--

YDRretfawolBDRdloH

egdegnisir

sn0--

ELAneewtebemiT

egdegnillaf

BDRdna

egdegnillaf

sn0--

BDR(sesseccaevitucesnocneewtebemiT

egdegnisir

ELAot

egdegnisir

)sn023--

Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23)Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23)

Table 36. Read Access Timing in MULTIPLEXED Mode (for use with Figure 23)

Figure 23. Read Access Timing in MULTIPLEXED ModeFigure 23. Read Access Timing in MULTIPLEXED Mode

Figure 23. Read Access Timing in MULTIPLEXED Mode

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Note 1: Timing with RDY. If RDY not used, tpw1 becomes 180 ns.

address data

Z Z

tsu3

td2 tpw2 th3

td3

th4

th1

th2

tpw1

CSB

WRB

RDY

RDB

td5

ALE

pw3

su1

X X

tp1

su2

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

ELAotdilavsserddaDAputeS

egdegnillaf

sn2--

2us

BSCputeS

egdegnillaf

BRWot

egdegnillaf

sn0--

3us

BRWotdilavatadDAputeS

egdegnisir

sn3--

BSCyaleD

egdegnillaf

evitcaYDRot--sn31

BRWyaleD

egdegnillaf

YDRot

egdegnillaf

-- sn51

BSCyaleD

egdegnisir

Z-hgihYDRot sn9

1wp

emitwolBRW sn784

)1(

2wp

emitwolYDR sn013- sn274

3wp

emithgihELA sn2--

ELAretfadilavsserddaDAdloH

egdegnillaf

sn3--

BRWretfawolBSCdloH

egdegnisir

sn0--

YDRretfawolBRWdloH

egdegnisir

sn0--

BRWretfadilavdlohatadDA

egdegnisir

sn4

ELAneewtebemiT

egdegnillaf

BRWdna

egdegnillaf

sn0--

BRW(sesseccaevitucesnocneewtebemiT

egdegnisir

ELAot

egdegnisir

)sn023--

Figure 24. Write Access Timing in MULTIPLEXED ModeFigure 24. Write Access Timing in MULTIPLEXED Mode

Figure 24. Write Access Timing in MULTIPLEXED Mode

Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24)Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24)

Table 37. Write Access Timing in MULTIPLEXED Mode (for use with Figure 24)

www.semtech.com69

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Serial ModeSerial Mode

Serial Mode

In Serial mode, the device is configured to interface with a serial microprocessor bus.The combined minimum

High and Low times for SCLK define the maximum clock rate.

For Write access this is 2.77 MHz (360 ns). For Read access the maximum SCLK rate is slightly slower and is

affected by the setting of CLKE, being either 2.0 MHz (500 ns) or 1 MHz (1 us).

This mismatch in rates is caused by the sampling technique used to detect the end of the address field in Read

mode. It takes up to 3 cycles of an internal 6.40 MHz clock to start the Read process following receipt of the final

address bit. This is 468 ns. The Read data is then decoded and clocked out onto SDO directly using SCLK. With

CLKE=1, the falling edge of SCLK is used to clock out the SDO. With CLKE=0, the rising edge of SCLK is used to clock

out the SDO.

A minimum period of 500 ns (468 capture plus 32 decode) is required between the final address bit and clocking

it out onto SDO. This means that to guarantee the correct operation of the Serial interface, with CLKE=0, SCLK has

a maximum clock rate of 2 MHz. With CLKE=1, SCLK has a maximum clock rate of 1 MHz.

SCLK is not required to run between accesses (i.e., when CSB = 1). The following Figures show the timing

diagrams for Write and Read access for this mode.

Figure 25. Read Access Timing in Serial ModeFigure 25. Read Access Timing in Serial Mode

Figure 25. Read Access Timing in Serial Mode

F8525D_013ReadAccSerial_01

SCLK

CSB

CLKE = 0; SDO data is clocked out on the rising edge of SCLK

CLKE = 1; SDO data is clocked out on the falling edge of SCLK

R/W

Output not driven, pulled low by internal resistor

SDI

SDO

su2

su1

pw1

pw2

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

SCLK

CSB

R/W

Output not driven, pulled low by internal resistor

SDI

SDO

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

www.semtech.com70

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

KLCSotdilavIDSputeS

egdegnisir

0sn- -

2us

BSCputeS

egdegnillaf

KLCSot

egdegnisir

sn061--

KLCSyaleD

egdegnisir

KLCS(

egdegnillaf

dilavODSot)1=EKLCrof--sn71

BSCyaleD

egdegnisir

Z-hgihODSot--sn01

1wp

emitwolKLCS

0=EKLC

1=EKLC

sn052

sn005

2wp

emithgihKLCS

0=EKLC

1=EKLC

sn052

sn005

KLCSretfadilavIDSdloH

egdegnisir

sn071--

KLCSretfawolBSCdloH

egdegnisir

0=EKLCrof,

KLCSretfawolBSCdloH

egdegnillaf

1=EKLCrof, sn5--

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn061--

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

1us

KLCSotdilavIDSputeS

egdegnisir

0sn- -

2us

BSCputeS

egdegnillaf

KLCSot

egdegnisir

sn061--

1wp

emitwolKLCS sn081--

2wp

emithgihKLCS sn081--

KLCSretfadilavIDSdloH

egdegnisir

sn071--

KLCSretfawolBSCdloH

egdegnisir

sn5--

BSC(sesseccaevitucesnocneewtebemiT

egdegnisir

BSCot

egdegnillaf

)sn061--

Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25)Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25)

Table 38. Read Access Timing in SERIAL Mode (for use with Figure 25)

Figure 26. Write Access Timing in SERIAL ModeFigure 26. Write Access Timing in SERIAL Mode

Figure 26. Write Access Timing in SERIAL Mode

Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26)Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26)

Table 39. Write Access Timing in SERIAL Mode (for use with Figure 26)

ALE=SCLK

CSB

R/W

Output not driven, pulled low by internal resistor

A(0)=SDI

AD(0)=SDO

su2

su1

pw1

pw2

A0 A1 A2 A3 A4 A5 A6

D0 D1 D2 D3 D4 D5 D6 D7

F8110D_014WriteAccSerial_02

www.semtech.com71

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

EPROM ModeEPROM Mode

EPROM Mode

In EPROM mode, the ACS8510 takes control of the bus as Master, and reads the device set-up from an AMD

AM27C64 type EPROM at lowest speed (250ns), after device start-up (system reset). The EPROM access state

machine in the up interface sequences the accesses.

Further details can be found in the AMD AM27C64 data sheet.

address

data

Z Z

tacc

CSB (=OEB)

lobmySlobmyS lobmyS lobmySlobmyS retemaraPretemaraP retemaraP retemaraPretemaraP NIMNIM NIM NIMNIM PYTPYT PYT PYTPYT XAMXAM XAM XAMXAM

cca

BSCyaleD

egdegnillaf

dilavDAotegnahcAro--sn029

Figure 27. Access Timing in EPROM ModeFigure 27. Access Timing in EPROM Mode

Figure 27. Access Timing in EPROM Mode

Table 40. Access Timing in EPROM Mode (for use with Figure 27)Table 40. Access Timing in EPROM Mode (for use with Figure 27)

Table 40. Access Timing in EPROM Mode (for use with Figure 27)

www.semtech.com72

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Package Information Package Information

Package Information

AA2

A1 b

c c1

AN4

AN3

AN2

AN1

Section A-A

Section B-B

Seating plane

Notes

The top package body may be smaller than the bottom package body by as much as 0.15 mm.

To be determined at seating plane.

Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side.

D1 and E1 are maximum plastic body size dimensions including mold mismatch.

Details of pin 1 identifier are optional but will be located within the zone indicated.

Exact shape of corners can vary.

A1 is defined as the distance from the seating plane to the lowest point of the package body.

These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

Shows plating.

123

Figure 28. LQFP PackageFigure 28. LQFP Package

Figure 28. LQFP Package

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ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Thermal ConditionsThermal Conditions

Thermal Conditions

The device is rated for full temperature range when this package is used with a 4 layer or more

PCB. Copper coverage must exceed 50%. All pins must be soldered to the PCB. Maximum

operating temperature must be reduced when the device is used with a PCB with less than these

requirements.

PFQL001PFQL001 PFQL001 PFQL001PFQL001

egakcaPegakcaP egakcaP egakcaPegakcaP

snoisnemiDsnoisnemiD snoisnemiD snoisnemiDsnoisnemiD

mmnimmni mmni mmnimmni

E/DE/D E/D E/DE/D1E/1D1E/1D 1E/1D 1E/1D1E/1DAA

AA1A1A1A1A1A2A2A2A2A2Aee

ee1NA1NA 1NA 1NA1NA2NA2NA 2NA 2NA2NA3NA3NA 3NA 3NA3NA4NA4NA 4NA 4NA4NA1R1R1R1R1R2R2R2R2R2RLL

LL1L1L1L1L1LSS

SSbb

bb1b1b1b1b1bcc

cc1c1c1c1c1c

niM04.150.053.1°11°11°0°080.080.054.002.071.071.090.090.0

moN00.6100.4105.101.004.105.0°21°21- °5.3-- 06.0 00.1

)fer( -22.002.0--

xaM06.151.054.1°31°31-°7- 02.057.0-72.032.002.061.0

Width 0.3 mm

Pitch 0.5 mm

14.6 mm

17.0 mm (1)

18.3 mm

1.85 mm

Notes

(1) Solderable to this limit.

Square package - dimensions apply in both X and Y directions.

Typical example. The user is reponsible for ensuring compatibility with PCB manufacturing process, etc.

Figure 29. Typical 100 Pin LQFP FootprintFigure 29. Typical 100 Pin LQFP Footprint

Figure 29. Typical 100 Pin LQFP Footprint

Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28)Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28)

Table 41. 100 Pin LQFP Package Dimension Data (for use with Figure 28)

www.semtech.com74

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Application Information Application Information

Application Information

Figure 30. Simplified Application SchematicFigure 30. Simplified Application Schematic

Figure 30. Simplified Application Schematic

www.semtech.com75

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Revision History Revision History

Revision History

Table 42. Changes from Revision 1.06 to 2.00 September 2003Table 42. Changes from Revision 1.06 to 2.00 September 2003

Table 42. Changes from Revision 1.06 to 2.00 September 2003

Item Section Page Description

1Non-Revertive

Mode 36-37 Updated description of Non-Revertive Mode Operation

www.semtech.com76

ACS8510 Rev2.1 SETS

ADVANCED COMMUNICATIONS FINAL

Revision 2.00/September 2003 Semtech Corp.

Ordering Information Ordering Information

Ordering Information

ISO9001

CERTIFIED

REBMUNTRAPREBMUNTRAP REBMUNTRAP REBMUNTRAPREBMUNTRAP NOITPIRCSEDNOITPIRCSED NOITPIRCSED NOITPIRCSEDNOITPIRCSED

1.2veR0158SCA PFQLnip001,noitasinorhcnySHDS/TENOS

For additional information, contact the following:

Semtech Corporation Advanced Communications ProductsSemtech Corporation Advanced Communications Products

Semtech Corporation Advanced Communications Products

E-Mail: sales@semtech.com acsupport@semtech.com

Internet: http://www.semtech.com

USA: Mailing Address: P.O. Box 6097, Camarillo, CA 93011-6097

Street Address: 200 Flynn Road, Camarillo, CA 93012-8790

Tel: +1 805 498 2111, Fax: +1 805 498 3804

FAR EAST: 11F, No. 46, Lane 11, Kuang Fu North Road, Taipei, Taiwan, R.O.C.

Tel: +886 2 2748 3380, Fax: +886 2 2748 3390

EUROPE: Units 2 & 3 Park Court, Premier Way, Abbey Park Industrial Estate,

Romsey, Hampshire, SO51 9DN, UK

Tel: +44 1794 527 600, Fax: +44 1794 527 601

DisclaimersDisclaimers

Disclaimers

Life support - This product is not designed or intended for use in life suport equipment, devices or systems, or

other critical applications. This product is not authorized or warranted by Semtech Corporation for such use.

Right to change - Semtech Corporation reserves the right to make changes, without notice, to this product.

Customers are advised to obtain the latest version of the relevant information before placing orders.

Compliance to relevant standards - Operation of this device is subject to the user’s implementation, and design

practices. The user is responsible to ensure equipment using this device is compliant to any relevant standards.