AT65609EHV-DJ40SR - Atmel Corporation

PRELIMINARY

7832B–AERO–11/09

Features

•Operating Voltage: 5V

•Access Time: 40 ns

•Very Low Power Consumption

– Active: 275 mW (Max)

– Standby: 10 mW (Typ)

•Wide Temperature Range: -55⋅C to +125⋅C

•400 Mils Width Packages: FP32 and SB32

•TTL Compatible Inputs and Outputs

•Asynchronous

•No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2@125°C

•Tested up to a Total Dose of 300 krads (Si) according to MIL STD 883 Method 1019

•ESD better than 4000V

•Deliveries at least equivalent to QML procurement according to MIL-PRF38535

Description

The AT65609EHV is a very low power CMOS static RAM organized as 131072 x 8

bits. Utilizing an array of six transistors (6T) memory cells, the AT65609EHV com-

bines an extremely low standby supply current with a fast access time at 40 ns over

the full military temperature range. The high stability of the 6T cell provides excellent

protection against soft errors due to noise.

The AT65609EHV is processed according to the methods of the latest revision of the

MIL PRF 38535 or ESCC 9000.

It is manufactured on the same process as the MH1RT RAD-hard sea of gates series.

Rad. Tolerant

128K x 8

5-volts

Very Low Power

CMOS SRAM

AT65609EHV

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AT65609EHV

PRELIMINARY

Block Diagram

Pin Configuration

32-lead DIL side-brazed or 32-lead Flat Pack - 400 Mils

Note: NC pin is not bonded internally. So, it can be connected to GND or VCC.

GND

I/O2

I/O1

I/O0

A12

I/O3

I/O4

I/O5

I/O6

I/O7

A10

A11

A13

Vcc

CS1

A16

A14

A15

CS2

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AT65609EHV

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Pin Description

Table 1. Pin Names

Table 2. Truth Table

Note: L = low, H = high, X = H or L, Z = high impedance.

Names Description

A0 - A16 Address inputs

I/O0 - I/O7 Data Input/Output

CS1 Chip select 1

CS2 Chip select 2

WE Write Enable

OE Output Enable

VCC Power

GND Ground

CS1 CS2 WEOE Inputs/ Outputs Mode

HXXX Z Deselect/Power-down

XLXX Z Deselect/Power-down

L H H L Data Out Read

L H L X Data In Write

LHHH Z Output Disable

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AT65609EHV

PRELIMINARY

Electrical Characteristics

Absolute Maximum Ratings

Military Operating Range

Recommended DC Operating Conditions

Capacitance

Note: 1. Guaranteed but not tested.

Supply voltage to GND potential:..........................-0.5V + 7.0V

DC input voltage: ..............................GND - 0.5V to VCC + 0.5

DC output voltage high Z state: ........GND - 0.5V to VCC + 0.5

Storage temperature:.......................................-65⋅C to +150⋅C

Output current into outputs (low): .................................. 20 mA

Electro Static Discharge voltage with HBM method

(MIL STD 883D method 3015): ................................. > 4000V

Electro Static Discharge voltage with Socketed CDM method

(ANSI/ESD SP5.3.2-2004): ....................................... > 1000V

*NOTE: Stresses beyond those listed under "Abso-

lute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress

rating only and functional operation of the

device at these or any other conditions

beyond those indicated in the operational

sections of this specification is not implied.

Exposure between recommended DC

operating and absolute maximum rating

conditions for extended periods may

affect device reliability.

Operating Voltage Operating Temperature

5V + 10% -55⋅C to + 125°C⋅

Parameter Description Minimum Typical Maximum Unit

VCC Supply voltage 4.5 5.0 5.5 V

GND Ground 0.0 0.0 0.0 V

VIL Input low voltage GND - 0.5 0.0 0.8 V

VIH Input high voltage 2.2 – VCC + 0.5 V

Parameter Description Minimum Typical Maximum Unit

Cin(1) Input low voltage ––8pF

Cout(1) Output high voltage ––8pF

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AT65609EHV

PRELIMINARY

DC Parameters

DC Test Conditions TA = -55°C to + 125°C; Vss = 0V; VCC = 4.5V to 5.5V

Consumption

Symbol Description Minimum Typical Maximum Unit

IIX (1)

1. GND < Vin < VCC, GND < Vout < VCC Output Disabled.

Input leakage current -1 – 1 µA

IOZ(1) Output leakage current -1 – 1 µA

VOL (2)

2. VCC min. IOL = 8 mA

Output low voltage ––0.4V

VOH (3)

3. VCC min. IOH = -4 mA.

Output high voltage 2.4 – – V

Symbol Description AT65609EHV Unit Value

ICCSB (1)

1. CS1 > VIH or CS2 < VIL and CS1 < VIL.

Standby supply current 5mAmax

ICCSB1 (2)

2. CS1 > VCC - 0.3V or, CS2 < GND + 0.3V and CS1 < 0.2V.

Standby supply current 3mAmax

ICCOP (3)

3. F = 1/TAVAV, Iout = 0 mA, WE = OE = VCC, Vin = GND or VCC, VCC max, CS1=VIL, CS2=VIH

Dynamic operating current 50 mA max

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AT65609EHV

PRELIMINARY

AC Parameters

AC Test Conditions

Input Pulse Levels: ............................................................................................... GND to 3.0V

Input Rise/Fall Times: ......................................................................................................... 5 ns

Input Timing Reference Levels: ......................................................................................... 1.5V

Output loading IOL/IOH (see Figure 1 and Figure 2): ................................................... +30 pF

AC Test Loads Waveforms

Figure 1 Figure 2 Figure 3

7832B–AERO–11/09

AT65609EHV

PRELIMINARY

Data Retention Mode

Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage and sup-

ply current are guaranteed over temperature. The following rules ensure data retention:

1. During data retention chip select CS1 must be held high within VCC to VCC -0.2V or,

chip select CS2 must be held down within GND to GND +0.2V.

2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, mini-

mizing power dissipation.

3. During power up and power-down transitions CS1 and OE must be kept between VCC +

0.3V and 70% of VCC, or with CS2 between GND and GND -0.3V.

4. The RAM can begin operation > TR ns after VCC reaches the minimum operation volt-

ages (4.5V).

Timing

Data Retention Characteristics

Notes: 1. TAVAV = Read Cycle Time

2. CS1 = VCC or CS2 = CS1 = GND, Vin = GND/VCC, this parameter is only tested at

VCC = 2V.

Parameter Description Minimum

Typical

TA = 25 ⋅C Maximum Unit

VCCDR VCC for data retention 2.0 – – V

TCDR Chip deselect to data retention time 0.0 – – ns

TR Operation recovery time TAVAV(1) ––ns

ICCDR1(2) Data retention current at 2.0V –11.5mA

ICCDR2(2) Data retention current at 3.0V –1.52mA

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Write Cycle

Note: Parameters guaranteed, not tested, with output loading 5 pF.

Write Cycle 1 WE Controlled, OE High During Write

Symbol Parameter AT65609EHV Unit Value

TAVAW Write cycle time 35 ns min

TAVWL Address set-up time 0nsmin

TAVWH Address valid to end of write 30 ns min

TDVWH Data set-up time 20 ns min

TE1LWH CS1 low to write end 30 ns min

TE2HWH CS2 high to write end 30 ns min

TWLQZ Write low to high Z(1) 12 ns max

TWLWH Write pulse width 30 ns min

TWHAX Address hold from to end of write 3nsmin

TWHDX Data hold time 0nsmin

TWHQX Write high to low Z(1) 0nsmin

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PRELIMINARY

Write Cycle 2 WE Controlled, OE Low

Write Cycle 3 CS1 or CS2 Controlled

Note: The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and

WE LOW. Both signals must be actived to initiate a write and either signal can terminate a write by

going in actived. The data input setup and hold timing should be referenced to the actived edge of

the signal that terminates the write. Data out is high impedance if OE = VIH.

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AT65609EHV

PRELIMINARY

Read Cycle

Note: 1. Parameters Guaranteed, not tested, with output loading 5 pF.

Symbol Parameter AT65609EHV Unit Value

TAVAV Read cycle time 40 ns min

TAVQV Address access time 40 ns max

TAVQX Address valid to low Z(1) 3nsmin

TE1LQV Chip-select1 access time 40 ns max

TE1LQX CS1 low to low Z(1) 3nsmin

TE1HQZ CS1 high to high Z(1) 15 ns max

TE2HQV Chip-select2 access time 40 ns max

TE2HQX CS2 high to low Z(1) 3nsmin

TE2LQZ CS2 low to high Z(1) 15 ns max

TGLQV Output Enable access time 12 ns max

TGLQX OE low to low Z(1) 0nsmin

TGHQZ OE high to high Z(1) 10 ns max

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AT65609EHV

PRELIMINARY

Read Cycle 1 Address Controlled (CS1 = OE Low, CS2 = WE High)

Read Cycle 2 CS1 Controlled (CS2 = WE High)

Read Cycle 3 CS2 Controlled (WE High, CS1 Low)

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AT65609EHV

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Ordering Information

Note: 1. Contact Atmel for availability.

Part Number Temperature Range Speed Package Flow

AT65609EHV-C940-E (1) 25⋅C 40 ns SB32.4 Engineering Samples

AT65609EHV-DJ40-E (1) 25⋅C 40 ns FP32.4

AT65609EHV-C940MQ -55⋅ to +125⋅C 40 ns SB32.4 Mil Level B

AT65609EHV-DJ40MQ -55⋅ to +125⋅C 40 ns FP32.4

AT65609EHV-C940SV -55⋅ to +125⋅C 40 ns SB32.4 Space Level B

AT65609EHV-DJ40SV -55⋅ to +125⋅C 40 ns FP32.4

AT65609EHV-C940SR -55⋅ to +125⋅C 40 ns SB32.4 Space Level B RHA

AT65609EHV-DJ40SR -55⋅ to +125⋅C 40 ns FP32.4

7832B–AERO–11/09

AT65609EHV

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Package Drawings

32-lead Flat Pack 400 Mils

7832B–AERO–11/09

AT65609EHV

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32-lead Side Braze 400 Mils

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Document Revision History

Changes from 7832A to 7832B

1. Page 1 : total dose value updated and ESD item added

2. Page 5 : ESD HBM improved and ESD Socketed CDM added

3. Page 6 : note 3 of consumption table updated

4. Page 13 : ordering information section updated

7832B–AERO–11/09

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