THIS SPEC IS OBSOLETE
Spec No
:
38
-
05473
Spec
Title
:
CY7C1041DV33, 4
-
MBIT (256K X 16) STATIC
RAM
R
eplaced by:
None
CY7C1041DV33
4-Mbit (256K × 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-05473 Rev. *O Revised November 8, 2016
4-Mbit (256K × 16) Static RAM
Features
■Temperature ranges
❐Industrial: –40 °C to 85 °C
■Pin and function compatible with CY7C1041CV33
■High speed
❐tAA = 10 ns
■Low active power
❐ICC = 90 mA
■Low CMOS standby power
❐ISB2 = 10 mA
■2.0 V data retention
■Automatic power-down when deselected
■TTL compatible inputs and outputs
■Easy memory expansion with CE and OE features
■Available in Pb-free 48-ball VFBGA, 44-pin (400-mil) molded
SOJ, and 44-pin TSOP II Packages
Functional Description
The CY7C1041DV33 is a high performance CMOS Static RAM
organized as 256K words by 16-bits. To write to the device, take
chip enable (CE) and write enable (WE) inputs LOW. If byte low
enable (BLE) is LOW, then data from I/O pins (I/O0 to I/O7) is
written into the location specified on the address pins (A0 to A17).
If byte high enable (BHE) is LOW, then data from I/O pins (I/O8
to I/O15) is written into the location specified on the address pins
(A0 to A17).
To read from the device, take chip enable (CE) and output enable
(OE) LOW while forcing the write enable (WE) HIGH. If BLE is
LOW, then data from the memory location specified by the
address pins appears on I/O0 to I/O7. If BHE is LOW, then data
from memory appears on I/O8 to I/O15. See the Truth Table on
page 11 for a complete description of read and write modes.
The input and output pins (I/O0 to I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH),
outputs are disabled (OE HIGH), BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
The CY7C1041DV33 is available in a standard 44-pin 400-mil
wide SOJ and 44-pin TSOP II package with center power and
ground (revolutionary) pinout and a 48-ball FBGA package.
For a complete list of related documentation, click here.
14
15
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
256K × 16
A0
A11
A13
A12
A
A
A16
A17
A9
A10
I/O0–I/O7
OE
I/O8–I/O15
CE
WE
BLE
BHE
Logic Block Diagram
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 2 of 18
Contents
Selection Guide ................................................................3
Pin Configuration .............................................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
AC Switching Characteristics .........................................7
Switching Waveforms ...................................................... 8
Truth Table ......................................................................11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 3 of 18
Selection Guide
Description -10 (Industrial) Unit
Maximum access time 10 ns
Maximum operating current 90 mA
Maximum CMOS standby current 10 mA
Pin Configuration
Figure 1. 48-ball VFBGA (Pinout 1) [1, 2] Figure 2. 48-ball VFBGA (Pinout 2) [1, 2]
Figure 3. 44-pin SOJ/TSOP II pinout
WE
V
CC
A11
A10
NC
A6
A0
A3CE
I/O
2
I/O0
I/O
1
A4
A5
I/O3
I/O
5
I/O
4
I/O
6
I/O
7
V
SS
A9
A
8
OE
V
SS
A7
I/O
8
BHE
NC
A17
A2
A1
BLE
V
CC
I/O
9
I/O
10
I/O11
I/O
12
I/O
13 I/O
14
I/O
15
A15
A14
A
13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
WE
V
CC
A11
A10
NC
A6
A0
A3CE
I/O
10
I/O8
I/O
9
A4
A5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A9
A8
OE
V
SS
A7
I/O
0
BHE
NC
A17
A2
A1
BLE
V
CC
I/O
2
I/O1
I/O
3
I/O
4
I/O
5I/O
6
I/O
7
A15
A
14
A13
A
12
NC
NC NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
A
17
18
17
20
19
27
28
25
26
22
21
23
24
A
16
A
15
A
0
A
1
A
2
A
3
A
4
A
7
A
6
A
14
A
13
A
12
A
11
A
9
A
8
A
10
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
NC
10
A
5
Notes
1. NC pins are not connected on the die.
2. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls) are swapped.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 4 of 18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage on VCC relative to GND [3] ...–0.3 V to +4.6 V
DC voltage applied to outputs
in high Z State [3] ................................ –0.3 V to VCC + 0.3 V
DC input voltage [3] ............................. –0.3 V to VCC + 0.3 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, method 3015) ................................. > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Range Ambient
Temperature VCC Speed
Industrial –40 C to +85 C 3.3 V 0.3 V 10 ns
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions -10 (Industrial) Unit
Min Max
VOH Output HIGH voltage VCC = Min, IOH = –4.0 mA 2.4 – V
VOL Output LOW voltage VCC = Min, IOL = 8.0 mA – 0.4 V
VIH[3] Input HIGH voltage 2.0 VCC + 0.3 V
VIL[3] Input LOW voltage –0.3 0.8 V
IIX Input leakage current GND < VI < VCC –1 +1 A
IOZ Output leakage current GND < VOUT < VCC, output disabled –1 +1 A
ICC VCC operating supply current VCC = Max, f = fMAX = 1/tRC 100 MHz – 90 mA
83 MHz – 80 mA
66 MHz – 70 mA
40 MHz – 60 mA
ISB1 Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–20mA
ISB2 Automatic CE power-down
current – CMOS inputs
Max VCC,
CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V,
f = 0
–10mA
Note
3. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 5 of 18
Capacitance
Parameter [4] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = 3.3 V 8 pF
COUT I/O capacitance 8pF
Thermal Resistance
Parameter [4] Description Test Conditions 48-ball FBGA
Package
44-pin SOJ
Package
44-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still Air, soldered on a
3 × 4.5 inch, four layer
printed circuit board
27.89 57.91 50.66 C/W
JC Thermal resistance
(junction to case)
14.74 36.73 17.17 C/W
AC Test Loads and Waveforms
The AC test loads and waveform diagram follows.
Figure 4. AC Test Loads and Waveforms [5]
90%
10%
3.0 V
GND
90%
10%
ALL INPUT PULSES
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Rise Time: 1 V/ns Fall Time: 1 V/ns
30 pF*
OUTPUT
Z = 50
50
1.5 V
(b)
(a)
3.3 V
OUTPUT
5 pF
(c)
R 317
R2
351
High Z Characteristics
10 ns device
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except high Z) are tested using the load conditions shown in Figure 4 (a). High Z characteristics are tested for all speeds using the test load shown
in Figure 4 (c).
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 6 of 18
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions[6] Min Max Unit
VDR VCC for data retention 2.0 – V
ICCDR Data retention current VCC = VDR = 2.0 V, CE > VCC – 0.3 V,
VIN > VCC – 0.3 V or VIN < 0.3 V
–10
mA
tCDR[7] Chip deselect to data retention
time 0–ns
tR[8] Operation recovery time tRC –ns
Data Retention Waveform
Figure 5. Data Retention Waveform
3.0 V3.0 V
tCDR
VDR >2 V
DATA RETENTION MODE
tR
CE
VCC
Notes
6. No input may exceed VCC + 0.3 V.
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 7 of 18
AC Switching Characteristics
Over the Operating Range
Parameter [9] Description -10 (Industrial) Unit
Min Max
Read Cycle
tpower[10] VCC(Typical) to the first access 100 – s
tRC Read cycle time 10 – ns
tAA Address to data valid – 10 ns
tOHA Data hold from address change 3 – ns
tACE CE LOW to data valid – 10 ns
tDOE OE LOW to data valid – 5 ns
tLZOE OE LOW to low Z[11] 0–ns
tHZOE OE HIGH to high Z[11, 12] –5ns
tLZCE CE LOW to low Z[11] 3–ns
tHZCE CE HIGH to high Z[11, 12] –5ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down – 10 ns
tDBE Byte enable to data valid – 5 ns
tLZBE Byte enable to low Z 0 – ns
tHZBE Byte disable to high Z – 6 ns
Write Cycle[13, 14]
tWC Write cycle time 10 – ns
tSCE CE LOW to write end 7 – ns
tAW Address setup to write end 7 – ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7–ns
tSD Data setup to write end 5 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low Z[11] 3–ns
tHZWE WE LOW to high Z[11, 12] –5ns
tBW Byte enable to end of write 7 – ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
10. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
11. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, tHZBE is less than tLZBE, and tHZWE is less than tLZWE for any given
device.
12. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 4. Transition is measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of CE LOW and BHE or BLE, and WE LOW. All signals must be in valid states to initiate a Write, but
any one signal can go inactive to terminate the write.
14. The minimum write cycle time for Write Cycle No. 4 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 8 of 18
Switching Waveforms
Figure 6. Read Cycle No. 1 [15, 16]
Figure 7. Read Cycle No. 2 (OE Controlled) [16, 17]
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZBE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
tDBE
tLZBE
tHZCE
BHE,BLE
CURRENT
ICC
ISB
Notes
15. Device is continuously selected. OE, CE, BHE, and BLE = VIL.
16. WE is HIGH for read cycle.
17. Address valid prior to or coincident with CE transition LOW.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 9 of 18
Figure 8. Write Cycle No. 1 (CE Controlled) [18, 19]
Figure 9. Write Cycle No. 2 (BLE or BHE Controlled)
Switching Waveforms (continued)
tHD
tSD
tSCE
tSA
tHA
tAW
tPWE
tWC
BW
DATAI/O
ADDRESS
CE
WE
BHE, BLE
t
tHD
tSD
tBW
tSA
tHA
tAW
tPWE
tWC
tSCE
DATAI/O
ADDRESS
BHE,BLE
WE
CE
Notes
18. Data I/O is high impedance if OE or BHE and BLE = VIH.
19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 10 of 18
Figure 10. Write Cycle No. 3 (WE Controlled, OE HIGH During Write) [20, 21]
Figure 11. Write Cycle No. 4 (WE Controlled, OE LOW)
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
t
HZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 22
BHE,BLE
tHD
tSD
tSCE
tHA
tAW
tPWE
tWC
tBW
DATA I/O
ADDRESS
CE
WE
BHE,BLE
tSA
tLZWE
tHZWE
NOTE 22
Notes
20. Data I/O is high impedance if OE or BHE and BLE = VIH.
21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
22. During this period the I/Os are in the output state and input signals should not be applied.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 11 of 18
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
H X X X X High Z High Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out High Z Read lower bits only Active (ICC)
L L H H L High Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in High Z Write lower bits only Active (ICC)
L X L H L High Z Data in Write upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
L X X H H High Z High Z Selected, outputs disabled Active (ICC)
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 12 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type
Operating
Range
10 CY7C1041DV33-10BVI 51-85150 48-ball VFBGA Pinout - 1[23] Industrial
CY7C1041DV33-10BVXI 48-ball VFBGA (Pb-free) Pinout - 1[23]
CY7C1041DV33-10BVJXI 48-ball VFBGA (Pb-free) Pinout - 2[23]
CY7C1041DV33-10VXI 51-85082 44-pin (400-mil) Molded SOJ (Pb-free)
CY7C1041DV33-10ZSXI 51-85087 44-pin TSOP II (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Temperature Range:
I = Industrial
Pb-free
Package Type: xxx = BV or BVJ or V or ZS
BV = 48-ball VFBGA Pinout - 1
BVJ = 48-ball VFBGA Pinout - 2
V = 44-pin (400-mil) Molded SOJ
ZS = 44-pin TSOP II
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
Process Technology: D = C9, 90 nm Technology
Data Width: 1 = Data width × 16-bits
Density: 04 = 4-Mbit density
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 V33 - 10 XXX704 1 D IX
Note
23. Pinout 1 is compliant with CY7C1041CV33 and pinout 2 is JEDEC compliant. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and
I/O[15:8] balls) are swapped.
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 13 of 18
Package Diagrams
Figure 12. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 14 of 18
Figure 13. 44-pin Molded SOJ (400-mil) V44.4 Package Outline, 51-85082
Figure 14. 44-pin TSOP Z44-II Package Outline, 51-85087
Package Diagrams (continued)
51-85082 *E
51-85087 *E
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 15 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
FBGA Fine-Pitch Ball Grid Array
I/O Input/Output
OE Output Enable
SOJ Small Outline J-lead
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
µA microampere
µs microsecond
mA milliampere
mm millimeter
ns nanosecond
pF picofarad
Vvolt
Wwatt
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 16 of 18
Document History Page
Document Title: CY7C1041DV33, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05473
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 201560 SWI See ECN Advance Data sheet for C9 IPP
*A 233729 RKF See ECN 1.AC, DC parameters are modified as per EROS(Spec # 01-2165)
2.Pb-free offering in the ‘Ordering information’
*B 351117 PCI See ECN Changed from Advance to Preliminary
Removed 15 and 20 ns Speed bin
Corrected DC voltage (min) value in maximum ratings section from - 0.5 to
- 0.3V
Redefined ICC values for Com’l and Ind’l temperature ranges
ICC (Com’l): Changed from 100, 80 and 67 mA to 90, 80 and 75 mA for 8, 10
and 12ns speed bins respectively
ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed
bins respectively
Added Static Discharge Voltage and latch-up current spec
Added VIH(max) spec in Note# 2
Changed Note# 4 on AC Test Loads
Changed reference voltage level for measurement of Hi-Z parameters from 500
mV to 200 mV
Added Data Retention Characteristics/Waveform and footnote # 11, 12
Added Write Cycle (WE Controlled, OE HIGH During Write) Timing Diagram
Changed Package Diagram name from 44-Pin TSOP II Z44 to 44-Pin TSOP II
ZS44 and from 44-Pin (400-mil) Molded SOJ V34 to 44-Pin (400-mil) Molded
SOJ V44
Changed part names from Z to ZS in the Ordering Information Table
Added 8 ns Product Information
Added Pin-Free Ordering Information
Shaded Ordering Information Table
*C 446328 NXR See ECN Converted from Preliminary to Final
Removed -8 speed bin
Removed Commercial Operating Range product information
Included Automotive Operating Range product information
Updated Thermal Resistance table
Updated footnote #8 on High-Z parameter measurement
Updated the ordering information and replaced Package Name column with
Package Diagram in the Ordering Information Table
CY7C1041DV33
Document Number: 38-05473 Rev. *O Page 17 of 18
*D 480177 VKN See ECN Added -10BVI product ordering code in the Ordering Information table
*E 2541850 VKN /
PYRS
07/22/08 Added -10BVJXI part
*F 2752971 VKN 08/18/2009 Added Automotive-A information
For 12 ns speed, changed ISB1 spec from 25 mA to 15 mA
For 12 ns speed, changed tDOE and tDBE specs from 6 ns to 7 ns
Updated ordering information table
*G 3034079 PRAS 09/20/2010 Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits
*H 3082285 HRP 11/09/2010 Corrected typo in Note 20.
*I 3149096 AJU 01/24/2011 No technical updates.
*J 3182129 HRP 03/02/2011 No technical updates.
*K 3271586 PRAS 06/01/2011 Updated Features (Dislodged automotive part information to 001-69789).
Updated Functional Description (Removed “For best practice
recommendations, refer to the Cypress application note AN1064, SRAM
System Guidelines.”).
Updated Selection Guide (Dislodged automotive part information to 001-69789).
Updated Operating Range (Dislodged automotive part information to
001-69789).
Updated DC Electrical Characteristics (Dislodged automotive part information
to 001-69789).
Updated AC Switching Characteristics (Dislodged automotive part information
to 001-69789).
Updated Data Retention Characteristics (Dislodged automotive part information
to 001-69789).
Updated Truth Table.
Updated Ordering Information (Dislodged automotive part information to
001-69789).
Updated to new template.
*L 3438781 TAVA 11/15/2011 Updated Package Diagrams.
*M 4170254 MEMJ 10/22/2013 Updated Package Diagrams:
spec 51-85150 – Changed revision from *G to *H.
spec 51-85082 – Changed revision from *D to *E.
spec 51-85087 – Changed revision from *D to *E.
Updated to new template.
*N 4578500 MEMJ 12/16/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated AC Switching Characteristics:
Updated Note 13.
*O 5514203 VINI 11/08/2016 Obsolete document.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY7C1041DV33, 4-Mbit (256K × 16) Static RAM
Document Number: 38-05473
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 38-05473 Rev. *O Revised November 8, 2016 Page 18 of 18
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY7C1041DV33
© Cypress Semiconductor Corporation, 2004-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive cypress.com/go/automotive
Clocks & Buffers cypress.com/go/clocks
Interface cypress.com/go/interface
Lighting & Power Control cypress.com/go/powerpsoc
cypress.com/go/plc
Memory cypress.com/go/memory
PSoC cypress.com/go/psoc
Touch Sensing cypress.com/go/touch
USB Controllers cypress.com/go/USB
Wireless/RF cypress.com/go/wireless
PSoC® Solutions
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
