Synchronous Buck Controller with
Constant On Time and Valley Current Mode
Data Sheet ADP1878/ADP1879
Rev. B Document Feedback
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FEATURES
Power input voltage range: 2.95 V to 20 V
On-board bias regulator
Minimum output voltage: 0.6 V
0.6 V reference voltage with ±1.0% accuracy
Supports all N-channel MOSFET power stages
Available in 300 kHz, 600 kHz, and 1.0 MHz options
No current sense resistor required
Power saving mode (PSM) for light loads (ADP1879 only)
Resistor programmable current limit
Power good with internal pull-up resistor
Externally programmable soft start
Thermal overload protection
Short-circuit protection
Standalone precision enable input
Integrated bootstrap diode for high-side drive
Starts into a precharged output
Available in a 14-lead LFCSP_WD package
APPLICATIONS
Telecommunications and networking systems
Mid-to-high end servers
Set-top boxes
DSP core power supplies
TYPICAL APPLICATIONS CIRCUIT
Figure 1.
GENERAL DESCRIPTION
The ADP1878/ADP1879 are versatile current-mode, synchronous
step-down controllers. They provide superior transient response,
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current-limit,
current control scheme. These devices offer optimum performance
at low duty cycles by using a valley, current-mode control architec-
ture allowing the ADP1878/ADP1879 to drive all N-channel power
stages to regulate output voltages to as low as 0.6 V.
The ADP1879 is the power saving mode (PSM) version of the
device and is capable of pulse skipping to maintain output
regulation while achieving improved system efficiency at light
loads (see the ADP1879 Power Saving Mode (PSM) section for
more information).
Available in three frequency options (300 kHz, 600 kHz, and
1.0 MHz) plus the PSM option, the ADP1878/ADP1879 are well
suited for a wide range of applications that require a single input
power supply range from 2.95 V to 20 V. Low voltage biasing is
supplied via a 5 V internal low dropout regulator (LDO). In
addition, soft start programmability is included to limit input
inrush current from the input supply during startup and to
provide reverse current protection during precharged output
conditions. The low-side current sense, current gain scheme and
integration of a boost diode, together with the PSM/forced
pulse-width modulation (PWM) option, reduce the external
device count and improve efficiency.
The ADP1878/ADP1879 operate over the −40°C to +125°C
junction temperature range and are available in a 14-lead
LFCSP_WD package.
Figure 2. ADP1878/ADP1879 Efficiency vs. Load Current (VOUT = 1.8 V, 300 kHz)
COMP BST
FB
DRVH
GND
SW
VREG
RES
DRVL
SS C
SS
PGND
VIN
C
C
C
VREG
C
VREG2
C
C2
R
C
R
BOT
R
TOP
V
OUT
EN
10k
V
REG
Q1
Q2
L
C
OUT
V
OUT
C
BST
LOAD
C
IN
V
IN
= 2.95V TO 20
V
ADP1878/
ADP1879
R
RES
PGOOD R
PGD
V
EXT
09441-001
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
10 100 1k 10k 100k
EFFICIENCY (%)
LOAD CURRENT (mA)
T
A
= 25°C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTOR:
744325120, L = 1.2µH, DCR = 1.8m
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
V
IN
= 5V (PSM)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-102
ADP1878/ADP1879 Data Sheet
Rev. B | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Applications Circuit ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ....................................................... 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 17
Block Diagram ............................................................................ 17
Startup .......................................................................................... 18
Soft Start ...................................................................................... 18
Precision Enable Circuitry ........................................................ 18
Undervoltage Lockout ............................................................... 18
On-Board Low Dropout (LDO) Regulator ............................. 18
Thermal Shutdown ..................................................................... 19
Programming Resistor (RES) Detect Circuit .......................... 19
Valley Current-Limit Setting .................................................... 19
Hiccup Mode During Short Circuit ......................................... 21
Synchronous Rectifier ................................................................ 21
ADP1879 Power Saving Mode (PSM) ...................................... 21
Timer Operation ......................................................................... 22
Pseudo Fixed Frequency............................................................ 22
Power-Good Monitoring ........................................................... 23
Applications Information .............................................................. 24
Feedback Resistor Divider ........................................................ 24
Inductor Selection ...................................................................... 24
Output Ripple Voltage (ΔVRR) .................................................. 24
Output Capacitor Selection....................................................... 24
Compensation Network ............................................................ 25
Efficiency Consideration ........................................................... 26
Input Capacitor Selection .......................................................... 27
Thermal Considerations ............................................................ 27
Design Example .......................................................................... 29
External Component Recommendations .................................... 31
Layout Considerations ................................................................... 33
IC Section (Left Side of Evaluation Board) ............................. 35
Power Section ............................................................................. 35
Differential Sensing .................................................................... 36
Typical Application Circuits ......................................................... 37
12 A, 300 kHz High Current Application Circuit .................. 37
5.5 V Input, 600 kHz Current Application Circuit ................ 37
300 kHz High Current Application Circuit ............................ 38
Packaging and Ordering Information ......................................... 39
Outline Dimensions ................................................................... 39
Ordering Guide .......................................................................... 40
REVISION HISTORY
9/12—Rev. A to Rev. B
Changes to Table 7 ........................................................................... 20
6/12—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................. 3
7/11—Revision 0: Initial Version
Data Sheet ADP1878/ADP1879
Rev. B | Page 3 of 40
SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). VREG = 5 V,
BST − SW = VREG − VRECT_DROP (see Figure 40 to Figure 42). VIN = 12 V. The specifications are valid for TJ = −40°C to +125°C,
unless otherwise specified.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY CHARACTERISTICS
High Input Voltage Range VIN C
VIN
= 22 µF(25 V rating) right at Pin 1 to PGND (Pin 11)
ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.95 12 20 V
ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.95 12 20 V
ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.25 12 20 V
Quiescent Current IQ_REG +
I
Q_BST
FB = 1.5 V, no switching 1.1 mA
Shutdown Current IREG,SD +
I
BST,SD
EN < 600 mV 140 225 µA
Undervoltage Lockout UVLO Rising VIN (see Figure 35 for temperature variation) 2.65 V
UVLO Hysteresis Falling VIN from operational state 178 mV
INTERNAL REGULATOR
CHARACTERISTICS
Do not load VREG externally because it is intended to
bias internal circuitry only
VREG Operational Output Voltage
VREG
CVREG = 4.7 µF to PGND, 0.22 µF to GND, VIN = 2.95 V to 20 V
ADP1878ACPZ-0.3-R7/ADP1879ACPZ-0.3-R7 (300 kHz) 2.75 5 5.5 V
ADP1878ACPZ-0.6-R7/ADP1879ACPZ-0.6-R7 (600 kHz) 2.75 5 5.5 V
ADP1878ACPZ-1.0-R7/ADP1879ACPZ-1.0-R7 (1.0 MHz) 3.05 5 5.5 V
VREG Output in Regulation V
IN
= 7 V, 100 mA 4.82 4.981 5.16 V
V
IN
= 12 V, 100 mA 4.83 4.982 5.16 V
Load Regulation 0 mA to 100 mA, V
IN
= 7 V 32 mV
0 mA to 100 mA, V
IN
= 20 V 34 mV
Line Regulation V
IN
= 7 V to 20 V, 20 mA 1.8 mV
V
IN
= 7 V to 20 V, 100 mA 2.0 mV
VIN to VREG Dropout Voltage 100 mA out of VREG, V
IN
≤ 5 V 306 415 mV
Short VREG to PGND V
IN
= 20 V 229 320 mA
SOFT START Connect external capacitor from SS pin to GND,
Soft Start Period Calculation C
SS
= 10 nF/ms 10 nF/ms
ERROR AMPLIFER
FB Regulation Voltage V
FB
T
J
= 25°C 600 mV
T
J
= −40°C to +85°C 596 600 604 mV
T
J
= −40°C to +125°C 594.2 600 605.8 mV
Transconductance G
m
320 496 670 µS
FB Input Leakage Current I
FB, LEAK
FB = 0.6 V, EN = VREG 1 50 nA
CURRENT SENSE AMPLIFIER GAIN
Programming Resistor (RES)
Value from RES to PGND
RES = 47 kΩ ± 1% 2.7 3 3.3 V/V
RES = 22 kΩ ± 1% 5.5 6 6.5 V/V
RES = none 11 12 13 V/V
RES = 100 kΩ ± 1%
22
24
26
V/V
SWITCHING FREQUENCY Typical values measured at 50% time points with 0 nF at
DRVH and DRVL; maximum values are guaranteed by
bench evaluation1
ADP1878ACPZ-0.3-R7/
ADP1879ACPZ-0.3-R7
300 kHz
On Time V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C 1120 1200 1345 ns
Minimum On Time V
IN
= 20 V 145 190 ns
Minimum Off Time 84% duty cycle (maximum) 340 400 ns
ADP1878/ADP1879 Data Sheet
Rev. B | Page 4 of 40
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
ADP1878ACPZ-0.6-R7/
ADP1879ACPZ-0.6-R7
600 kHz
On Time V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C 500 540 605 ns
Minimum On Time V
IN
= 20 V, V
OUT
= 0.8 V 82 110 ns
Minimum Off Time 65% duty cycle (maximum) 340 400 ns
ADP1878ACPZ-1.0-R7/
ADP1879ACPZ-1.0-R7
1.0 MHz
On Time V
IN
= 5 V, V
OUT
= 2 V, T
J
= 25°C 285 312 360 ns
Minimum On Time V
IN
= 20 V 52 85 ns
Minimum Off Time 45% duty cycle (maximum) 340 400 ns
OUTPUT DRIVER CHARACTERISTICS
High-Side Driver
Output Source Resistance I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 2.20 3 Ω
Output Sink Resistance I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.72 1 Ω
Rise Time2 t
r, DRVH
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 59) 25 ns
Fall Time2 t
f, DRVH
BST − SW = 4.4 V, C
IN
= 4.3 nF (see Figure 60) 11 ns
Low-Side Driver
Output Source Resistance I
SOURCE
= 1.5 A, 100 ns, positive pulse (0 V to 5 V) 1.5 2.2 Ω
Output Sink Resistance I
SINK
= 1.5 A, 100 ns, negative pulse (5 V to 0 V) 0.7 1 Ω
Rise Time2 t
r,DRVL
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 60) 18 ns
Fall Time2 t
f,DRVL
V
REG
= 5.0 V, C
IN
= 4.3 nF (see Figure 59) 16 ns
Propagation Delays
DRVL Fall to DRVH Rise
2
t
tpdhDRVH
BST − SW = 4.4 V (see Figure 59) 15.7 ns
DRVH Fall to DRVL Rise
2
t
tpdhDRVL
BST − SW = 4.4 V (see Figure 60) 16 ns
SW Leakage Current I
SWLEAK
BST = 25 V, SW = 20 V, V
REG
= 5 V 110 µA
Integrated Rectifier
Channel Impedance I
SINK
= 10 mA 22.3 Ω
PRECISION ENABLE THRESHOLD
Logic High Level V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V 605 634 663 mV
Enable Hysteresis V
IN
= 2.9 V to 20 V, V
REG
= 2.75 V to 5.5 V 31 mV
COMP VOLTAGE
COMP Clamp Low Voltage VCOMP(LOW) Tie EN pin to VREG to enable device
(2.75 V ≤ V
REG
≤ 5.5 V)
0.47 V
COMP Clamp High Voltage V
COMP(HIGH)
(2.75 V ≤ V
REG
≤ 5.5 V) 2.55 V
COMP Zero Current Threshold V
COMP_ZCT
(2.75 V ≤ V
REG
≤ 5.5 V) 1.10 V
THERMAL SHUTDOWN T
TMSD
Thermal Shutdown Threshold Rising temperature 155 °C
Thermal Shutdown Hysteresis 15 °C
CURRENT LIMIT
Hiccup Current-Limit Timing COMP = 2.4 V 6 ms
OVERVOLTAGE AND POWER-
GOOD THRESHOLDS
PGOOD
FB Power-Good Threshold FB
PGD
V
FB
rising during system power up 542 566 mV
FB Power-Good Hysteresis 34 55 mV
FB Overvoltage Threshold FB
OV
V
FB
rising during overvoltage event, I
PGOOD
= 1 mA 691 710 mV
FB Overvoltage Hysteresis 35 55 mV
PGOOD Low Voltage During Sink V
PGOOD
I
PGOOD
= 1 mA 143 200 mV
PGOOD Leakage Current PGOOD = 5 V 1 100 nA
1 The maximum specified values are with the closed loop measured at 10% to 90% time points (see Figure 59 and Figure 60), CGATE = 4.3 nF, and the high- and low-side
MOSFETs being Infineon BSC042N03MS G.
2 Not automatic test equipment (ATE) tested.
Data Sheet ADP1878/ADP1879
Rev. B | Page 5 of 40
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VREG to PGND, GND −0.3 V to +6 V
VIN, EN, PGOOD to PGND −0.3 V to +28 V
FB, COMP, RES, SS to GND −0.3 V to (VREG + 0.3 V)
DRVL to PGND −0.3 V to (VREG + 0.3 V)
SW to PGND −2.0 V to +28 V
BST to SW −0.6 V to (VREG + 0.3 V)
BST to PGND −0.3 V to +28 V
DRVH to SW −0.3 V to VREG
PGND to GND ±0.3 V
PGOOD Input Current 35 mA
θJA (14-Lead LFCSP_WD)
4-Layer Board 30°C/W
Operating Junction Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Soldering Conditions JEDEC J-STD-020
Maximum Soldering Lead Temperature
(10 sec)
300°C
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified, all other voltages are
referenced to PGND.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Boundary Condition
In determining the values given in Table 2 and Table 3, natural
convection is used to transfer heat to a 4-layer evaluation board.
Table 3. Thermal Resistance
Package Type θJA Unit
θJA (14-Lead LFCSP_WD)
4-Layer Board 30 °C/W
ESD CAUTION
Stresses abo
v
e those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
de
v
ice reliability.
ADP1878/ADP1879 Data Sheet
Rev. B | Page 6 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin
No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET.
2 COMP Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see
the Compensation Network section).
3 EN IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC.
4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected.
5 GND Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout
Considerations section).
6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5).
7 VREG Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers).
Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are
recommended.
8 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value
of 10 nF for every 1 ms of soft start delay.
9 PGOOD Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown.
Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used.
10 DRVL Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin
(see Figure 69).
11 PGND Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET.
12 DRVH Drive Output for the External High-Side N-Channel MOSFET.
13 SW Switch Node Connection.
14 BST Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected
between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected
between VREG and BST for increased gate drive capability.
EP Exposed Pad. Connect the exposed pad to the analog ground pin (GND).
TOP VIEW
(Not to Scale)
09441-003
14
13
12
11
10
9
8
6
5
4
2
3
1
7
VIN
COMP
EN
FB
GND
RES
VREG
BST
SW
DRVH
PGND
DRVL
PGOOD
SS
ADP1878
/
A
DP1879
NOTES
1. CONNECT THE EXPOSED PAD TO THE
ANALOG GRO UND P IN (GND).
Data Sheet ADP1878/ADP1879
Rev. B | Page 7 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Efficiency—300 kHz, VOUT = 0.8 V
Figure 5. Efficiency—300 kHz, VOUT = 1.8 V
Figure 6. Efficiency—300 kHz, VOUT = 7 V
Figure 7. Efficiency—600 kHz, VOUT = 0.8 V
Figure 8. Efficiency—600 kHz, VOUT = 1.8 V
Figure 9. Efficiency—600 kHz, VOUT = 5 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 0.8V
f
SW
= 300kHz
WÜRTH INDUCTO R:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-004
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 1.8V
f
SW
= 300kHz
WÜRTH INDUCTO R:
744325120, L = 1.2µH, DCR = 1.8mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 5V (PSM)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-005
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 7V
f
SW
= 300kHz
WÜRTH INDUCTO R:
7443551200, L = 2.0µH, DCR = 2.6mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-006
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 0.8V
f
SW
= 600kHz
WÜRTH INDUCTO R:
744355147, L = 0.47µH, DCR = 0.67mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 13V (PSM)
V
IN
= 16.5V
(PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-007
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 1.8V
f
SW
= 600kHz
WÜRTH INDUCTO R:
744325072, L = 0.72µH, DCR = 1.3mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-008
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
010 100 1k 10k 100k
EF FICIENCY ( %)
LOAD CURRENT ( mA)
T
A
= 25° C
V
OUT
= 5V
f
SW
= 600kHz
WÜRTH INDUCTO R:
744318180, L = 1.4µH, DCR = 3.2mΩ
INFINEON FETs:
BSC042N03MS G (UPP E R/L OWE R)
V
IN
= 20V (PSM)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 20V
V
IN
= 16.5V
09441-009
ADP1878/ADP1879 Data Sheet
Rev. B | Page 8 of 40
Figure 10. Efficiency—1.0 MHz, VOUT = 0.8 V
Figure 11. Efficiency—1.0 MHz, VOUT = 1.8 V
Figure 12. Efficiency—1.0 MHz, VOUT = 5 V
Figure 13. Output Voltage Accuracy—300 kHz, VOUT = 0.8 V
Figure 14. Output Voltage Accuracy—300 kHz, VOUT = 1.8 V
Figure 15. Output Voltage Accuracy—300 kHz, VOUT = 7 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10 100 1k 10k 100k
EFFICIENCY (%)
LOAD CURRENT (mA)
T
A
= 25°C
V
OUT
= 0.8V
f
SW
= 1.0MHz
WÜRTH INDUCTOR:
744303012, L = 0.12µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
V
IN
= 13V (PSM)
V
IN
= 16.5V (PSM)
V
IN
= 13V
V
IN
= 16.5V
09441-010
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10 100 1k 10k 100k
EFFICIENCY (%)
LOAD CURRENT (mA)
TA = 25°C
VOUT = 1.8V
f
SW = 1.0MHz
WÜRTH INDUCTOR:
744303022, L = 0.22µH, DCR = 0.33mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
VIN = 13V (PSM)
VIN = 16.5V (PSM)
VIN = 13V
VIN = 16.5V
09441-011
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
10 100 1k 10k 100k
EFFICIENCY (%)
LOAD CURRENT (mA)
TA = 25°C
VOUT = 5V
f
SW = 1.0MHz
WÜRTH INDUCTOR:
744355090, L = 0.9µH, DCR = 1.6mΩ
INFINEON FETs:
BSC042N03MS G (UPPER/LOWER)
VIN = 13V (PSM)
VIN = 16.5V (PSM) VIN = 13V
VIN = 16.5V
09441-012
0.807
0.806
0.805
0.804
0.803
0.802
0.801
0.800
0.799
0.798
0.797
0.796
0.795
0.794
0.793
0.792
0 2000 4000 6000 8000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 13V
+125°C
+25°C
–40°C
V
IN
= 16.5V
09441-013
1.821
1.816
1.811
1.806
1.801
1.796
1.791
1.786
0 1500 3000 4500 6000 7500 9000 10,500 12,000 13,500 15,000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 5.5V
+125°C
+25°C
–40°C
V
IN
= 13V
+125°C
+25°C
–40°C
V
IN
= 16.5V
09441-014
7.100
7.095
7.090
7.085
7.080
7.075
7.070
7.065
7.060
7.055
7.050
7.045
7.040
7.035
7.030
7.025
7.020
7.015
7.010
7.005
7.000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
+125°C
+25°C
–40°C
V
IN
= 13V
V
IN
= 16.5V
09441-015
Data Sheet ADP1878/ADP1879
Rev. B | Page 9 of 40
Figure 16. Output Voltage Accuracy—600 kHz, VOUT = 0.8 V
Figure 17. Output Voltage Accuracy—600 kHz, VOUT = 1.8 V
Figure 18. Output Voltage Accuracy—600 kHz, VOUT = 5 V
Figure 19. Output Voltage Accuracy—1.0 MHz, VOUT = 0.8 V
Figure 20. Output Voltage Accuracy—1.0 MHz, VOUT = 1.8 V
Figure 21. Output Voltage Accuracy—1.0 MHz, VOUT = 5 V
0.808
0.792
0.794
0.796
0.798
0.800
0.802
0.804
0.806
0 1000 2000 3000 4000 5000 6000 7000 8000 10,0009000
FRE QUENCY (kHz)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V
V
IN
= 16.5V
09441-016
1.818
1.770
1.772
1.774
1.776
1.778
1.780
1.782
1.784
1.786
1.788
1.790
1.792
1.794
1.796
1.798
1.800
1.802
1.804
1.806
1.808
1.810
1.812
1.814
1.816
0 12,00010,500900075006000450030001500
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09441-017
5.030
5.025
5.005
5.010
5.015
5.020
5.000
4.995
4.990
4.985
4.980
4.975
4.970 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V
V
IN
= 16. 5 V
V
IN
= 20V
09441-018
0 2000 4000 6000 8000 10,000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
0.787
0.789
0.791
0.793
0.795
0.797
0.799
0.801
0.803
0.805
0.807
09441-019
1.820
1.815
1.810
1.805
1.800
1.795
1.790
0
10,0000 1000 2000 3000 4000 5000 6000 7000 8000 9000
OUTPUT VOLTAGE (V)
LOAD CURRENT ( mA)
+125°C
+25°C
–40°C
V
IN
= 13V +125°C
+25°C
–40°C
V
IN
= 16.5V
09441-020
7200640056004800400024001600 32000 960088008000800
5.04
4.90
4.91
4.92
4.93
4.94
4.95
4.96
4.97
4.98
4.99
5.00
5.01
5.02
5.03
OUTPUT VOLTAGE (V)
LO AD CURRENT (mA)
+125°C
+25°C
–40°C
VIN = 13V +125°C
+25°C
–40°C
VIN = 16. 5V
09441-021
ADP1878/ADP1879 Data Sheet
Rev. B | Page 10 of 40
Figure 22. Feedback Voltage vs. Temperature
Figure 23. Switching Frequency vs. High Input Voltage, 300 kHz, ±10% of 12 V
Figure 24. Switching Frequency vs. High Input Voltage, 600 kHz, VOUT = 1.8 V,
VIN Range = 13 V to 16.5 V
Figure 25. Switching Frequency vs. High Input Voltage, 1.0 MHz,
VIN Range = 13 V to 16.5 V
Figure 26. Frequency vs. Load Current, 300 kHz, VOUT = 0.8 V
Figure 27. Frequency vs. Load Current, 300 kHz, VOUT = 1.8 V
601.0
600.5
600.0
599.5
599.0
598.5
598.0
597.5
597.0
–40.0 –7.5 25.0 57.5 90.0 122.5
FEE DBACK V O L T AGE (V )
TE M P ERATURE (°C)
V
REG
= 5V, V
IN
= 13V
V
REG
= 5V, V
IN
= 20V
09441-022
325
315
305
295
285
275
265
255
10.8 11.0 11.2 11.4 11.6 11.8 12.0 12.2 12.4 12.6 12.8 13.0 13.2
SWITCHING FREQUENCY (kHz)
VIN (V)
+125°C
+25°C
–40°C
NO LOAD
09441-023
650
600
550
500
450
400
13.0 13.4 13.8 14.2 14.6 15.0 15.4 15.8 16.2
SWITCHING FREQUENCY (kHz)
V
IN
(V)
+125°C
+25°C
–40°C
NO L OAD
09441-024
900
880
860
840
820
800
780
760
740
720
700
13.0 13.5 14.0 14.5 15.0 15.5 16.0 16.5
SWITCHING FREQUENCY (kHz)
V
IN
(V)
+125°C
+25°C
–40°C
09441-025
280
190
205
220
235
250
265
0 10,0008000600040002000
FRE QUENCY (kHz)
LOAD CURRENT (mA)
V
IN
= 13V
V
IN
= 20V
V
IN
= 16.5V
+125°C
+25°C
–40°C
09441-026
330
240
250
260
270
280
290
300
310
320
015,00012,000 13,50010,500900075006000450030001500
FRE QUENCY (kHz)
LOAD CURRENT (mA)
V
IN
= 20V
V
IN
= 13V
V
IN
= 16.5 V
+125°C
+25°C
–40°C
09441-027
Data Sheet ADP1878/ADP1879
Rev. B | Page 11 of 40
Figure 28. Frequency vs. Load Current, 300 kHz, VOUT = 7 V
Figure 29. Frequency vs. Load Current, 600 kHz, VOUT = 0.8 V
Figure 30. Frequency vs. Load Current, 600 kHz, VOUT = 1.8 V
Figure 31. Frequency vs. Load Current, 600 kHz, VOUT = 5 V
Figure 32. Frequency vs. Load Current, VOUT = 1.0 MHz, 0.8 V
Figure 33. Frequency vs. Load Current, 1.0 MHz, VOUT = 1.8 V
338
298
302
306
310
314
318
322
326
330
334
0 6400 7200 8000 8800560048004000320024001600800
FRE QUENCY (kHz)
LO AD CURRENT ( mA)
V
IN
= 13V
V
IN
= 16.5V +125°C
+25°C
–40°C
09441-028
300
330
360
390
420
450
480
510
540
012,0001200 2400 3600 4800 6000 7200 8400 9600 10,800
FREQ UE NCY ( kHz)
LO AD CURRENT (mA)
V
IN
= 16. 5V
V
IN
= 13V +125°C
+25°C
–40°C
09441-029
675
495
515
535
555
575
595
615
635
655
0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
FRE QUENCY (kHz)
LOAD CURRENT (mA)
V
IN
= 16.5V
V
IN
= 13V
+125°C
+25°C
–40°C
09441-030
740
621
628
635
642
649
656
663
670
677
684
691
698
705
712
719
726
733
096008800800072006400560048004000320024001600800
FRE QUENCY (kHz)
LOAD CURRENT (mA)
V
IN
= 13V
V
IN
= 16. 5V +125°C
+25°C
–40°C
09441-031
850
775
700
625
550
475
400 0 12,00010,0008000600040002000
FRE QUENCY (kHz)
LOAD CURRENT (m A)
V
IN
= 16. 5V
V
IN
= 13V +125°C
+25°C
–40°C
09441-032
550
625
700
775
850
925
1000
1075
1150
1225
012,0009600 10,8008400720060004800360024001200
FRE QUENCY (kHz)
LO AD CURRENT (mA)
V
IN
= 16. 5V
V
IN
= 13V +125°C
+25°C
–40°C
09441-033
ADP1878/ADP1879 Data Sheet
Rev. B | Page 12 of 40
Figure 34. Frequency vs. Load Current, 1.0 MHz, VOUT = 5 V
Figure 35. UVLO vs. Temperature
Figure 36. Maximum Duty Cycle vs. Frequency
Figure 37. Maximum Duty Cycle vs. High Voltage Input (VIN)
Figure 38. Minimum Off Time vs. Temperature
Figure 39. Minimum Off Time vs. VREG (Low Input Voltage)
1000
1450
1400
1350
1300
1250
1200
1150
1100
1050
0 8000800 1600 2400 3200 4000 4800 5600 6400 7200
FRE QUENCY (kHz)
LO AD CURRENT (mA)
V
IN
= 16. 5 V
V
IN
= 13V +125°C
+25°C
–40°C
09441-034
2.649
2.658
2.657
2.656
2.655
2.654
2.653
2.652
2.651
2.650
–40 120100806040200–20
UVLO (V )
TEM P ERATURE (°C)
09441-035
55
60
65
70
75
80
85
90
95
300 400 500 600 700 800 900 1000
MAXIMUM DUTY CYCLE ( %)
FRE QUENCY ( kHz )
+125°C
+25°C
–40°C
09441-036
62
64
66
68
70
72
74
76
78
80
82
5.5 6.7 7.9 9.1 10.3 11.5 12.7 13.9 15.1 16.3
MAXIMUM DUTY CYCLE (%)
V
IN
(V)
+125°C
+25°C
–40°C
09441-037
180
680
630
580
530
480
430
380
330
280
230
–40 120100806040200–20
MINiMUM OFF T I ME (n s)
TEMP E RATUR E ( °C)
V
REG
= 2.7V
V
REG
= 5.5V
V
REG
= 3.6V
09441-038
180
680
630
580
530
480
430
380
330
280
230
2.7 5.55.14.74.33.93.53.1
MINIMUM OFF TIME (ns)
VREG (V)
+125°C
+25°C
–40°C
09441-039
Data Sheet ADP1878/ADP1879
Rev. B | Page 13 of 40
Figure 40. Internal Rectifier Drop vs. Frequency
Figure 41. Internal Boost Rectifier Drop vs. VREG (Low Input Voltage)
Over VIN Variation
Figure 42. Internal Boost Rectifier Drop vs. VREG
Figure 43. Low-Side MOSFET Body Diode Conduction Time vs. VREG
Figure 44. Power Saving Mode (PSM) Operational Waveform, 100 mA
Figure 45. PSM Waveform at Light Load, 500 mA
80
800
720
640
560
480
400
320
240
160
300 400 500 600 700 800 900 1000
RECTIFIER DROP (mV)
FREQUENCY (kHz)
V
REG
= 2.7V
V
REG
= 5.5V
V
REG
= 3.6V
+125°C
+25°C
–40°C
09441-040
80
1280
720
640
560
480
1040
1120
1200
960
880
800
400
320
240
160
2.73.13.53.94.34.75.15.5
RECTIFIER DROP (mV)
V
REG
(V)
V
IN
= 5.5V
V
IN
= 16.5V
V
IN
= 13V
1MHz
300kHz T
A
= 25°C
09441-041
80
720
640
560
480
400
320
240
160
2.73.13.53.94.34.75.15.5
RECTIFIER DROP (mV)
V
REG
(V)
1MHz
300kHz +125°C
+25°C
–40°C
09441-042
8
80
64
72
56
48
40
32
24
16
2.73.13.53.94.34.75.15.5
BODY DIODE CONDUCTION TIME (ns)
V
REG
(V)
1MHz
300kHz +125°C
+25°C
–40°C
09441-043
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V
M400ns A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
SW NODE
LOW SIDE
09441-044
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V
M4.0µs A CH2 3.90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRENT
SW NODE
LOW SIDE
09441-045
ADP1878/ADP1879 Data Sheet
Rev. B | Page 14 of 40
Figure 46. CCM Operation at Heavy Load, 12 A
(See Figure 95 for Application Circuit)
Figure 47. Load Transient Step—PSM Enabled, 12 A
(See Figure 95 Application Circuit)
Figure 48. Positive Step During Heavy Load Transient Behavior—PSM Enabled,
12 A, VOUT = 1.8 V (See Figure 95 Application Circuit)
Figure 49. Negative Step During Heavy Load Transient Behavior—PSM Enabled,
12 A (See Figure 95 Application Circuit)
Figure 50. Load Transient Step—Forced PWM at Light Load, 12 A
(See Figure 95 Application Circuit)
Figure 51. Positive Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A, VOUT = 1.8 V (See Figure 95 Application Circuit)
CH1 5A Ω
CH3 10V CH4 100mV
BW
M400ns A CH3 2.20V
T 30.6%
1
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
09441-046
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M2ms A CH1 3.40A
T 75.6%
1
2
3
4
OUTPUT VOLTAGE
12A ST E P
SW NODE
LOW SIDE
09441-047
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 30.6%
1
2
3
4
OUTPUT VOLTAGE
12A POSI T I VE ST EP
SW NODE
LOW SIDE
09441-048
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M20µs A CH1 3.40A
T 48.2%
1
2
3
4
OUTPUT VOLTAGE
12A NEG ATIV E S TEP
SW NODE
LOW SIDE
09441-049
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV
BW
M2ms A CH1 6. 20A
T 15.6%
1
2
3
4
OUTPUT VOLTAGE
12A ST E P
SW NODE
LOW SIDE
09441-050
CH1 10A Ω CH2 5V
CH3 20V CH4 200mV
BW
M20µs A CH1 6.20A
T 43.8%
1
2
3
4
OUTPUT VOLTAGE
12A POSI T I VE ST EP
SW NODE
LOW SIDE
09441-051
Data Sheet ADP1878/ADP1879
Rev. B | Page 15 of 40
Figure 52. Negative Step During Heavy Load Transient Behavior—Forced PWM
at Light Load, 12 A (See Figure 95 Application Circuit)
Figure 53. Output Short-Circuit Behavior Leading to Hiccup Mode
Figure 54. Magnified Waveform During Hiccup Mode
Figure 55. Start-Up Behavior at Heavy Load, 12 A, 300 kHz
(See Figure 95 Application Circuit)
Figure 56. Power-Down Waveform During Heavy Load
Figure 57. Output Voltage Ripple Waveform During PSM Operation
at Light Load, 2 A
CH1 10A Ω CH2 200mV
BW
CH3 20V CH4 5V M10µs A CH1 5.60A
T 23.8%
1
2
3
4
OUTPUT VOLTAGE
12A NEG ATIV E S TEP
SW NODE
LOW
SIDE
09441-052
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 920mV
T 49.4%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09441-053
CH1 5V
BW
CH2 10A Ω
CH3 10V CH4 5V M10µs A CH2 8.20A
T 36.2%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09441-054
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M2ms A CH1 720mV
T 32.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09441-055
CH1 2V
BW
CH2 5A Ω
CH3 10V CH4 5V M4ms A CH1 720mV
T 41.6%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09441-056
CH1 50mV
BW
CH2 5A Ω
CH3 10V
BW
CH4 5V M2µs A CH2 3. 90A
T 35.8%
1
2
3
4
OUTPUT VOLTAGE
INDUCTOR CURRE NT
SW NODE
LOW SIDE
09441-057
ADP1878/ADP1879 Data Sheet
Rev. B | Page 16 of 40
Figure 58. Output Drivers and SW Node Waveforms
Figure 59. High-Side Driver Rising and Low-Side Falling Edge Waveforms (CIN =
4.3 nF (High-/Low-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Figure 60. High-Side Driver Falling and Low-Side Rising Edge Waveforms (CIN =
4.3 nF (High-/Low-Side MOSFET), QTOTAL = 27 nC (VGS = 4.4 V (Q1), VGS = 5 V (Q3))
Figure 61. Transconductance vs. Temperature
Figure 62. Transconductance vs. VREG
Figure 63. Quiescent Current vs. VREG
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIGH SI DE
HS MINUS
SW
SW NODE
LOW SIDE T
A
= 25°C
09441-058
2
CH2 5V
CH3 5V
MAT H 2V 40ns CH4 2V M40ns A CH2 4.20V
T 29.0%
3
M
4
HIG H S IDE
HS MINUS
SW
SW NODE
LOW SIDE 16ns (
t
f
,DRVL
)
25ns (
t
r
,DRVH
)
22ns (
t
pdh
DRVH
)
T
A
= 25°C
09441-059
2
CH2 5V
CH3 5V
MAT H 2V 20ns CH4 2V M20ns A CH2 4. 20V
T 39.2%
3
M
4
HIG H SIDE
HS MI NUS
SW SW NODE
LOW SIDE
18ns (
t
r
,DRVL
)
24ns (
t
pdh
,DRVL
)
11ns (
t
f
,DRVH
)
T
A
= 25° C
09441-060
570
550
530
510
490
470
450
430
–40 –20 120100806040200
TRANSCONDUCTANCE (µS)
TEM P ERATURE (°C)
V
REG
= 5.5V
V
REG
= 3.6V
V
REG
= 2.7V
09441-061
680
330
380
430
480
530
580
630
2.7 3.0 5.44.8 5.14.54.23.93.63.3
TRANSCO NDUCT ANCE ( µS)
V
REG
(V)
+125°C
+25°C
–40°C
09441-062
1.30
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.702.7 5.55.14.74.3
–40°C
+25°C
+125°C
3.93.53.1
QUIESCENT CURRENT (mA)
V
REG
(V)
09441-063
Data Sheet ADP1878/ADP1879
Rev. B | Page 17 of 40
THEORY OF OPERATION
BLOCK DIAGRAM
Figure 64. ADP1878/ADP1879 Block Diagram
The ADP1878/ADP1879 are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current
sense gain, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current-
mode control architecture. This allows the ADP1878/ADP1879
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
09441-064
DRVH
GND
IREV
COMP
ADP1878/ADP1879
C
R (TRIMMED)
VREG
tON
TIMER
tON
= 2RC(V
OUT
/V
IN
)
I
SW
INFORMATION
SW FILTER
STATE
MACHINE
TON
BG_REF
IN_PSM
IN_SS
PWM
COMP
HS_0
HS
SW
LS
LS_0
IREV
LEVEL
SHIFT HS
VREG
LS
VREG
300kΩ
800kΩ
8kΩ
SW
DRVL
PGND
BST
VIN
PSM
REF_ZERO
IN_HICCUP
SS
COMP
ERROR
AMP
SS_REF
0.6V
LOWER
COMP
CLAMP
REF_ZERO
CS
AMP
PWM
FB
COMP
VREG
I
SS
SS
0.4V
ADC RES DE TECT AND
GAIN SET
CS G AIN SET
BIAS BLOCK
AND REF E RE NCE
REF
LDO
PRECISION
ENABLE
630mV
TO ENABL E
ALL BLOCKS
EN
RES
530mV
690mV
FB
600mV
PGOOD
THRESHOLD/
HYSTERESIS
ADP1878/ADP1879 Data Sheet
Rev. B | Page 18 of 40
STARTUP
Each ADP1878/ADP1879 has an internal regulator (VREG)
for biasing and supplying power for the integrated N-channel
MOSFET drivers. Place a bypass capacitor directly across the
VREG (Pin 7) and PGND (Pin 13) pins. Included in the power-
up sequence is the biasing of the current sense amplifier, the
current sense gain circuit (see the Programming Resistor (RES)
Detect Circuit section), the soft start circuit, and the error
amplifier.
The current sense blocks provide valley current information
(see the Programming Resistor (RES) Detect Circuit section)
and they are a variable of the compensation equation for loop
stability (see the Compensation Network section). In a process
performed by the RES detect circuit, the valley current informa-
tion is extracted by forcing 0.4 V across the RES and PGND pins
generating current. The current through the RES resistor is used
to set the current sense amplifier gain (see the Programming
Resistor (RES) Detect Circuit section). This process takes approx-
imately 800 µs, after which time the drive signal pulses appear at
the DRVL and DRVH pins synchronously, and the output voltage
begins to rise in a controlled manner through the soft start
sequence.
The soft start and error amplifier blocks determine the rise time
of the output voltage (see the Soft Start section). At the beginning
of a soft start, the error amplifier charges the external compensa-
tion capacitor, causing the COMP pin to rise (see Figure 65).
Tying the VREG pin to the EN pin via a pull-up resistor causes
the voltage at the EN pin to rise above the enable threshold of
630 m V, t h ereby enabling the ADP1878/ADP1879.
Figure 65. COMP Voltage Range
SOFT START
The ADP1878 employs externally programmable, soft start
circuitry that charges up a capacitor tied to the SS pin to GND.
This prevents input inrush current through the external MOSFET
from the input supply (VIN). The output tracks the ramping voltage
by producing PWM output pulses to the high-side MOSFET. The
purpose is to limit the inrush current from the high voltage
input supply (VIN) to the output (VOUT).
PRECISION ENABLE CIRCUITRY
The ADP1878/ADP1879 have precision enable circuitry. The
precision enable threshold is 630 mV including 30 mV of
hysteresis (see Figure 66). Connecting the EN pin to GND
disables the ADP1878/ADP1879, reducing the supply current
of the device to approximately 140 µA.
Figure 66. Connecting EN Pin to VREG via a Pull-Up Resistor to Enable the
ADP1878/ADP1879
UNDERVOLTAGE LOCKOUT
The undervoltage lockout (UVLO) feature prevents the device
from operating both the high- and low-side N-channel MOSFETs
at extremely low or undefined input voltage (VIN) ranges.
Operation at an undefined bias voltage can result in the
incorrect propagation of signals to the high-side power switches.
This, in turn, results in invalid output behavior that can cause
damage to the output devices, ultimately destroying the device
tied at the output. The UVLO level is set at 2.65 V (nominal).
ON-BOARD LOW DROPOUT (LDO) REGULATOR
The ADP1878/ADP1879 use an on-board LDO to bias the
internal digital and analog circuitry. With proper bypass
capacitors connected to the VREG pin (output of the internal
LDO), this pin also provides power for the internal MOSFET
drivers. It is recommended to float VREG if VIN is used for
greater than 5.5 V operation. The minimum voltage at which
bias is guaranteed to operate is 2.75 V at VREG (see Figure 67).
Figure 67. On-Board Regulator
For applications where VIN is decoupled from VREG, the
minimum voltage at VIN must be 2.9 V. It is recommended to tie
VIN and VREG together if the VIN pin is subjected to a 2.75 V rail.
COMP
>2.4V
2.4V
1.0V
500mV
0V
HICCUP MODE INITIALIZED
MAXIMUM CURRE NT (UPP E R CLAMP )
ZE RO CURRENT
USABLE RANG E ONLY AFT ER SOFT ST ART
PERI OD I F CONTINUOUS CO NDUCT ION
MODE O F OPERATI ON I S SELECTED.
LOW E R CLAMP
09441-066
PRECISION
ENABL E COMP.
TO ENABL E
ALL BLOCKS
EN
630mV
VREG
10kΩ
09441-065
REF
VREG VIN
ON-BOARD REGUL ATOR
09441-067
Data Sheet ADP1878/ADP1879
Rev. B | Page 19 of 40
Table 5. Power Input and LDO Output Configurations
VIN VREG Comments
>5.5 V Float Must use the LDO
<5.5 V Connect to VIN LDO drop voltage is not
realized (that is, if VIN = 2.75 V,
then VREG = 2.75 V)
<5.5 V Float LDO drop is realized
VIN ranging
above and
below 5.5 V
Float LDO drop is realized, minimum
VIN recommendation is 2.95 V
THERMAL SHUTDOWN
Thermal shutdown is a protection feature that prevents the IC
from damage caused by a very high operating junction temper-
ature. If the junction temperature of the device exceeds 155°C,
the device enters the thermal shutdown state. In this state, the
device shuts off both the high- and low-side MOSFETs and disables
the entire controller immediately, thus reducing the power con-
sumption of the IC. The device resumes operation after the
junction temperature of the device cools to less than 140°C.
PROGRAMMING RESISTOR (RES) DETECT CIRCUIT
Upon startup, one of the first blocks to become active is the RES
detect circuit. This block powers up before soft start begins. It
forces a 0.4 V reference value at the RES pin (see Figure 68) and is
programmed to identify four possible resistor values: 47 kΩ, 22 kΩ,
open, and 100 kΩ.
The RES detect circuit digitizes the value of the resistor at the
RES pin (Pin 6). An internal ADC outputs a 2-bit digital code
that is used to program four separate gain configurations in the
current sense amplifier (see Figure 69). Each configuration corre-
sponds to a current sense gain (ACS) of 3 V/V, 6 V/V, 12 V/V, or
24 V/V, respectively (see Table 6 and Table 7). This variable is used
for the valley current-limit setting, which sets up the appropriate
current sense gain for a given application and sets the compensation
necessary to achieve loop stability (see the Valley Current-Limit
Setting section and the Compensation Network section).
Figure 68. Programming Resistor Location
Figure 69. RES Detect Circuit for Current Sense Gain Programming
Table 6. Current Sense Gain Programming
Resistor ACS
47 kΩ 3 V/V
22 kΩ 6 V/V
Open 12 V/V
100 kΩ 24 V/V
VALLEY CURRENT-LIMIT SETTING
The architecture of the ADP1878/ADP1879 is based on valley
current-mode control. The current limit is determined by three
components: the RON of the low-side MOSFET, the output voltage
swing of the current sense amplifier, and the current sense gain.
The output range of the current sense amplifier is internally
fixed at 1.4 V. The current sense gain is programmable via an
external resistor at the RES pin (see the Programming Resistor
(RES) Detect Circuit section). The RON of the low-side MOSFET
can vary over temperature and usually has a positive TC (meaning
that it increases with temperature); therefore, it is recommended to
program the current sense, gain resistor based on the rated RON of
the MOSFET at 125°C.
Because the ADP1878/ADP1879 are based on valley current
control, the relationship between ICLIM and ILOAD is
1
2
where:
KI is the ratio between the inductor ripple current and the
desired average load current (see Figure 70).
ICLIM is the desired valley current limit.
ILOAD is the current load.
Establishing KI helps to determine the inductor value (see the
Inductor Selection section), but in most cases, KI = 0.33.
Figure 70. Valley Current Limit to Average Current Relation
DRVH
DRVL
Q1
SW
Q2
RES CS GAIN
PROGRAMMING
09441-068
SW
PGND
CS GAIN
SET
CS
AMP
ADC
RES
0.4V
09441-069
LOAD CURRENT
VALLEY CURRE NT L IMI T
RIPP LE CURRENT = I
LOAD
3
09441-070
ADP1878/ADP1879 Data Sheet
Rev. B | Page 20 of 40
When the desired valley current limit (ICLIM) has been determined,
the current sense gain can be calculated as follows:
1.4V
where:
RON is the channel impedance of the low-side MOSFET.
ACS is the current sense gain multiplier (see Table 6 and Table 7).
Although the ADP1878/ADP1879 have only four discrete current
sense gain settings for a given RON variable, Table 7 and Figure 71
outline several available options for the valley current setpoint
based on various RON values.
Table 7. Valley Current Limit Program (See Figure 71)
RON
(mΩ)
Valley Current Level (A)1
47 kΩ, 22 kΩ, Open, 100 kΩ,
ACS = 3 V/V ACS = 6 V/V ACS = 12 V/V ACS = 24 V/V
1.5 38.9
2 29.2
2.5 23.3
3 39.0 19.5
3.5 33.4 16.7
4.5 26.0 13
5 23.4 11.7
5.5 21.25 10.6
10 23.3 11.7 5.83
15 31.0 15.5 7.75 3.87
18 26.0 13.0 6.5 3.25
1 Blank cells are not applicable.
Figure 71. Valley Current-Limit Value vs. RON of the Low-Side MOSFET
for Each Programming Resistor (RES)
The valley current limit is programmed as listed in Table 7 and
shown in Figure 71. The inductor that is chosen must be rated
to handle the peak current, which is equal to the valley current
from Table 7 plus the peak-to-peak inductor ripple current (see
the Inductor Selection section). In addition, the peak current
value must be used to compute the worst-case power dissipation
in the MOSFETs (see Figure 72).
Figure 72. Valley Current-Limit Threshold in Relation to Inductor Ripple Current
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VALLEY CURRENT LIMIT (A)
R
ON
(mΩ)
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
RES = 47kΩ
A
CS
= 3V/V
RES = 22kΩ
A
CS
= 6V/V
RES = NO RES
A
CS
= 12V/V
RES = 100kΩ
A
CS
= 24V/V
09441-071
INDUCTOR
CURRENT
VALLEY CURRENT-LIMIT
THRESHOLD (SET FOR 25A)
∆I = 33%
OF 30A
CS AMP
OUTPUT
SWING
CURRENT
SENSE
AMPLIFIER
OUTPUT
2.4V
1V0A
35A
30A
32.25A
37A
49
A
39.5A
∆I = 45%
OF 32.25A
∆I = 65%
OF 37A
MAXIMUM DC LOAD
CURRENT
09441-072
Data Sheet ADP1878/ADP1879
Rev. B | Page 21 of 40
Figure 73. Idle Mode Entry Sequence Due to Current-Limit Violation
HICCUP MODE DURING SHORT CIRCUIT
A current-limit violation occurs when the current across the
source and drain of the low-side MOSFET exceeds the current-
limit setpoint. When 32 current-limit violations are detected,
the controller enters idle mode and turns off the MOSFETs for
6 ms, allowing the converter to cool down. Then, the controller
reestablishes soft start and begins to cause the output to ramp
up again (see Figure 73). While the output ramps up, the current
sense amplifier output is monitored to determine if the violation is
still present. If it is still present, the idle event occurs again, followed
by the full chip, power-down sequence. This cycle continues
until the violation no longer exists. If the violation disappears,
the converter is allowed to switch normally, maintaining
regulation.
SYNCHRONOUS RECTIFIER
The ADP1878/ADP1879 employ internal MOSFET drivers for
the external high- and low-side MOSFETs. The low-side
synchronous rectifier not only improves overall conduction
efficiency, but it also ensures proper charging of the bootstrap
capacitor located at the high-side driver input. This is beneficial
during startup to provide sufficient drive signal to the external
high-side MOSFET and to attain fast turn-on response, which is
essential for minimizing switching losses. The integrated high-
and low-side MOSFET drivers operate in complementary
fashion with built-in anti cross conduction circuitry to prevent
unwanted shoot through current that may potentially damage the
MOSFETs or reduce efficiency because of excessive power loss.
ADP1879 POWER SAVING MODE (PSM)
A power saving mode is provided in the ADP1879. The ADP1879
operates in the discontinuous conduction mode (DCM) and
pulse skips at light to medium load currents. The controller outputs
pulses as necessary to maintain output regulation. Unlike the
continuous conduction mode (CCM), DCM operation prevents
negative current, thus allowing improved system efficiency at
light loads. Current in the reverse direction through this pathway,
however, results in power dissipation and, therefore, a decrease in
efficiency.
Figure 74. Discontinuous Mode of Operation (DCM)
To minimize the chance of negative inductor current buildup,
an on-board zero-cross comparator turns off all high- and low-
side switching activities when the inductor current approaches
the zero current line, causing the system to enter idle mode,
where the high- and low-side MOSFETs are turned off. To ensure
idle mode entry, a 10 mV offset, connected in series at the SW
node, is implemented (see Figure 75).
Figure 75. Zero-Cross Comparator with 10 mV of Offset
As soon as the forward current through the low-side MOSFET
decreases to a level where
10 mV = IQ2 × RON(Q2)
the zero-cross comparator (or IREV comparator) emits a signal to
turn off the low-side MOSFET. From this point, the slope of the
inductor current ramping down becomes steeper (see Figure 76)
as the body diode of the low-side MOSFET begins to conduct
current and continues conducting current until the remaining
energy stored in the inductor has been depleted.
HS
CLIM
ZERO
CURRENT
REPEATED CURRENT-LIMIT
VIOL ATION DETECTED
A PREDETERM INED NUM BER
OF PULSES IS COUNTED TO
ALLO W T HE CONVE RTER
TO COOL DOWN
SOFT ST ART IS
REINITIALIZED TO
MO NITOR IF THE
VIOLATION
STILL EXISTS
09441-073
HS
HS AND L S ARE OF F
OR IN IDLE MODE
LS
0A
I
LOAD
AS THE INDUCTOR
CURRENT AP PROACHE S
ZERO CURRENT, THE STAT E
MACHI NE TURNS OFF T HE
LOWER-SIDE MOSFET.
t
ON
t
OFF
09441-074
10mV
ZERO-CROSS
COMPARATOR
Q2
LS
SW I
Q2
09441-075
ADP1878/ADP1879 Data Sheet
Rev. B | Page 22 of 40
Figure 76. 10 mV Offset to Ensure Prevention of Negative Inductor Current
The system remains in idle mode until the output voltage drops
below regulation. Next, a PWM pulse is produced, turning on the
high-side MOSFET to maintain system regulation. The ADP1879
does not have an internal clock; it switches purely as a hysteretic
controller, as described in this section.
TIMER OPERATION
The ADP1878/ADP1879 employ a constant on-time architecture,
which provides a variety of benefits, including improved load
and line transient response when compared with a constant
(fixed) frequency current-mode control loop of comparable
loop design. The constant on-time timer, or tON timer, senses
the high-side input voltage (VIN) and the output voltage (VOUT)
using SW waveform information to produce an adjustable one
shot PWM pulse. The pulse varies the on-time of the high-side
MOSFET in response to dynamic changes in input voltage, output
voltage, and load current conditions to maintain output regula-
tion. The timer generates an on-time (tON) pulse that is inversely
proportional to VIN.
where K is a constant that is trimmed using an RC timer product
for the 300 kHz, 600 kHz, and 1.0 MHz frequency options.
Figure 77. Constant On-Time Time
The constant on-time (tON) is not strictly constant because it
varies with VIN and VOUT. However, this variation occurs in such
a way as to keep the switching frequency virtually independent
of VIN and VOUT.
The tON timer uses a feedforward technique that, when applied
to the constant on-time control loop, makes it a pseudo fixed
frequency to a first-order approximation.
Second-order effects, such as dc losses in the external power
MOSFETs (see the Efficiency Consideration section), cause some
variation in frequency vs. load current and line voltage. These
effects are shown in Figure 23 to Figure 34. The variations in
frequency are much reduced compared with the variations
generated if the feedforward technique is not used.
The feedforward technique establishes the following relationship:
1
where fSW is the controller switching frequency (300 kHz,
600 kHz, and 1.0 MHz).
The tON timer senses VIN and VOUT to minimize frequency
variation as previously explained. This provides pseudo fixed
frequency as explained in the Pseudo Fixed Frequency section.
To al low headroom for VIN and VOUT sensing, adhere to the
following equations:
VREG ≥ VIN/8 + 1.5
VREG ≥ VOUT/4
For typical applications where VREG is 5 V, these equations are
not relevant; however, for lower VREG inputs, care may be required.
PSEUDO FIXED FREQUENCY
The ADP1878/ADP1879 employ a constant on-time control
scheme. During steady state operation, the switching frequency
stays relatively constant, or pseudo fixed. This is due to the one
shot tON timer that produces a high-side PWM pulse with a
fixed duration, given that external conditions such as input
voltage, output voltage, and load current are also at steady state.
During load transients, the frequency momentarily changes for
the duration of the transient event so that the output comes
back within regulation quicker than if the frequency were fixed,
or if it were to remain unchanged. After the transient event is
complete, the frequency returns to a pseudo fixed value.
To illustrate this feature more clearly, this section describes one
such load transient event—a positive load step—in detail. During
load transient events, the high-side driver output pulse width
stays relatively consistent from cycle to cycle; however, the off
time (DRVL on time) dynamically adjusts according to the
instantaneous changes in the external conditions mentioned.
When a positive load step occurs, the error amplifier (out of phase
with the output, VOUT) produces new voltage information at its
output (COMP). In addition, the current sense amplifier senses
new inductor current information during this positive load
transient event. The output voltage reaction of the error amplifier is
compared with the new inductor current information that sets
the start of the next switching cycle. Because current information
is produced from valley current sensing, it is sensed at the down
ramp of the inductor current, whereas the voltage loop information
HS AND LS
IN IDLE MODE
10mV = R
ON
× I
LOAD
ZERO-CROSS COMP ARATO R
DETECTS 10mV OFF SET AND
TURNS O FF L S
SW
LS
0A
I
LOAD
t
ON
ANOTHER
t
ON
EDGE IS
TRIGGERE D WHEN V
OUT
FALLS BELOW REGULATION
09441-076
C
R(TRIMMED)
VREG
t
ON
V
IN
I
SW
INFORMATION
09441-077
Data Sheet ADP1878/ADP1879
Rev. B | Page 23 of 40
is sensed through the counter action upswing of the output
(COMP) of the error amplifier.
The result is a convergence of these two signals (see Figure 78),
which allows an instantaneous increase in switching frequency
during the positive load transient event. In summary, a positive
load step causes VOUT to transient down, which causes COMP to
transient up and, therefore, shortens the off time. This resulting
increase in frequency during a positive load transient helps to
quickly bring VOUT back up in value and within the regulation
window.
Similarly, a negative load step causes the off time to lengthen in
response to VOUT rising. This effectively increases the inductor
demagnetizing phase, helping to bring VOUT within regulation.
In this case, the switching frequency decreases, or experiences a
foldback, to help facilitate output voltage recovery.
Because the ADP1878/ADP1879 have the ability to respond rapidly
to sudden changes in load demand, the recovery period in which
the output voltage settles back to its original steady state operating
point is much quicker than it would be for a fixed frequency
equivalent. Therefore, using a pseudo fixed frequency results in
significantly better load transient performance compared to
using a fixed frequency.
Figure 78. Load Transient Response Operation
POWER-GOOD MONITORING
The ADP1878/ADP1879 power-good circuitry monitors the
output voltage via the FB pin. The PGOOD pin is an open-
drain output that can be pulled up by an external resistor to a
voltage rail that does not necessarily have to be VREG. When
the internal NMOS switch is in high impedance (off state), this
means that the PGOOD pin is logic high and the output voltage
via the FB pin is within the specified regulation window. When
the internal switch is turned on, PGOOD is internally pulled low
when the output voltage via the FB pin is outside this regulation
window.
The power-good window is defined with a typical upper speci-
fication of +90 mV and a lower specification of −70 mV below
the FB voltage of 600 mV. When an overvoltage event occurs at the
output, there is a typical propagation delay of 12 μs prior to the
deassertion (logic low) of the PGOOD pin. When the output
voltage reenters the regulation window, there is a propagation
delay of 12 μs prior to PGOOD reasserting back to a logic high
state. When the output is outside the regulation window, the
PGOOD open-drain switch is capable of sinking 1 mA of
current and providing 140 mV of drop across this switch. The
user is free to tie the external pull-up resistor (RRES) to any
voltage rail up to 20 V. The following equation provides the
proper external pull-up resistor value:
140mV
1mA
where:
RPGD is the PGOOD external resistor.
VEXT is a user chosen voltage rail.
Figure 79. Power Good, Output Voltage Monitoring Circuit
Figure 80. Power-Good Timing Diagram, tPGD = 12 μs (Diagram May Look
Disproportionate For Illustration Purposes)
VALLEY
TRIP POINTS
LO AD CU RREN T
DEMAND
ERRO R AMP
OUTPUT
PWM OUTPUT
f
SW >
f
SW
CS AM P
OUTPUT
09441-078
530mV
690mV
FB
600mV
PGOOD
1mA
–
140mV
+
V
EXT
RPGD
09441-079
690mV
640mV
600mV
530mV
FB
HYSTERESIS (50mV)
OUTPUT O
V
ER
V
OLT
A
GE
PGOOD DEASSERT
PGOOD
REASSERT
PGOOD
ASSERTION
AT POWER-UP PGOOD
DEASSERTION
AT POWER-DOWN
SOFT START
VEXT
PGOOD
0V
0V
t
PGD
t
PGD
t
PGD
t
PGD
09441-080
ADP1878/ADP1879 Data Sheet
Rev. B | Page 24 of 40
APPLICATIONS INFORMATION
FEEDBACK RESISTOR DIVIDER
The required resistor divider network can be determined for a
given VOUT value because the internal band gap reference (VREF)
is fixed at 0.6 V. Selecting values for RT and RB determine the
minimum output load current of the converter. Therefore, for a
given value of RB, the RT value can be determined through the
following expression:
=×( 0.6 V)
0.6 V
INDUCTOR SELECTION
The inductor value is inversely proportional to the inductor
ripple current. The peak-to-peak ripple current is given by
=×
3
where KI is typically 0.33.
The equation for the inductor value is given by
=( )
× ×
where:
VIN is the high voltage input.
VOUT is the desired output voltage.
fSW is the controller switching frequency (300 kHz, 600 kHz, and
1.0 MHz).
When selecting the inductor, choose an inductor saturation
rating that is above the peak current level, and then calculate
the inductor current ripple (see the Valley Current-Limit
Setting section and Figure 81).
Figure 81. Peak Inductor Current vs. Valley Current Limit for 33%, 40%, and
50% of Inductor Ripple Current
Table 8. Recommended Inductors
L
(µH)
DCR
(mΩ)
I
SAT
(A)
Dimensions
(mm) Manufacturer
Model
Number
0.12 0.33 55 10.2 × 7 Würth Elek. 744303012
0.22 0.33 30 10.2 × 7 Würth Elek. 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elek. 744355147
0.72
1.65
35
10.5 × 10.2
Würth Elek.
744325072
0.9
1.6
32
14 × 12.8
Würth Elek.
744318120
1.2 1.8 25 10.5 × 10.2 Würth Elek. 744325120
1.0 3.8 16 10.2 × 10.2 Würth Elek. 7443552100
1.4 3.2 24 14 × 12.8 Würth Elek. 744318180
2.0 2.6 23 10.2 × 10.2 Würth Elek. 7443551200
0.8 27.5 Sumida CEP125U-0R8
OUTPUT RIPPLE VOLTAGE (ΔVRR)
The output ripple voltage is the ac component of the dc output
voltage during steady state. For a ripple error of 1.0%, the output
capacitor value needed to achieve this tolerance can be determined
using the following equation. (Note that an accuracy of 1.0% is
possible during steady state conditions only, not during load
transients.)
ΔVRR = (0.01) × VOUT
OUTPUT CAPACITOR SELECTION
The primary objective of the output capacitor is to facilitate the
reduction of the output voltage ripple; however, the output capacitor
also assists in the output voltage recovery during load transient
events. For a given load current step, the output voltage ripple
generated during this step event is inversely proportional to the
value chosen for the output capacitor. The speed at which the
output voltage settles during this recovery period depends on
where the crossover frequency (loop bandwidth) is set. This
crossover frequency is determined by the output capacitor, the
equivalent series resistance (ESR) of the capacitor, and the
compensation network.
To calculate the small signal voltage ripple (output ripple voltage) at
the steady state operating point, use the following equation:
=×1
8× ×[ (×)]
where ESR is the equivalent series resistance of the output
capacitors.
To calculate the output load step, use the following equation:
= 2 ×
× ( ×)
where ΔVDROOP is the amount that VOUT is allowed to deviate for
a given positive load current step (ΔILOAD).
52
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
6 8 10 12 14 16 18 20 22 24 26 28 30
PEAK INDUCTOR CURRENT (A)
VAL LEY CURRE NT L IMI T (A)
ΔI = 50%
ΔI = 40%
ΔI = 33%
09441-081
Data Sheet ADP1878/ADP1879
Rev. B | Page 25 of 40
Ceramic capacitors are known to have low ESR. However, there
is a trade-off in using the popular X5R capacitor technology
because as much as 80% of its capacitance may be lost due to
derating as the voltage applied across the capacitor is increased
(see Figure 82). Although X7R series capacitors can also be
used, the available selection is limited to 22 µF maximum.
Figure 82. Capacitance vs. DC Voltage Characteristics for Ceramic Capacitors
Electrolytic capacitors satisfy the bulk capacitance requirements
for most high current applications. However, because the ESR of
electrolytic capacitors is much higher than that of ceramic capaci-
tors, mount several MLCCs in parallel with the electrolytic
capacitors to reduce the overall series resistance.
COMPENSATION NETWORK
Due to its current-mode architecture, the ADP1878/ADP1879
require Type II compensation. To determine the component
values needed for compensation (resistance and capacitance
values), it is necessary to examine the overall loop gain (H) of the
converter at the unity-gain frequency (fSW/10) when H = 1 V/V:
= 1 V V
=× ×
× ×
Examining each variable at high frequency enables the unity-
gain transfer function to be simplified to provide expressions
for the RCOMP and CCOMP component values.
Output Filter Impedance (ZFILT)
Examining the transfer function of the filter at high frequencies
simplifies to
=×1 + ××
1 + (+)
at the crossover frequency (s = 2πfCROSS). ESR is the equivalent
series resistance of the output capacitors.
Error Amplifier Output Impedance (ZCOMP)
Assuming CC2 is significantly smaller than CCOMP, CC2 can be
omitted from the output impedance equation of the error
amplifier. The transfer function simplifies to
=
×+
and
=1
12 ×
where fZERO, the zero frequency, is set to be 1/4th of the crossover
frequency for the ADP1878.
Error Amplifier Gain (Gm)
The error amplifier gain (transconductance) is
Gm = 500 µA/V (µs)
Current-Sense Loop Gain (GCS)
The current-sense loop gain is
=1
× (
)
where:
ACS (V/V) is programmable for 3 V/V, 6 V/V, 12 V/V, and 24 V/V
(see the Programming Resistor (RES) Detect Circuit and Valley
Current-Limit Setting sections).
RON is the channel impedance of the low-side MOSFET.
Crossover Frequency
The crossover frequency is the frequency at which the overall
loop (system) gain is 0 dB (H = 1 V/V). It is recommended for
current-mode converters, such as the ADP1878, that the user set
the crossover frequency between 1/10th and 1/15th of the switching
frequency.
=1
12
The relationship between CCOMP and fZERO (zero frequency) is as
follows:
=1
2× ×
The zero frequency is set to 1/4th of the crossover frequency.
Combining all of the above parameters results in
=
+×1+ ((+))
1+ (××)×1
×
×1
where ESR is the equivalent series resistance of the output
capacitors.
=1
2×× ×
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 0 5 10 15 20 25 30
CAPACI TANCE CHARG E ( %)
DC VOLTAGE (V
DC
)
X7R (50V )
X5R (25V )
X5R (16V )
10µF TDK 25V, X7R, 1210 C3225X 7R1E 106M
22µF M URATA 25V, X7R, 1210 GRM32E R71E 226KE 15L
47µF M URATA 16V, X5R, 1210 GRM32E R61C476KE 15L
09441-082
ADP1878/ADP1879 Data Sheet
Rev. B | Page 26 of 40
EFFICIENCY CONSIDERATION
An important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents of up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
VGS (TH) is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
RDS (ON) is the on resistance of the MOSFET during channel
conduction.
QG is the total gate charge.
CN1 is the input capacitance of the high-side switch.
CN2 is the input capacitance of the low-side switch.
The following are the losses experienced through the external
component during normal switching operation:
Channel conduction loss (both of the MOSFETs).
MOSFET driver loss.
MOSFET switching loss.
Body diode conduction loss (low-side MOSFET).
Inductor loss (copper and core loss).
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the high-side MOSFET is directly proportional
to the duty cycle (D) for each switching period, and the power
loss through the low-side MOSFET is directly proportional to
1 − D for each switching period. The selection of MOSFETs is
governed by the maximum dc load current that the converter is
expected to deliver. In particular, the selection of the low-side
MOSFET is dictated by the maximum load current because a
typical high current application employs duty cycles of less than
50%. Therefore, the low-side MOSFET is in the on state for
most of the switching period.
1,2
112
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through the driver
during operation and the QGATE parameter of the external MOSFETs.
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG ×
(fSWClowerFETVREG + IBIAS)]
where:
CupperFET is the input gate capacitance of the high-side MOSFET.
ClowerFET is the input gate capacitance of the low-side MOSFET.
IBIAS is the dc current flowing into the high- and low-side drivers.
VDR is the driver bias voltage (that is, the low input voltage (VREG)
minus the rectifier drop (see Figure 83)).
VREG is the bias voltage.
Figure 83. Internal Rectifier Voltage Drop vs. Switching Frequency
MOSFET Switching Loss
The SW node transitions due to the switching activities of the
high- and low-side MOSFETs. This causes removal and reple-
nishing of charge to and from the gate oxide layer of the MOSFET,
as well as to and from the parasitic capacitance associated with
the gate oxide edge overlap and the drain and source terminals.
The current that enters and exits these charge paths presents
additional loss during these transition times. This can be approxi-
mately quantified by using the following equation, which represents
the time in which charge enters and exits these capacitive regions:
tSW-TRANS = RGATE × CTOTAL
where:
CTOTAL is the CGD + CGS of the external MOSFET.
RGATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
-TRANS
2
or
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
Body Diode Conduction Loss
The ADP1878/ADP1879 employ anti cross conduction circuitry
that prevents the high- and low-side MOSFETs from conducting
current simultaneously. This overlap control is beneficial, avoiding
large current flow that may lead to irreparable damage to the
external components of the power stage. However, this blanking
period comes with the trade-off of a diode conduction loss
occurring immediately after the MOSFETs change states and
continuing well into idle mode.
800
720
640
560
480
400
320
240
160
80
300 1000900800700600500400
RECT IF IER V OLTAGE DROP ( mV )
SW IT CHING FREQUENCY (kHz)
+125°C
+25°C
–40°C
V
REG
= 2. 7V
V
REG
= 3. 6V
V
REG
= 5. 5V
09441-083
Data Sheet ADP1878/ADP1879
Rev. B | Page 27 of 40
The amount of loss through the body diode of the low-side
MOSFET during the anti overlap state is given by the following
expression:
2
where:
tBODY(LOSS) is the body conduction time (refer to Figure 84 for
dead time periods).
tSW is the period per switching cycle.
VF is the forward drop of the body diode during conduction.
(Refer to the selected external MOSFET data sheet for more
information about the VF parameter.)
Figure 84. Body Diode Conduction Time vs. Low Voltage Input (VREG)
Inductor Loss
During normal conduction mode, further power loss is caused
by the conduction of current through the inductor windings,
which have dc resistance (DCR). Typically, larger sized inductors
have smaller DCR values.
The inductor core loss is a result of the eddy currents generated
within the core material. These eddy currents are induced by the
changing flux, which is produced by the current flowing through
the windings. The amount of inductor core loss depends on the
core material, the flux swing, the frequency, and the core volume.
Ferrite inductors have the lowest core losses, whereas powdered iron
inductors have higher core losses. It is recommended to use shielded
ferrite core material type inductors with the ADP1878/ADP1879
for a high current, dc-to-dc switching application to achieve
minimal loss and negligible electromagnetic interference (EMI).
INPUT CAPACITOR SELECTION
The goal in selecting an input capacitor is to reduce or minimize
input voltage ripple and to reduce the high frequency source
impedance, which is essential for achieving predictable loop
stability and transient performance.
The problem with using bulk capacitors, other than their physical
geometries, is their large equivalent series resistance (ESR) and
large equivalent series inductance (ESL). Aluminum electrolytic
capacitors have such high ESR that they cause undesired input
voltage ripple magnitudes and are generally not effective at high
switching frequencies.
If bulk electrolytic capacitors are used, it is recommended to use
multilayered ceramic capacitors (MLCC) in parallel due to their
low ESR values. This dramatically reduces the input voltage ripple
amplitude as long as the MLCCs are mounted directly across the
drain of the high-side MOSFET and the source terminal of the
low-side MOSFET (see the Layout Considerations section).
Improper placement and mounting of these MLCCs may cancel
their effectiveness due to stray inductance and an increase in
trace impedance.
,
,
The maximum input voltage ripple and maximum input capacitor
rms current occur at the end of the duration of 1 − D while the
high-side MOSFET is in the off state. The input capacitor rms
current reaches its maximum at time D. When calculating the
maximum input voltage ripple, account for the ESR of the input
capacitor as follows:
VMAX,RIPPLE = VRIPP + (ILOAD,MAX × ESR)
where:
VRIPP is usually 1% of the minimum voltage input.
ILOAD,MAX is the maximum load current.
ESR is the equivalent series resistance rating of the input capacitor.
Inserting VMAX,RIPPLE into the charge balance equation to
calculate the minimum input capacitor requirement gives
, ,
, 1
or
, ,
4,
where D = 50%.
THERMAL CONSIDERATIONS
The ADP1878/ADP1879 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current and be subjected to high ambient
temperature, the selection of external high- and low-side MOSFETs
must be associated with careful thermal consideration to not
exceed the maximum allowable junction temperature of 125°C.
To avoid permanent or irreparable damage, if the junction temper-
ature reaches or exceeds 155°C, the part enters thermal shutdown,
turning off both external MOSFETs, and is not reenabled until
the junction temperature cools to 140°C (see the On-Board Low
Dropout (LDO) Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1878/ADP1879 employ an
on-board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs, adds another element of
80
72
64
56
48
40
32
24
16
8
2.7 5.54.84.13.4
BODY DIO DE CONDUCT I O N T I ME ( n s)
VREG (V)
+125°C
+25°C
–40°C
1MHz
300kHz
09441-084
ADP1878/ADP1879 Data Sheet
Rev. B | Page 28 of 40
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO. Table 9 lists the thermal impedance for the
ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD.
Table 9. Thermal Impedance for 14-Lead LFCSP_WD
Package Thermal Impedance
14-Lead LFCSP_WD θJA
4-Layer Board 30°C/W
Figure 85 specifies the maximum allowable ambient temperature
that can surround the ADP1878/ADP1879 IC for a specified
high input voltage (VIN). Figure 85 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for the 14-lead LFCSP_WD
package. All temperature derating criteria are based on a
maximum IC junction temperature of 125°C.
Figure 85. Ambient Temperature vs. VIN,
4-Layer Evaluation Board, CIN = 4.3 nF (High-/Low-Side MOSFET)
The maximum junction temperature allowed for the ADP1878/
ADP1879 IC is 125°C. This means that the sum of the ambient
temperature (TA) and the rise in package temperature (TR), which is
caused by the thermal impedance of the package and the internal
power dissipation, should not exceed 125°C, as dictated by the
following expression:
TJ = TR × TA (1)
where:
TJ is the maximum junction temperature.
TR is the rise in package temperature due to the power
dissipated from within.
TA is the ambient temperature.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
TR = θJA × PDR(LOSS) (2)
where:
θJA is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
PDR(LOSS) is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance of
the external MOSFETs and current running through the on-board
LDO. The power loss equations for the MOSFET drivers and
internal low dropout regulator (see the MOSFET Driver Loss
section and the Efficiency Consideration section) are:
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFET VREG + IBIAS)] (3)
where:
CupperFET is the input gate capacitance of the high-side MOSFET.
ClowerFET is the input gate capacitance of the low-side MOSFET.
IBIAS is the dc current (2 mA) flowing into the high- and low-
side drivers.
VDR is the driver bias voltage (the low input voltage (VREG) minus
the rectifier drop (see Figure 83)).
VREG is the LDO output/bias voltage.
PDISS(LDO) = PDR(LOSS) + (VIN – VREG) × (fSW × CTOTAL ×
VREG + IBIAS (4)
where PDISS(LDO) is the power dissipated through the pass device
in the LDO block across VIN and VREG.
PDR(LOSS) is the MOSFET driver loss.
VIN is the high voltage input.
VREG is the LDO output voltage and bias voltage.
CTOTAL is the CGD + CGS of the external MOSFET.
IBIAS is the dc input bias current.
For example, if the external MOSFET characteristics are θJA
(14-lead LFCSP_WD) = 30°C/W, fSW = 300 kHz, IBIAS = 2 mA,
CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V,
then the power loss is
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +
[VREG × (fSWClowerFETVREG + IBIAS)]
= (4.62 × (300 × 103 × 3.3 × 10−9 × 4.62 + 0.002)) +
(5.0 × (300 × 103 × 3.3 × 10−9 × 5.0 + 0.002))
= 57.12 mW
PDISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS) =
(13 V – 5 V) × (300 × 103 × 3.3 × 10−9 × 5 + 0.002)
= 55.6 mW
PDISS(TOTAL) = PDISS(LDO) + PDR(LOSS)
= 77.13 mW + 55.6 mW
= 132.73 mW
130
90
100
110
120
5.5 19.017.516.014.513.011.510.08.57.0
MAXIM UM AL LOWABLE AMBIENT
TEMPERATURE (°C)
V
IN
(V)
09441-085
300kHz
600kHz
1MHz
V
OUT
= 0.8V
V
OUT
= 1.8V
V
OUT
= HIGH SETPOINT
Data Sheet ADP1878/ADP1879
Rev. B | Page 29 of 40
The rise in package temperature (for a 14-lead LFCSP_WD) is
TR = θJA × PDR(LOSS)
= 30°C × 132.05 mW
= 4.0°C
Assuming a maximum ambient temperature environment of 85°C,
TJ = TR × TA = 4.0°C + 85°C = 89.0°C,
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1878/ADP1879 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: VOUT = 1.8 V, ILOAD = 15 A (pulsing),
VIN = 12 V (typical), and fSW = 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
VRIPP = 120 mV
VMAX,RIPPLE = VRIPP − (ILOAD,MAX × ESR)
= 120 mV − (15 A × 0.001) = 45 mV
, =,
4, =15 A
4 × 300 × 10 × 105 mV
= 120 µF
Choose five 22 µF ceramic capacitors. The overall ESR of five
22 µF ceramic capacitors is less than 1 mΩ.
IRMS = ILOAD/2 = 7.5 A
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
Inductor
Determining inductor ripple current amplitude:
3= 5 A
Then, calculating for the inductor value
=,
×
,
=13.2 V – 1.8 V
5 V×300 ×10×1.8 V
13.2 V
= 1.03 µH
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 µH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) with a peak
current handling of 20 A.
()= ×
= 0.003 × (15 A)2 = 675 mW
Current-Limit Programming
The valley current is approximately
15 A − (5 A × 0.5) = 12.5 A
Assuming a low-side MOSFET RON of 4.5 mΩ and 13 A, as the
valley current limit from Table 7 and Figure 71 indicate, a pro-
gramming resistor (RES) of 100 kΩ corresponds to an ACS
of 24 V/V.
Choose a programmable resistor of RRES = 100 kΩ for a current
sense gain of 24 V/V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% output deviation is allowed from the steady state operating
point. In this case, the advantage of the ADP1878 is that because
the frequency is pseudo fixed, the converter is able to respond
quickly because of the immediate, though temporary, increase
in switching frequency.
ΔVDROOP = 0.05 × 1.8 V = 90 mV
Assuming the overall ESR of the output capacitor ranges from
5 mΩ to 10 mΩ,
= 2 ×
×()
= 2 × 15 A
300 ×10×(90 mV)
= 1.11 mF
Therefore, an appropriate inductor selection is five 270 µF
polymer capacitors with a combined ESR of 3.5 mΩ.
Assuming an overshoot of 45 mV, determine if the output
capacitor that was calculated previously is adequate
=(×
)
(( )())
=1×10 × (15 A)
(1.8 45 mV)(1.8)
= 1.4 mF
Choose five 270 µF polymer capacitors.
The rms current through the output capacitor is
=1
2×1
3
,
× ×
,
=1
2×1
3
(13.2 V – 1.8 V)
F×300×103×1.8 V
13.2 V =1.49 A
The power loss dissipated through the ESR of the output
capacitor is
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
ADP1878/ADP1879 Data Sheet
Rev. B | Page 30 of 40
Feedback Resistor Network Setup
Choosing RB = 1 kΩ as an example. Calculate RT as follows:
= 1 k×(1.8 V 0.6 V)
0.6 V = 2 k
Compensation Network
To calculate RCOMP, CCOMP, and CPAR, the transconductance
parameter and the current sense gain variable are required. The
transconductance parameter (Gm) is 500 µA/V, and the current
sense loop gain is
=1
=1
24 × 0.005 = 8.33 A/V
where ACS and RON are taken from setting up the current limit
(see the Programming Resistor (RES) Detect Circuit section
and the Valley Current-Limit Setting section).
The crossover frequency is 1/12th of the switching frequency:
300 kHz/12 = 25 kHz
The zero frequency is 1/4th of the crossover frequency:
25 kHz/4 = 6.25 kHz
=
+×1+ ((+))
1+ (××)×
1
×
×1
=25 k
25 k+ 6.25 k×
1+ (2×25 k× ((1.8/15)+ 0.0035) × 0.0011)
1+ (2×25 k× 0.0035 × 0.0011)×
1.8
0.6 ×1
500 ×10 × 8.3 ×15
1.8
= 60.25 kΩ
=1
2
=1
2 × 3.14 ×60.25 ×10× 6.25 ×10
= 423 pF
Loss Calculations
Duty cycle = 1.8/12 V = 0.15
RON(N2) = 5.4 mΩ
tBODY(LOSS) = 20 ns (body conduction time)
VF = 0.84 V (MOSFET forward voltage)
CIN = 3.3 nF (MOSFET gate input capacitance)
QN1,N2 = 17 nC (total MOSFET gate charge)
RGATE = 1.5 Ω (MOSFET gate input resistance)
1,()= ×1()+(1)×()×
= (0.15 × 0.0054 + 0.85 × 0.0054) × (15 A)2
= 1.215 W
()=()
× ×× 2
= 20 ns × 300 × 103 × 15 A × 0.84 × 2
= 151.2 mW
PSW(LOSS) = fSW × RGATE × CTOTAL × ILOAD × VIN × 2
= 300 × 103 × 1.5 Ω × 3.3 × 10−9 × 15 A × 12 × 2
= 534.6 mW
PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] + [VREG ×
(fSWClowerFETVREG +IBIAS)]
=(4.62 × (300 ×103 × 3.3 × 10−9 × 4.62 + 0.002)) +
(5.0 × (300 × 103 × 3.3 × 10−9 × 5.0 + 0.002))
= 57.12 mW
PDISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS)
= (13 V – 5 V) × (300 × 103 × 3.3 × 10−9 × 5 + 0.002)
= 55.6 mW
PCOUT = (IRMS)2 × ESR = (1.5 A)2 × 1.4 mΩ = 3.15 mW
2
)( LOAD
LOSSDCR IDCRP×=
= 0.003 × (15 A)2 = 675 mW
PCIN = (IRMS)2 × ESR = (7.5 A)2 × 1 mΩ = 56.25 mW
PLOSS = PN1,N2 + PBODY(LOSS) + PSW + PDCR + PDR + PDISS(LDO) + PCOUT
+ PCIN = 1.215 W + 151.2 mW + 534.6 mW + 57.12 mW +
55.6 + 3.15 mW + 675 mW + 56.25 mW = 2.655 W
Data Sheet ADP1878/ADP1879
Rev. B | Page 31 of 40
EXTERNAL COMPONENT RECOMMENDATIONS
The configurations listed in Table 10 are with fCROSS = 1/12 × fSW, fZERO = ¼ × fCROSS, RRES = 100 k, RBOT = 1k, RON = 5.4 mΩ (BSC042N03MS G),
VREG = 5 V (float), and a maximum load current of 14 A. The ADP1879 models listed in Table 10 are the PSM versions of the device.
Table 10. External Component Values
Model
VOUT
(V)
VIN
(V)
CIN
(μF) COUT (μF)
L1
(μH)
RC
(kΩ)
CCOMP
(pF)
CPAR
(pF)
RTOP
(kΩ)
ADP1878ACPZ-0.3-R7/ 0.8 13 5 × 222 5 × 5603 0.72 56.9 620 62 0.3
ADP1879ACPZ-0.3-R7 1.2 13 5 × 222 4 × 5603 1.0 56.9 620 62 1.0
1.8 13 4 × 222 4 × 2704 1.2 56.9 470 47 2.0
2.5 13 4 × 222 3 × 2704 1.53 57.6 470 47 3.2
3.3 13 5 × 222 2 × 3305 2.0 56.9 470 47 4.5
5 13 4 × 222 3305 3.27 40.7 680 68 7.3
7 13 4 × 222 222 + ( 4 × 476) 3.44 40.7 680 68 10.7
1.2 16.5 4 × 222 4 × 5603 1.0 56.9 620 62 1.0
1.8 16.5 3 × 222 4 × 2704 1.0
56.9 470 47 2.0
2.5 16.5 3 × 222 4 × 2704 1.67 57.6 470 47 3.2
3.3 16.5 3 × 222 2 × 3305 2.00 56.9 510 51 4.5
5 16.5 3 × 222 2 × 1507 3.84 41.2 680 68 7.3
7 16.5 3 × 222 222 + 4 × 476 4.44 40.7 680 68 10.7
ADP1878ACPZ-0.6-R7/ 0.8 5.5 5 × 222 4 × 5603 0.22 56.2 300 300 0.3
ADP1879ACPZ-0.6-R7 1.2 5.5 5 × 222 4 × 2704 0.47 56.9 270 27 1.0
1.8 5.5 5 × 222 3 × 2704 0.47 56.9 220 22 2.0
2.5 5.5 5 × 222 3 × 1808 0.47 56.9 220 22 3.2
1.2 13 3 × 222 5 × 2704 0.47 56.9 360 36 1.0
1.8 13 5 × 109 3 × 3305 0.47 56.2 270 27 2.0
2.5 13 5 × 109 3 × 2704 0.90 57.6 240 24 3.2
3.3 13 5 × 109 2 × 2704 1.00 57.6 240 24 4.5
5 13 5 × 109 1507 1.76 40.7 360 36 7.3
1.2 16.5 3 × 109 4 × 2704 0.47 56.9 300 30 1.0
1.8 16.5 4 × 109 2 × 3305 0.72 53.6 270 27 2.0
2.5 16.5 4 × 109 3 × 2704 0.90 57.6 270 27 3.2
3.3 16.5 4 × 109 3305 1.0 53.0 270 27 4.5
5 16.5 4 × 109 4 × 476 2.0 41.2 360 36 7.3
7 16.5 4 × 109 3 × 476 2.0 40.7 300 30 10.7
ADP1878ACPZ-1.0-R7/ 0.8 5.5 5 × 222 4 × 2704 0.22 54.9 200 20 0.3
ADP1879ACPZ-1.0-R7 1.2 5.5 5 × 222 2 × 3305 0.22 49.3 220 22 1.0
1.8 5.5 3 × 222 3 × 1808 0.22 56.9 130 13 2.0
2.5 5.5 3 × 222 2704 0.22 54.9 130 13 3.2
1.2 13 3 × 109 3 × 3305 0.22 53.6 200 20 1.0
1.8 13 4 × 109 3 × 2704 0.47 56.9 180 18 2.0
2.5 13 4 × 109 2704 0.47 54.9 180 18 3.2
3.3 13 5 × 109 2704 0.72 56.2 180 18 4.5
5 13 4 × 109 3 × 476 1.0 40.7 220 22 7.3
1.2 16.5 3 × 109 4 × 2704 0.47 56.9 270 27 1.0
1.8 16.5 3 × 109 3 × 2704 0.47 56.9 220 22 2.0
2.5 16.5 4 × 109 3 × 1808 0.72 56.9 200 20 3.2
3.3 16.5 4 × 109 2704 0.72 56.2 180 18 4.5
5 16.5 3 × 109 3 × 476 1.2 40.7 220 22 7.3
7 16.5 3 × 109 222 + 476 1.2 40.7 180 18 10.7
1 See the Inductor Selection section and Table 11.
2 22 μF Murata 25 V, X7R, 1210 GRM32ER71E226KE15L (3.2 mm × 2.5 mm × 2.5 mm).
3 560 μF Panasonic (SP-series) 2 V, 7 mΩ, 3.7 A EEFUE0D561LR (4.3 mm × 7.3 mm × 4.2 mm).
4 270 μF Panasonic (SP-series) 4 V, 7 mΩ, 3.7 A EEFUE0G271LR (4.3 mm × 7.3 mm × 4.2 mm).
5 330 μF Panasonic (SP-series) 4 V, 12 mΩ, 3.3 A EEFUE0G331R (4.3 mm × 7.3 mm × 4.2 mm).
6 47 μF Murata 16 V, X5R, 1210 GRM32ER61C476KE15L (3.2 mm × 2.5 mm × 2.5 mm).
7 150 μF Panasonic (SP-series) 6.3 V, 10 mΩ, 3.5 A EEFUE0J151XR (4.3 mm × 7.3 mm × 4.2 mm).
8 180 μF Panasonic (SP-series) 4 V, 10 mΩ, 3.5 A EEFUE0G181XR (4.3 mm × 7.3 mm × 4.2 mm).
9 10 μF TDK 25 V, X7R, 1210 C3225X7R1E106M.
ADP1878/ADP1879 Data Sheet
Rev. B | Page 32 of 40
Table 11. Recommended Inductors
L (μH) DCR (mΩ) ISAT (A) Dimension (mm) Manufacturer Model Number
0.12 0.33 55 10.2 × 7 Würth Elektronik 744303012
0.22 0.33 30 10.2 × 7 Würth Elektronik 744303022
0.47 0.8 50 14.2 × 12.8 Würth Elektronik 744355147
0.72 1.65 35 10.5 × 10.2 Würth Elektronik 744325072
0.9 1.6 32 14 × 12.8 Würth Elektronik 744318120
1.2 1.8 25 10.5 × 10.2 Würth Elektronik 744325120
1.0 3.8 16 10.2 × 10.2 Würth Elektronik 7443552100
1.4 3.2 24 14 × 12.8 Würth Elektronik 744318180
2.0 2.6 23 10.2 × 10.2 Würth Elektronik 7443551200
0.8 27.5 Sumida CEP125U-0R8
Table 12. Recommended MOSFETs
VGS = 4.5 V RON (mΩ) ID (A) VDS (V) CIN (nF) QTOTAL (nC) Package Manufacturer Model Number
High-Side MOSFET
(Q1/Q2)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2 53 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
9 14 30 2.4 25 SO-8 International Rectifier IRF7811
Low-Side MOSFET
(Q3/Q4)
5.4 47 30 3.2 20 PG-TDSON8 Infineon BSC042N03MS G
10.2 82 30 1.6 10 PG-TDSON8 Infineon BSC080N03MS G
6.0 19 30 35 SO-8 Vishay Si4842DY
Data Sheet ADP1878/ADP1879
Rev. B | Page 33 of 40
LAYOUT CONSIDERATIONS
The performance of a dc-to-dc converter depends highly on
how the voltage and current paths are configured on the printed
circuit board (PCB). Optimizing the placement of sensitive
analog and power components are essential to minimize output
ripple, maintain tight regulation specifications, and reduce
PWM jitter and electromagnetic interference.
Figure 86 shows the schematic of a typical ADP1878/ADP1879
used for a high current application. Blue traces denote high current
pathways. VIN, PGND, and VOUT traces should be wide and
possibly replicated, descending down into the multiple layers.
Vias should populate, mainly around the positive and negative
terminals of the input and output capacitors, alongside the source
of Q1/Q2, the drain of Q3/Q4, and the inductor.
Figure 86. ADP1878 High Current Evaluation Board Schematic (Blue Traces Indicate High Current Paths)
Figure 87. Overall Layout of the ADP1878/ADP1879 High Current Evaluation Board
MURAT A: ( HIGH V OL TAGE INPUT CAPACITORS)
22µF , 25V, X7R, 1210 GRM32E R71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TO RS )
270µF, SP-SERIES, 4V, 7mΩ, EEFUE0G271LR
INFINEON FETs:
BSC042N03MS G (L OW E R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTO RS :
1µH, 3.8mΩ, 16A, 7443552100
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C
BST
100nF
V
OUT
= 1.8V , 15A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.0µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
14
BST
2
COMP
13
SW
3
EN
12
DRVH
5
GND
10
DRVL
ADP1878/
ADP1879
C
C
430pF
C
PAR
53pF R
C
57kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
11
PGND
6
RES
9
PGOOD
7
VREG
8
SS
5kΩ V
REG
C
SS
34nF
V
REG
09441-086
INP UT CAPACI TO RS
ARE MOUNTE D CLO S E
TO DRAIN OF Q1/Q2
AND SO URCE OF Q3/ Q4
SEP ARATE ANAL OG
GROUND PL ANE FO R
COM P E NS ATION AND
FE E DBACK RE S IST ORS
SENSITIVE ANALOG
COMPONENTS
LOCATE D FAR
FROM NOISY
POWER SECTIO N
OUTPUT
CAPACITORS
ARE MOUNTE D
AT RIGHTMOST
AREA O F
EVALUATION
BOARD
09441-087
ADP1878/ADP1879 Data Sheet
Rev. B | Page 34 of 40
Figure 88. Layer 2 of Evaluation Board
Figure 89. Layer 3 of Evaluation Board
09441-088
TOP RESISTOR
FE E DBACK TAP
VOUT SENSE TAP LINE
EXTENDI NG BACK T O THE
TOP RESISTOR IN THE
FE E DBACK DIVI DE R
NETWORK. THIS OVERLAPS
WITH P GND SE NS E TAP
LINE EXTENDING TO THE
ANALOG GRO UND P LANE
09441-089
Data Sheet ADP1878/ADP1879
Rev. B | Page 35 of 40
Figure 90. Layer 4 (Bottom Layer) of Evaluation Board
IC SECTION (LEFT SIDE OF EVALUATION BOARD)
A dedicated plane for the analog ground plane (GND) should
be separate from the main power ground plane (PGND). With
the shortest path possible, connect the analog ground plane to
the GND pin (Pin 5). Place this plane on the top layer only of
the evaluation board. To avoid crosstalk interference, do not
allow any other voltage or current pathway directly below this
plane on Layer 2, Layer 3, or Layer 4. Connect the negative
terminals of all sensitive analog components to the analog
ground plane. Examples of such sensitive analog components
include the bottom resistor of the resistor divider, the high
frequency bypass capacitor for biasing (0.1 µF), and the
compensation network.
Mount a 1 µF bypass capacitor directly across the VREG pin
(Pin 7) and the PGND pin (Pin 11). In addition, tie a 0.1 µF
across the VREG pin (Pin 7) and the GND pin (Pin 5).
POWER SECTION
As shown in Figure 87, an appropriate configuration to localize
large current transfer from the high voltage input (VIN) to the
output (VOUT) and then back to the power ground is to put the
VIN plane on the left, the output plane on the right, and the main
power ground plane in between the two. Current transfers from
the input capacitors to the output capacitors, through Q1/Q2,
during the on state (see Figure 91). The direction of this current
(yellow arrow) is maintained as Q1/Q2 turns off and Q3/Q4 turns
on. When Q3/Q4 turns on, the current direction continues to be
maintained (red arrow) as it circles from the power ground
terminal of the bulk capacitor to the output capacitors, through
the Q3/Q4. Arranging the power planes in this manner minimizes
the area in which changes in flux occur if the current through
Q1/Q2 stops abruptly. Sudden changes in flux, usually at the
source terminals of Q1/Q2 and the drain terminal of Q3/Q4,
cause large dV/dt at the SW node.
The SW node is near the top of the evaluation board. The SW
node should use the least amount of area possible and be away
from any sensitive analog circuitry and components. This is
because the SW node is where most sudden changes in flux
density occur. When possible, replicate this pad onto Layer 2
and Layer 3 for thermal relief and eliminate any other voltage and
current pathways directly beneath the SW node plane. Populate
the SW node plane with vias, mainly around the exposed pad of
the inductor terminal and around the perimeter of the source of
Q1/Q2 and the drain of Q3/Q4.
The output voltage power plane (VOUT) is at the rightmost end of
the evaluation board. This plane should be replicated, descending
down to multiple layers with vias surrounding the inductor
terminal and the positive terminals of the output bulk capacitors.
Ensure that the negative terminals of the output capacitors are
placed close to the main power ground (PGND), as previously
mentioned. All of these points form a tight circle (component
geometry permitting) that minimizes the area of flux change as
the event switches between D and 1 − D.
BOTTOM
RESISTOR TAP
TO ANALOG
GROUND PL ANE
PGND SENSE TAP FROM
NEGATIVE TERMINALS OF
THE OUTP UT BUL K
CAPACI TORS . T HIS
TRACK P LACEME NT
SHO ULD BE DI RE CTL Y
BELOW T HE VOUT SENSE
LINE OF LAYER 3.
09441-090
ADP1878/ADP1879 Data Sheet
Rev. B | Page 36 of 40
Figure 91. Primary Current Pathways During the On State of the High-Side
MOSFET (Left Arrow) and the On State of the Low-Side MOSFET (Right Arrow)
DIFFERENTIAL SENSING
Because the ADP1878/ADP1879 operate in valley current-mode
control, a differential voltage reading is taken across the drain
and source of the low-side MOSFET. Connect the drain of the
low-side MOSFET s as close as possible to the SW pin (Pin 13) of
the IC. Likewise, connect the source as close as possible to the
PGND pin (Pin 11) of the IC. When possible, keep both of
these track lines narrow and away from any other active device
or voltage/current path.
Figure 92. Drain/Source Tracking Tapping of the Low-Side MOSFET for CS
Amp Differential Sensing (Yellow Sense Line on Layer 2)
In addition, employ differential sensing between the outermost
output capacitor and the feedback resistor divider (see Figure 89
and Figure 90). Connect the positive terminal of the output
capacitor to the top resistor (RT). Connect the negative terminal
of the output capacitor to the negative terminal of the bottom
resistor, which connects to the analog ground plane as well.
Keep both of these track lines, as previously mentioned, narrow
and away from any other active device or voltage/ current path.
09441-091
LAYER 1: SENSE LI NE FO R SW
(DRAIN OF LOWER MOSFET) LAYER 1: SENSE LINE FO R PGND
(SOURCE OF LOWER MOSFET)
PGND
SW
09441-092
Data Sheet ADP1878/ADP1879
Rev. B | Page 37 of 40
TYPICAL APPLICATION CIRCUITS
12 A, 300 kHz HIGH CURRENT APPLICATION CIRCUIT
Figure 93. Application Circuit for 12 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
5.5 V INPUT, 600 kHz CURRENT APPLICATION CIRCUIT
Figure 94. Application Circuit for 5.5 V Input, 2.5 V Output, 12 A, 600 kHz (Q2/Q4 No Connect)
MURAT A: ( HIGH V OL TAGE INPUT CAPACITORS)
22µF , 25V, X7R, 1210 GRM32E R71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TO RS )
270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTO RS :
1.2µH, 2mΩ, 20A, 744325120
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 12V
C
BST
100nF
V
OUT
= 1.8V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.2µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
14
BST
2
COMP
13
SW
3
EN
12
DRVH
5
GND
10
DRVL
ADP1878/
ADP1879
C
C
560pF
C
PAR
56pF R
C
49.3kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
11
PGND
6
RES
9
PGOOD
7
VREG
8
SS
5kΩ V
REG
C
SS
34nF
V
REG
09441-093
MURAT A: ( INPUT CAP ACIT ORS)
22µF , 25V, X7R, 1210 GRM32E R71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TO RS )
180µF (SP-SERIES), 4V, 10mΩ, EEFUE0G181XR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTO RS :
0.47µH, 0.8mΩ, 30A, 744355147
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 5.5V
C
BST
100nF
V
OUT
= 2.5V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
N/A +
C22
180µF +
C21
180µF +
C20
180µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
0.47µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
32kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
14
BST
2
COMP
13
SW
3
EN
12
DRVH
5
GND
10
DRVL
ADP1878/
ADP1879
C
C
220pF
C
F
22pF R
C
56.9kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
11
PGND
6
RES
9
PGOOD
7
VREG
8
SS
5kΩ V
REG
C
SS
34nF
V
REG
09441-094
ADP1878/ADP1879 Data Sheet
Rev. B | Page 38 of 40
300 kHz HIGH CURRENT APPLICATION CIRCUIT
Figure 95. Application Circuit for 13 V Input, 1.8 V Output, 12 A, 300 kHz (Q2/Q4 No Connect)
MURAT A: ( HIGH V OL TAGE INPUT CAPACITORS)
22µF , 25V, X7R, 1210 GRM32E R71E 226KE 15L
PANASONIC: ( OUT P UT CAPACI TO RS )
270µF (SP-SERIES), 4V, 7mΩ, EEFUE0G271LR
INFINEON MOSFETs:
BSC042N03MS G (L OW E R S IDE)
BSC080N03MS G (UPP E R S IDE)
WÜRTH INDUCTO RS :
1.2µH, 2mΩ, 20A, 744325120
Q3 Q4
Q1 Q2
HIGH VOLTAGE INPUT
V
IN
= 13V
C
BST
100nF
V
OUT
= 1.8V , 12A
C3
22µF C4
22µF C5
22µF C6
22µF C7
22µF C8
N/A C9
N/A
C23
270µF +
C22
270µF +
C21
270µF +
C20
270µF +
C27
N/A C14 TO C19
N/A
+
C26
N/A +
C25
N/A +
C24
N/A +
1.2µH
R
SNB
2Ω
C
SNB
1.5nF
R
TOP
2kΩ
R7 10kΩ
R
BOT
1kΩ
V
OUT
1
VIN
14
BST
2
COMP
13
SW
3
EN
12
DRVH
5
GND
10
DRVL
ADP1878/
ADP1879
C
C
560pF
C
PAR
56pF R
C
49.3kΩ
C1
1µF
C
VIN
22µF
C2
0.1µF
JP3
R
RES
100kΩ
4
FB
11
PGND
6
RES
9
PGOOD
7
VREG
8
SS
5kΩ V
REG
C
SS
34nF
V
REG
09441-095
Data Sheet ADP1878/ADP1879
Rev. B | Page 39 of 40
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
Figure 96. 14-Lead Lead Frame Chip Scale Package [LFCSP_WD]
4 mm × 3 mm Body, Very Very Thin Dual
(CP-14-2)
Dimensions shown in millimeters
101309-A
COMPLIANT
TO
JEDEC STANDARDS MO-229-WEGD
BOTTOM VIEW
TOP VIEW END VIEW
SIDE VIEW
1
7
814
SEATING
PLANE
0.80
0.75
0.70
0.30
0.25
0.20
0.05 MAX
0.02 NOM
0.15 REF
0.10
REF
0.90
REF
0.30
REF
0.50 BSC
COPLANARITY
0.08
PIN 1 INDICATOR
(LASER MARKING)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
0.50
0.40
0.30
1.80
1.70
1.55
3.40
3.30
3.15
3.10
3.00
2.90
4.10
4.00
3.90 0.20 MIN
ADP1878/ADP1879 Data Sheet
Rev. B | Page 40 of 40
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADP1878ACPZ-0.3-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1878ACPZ-0.6-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1878ACPZ-1.0-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1878-0.3-EVALZ Evaluation Board
ADP1878-0.6-EVALZ Evaluation Board
ADP1878-1.0-EVALZ Evaluation Board
ADP1879ACPZ-0.3-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1879ACPZ-0.6-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1879ACPZ-1.0-R7 −40°C to +125°C 14-Lead Frame Chip Scale Package [LFCSP_WD] CP-14-2
ADP1879-0.3-EVALZ
Evaluation Board
ADP1879-0.6-EVALZ Evaluation Board
ADP1879-1.0-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered
trademarks are the property of their
respective owners.
D09441-0-9/12(B)
www.analog.com/ADP1878/ADP1879
