CD74FCT240M96 - Texas Instruments

CD74FCT240

BiCMOS OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCBS729 – JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BiCMOS Technology With Low Quiescent

Power

Buffered Inputs

Inverted Outputs

Input/Output Isolation From VCC

Controlled Output Edge Rates

64-mA Output Sink Current

Output Voltage Swing Limited to 3.7 V

SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

Package Options Include Plastic

Small-Outline (M) and Shrink Small-Outline

(SM) Packages and Standard Plastic (E) DIP

description

The CD74FCT240 is an octal buffer/line driver with 3-state outputs, using a small-geometry BiCMOS

technology . The output stages are a combination of bipolar and CMOS transistors that limit the output high level

to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing

[a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their

effects during simultaneous output switching. The output configuration also enhances switching speed and is

capable of sinking 64 mA.

The CD74FCT240 is organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE)

inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs

are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT240 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each buffer/driver)

INPUTS OUTPUT

OE AY

L H L

LLH

H X Z

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

VCC

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

E, M, OR SM PACKAGE

(TOP VIEW)

CD74FCT240

BiCMOS OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCBS729 – JULY 2000

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol†

1A1 4

1A2 6

1A3 8

1A4

1Y1

1Y2

1Y3

1Y4

2A1 13

2A2 15

2A3 17

2A4

2Y1

2Y2

2Y3

2Y4

1OE

†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2OE EN

logic diagram (positive logic)

218

1Y1

1OE

1A1

416

1Y2

1A2

614

1Y3

1A3

812

1Y4

1A4

11 9 2Y1

2OE

2A1

13 7 2Y2

2A2

15 5 2Y3

2A3

17 3 2Y4

2A4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡

DC supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC input clamp current, IIK (VI < –0.5 V) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC output clamp current, IOK (VO < –0.5 V) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC output sink current per output pin, IOL 70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DC output source current per output pin, IOH –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC, ICC 140 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through GND 528 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 1): E package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

M package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SM package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

CD74FCT240

BiCMOS OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCBS729 – JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 2)

MIN MAX UNIT

VCC Supply voltage 4.75 5.25 V

VIH High-level input voltage 2 V

VIL Low-level input voltage 0.8 V

VIInput voltage 0 VCC V

VOOutput voltage 0 VCC V

IOH High-level output current –15 mA

IOL Low-level output current 64 mA

∆t/∆vInput transition rise or fall rate (slew rate) 0 10 ns/V

TAOperating free-air temperature 0 70 °C

NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST

CONDITIONS

CC MIN MAX

MIN

MAX

UNIT

VIK II = –18 mA 4.75 V –1.2 –1.2 V

VOH IOH = –15 mA 4.75 V 2.4 2.4 V

VOL IOL = 64 mA 4.75 V 0.55 0.55 V

IIVI = VCC or GND 5.25 V ±0.1 ±1

IOZ VO = VCC or GND 5.25 V ±0.5 ±10

IOS†VI = VCC or GND, VO = 0 5.25 V –60 –60 mA

ICC VI = VCC or GND, IO = 0 5.25 V 8 80

∆ICC‡One input at 3.4 V,

Other inputs at VCC or GND 5.25 V 1.6 1.6 mA

CiVI = VCC or GND 10 10 pF

CoVO = VCC or GND 15 15 pF

†Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms.

‡This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ± 0.25 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM TO TA = 25°C

MIN

MAX

UNIT

PARAMETER

(INPUT) (OUTPUT) TYP

MIN

MAX

UNIT

tpd AY5 1.5 8 ns

ten OE Y 7 1.5 10 ns

tdis OE Y 6 1.5 9.5 ns

noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C

PARAMETER MIN TYP MAX UNIT

VOL(P) Quiet output, maximum dynamic VOL 1 V

VOH(V) Quiet output, minimum dynamic VOH 0.5 V

VIH(D) High-level dynamic input voltage 2 V

VIL(D) Low-level dynamic input voltage 0.8 V

CD74FCT240

BiCMOS OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCBS729 – JULY 2000

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance No load, f = 1 MHz 38 pF

CD74FCT240

BiCMOS OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

SCBS729 – JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

tsu

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Data Input

tPLH

tPHL

tPLH

VOH

VOL

3 V

0 V

1.5 V1.5 V

Input

Out-of-Phase

Output

In-Phase

Output

Timing Input

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

Output

Control

Output

W aveform 1

(see Note B)

Output

W aveform 2

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈3.5 V

0 V

1.5 V VOL + 0.3 V

1.5 V ≈0 V

3 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open Drain

Open

7 V

Open

7 V

TEST S1

3 V

0 V

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

Input

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr and tf = 2.5 ns.

D. The outputs are measured one at a time with one input transition per measurement.

E. tPLZ and tPHZ are the same as tdis.

F. tPZL and tPZH are the same as ten.

G. tPHL and tPLH are the same as tpd.

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR

3-STATE AND OPEN-DRAIN OUTPUTS

S1 7 V

500 ΩGND

From Output

Under Test

CL = 50 pF

(see Note A)

Test

Point

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

Open

VOH – 0.3 V

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

1.5 V1.5 V

500 Ω

1.5 V 1.5 V

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

1.5 V

1.5 V 10%10% 90% 90% 3 V

0 V

trtf

Figure 1. Load Circuit and Voltage Waveforms

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CD74FCT240E OBSOLETE PDIP N 20 TBD Call TI Call TI

CD74FCT240M OBSOLETE SOIC DW 20 TBD Call TI Call TI

CD74FCT240M96 OBSOLETE SOIC DW 20 TBD Call TI Call TI

CD74FCT240SM OBSOLETE SSOP DB 20 TBD Call TI Call TI

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Sep-2008

Addendum-Page 1

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

4040065 /E 12/01

28 PINS SHOWN

Gage Plane

8,20

7,40

0,55

0,95

0,25

12,90

12,30

10,50

8,50

Seating Plane

9,907,90

10,50

9,90

0,38

5,60

5,00

0,22

2016

6,50

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65 M

0,15

0°–ā8°

0,10

0,09

0,25

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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