DG406/407
Vishay Siliconix
Document Number: 70061
S-00399—Rev. H, 13-Sep-99 www.siliconix.com FaxBack 408-970-5600
5-1
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
Low On-Resistance—rDS(on): 50
Low Charge Injection—Q: 15 pC
Fast Transition Time—tTRANS: 200 ns
Low Power: 0.2 mW
Single Supply Capability
44-V Supply Max Rating
Higher Accuracy
Reduced Glitching
Improved Data Throughput
Reduced Power Consumption
Increased Ruggedness
Wide Supply Ranges: 5 V to 20 V
Data Acquisition Systems
Audio Signal Routing
Medical Instrumentation
ATE Systems
Battery Powered Systems
High-Rel Systems
Single Supply Systems
The DG406 is a 16-channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common output as
determined by a 4-bit binary address. The DG407 selects one of
eight differential inputs to a common differential output.
Break-before-make switching action protects against momentary
shorting of inputs.
An on channel conducts current equally well in both directions. In
the off state each channel blocks voltages up to the power supply
rails. An enable (EN) function allows the user to reset the
multiplexer/demultiplexer to all switches off for stacking several
devices. All control inputs, address (Ax) and enable (EN) are TTL
compatible over the full specified operating temperature range.
Applications for the DG406/407 include high speed data
acquisition, audio signal switching and routing, ATE systems, and
avionics. High performance and low power dissipation make
them ideal for battery operated and remote instrumentation
applications. For additional application information order Faxback
document numbers 70601 and 70604.
Designed in the 44-V silicon-gate CMOS process, the absolute
maximum voltage rating is extended to 44 volts, allowing
operation with 20-V supplies. Additionally single (12-V) supply
operation is allowed. An epitaxial layer prevents latchup.
For applications information please request FaxBack documents
70601 and 70604.
DG407
V+
S3b
S2b
S1b
NC
NC
Da
S2a
S1a
GND
A1
A2
Db
Dual-In-Line and SOIC Wide-Body
A0
EN
V–
NC S8a
S8b S7a
S7b S6a
S6b S5a
S5b S4a
S4b S3a
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
920
10 19
11
12
18
17
13 16
14 15
V+
S11
S10
S9
NC
A3
D
S2
S1
GND
A1
A2
NC
Dual-In-Line and SOIC Wide-Body
A0
EN
V–
NC S8
S16 S7
S15 S6
S14 S5
S13 S4
S12 S3
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
Top View
920
10 19
11
12
18
17
13 16
14 15
DG406
Decoders/Drivers Decoders/Drivers
DG406/407
Vishay Siliconix
www.siliconix.com S FaxBack 408-970-5600
5-2 Document Number: 70061
S-00399—Rev. H, 13-Sep-99
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Decoders/Drivers
PLCC and LCC
7
8
9
5
20
19
21
22
23
24
25
1234
10
11
12 13 14 15 16 17 18
262728
Top View
6
S7b
S5a
S4b S4a
S7a
S3b
S6b S6a
S3a
S5b
S2b S2a
S1b S1a
PLCC and LCC
Top View
GND
NCNC
DNC
V+
D
V–
EN
S
2
1
0S
A
A
A
8b
8a
b
a
DG407
S13
S15
S5
S12 S4
S7
S11
S14 S6
S3
S10 S2
S9S1
SGND
NCNC
NC
3
V+
2D
1
V–
0SEN
DG406
A
A
A
A
16
8
Decoders/Drivers
7
8
9
5
20
19
21
22
23
24
25
1234
10
11
12 13 14 15 16 17 18
262728
6
TRUTH TABLE Ċ DG406
A3A2A1A0EN On Switch
X X X X 0 None
00001 1
00011 2
00101 3
00111 4
01001 5
01011 6
01101 7
01111 8
10001 9
10011 10
10101 11
10111 12
11001 13
11011 14
11101 15
11111 16
TRUTH TABLE Ċ DG407
A2A1A0EN On Switch Pair
X X X 0 None
0001 1
0011 2
0101 3
0111 4
1001 5
1011 6
1101 7
1111 8
Logic “0” = V AL v 0.8 V
L
og
i
c
“1” =V
AH
w 2.4 V
Logic
1
=
V
AH
w
2
.
4
V
X = Don’t Care
ORDERING INFORMATION Ċ DG406
Temp Range Package Part Number
40 85 C
28-Pin Plastic DIP DG406DJ
–40 to 85_C28-Pin PLCC DG406DN
28-Pin Widebody SOIC DG406DW
–
55 to 125
_
C
28-Pin CerDIP DG406AK/883,
5962-9562301QXA
–
55
to
125_C
LCC-28 DG406AZ/883,
5962-9562301Q3A
ORDERING INFORMATION Ċ DG407
Temp Range Package Part Number
40 85 C
28-Pin Plastic DIP DG407DJ
–40 to 85_C28-Pin PLCC DG407DN
28-Pin Widebody SOIC DG407DW
–
55 to 125
_
C
28-Pin CerDIP DG407AK/883’
5962-9562302QXA
–
55
to
125_C
LCC-28 DG407AZ/883
5962-9562302Q3A
DG406/407
Vishay Siliconix
Document Number: 70061
S-00399—Rev. H, 13-Sep-99 www.siliconix.com S FaxBack 408-970-5600
5-3
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to V–
V+ 44 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GND 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputsa, VS, VD(V–) –2 V to (V+) +2 V or. . . . . . . . . . . . . . . . . . . . . . . .
20 mA, whichever occurs first
Current (Any Terminal,) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 100 mA. . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature (AK, AZ Suffix) –65 to 150_C. . . . . . . . . . . . . .
(DJ, DN Suffix) –65 to 125_C. . . . . . . . . . . . . .
Power Dissipation (Package)b
28-Pin Plastic DIPc625 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin CerDIPd1.2 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Plastic PLCCc450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LCC-28e1.35 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Widebody SOIC 450 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. Signals on SX, DX or INX exceeding V+ or V– will be clamped by internal
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6 mW/_C above 75_C
d. Derate 12 mW/_C above 75_C
e. Derate 13.5 mW/_C above 75_C
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –15 V
VAL = 0.8 V, VAH = 2.4 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full –15 15 –15 15 V
Drain-Source On-Resistance rDS(on) VD = "10 V, IS = –10 mA
Sequence Each Switch On Room
Full 50 100
125 100
125 W
rDS(on) Matching Between
ChannelsgDrDS(on) VD = "10 V Room 5 %
Source Off
Leakage Current IS(off)
V0V
Room
Full 0.01 –0.5
–50 0.5
50 –0.5
–5 0.5
5
A
Drain Off
Lk C t
ID(off)
VEN = 0 V
VD = "10 V
V
S
= #10 V DG406 Room
Full 0.04 –1
–200 1
200 –1
–40 1
40
A
Leakage Current
I
D(off)
VS
=
#10
V
DG407 Room
Full 0.04 –1
–100 1
100 –1
–20 1
20 nA
Drain On
Lk C t
ID(on)
VS = VD = "10 V
Sequence Each
DG406 Room
Full 0.04 –1
–200 1
200 –1
–40 1
40
Leakage Current
I
D(on)
Sequence
Each
Switch On DG407 Room
Full 0.04 –1
–100 1
100 –1
–20 1
20
Digital Control
Logic High Input Voltage VINH Full 2.4 2.4
V
Logic Low Input Voltage VINL Full 0.8 0.8
V
Logic High Input Current IAH VA = 2.4 V, 15 V Full –1 1 –1 1
mA
Logic Low Input Current IAL VEN = 0 V, 2.4 V, VA = 0 V Full –1 1 –1 1 m
A
Logic Input Capacitance Cin f = 1 MHz Room 7 pF
Dynamic Characteristics
Transition Time tTRANS See Figure 2 Room
Full 200 350
450 350
450
Break-Before-Make Interval tOPEN See Figure 4 Room
Full 50 25
10 25
10
ns
Enable T urn-On T ime tON(EN)
See Figure 3
Room
Full 150 200
400 200
400
ns
Enable T urn-Of f Time tOFF(EN)
See
Figure
3
Room
Full 70 150
300 150
300
Charge Injection Q CL = 1 nF, VS = 0 V, Rs = 0 WRoom 15 pC
Off IsolationhOIRR VEN = 0 V, RL = 1 kW
f = 100 kHz Room –69 dB
Source Off Capacitance CS(off) VEN = 0 V, VS = 0 V, f = 1 MHz Room 8
F
Drain Off Capacitance
CD(off)
V0VV0V
Room 130
F
Drain
Off
Capacitance
C
D(off) VEN = 0 V, VD = 0 V
f1MH
DG407 Room 65 pF
Drain On Capacitance
CD(on)
EN ,D
f = 1 MHz DG406 Room 140
Drain
On
Capacitance
C
D(on) DG407 Room 70
DG406/407
Vishay Siliconix
www.siliconix.com S FaxBack 408-970-5600
5-4 Document Number: 70061
S-00399—Rev. H, 13-Sep-99
D Suffix
–40 to 85_C
A Suffix
–55 to 125_C
Test Conditions
Unless Otherwise Specified
Parameter UnitMaxd
Mind
Maxd
Mind
Typc
Tempb
V+ = 15 V, V– = –15 V
VAL = 0.8 V, VAH = 2.4 Vf
Symbol
Power Supplies
Positive Supply Current I+
VEN =V
A=0or5V
Room
Full 13 30
75 30
75
A
Negative Supply Current I–
V
EN =
V
A =
0
or
5
V
Room
Full –0.01 –1
–10 –1
–10
mA
Positive Supply Current I+
VEN
=
2.4 V, VA
=
0 V
Room
Full 50 500
900 500
700
m
A
Negative Supply Current I–
V
EN =
2
.
4
V
,
V
A =
0
V
Room
Full –0.01 –20
–20 –20
–20
Test Conditions
Unless Otherwise Specified
V12VV0V
A Suffix
–55 to 125_CD Suffix
–40 to 85_C
Parameter Symbol V+ = 12 V, V– = 0 V
VAL = 0.8 V, VAH = 2.4 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal RangeeVANALOG Full 0 12 0 12 V
Drain-Source
On-Resistance rDS(on) VD = 3 V, 10 V, IS = – 1 mA
S E hS it hO
Room 90 120 120 W
rDS(on) Matching Between
ChannelsgDrDS(on)
D,,
S
Sequence Each Switch On Room 5 %
Source Off
Leakage Current IS(off) VEN = 0 V
V 10Vor05V
Room 0.01
A
Drain Off
Lk C t
ID(off)
EN
VD = 10 V or 0.5 V
V
S
= 0.5 V or 10 V DG406 Room 0.04
nA
Leakage Current
I
D(off)
VS
=
0
.
5
V
or
10
V
DG407 Room 0.04 nA
Drain On
Lk C t
ID(on)
VS = VD = 10 V
S E hS it hO
DG406 Room 0.04
Leakage Current
I
D(on)
SD
Sequence Each Switch On DG407 Room 0.04
Dynamic Characteristics
Switching T ime of Multiplexer tTRANS VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V Room 300 450 450
Enable T urn-On T ime tON(EN) VINH = 2.4 V, VINL = 0 V
V5V
Room 250 600 600 ns
Enable T urn-Of f Time tOFF(EN)
INH ,INL
VS1 = 5 V Room 150 300 300
Charge Injection Q CL = 1 nF, VS= 6 V, RS = 0 Room 20 pC
Power Supplies
Positive Supply Current I+
VEN =0Vor5VV
A=0Vor5V
Room
Full 13 30
75 30
75
mA
Negative Supply Current I–
V
EN =
0
V
or
5
V
,
V
A =
0
V
or
5
V
Room
Full –0.01 –20
–20 –20
–20
m
A
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONL Y, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. DrDS(on) = rDS(on) MAX – rDS(on) MIN.
h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin.
DG406/407
Vishay Siliconix
Document Number: 70061
S-00399—Rev. H, 13-Sep-99 www.siliconix.com S FaxBack 408-970-5600
5-5
_
rDS(on) vs. VD and Supply rDS(on) vs. VD and Temperature
ID , IS Leakage Currents vs. Analog Voltage
VD – Drain Voltage (V)
VS , VD – Source Drain Voltage (V)
VD – Drain Voltage (V)
VD – Drain Voltage (V)
rDS(on) vs. VD and Supply
– Current (pA), I S
ID
160
120
80
40
0–20 20–4–12 4 12
5 V
10 V
12 V
15 V
20 V
8 V
0
40
30
20
10
80
70
60
50
15105–15 –10 –5 0
–55_C
–40_C
0_C
25_C
85_C
125_C
V+ = 15 V
V– = –15 V
160
120
80
40
00204 8 12 16
V+ = 7.5 V
200
240 V– = 0 V
10 V
12 V
15 V 20 V 22 V
120
–120–15 –10 –5 0 5 10 15
–80
–40
0
40
80
V+ = 15 V
V– = –15 V
VS = –VD for ID(off)
VD = VS(open) for ID(on)
DG406 ID(on), ID(off)
IS(off)
DG407 ID(on), ID(off)
– On-Resistance (rDS(on) )– On-Resistance (rDS(on) )
– On-Resistance (rDS(on) )
ID , IS Leakages vs. Temperature Switching Times vs. Bipolar Supplies
Temperature (_C) VSUPPLY – Supply Voltage (V)
T ime (ns)
– Current , I S
ID
V+ = 15 V
V– = –15 V
VD = ”14 V
ID(on), ID(off)
IS(off)
100 nA
10 nA
1 nA
100 pA
10 pA
1 pA
0.1 pA–55 –35 –15 5 25 45 65 85 105 125
350
300
150
100
50
0
510 15 20
200
250 tTRANS
tON(EN)
tOFF(EN)
DG406/407
Vishay Siliconix
www.siliconix.com S FaxBack 408-970-5600
5-6 Document Number: 70061
S-00399—Rev. H, 13-Sep-99
_
Switching Times vs. Single Supply Charge Injection vs. Analog Voltage
V+ – Supply Voltage (V) VS – Source Voltage (V)
Q (pC)
T ime (ns)
700
600
300
200
100
0510 1520
400
500
tTRANS
tON(EN)
tOFF(EN)
V– = 0 V
0
40
30
20
10
70
60
50
15105–15 –10 –5 0
V+ = 15 V,
V– = –15 V
V+ = 12 V,
V– = 0 V
Off-Isolation vs. Frequency Supply Currents vs. Switching Frequency
f – Frequency (Hz) f – Frequency (Hz)
I – Current (mA)
ISOL (dB)
–80
–60
–40
–20
010 k 100 k 1 M 10 M
–100
–120
1 k100
–140 10
–10 10 100 1 k 10 k 100 k 1 M 10 M
–8
–6
0
4
6
IGND
–4
–2
2
8
I–
I+
EN = 5 V
AX = 0 or 5 V
tON/tOFF vs. Temperature Switching Threshold vs. Supply Voltage
Temperature (_C) VSUPPLY – Supply Voltage (V)
(V)VTH
T ime (ns)
180
140
100
60
220
tON(EN)
tOFF(EN)
tTRANS
260
300
V+ = 15 V
V– = –15 V
3
1
05101520
2
0
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇ
–55 –35 125–15 5 25 45 65 85 105
DG406/407
Vishay Siliconix
Document Number: 70061
S-00399—Rev. H, 13-Sep-99 www.siliconix.com FaxBack 408-970-5600
5-7
FIGURE 1.
EN
A0
GND
S1
V+
D
V+
Sn
V–
Decode/
Drive
Level
Shift
V–
V+
VREF
AX
FIGURE 2. Transition Time
Logic
Input
Switch
Output
VS8
VO
tTRANS
tr <20 ns
tf <20 ns
S8 ONS1 ON tTRANS
0 V
VS1
50%
90%
90%
3 V
0 V
DG406
S1b
S8b
A2
Db
A1
*
A0
* = S1a – S8a, S2b – S7b, Da
50 300
VO
#10 V
"10 V
+2.4 V
+15 V
–15 V
EN V+
V–GND 35 pF
S1
S2 – S15
S16
A2
A1
A0
50 300
VO
A3
#10 V
"10 V
+2.4 V
+15 V
–15 V
EN V+
V–GND D
35 pF
DG407
DG406/407
Vishay Siliconix
www.siliconix.com FaxBack 408-970-5600
5-8 Document Number: 70061
S-00399—Rev. H, 13-Sep-99
FIGURE 3. Enable Switching Time
VO
tr <20 ns
tf <20 ns
VO
Logic
Input
tON(EN)
90%
Switch
Output
50%
tOFF(EN)
3 V
0 V
0 V
A1
50
A0
S1
VO
A2–5 V
+15 V
–15 V 300
EN
S2 – S16
V+
V–GND D
35 pF
A3
VO
S1b
A2S1a – S8a
S2b – S8b
A1
Da and Db
A0
50 300
+15 V
–15 V
EN
V+
V–GND 35 pF
DG406
DG407
–5 V
90%
FIGURE 4. Break-Before-Make Interval
50%
80%
Logic
Input
Switch
Output
VO
VS
tOPEN
tr <20 ns
tf <20 ns
0 V
3 V
0 V
50
A0
All S and Da
300
A3
D,Db
A1
A2
+2.4 V
+15 V
–15 V
EN V+
V–
VO
GND
+5 V
35 pF
DG406
DG407
DG406/407
Vishay Siliconix
Document Number: 70061
S-00399—Rev. H, 13-Sep-99 www.siliconix.com FaxBack 408-970-5600
5-9
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
tTRANS is given on the data sheet. Settling time at the load
depends on several parameters: rDS(on) of the multiplexer,
source impedance, multiplexer and load capacitances, charge
injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived from
the model shown in Figure 5. Assuming a low impedance
signal source like that presented by an op amp or a buffer
amplifier, the settling time of the RC network for a given
accuracy is equal to nt:
0.25 8 6
0.012 12 9
0.0017 15 11
RS = 0
rDS(on) VOUT
CD(on)
FIGURE 5. Simplified Model of One Multiplexer Channel
The maximum sampling frequency of the multiplexer is:
(1)fs = 1
N (tSETTLING + tTRANS)
where N = number of channels to scan
tSETTLING = nt = n x rDS(on) x CD(on)
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
(2)fs+1
16 (9 x 100 Wx10
–12F) )300 x 10–12 s
or
(3)fs = 694 kHz
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice the
maximum component frequency of the original signal. This
assumes perfect bandlimiting. In a real application sampling at
three to four times the filter cutoff frequency is a good practice.
Therefore from equation 2 above:
(4)fc = 1
4x fs = 173 kHz
From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its cutoff
frequency can be doubled.
The block diagram shown in Figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since this
method helps to reject any common mode noise. This is
especially important when the sensors are located at a
distance and it may eliminate the need for individual amplifiers.
A low rDS(on), low leakage multiplexer like the DG407 helps to
reduce measurement errors. The low power dissipation of the
DG407 minimizes on-chip thermal gradients which can cause
errors due to temperature mismatch along the parasitic
thermocouple paths. Please refer to Application Note AN203
for additional information.
12-Bit
A/D
Converter
Analog
Multiplexer
DG407
Controller
To
Sensor 1
To
Sensor 8
Inst
Amp S/H
FIGURE 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique.
