TN80C186EA20SF12 - Intel - Datasheet.Live

Intel®80C186EA/80C188EA AND

80L186EA/80L188EA

16-Bit High-Integration Embedded Processors

Datasheet

■

Intel®80C186 Upgrade for Power Critical Applications

■

Fully Static Operation

■

True CMOS Inputs and Outputs

Product Features

The Intel®80C186EA is a CHMOS high integration embedded microprocessor. The Intel®

80C186EA includes all of the features of an ``Enhanced Mode'' Intel®80C186 while adding the

additional capabilities of Idle and Powerdown Modes. In Numerics Mode, the Intel®80C186EA

interfaces directly with an Intel®80C187 Numerics Coprocessor.

■Integrated Feature Set

—Static 186 CPU Core

—Power Save, Idle and Powerdown

Modes

—ClockGenerator

—2 Independent DMA Channels

—3 Programmable 16-Bit Timers

—Dynamic RAM Refresh Control Unit

—Programmable Memory and Peripheral

Chip Select Logic

—Programmable Wait State Generator

—Local Bus Controller

—System-Level Testing Support (High

Impedance Test Mode)

■Speed Versions Available (3V)

—13MHz(Intel®80L186EA13/

80L188EA13)

■Direct Addressing Capability to 1 Mbyte

Memoryand64KbyteI/O

■Supports Intel®80C187 Numeric

Coprocessor Interface (Intel®80C186EA

only)

■Available in the Following Packages:

—68-Pin Plastic Leaded Chip Carrier

(PLCC)

■Available in Extended Temperature Range

(-40°C to +85°C)

■Speed Versions Available (5V):

—25 MHz (Intel®80C186EA25/80C188EA25)

—20 MHz (Intel®80C186EA20/80C188EA20)

—13 MHz (Intel®80C186EA13/80C188EA13)

Order Number: 272432-005

April 2002

2Datasheet

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intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel®80C186EA/80C188EA AND 80L186EA/80L188EA may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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Datasheet 3
Contents
Contents
0 Introduction....................................................................................................................................7
0 Intel® 80C186EA Core Architecture.............................................................................................9
1 Bus Interface Unit .................................................................................................................9
2 Clock Generator....................................................................................................................9
0 Intel® 80C186EA Peripheral Architecture .................................................................................11
1 Interrupt Control Unit ..........................................................................................................11
2 Timer/Counter Unit .............................................................................................................11
3 DMA Control Unit................................................................................................................14
4 Chip-Select Unit..................................................................................................................14
5 Refresh Control Unit ...........................................................................................................14
6 Power Management............................................................................................................14
7 80C187 Interface (80C186EA Only)...................................................................................15
8 ONCE Test Mode ...............................................................................................................15
0 Intel® 80C186XL and Intel® 80C186EA Differences.................................................................16
1 Pinout Compatibility............................................................................................................16
2 Operating Modes ................................................................................................................16
3 TTL vs. CMOS Inputs .........................................................................................................16
4 Timing Specifications..........................................................................................................16
5 Package Information...........................................................................................................17
6 Pin Descriptions..................................................................................................................17
0 Intel® 80C186EA Pinout..............................................................................................................22
0 Package Thermal Specifications................................................................................................24
0 Electrical Specification ...............................................................................................................25
1 Absolute Maximum Ratings*...............................................................................................25
2 Recommended Connections ..............................................................................................25
0 DC Specifications........................................................................................................................26
1 ICC Versus Frequency and Voltage ...................................................................................28
2 PDTMR Pin Delay Calculation............................................................................................29

Contents
4Datasheet
0 AC Specifications........................................................................................................................30
0 AC Test Conditions.....................................................................................................................34
0 AC Timing Waveforms................................................................................................................35
0 Derating Curves...........................................................................................................................38
0 Reset.............................................................................................................................................39
0 Bus Cycle Waveforms.................................................................................................................42
0 Product Name Execution Timings.............................................................................................49
0 Revision History..........................................................................................................................56
0 Errata............................................................................................................................................56

Datasheet 5
Contents
Figures
Product Name Block Diagram ......................................................................................................8
Clock Configurations...................................................................................................................10
68-Lead PLCC Pinout Diagram..................................................................................................23
AC Test Load..............................................................................................................................34
Input and Output Clock Waveform..............................................................................................35
Output Delay and Float Waveform .............................................................................................35
Input Setup and Hold..................................................................................................................36
Relative Signal Waveform ..........................................................................................................37
Typical Output Delay Variations Versus Load Capacitance.......................................................38
Typical Rise and Fall Variations Versus Load Capacitance.......................................................38
Powerup Reset Waveforms........................................................................................................40
Warm Reset Waveforms.............................................................................................................41
Read, Fetch and Refresh Cycle Waveform................................................................................42
Write Cycle Waveform................................................................................................................43
Halt Cycle Waveform..................................................................................................................44
INTA Cycle Waveform................................................................................................................45
HOLD/HLDA Waveform..............................................................................................................46
DRAM Refresh Cycle During Hold Acknowledge .......................................................................47
Ready Waveform........................................................................................................................48
Instruction Set Summary ............................................................................................................50
Tables
Peripheral Control Block Registers.............................................................................................12
Intel® 80C186EA Slave Mode Peripheral Control Block Registers............................................13
Prefix Identification .....................................................................................................................17
Pin Description Nomenclature....................................................................................................18
Pin Descriptions..........................................................................................................................19
PLCC Pin Names with Package Location...................................................................................22
PLCC Package Location with Pin Names...................................................................................22
Thermal Resistance (qCA) at Various Airflows (in °C/Watt).......................................................24
DC SPECIFICATIONS (80C186EA/80C188EA) ........................................................................26
DC SPECIFICATIONS (80L186EA/80L188EA)..........................................................................27
CDEV Values..............................................................................................................................28
AC Characteristics—80C186EA25/80C186EA20/80C186EA13................................................30
AC Characteristics—80L186EA13/80C186EA8 .........................................................................32
Relative Timings (80C186EA25/20/13, 80L186EA13)................................................................33

Contents

6Datasheet

Revision History

Date Revision Description

June 2002 005 Discontinued device reference removal and reformatting.

April 2002 004 Datasheet updates

Introduction

Product Name Datasheet 7

1.0 Introduction

Unless specifically noted, all references to the Intel® 80C186EA apply to the Intel®80C188EA,

Intel®80L186EA, and Intel®80L188EA. References to pins that differ between the Intel®

80C186EA/80L186EA and the Intel®80C188EA/ 80L188EA are given in parentheses. The “L” in

the part number denotes low voltage operation. Physically and functionally, the “C” and “L”

devices are identical.

The 80C186EA is the second product in a new generation of low-power, high-integration

microprocessors. It enhances the existing Intel®80C186XL family by offering new features and

operating modes. The 80C186EA is object code compatible with the 80C186XL embedded

processor.

The 80L186EA is the 3V version of the 80C186EA. The 80L186EA is functionally identical to the

80C186EA embedded processor. Current 80C186EA customers can easily upgrade their designs to

use the 80L186EA and benefit from the reduced power consumption inherent in 3V operation.

The feature set of the 80C186EA/80L186EA meets the needs of low-power, space-critical

applications. Low-power applications benefit from the static design of the CPU core and the

integrated peripherals as well as low voltage operation. Minimum current consumption is achieved

by providing a Powerdown Mode that halts operation of the device, and freezes the clock circuits.

Peripheral design enhancements ensure that non-initialized peripherals consume little current.

Space-critical applications benefit from the integration of commonly used system peripherals. Two

flexible DMA channels perform CPU-independent data transfers. A flexible chip select unit

simplifies memory and peripheral interfacing. The interrupt unit provides sources for up to

128 external interrupts and will prioritize these interrupts with those generated from the on-chip

peripherals. Three general purpose timer/counters round out the feature set of the 80C186EA.

Figure 1 shows a block diagram of the 80C186EA/ 80C188EA. The Execution Unit (EU) is an

enhanced 8086 CPU core that includes: dedicated hardware to speed up effective address

calculations, enhance execution speed for multiple-bit shift and rotate instructions and for multiply

and divide instructions, string move instructions that operate at full bus bandwidth, ten new

instructions, and static operation. The Bus Interface Unit (BIU) is the same as that found on the

original 80C186 family products. An independent internal bus is used to allow communication

between the BIU and internal peripherals.

Introduction

8Product Name Datasheet

Figure 1. Product Name Block Diagram

Note:

Pin names in parentheses apply to the 80C186EA / 80L188EA

Intel® 80C186EA Core Architecture

Product Name Datasheet 9

2.0 Intel®80C186EA Core Architecture

2.1 Bus Interface Unit

The 80C186EA core incorporates a bus controller that generates local bus control signals. In

addition, it employs a HOLD/HLDA protocol to share the local bus with other bus masters.

The bus controller is responsible for generating 20 bits of address, read and write strobes, bus cycle

status information and data (for write operations) information. It is also responsible for reading

data off the local bus during a read operation. SRDY and ARDY input pins are provided to extend

a bus cycle beyond the minimum four states (clocks).

The local bus controller also generates a control signal (DEN) when interfacing to external

transceiver chips. This capability allows the addition of transceivers for simple buffering of the

multiplexed address/data bus.

2.2 Clock Generator

The processor provides an on-chip clock generator for both internal and external clock generation.

The clock generator features a crystal oscillator, a divideby- two counter, and two low-power

operating modes.

The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-

overtone mode crystal network. Alternatively, the oscillator circuit may be driven from an external

clock source. Figure 2 shows the various operating modes of the oscillator circuit.

The crystal or clock frequency chosen must be twice the required processor operating frequency

due to the internal divide-by-two counter. This counter is used to drive all internal phase clocks and

the external CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to

drive other system components. All AC timings are referenced to CLKOUT.

The following parameters are recommended when choosing a crystal:

Temperature Range: Application Specific

ESR (Equivalent Series Resistance): 60 Ωmax

C0 (Shunt Capacitance of Crystal): 7 pF max

CL(Load Capacitance): 20 pF ± 2 pF

Drive Level: 2 mW maximum

Intel® 80C186EA Core Architecture

10 Product Name Datasheet

Figure 2. Clock Configurations

Note:

The L1C1 network is only required when using a third-overtone crystal.

272432±3

(A) Crystal Connection

272432±4

(B) Clock Connection

Intel® 80C186EA Peripheral Architecture

Product Name Datasheet 11

3.0 Intel®80C186EA Peripheral Architecture

The 80C186EA has integrated several common system peripherals with a CPU core to create a

compact, yet powerful system. The integrated peripherals are designed to be flexible and provide

logical interconnections between supporting units (e.g., the interrupt control unit supports interrupt

requests from the timer/counters or DMA channels).

The list of integrated peripherals include:

•4-Input Interrupt Control Unit

•3-Channel Timer/Counter Unit

•2-Channel DMA Unit

•13-Output Chip-Select Unit

•Refresh Control Unit

•Power Management Logic

The registers associated with each integrated peripheral are contained within a 128 x 16 register

file called the Peripheral Control Block (PCB). The PCB can be located in either memory or I/O

space on any 256 byte address boundary.

Table 1 provides a list of the registers associated with the PCB when the processor's Interrupt

Control Unit is in Master Mode. In Slave Mode, the definitions of some registers change. Table 2

provides register definitions specific to Slave Mode.

3.1 Interrupt Control Unit

The 80C186EA can receive interrupts from a number of sources, both internal and external. The

Interrupt Control Unit (ICU) serves to merge these requests on a priority basis, for individual

service by the CPU. Each interrupt source can be independently masked by the Interrupt Control

Unit or all interrupts can be globally masked by the CPU.

Internal interrupt sources include the Timers and DMA channels. External interrupt sources come

from the four input pins INT3:0. The NMI interrupt pin is not controlled by the ICU and is passed

directly to the CPU. Although the timers only have one request input to the ICU, separate vector

types are generated to service individual interrupts within the Timer Unit.

3.2 Timer/Counter Unit

The 80C186EA Timer/Counter Unit (TCU) provides three 16-bit programmable timers. Two of

these are highly flexible and are connected to external pins for control or clocking. A third timer is

not connected to any external pins and can only be clocked internally. However, it can be used to

clock the other two timer channels. The TCU can be used to count external events, time external

events, generate non-repetitive waveforms, generate timed interrupts, etc.

Intel® 80C186EA Peripheral Architecture

12 Product Name Datasheet

Table 1. Peripheral Control Block Registers

PCB

Offset Function PCB

Offset Function

00H Reserved 40H Reserved 80H Reserved C0H DMA0 Src. Lo

02H Reserved 42H Reserved 82H Reserved C2H DMA0 Src. Hi

04H Reserved 44H Reserved 84H Reserved C4H DMA0 Dest. Lo

06H Reserved 46H Reserved 86H Reserved C6H

08H Reserved 48H Reserved 88H Reserved C8H DMA0 Count

0AH Reserved 4AH Reserved 8AH Reserved CAH DMA0 Control

OCH Reserved 4CH Reserved 8CH Reserved CCH Reserved

0EH Reserved 4EH Reserved 8EH Reserved CEH Reserved

10H Reserved 50H Timer 0 Count 90H Reserved D0H DMA1 Src. Lo

12H Reserved 52H Timer 0 Compare A 92H Reserved D2H DMA1 Src. Hi

14H Reserved 54H Timer 0 Compare B 94H Reserved D4H DMA1 Dest. Lo

16H Reserved 56H Timer 0 Control 96H Reserved D6H DMA1 Dest. Hi

18H Reserved 58H Timer 1 Count 98H Reserved D8H DMA1 Count

1AH Reserved 5AH Timer 1 Compare A 9AH Reserved DAH DMA1 Control

1CH Reserved 5CH Timer 1 Compare B 9CH Reserved DCH Reserved

1EH Reserved 5EH Timer 1 Control 9EH Reserved DEH Reserved

20H Reserved 60H Timer 2 Count A0H UMCS E0H Refresh Base

22H End of Interrupt 62H Timer 2 Compare A2H LMCS E2H Refresh Time

24H Poll 64H Reserved A4H PACS E4H Refresh Control

26H Poll Status 66H Timer 2 Control A6H MMCS E6H Reserved

28H Interrupt Mask 68H Reserved A8H MPCS E8H Reserved

2AH Priority Mask 6AH Reserved AAH Reserved EAH Reserved

2CH In-Service 6CH Reserved ACH Reserved ECH Reserved

2EH Interrupt Request 6EH Reserved AEH Reserved EEH Reserved

30H Interrupt Status 70H Reserved B0H Reserved F0H Power-Save

32H Timer Control 72H Reserved B2H Reserved F2H Power Control

34H DMA0 Int. Control 74H Reserved B4H Reserved F4H Reserved

36H DMA0 Int. Control 76H Reserved B6H Reserved F6H Step ID

38H INT0 Control 78H Reserved B8H Reserved F8H Reserved

3AH INT1 Control 7AH Reserved BAH Reserved FAH Reserved

3CH INT2 Control 7CH Reserved BCH Reserved FCH Reserved

3EH INT3 Control 7EH Reserved BEH Reserved FEH Relocation

Intel® 80C186EA Peripheral Architecture

Product Name Datasheet 13

Table 2. Intel®80C186EA Slave Mode Peripheral Control Block Registers

PCB Offset Function

20H Interrupt Vector

22H Specific EOI

24H Reserved

26H Reserved

28H Interrupt Mask

2AH Priority Mask

2C In-Service

2E Interrupt Request

30 Interrupt Status

32 TMR0 Interrupt Control

34 DMA0 Interrupt Control

36 DMA1 Interrupt Control

38 TMR1 Interrupt Control

3A TMR2 Interrupt Control

3C Reserved

3E Reserved

Intel® 80C186EA Peripheral Architecture

14 Product Name Datasheet

3.3 DMA Control Unit

The 80C186EA DMA Control Unit provides two independent high-speed DMA channels. Data

transfers can occur between memory and I/O space in any combination: memory to memory,

memory to I/O, I/O to I/O or I/O to memory. Data can be transferred either in bytes or words.

Transfers may proceed to or from either even or odd addresses, but even-aligned word transfers

proceed at a faster rate. Each data transfer consumes two bus cycles (a minimum of eight clocks),

one cycle to fetch data and the other to store data. The chip-select/ready logic may be programmed

to point to the memory or I/O space subject to DMA transfers in order to provide hardware chip

select lines. DMA cycles run at higher priority than general processor execution cycles.

3.4 Chip-Select Unit

The 80C186EA Chip-Select Unit integrates logic which provides up to 13 programmable chip-

selects to access both memories and peripherals. In addition, each chip-select can be programmed

to automatically terminate a bus cycle independent of the condition of the SRDY and ARDY input

pins. The chip-select lines are available for all memory and I/O bus cycles, whether they are

generated by the CPU, the DMA unit, or the Refresh Control Unit.

3.5 Refresh Control Unit

The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to

keep dynamic or pseudo-static memory refreshed. A 9-bit counter controls the number of clocks

between refresh requests.

A 9-bit address generator is maintained by the RCU with the address presented on the A9:1 address

lines during the refresh bus cycle. Address bits A19:13 are programmable to allow the refresh

address block to be located on any 8 Kbyte boundary.

3.6 Power Management

The 80C186EA has three operational modes to control the power consumption of the device. They

are Power Save Mode, Idle Mode, and Powerdown Mode.

Power Save Mode divides the processor clock by a programmable value to take advantage of the

fact that current is linearly proportional to frequency. An unmasked interrupt, NMI, or reset will

cause the 80C186EA to exit Power Save Mode.

Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state

while all peripherals operate normally.

Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator.

All internal registers hold their values provided VCC is maintained. Current consumption is

reduced to transistor leakage only.

Intel® 80C186EA Peripheral Architecture

Product Name Datasheet 15

3.7 80C187 Interface (80C186EA Only)

The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to

include floating point and advanced integer instructions. Connecting the 80C186EA RESOUT and

TEST/ BUSY pins to the 80C187 enables Numerics Mode operation. In Numerics Mode, three of

the four Mid- Range Chip Select (MCS) pins become handshaking pins for the interface. The

exchange of data and control information proceeds through four dedicated I/O ports.

If an 80C187 is not present, the 80C186EA configures itself for regular operation at reset.

Note: The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA.

3.8 ONCE Test Mode

To facilitate testing and inspection of devices when fixed into a target system, the 80C186EA has a

test mode available which forces all output and input/ output pins to be placed in the high-

impedance state. ONCE stands for “ON Circuit Emulation.” The ONCE mode is selected by

forcing the UCS and LCS pins LOW (0) during a processor reset (these pins are weakly held to a

HIGH (1) level) while RESIN is active.

Intel® 80C186XL and Intel® 80C186EA Differences

16 Product Name Datasheet

4.0 Intel®80C186XL and Intel®80C186EA Differences

The 80C186EA is intended as a direct functional upgrade for 80C186XL designs. In many cases, it

will be possible to replace an existing 80C186XL with little or no hardware redesign. The

following sections describe differences in pinout, operating modes, and AC and DC specifications

to keep in mind.

4.1 Pinout Compatibility

The 80C186EA requires a PDTMR pin to time the processor's exit from Powerdown Mode. The

original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to

use for PDTMR. The arrangement of all the other leads in the 68-lead PLCC is identical between

the 80C186XL and the 80C186EA. Therefore, upgrading a PLCC 80C186XL to PLCC 80C186EA

is straightforward.

4.2 Operating Modes

The 80C186XL has two operating modes, Compatible and Enhanced. Compatible Mode is a pin-

to-pin replacement for the NMOS 80186, except for numerics coprocessing. In Enhanced Mode,

the processor has a Refresh Control Unit, the Power-Save feature and an interface to the 80C187

Numerics Coprocessor. The MCS0,MCS1,andMCS3pins change their functions to constitute

handshaking pins for the 80C187.

The 80C186EA allows all non-80C187 users to use all the MCS pins for chip-selects. In regular

operation, all 80C186EA features (including those of the Enhanced Mode 80C186) are present

except for the interface to the 80C187. Numerics Mode disables the three chip-select pins and

reconfigures them for connection to the 80C187.

4.3 TTL vs. CMOS Inputs

The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity,

but the 80C186XL inputs are rated for TTL switching levels. In particular, the 80C186EA requires

aminimumV

IH of 3.5V to recognize a logic one while the 80C186XL requires a minimum VIH of

only 1.9V (assuming 5.0V operation). The solution is to drive the 80C186EA with true CMOS

devices, such as those from the HC and AC logic families, or to use pull-up resistors where the

added current draw is not a problem.

4.4 Timing Specifications

80C186EA timing relationships are expressed in a simplified format over the 80C186XL. The AC

performance of an 80C186EA at a specified frequency will be very close to that of an 80C186XL

at the same frequency. Check the timings applicable to your design prior to replacing the

80C186XL.

Intel® 80C186XL and Intel® 80C186EA Differences

Product Name Datasheet 17

4.5 Package Information

This section describes the pins, pinouts, and thermal characteristics for the 80C186EA in the

Plastic Leaded Chip Carrier (PLCC) package. For complete package specifications and

information, see the Intel®Packaging Outlines and Dimensions Guide (Order Number: 231369).

With the extended temperature range operational characteristics are guaranteed over a temperature

range corresponding to -40 °C to +85 °C ambient. Package types are identified by a two-letter

prefix to the part number. The prefixes are listed in Table 3.

4.6 Pin Descriptions

Each pin or logical set of pins is described in Table 5. There are three columns for each entry in the

Pin Description Table.

The Pin Name column contains a mnemonic that describes the pin function. Negation of the signal

name (for example, RESIN) denotes a signal that is active low.

The Pin Type column contains two kinds of information. The first symbol indicates whether a pin

is power (P), ground (G), input only (I), output only (O) or input/output (I/O). Some pins have

multiplexed functions (for example, A19/S6). Additional symbols indicate additional

characteristics for each pin. Table 5 lists all the possible symbols for this column.

The Input Type column indicates the type of input (asynchronous or synchronous).

Asynchronous pins require that setup and hold times be met only in order to guarantee recognition

at a particular clock edge. Synchronous pins require that setup and hold times be met to guarantee

proper operation. For example, missing the setup or hold time for the SRDY pin (a synchronous

input) will result in a system failure or lockup. Input pins may also be edge- or level-sensitive. The

possible characteristics for input pins are S(E), S(L), A(E) and A(L).

The Output States column indicates the output state as a function of the device operating mode.

Output states are dependent upon the current activity of the processor. There are four operational

states that are different from regular operation: bus hold, reset, Idle Mode and Powerdown Mode.

Appropriate characteristics for these states are also indicated in this column, with the legend for all

possible characteristics in Table 4.

The Pin Description column contains a text description of each pin.

As an example, consider AD15:0. I/O signifies the pins are bidirectional. S(L) signifies that the

input function is synchronous and level-sensitive. H(Z) signifies that, as outputs, the pins are high-

impedance upon acknowledgement of bus hold. R(Z) signifies that the pins float during reset. P(X)

signifies that the pins retain their states during Powerdown Mode.

Table3. PrefixIdentification

Prefix Note Package Type Temperature Range

TN PLCC Extended

NOTE:

1. The 25 MHz version is only available in commercial temperature range corresponding to 0 °C to +70 °C

ambient.

Intel® 80C186XL and Intel® 80C186EA Differences

18 Product Name Datasheet

Table 4. Pin Description Nomenclature

Symbol Description

I/O

Power Pin (Apply +VCC Voltage)

Ground (Connect to VSS)

Input Only Pin

Output Only Pin

Input/Output Pin

S(E)

S(L)

A(E)

A(L)

Synchronous, Edge Sensitive

Synchronous, Level Sensitive

Asynchronous, Edge Sensitive

Asynchronous, Level Sensitive

H(1)

H(0)

H(Z)

H(Q)

H(X)

Output Driven to VCC during Bus Hold

Output Driven to VSS during Bus Hold

Output Floats during Bus Hold

Output Remains Active during Bus Hold

Output Retains Current State during Bus Hold

R(WH)

R(1)

R(0)

R(Z)

R(Q)

R(X)

Output Weakly Held at VCC during Reset

Output Driven to VCC during Reset

Output Driven to VSS during Reset

Output Floats during Reset

Output Remains Active during Reset

Output Retains Current State during Reset

I(1)

I(0)

I(Z)

I(Q)

I(X)

Output Driven to VCC during Idle Mode

Output Driven to VSS during Idle Mode

Output Floats during Idle Mode

Output Remains Active during Idle Mode

Output Retains Current State during Idle Mode

P(1)

P(0)

P(Z)

P(Q)

P(X)

Output Driven to VCC during Powerdown Mode

Output Driven to VSS during Powerdown Mode

Output Floats during Powerdown Mode

Output Remains Active during Powerdown Mode

Output Retains Current State during Powerdown Mode

Intel® 80C186XL and Intel® 80C186EA Differences

Product Name Datasheet 19

Table 5. Pin Descriptions (Sheet 1 of 3)

Pin Name Pin

Type Input

Type Output

States Description

VCC PPOWER connections consist of six pins which must be shorted

externally to a VCC board plane.

VSS GGROUND connections consist of five pins which must be shorted

externally to a VSS board plane.

CLKIN I A(E) CLocK INput is an input for an external clock. An external oscillator

operating at two times the required processor operating frequency can

be connected to CLKIN. For crystal operation, CLKIN (along with

OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCOUT O H(Q)

R(Q)

P(Q)

OSCillator OUTput is only used when using a crystal to generate the

external clock. OSCOUT (along with CLKIN) are the crystal R(Q)

connectionsto an internal Pierce oscillator. This pin is not to be P(Q)

used as 2X clock output for non-crystal applications (i.e., this pin is N.C.

for non-crystal applications). OSCOUT does not float in ONCE mode.

CLKOUT O H(Q)

R(Q)

P(Q)

CLocK OUTput provides a timing reference for inputs andoutputs of the

processor, and is one-half the input clock (CLKIN) frequency. CLKOUT

has a 50% duty cycle and transitions every falling edge of CLKIN.

RESIN IA(L) RESet IN causes the processor to immediately terminate any bus cycle

in progress and assume an initialized state. All pins will be driven to a

known state, and RESOUT will also be driven active. The rising edge

(low-to-high) transition synchronizes CLKOUT with CLKIN before the

processor begins fetching opcodes at memory location 0FFFF0H.

RESOUT O H(0)

R(I)

P(O)

RESet OUTput that indicates the processor is currently in the reset

state. RESOUT will remain active as long as RESIN remains active.

When tied to the TEST/BUSY pin, RESOUT forces the 80C186EA into

Numerics Mode.

PDTMR I/O A(L) H(WH)

R(Z)

P(1)

Power-Down TiMeR pin (normally connected to an external capacitor)

thatdetermines the amount of time the processor waits afteran exit from

power down before resuming normal operation. P(1) The duration of time

required will depend on the startup characteristics of the crystal

oscillator.

NMI I A(E) Non-Maskable Interrupt input causes a Type 2 interrupt to be serviced

by the CPU. NMI is latched internally.

TEST/BUSY

(TEST)IA(E) TEST/BUSY is sampled upon reset to determine whether the 80C186EA

is to enter Numerics Mode. In regular operation, the pin is TEST. TEST is

used during the execution of the WAIT instruction to suspend CPU

operation until the pin is sampled active (low). In Numerics Mode, the pin

is BUSY. BUSY notifies the 80C186EA of 80C187 Numerics

Coprocessor activity.

AD15:0

(AD7:0) I/O S(L) H(Z)

R(Z)

P(X)

These pins provide a multiplexed Address and Data bus. During the

address phase of the bus cycle, address bits 0 through 15 (0 through 7

on the 8-bit bus versions) are presented on the bus and can be latched

using ALE. 8- or 16-bit data information is transferred during the data

phase of the bus cycle.

A18:16

A19/S6–A16

(A19–A8)

OH(Z)

R(Z)

P(X)

These pins provide multiplexed Address during the address phase of

the bus cycle. Address bits 16 through 19 are presented on these pins

and can be latched using ALE. A18:16 are driven to a logic 0 during the

data phase of the bus cycle. On the 8-bit bus versions, A15–A8 provide

valid address information for the entire bus cycle. Also during the data

phase, S6 is driven to a logic 0 to indicate a CPU-initiated bus cycle or

logic 1 to indicate a DMA-initiated bus cycle or a refresh cycle.

Intel® 80C186XL and Intel® 80C186EA Differences

20 Product Name Datasheet

S2:0 OH(Z)

R(Z)

P(1)

Bus cycle Status are encoded on these pins to provide bus transaction

information. S2:0 are encoded as follows:

S2 S1 S0 Bus Cycle Initiated

Interrupt Acknowledge

Read I/O

Write I/O

Processor HALT

Queue Instruction Fetch

Read Memory

Write Memory

Passive (no bus activity)

ALE/QS0 O H(0)

R(0)

P(0)

Address Latch Enable output is used to strobe address information into

a transparent type latch during the address phase of the bus cycle. In

Queue Status Mode, QS0 provides queue status information along with

QS1.

BHE

(RFSH)OH(Z)

R(Z)

P(X)

Byte High Enable output to indicate that the bus cycle in progress is

transferring data over the upper half of the data bus. BHE andA0have

the following logical encoding:

A0 BHE Encoding (For 80C186EA/80L186EA Only)

Word Transfer

Even Byte Transfer

OddByteTransfer

Refresh Operation

On the 80C188EA/80L188EA, RFSH is asserted low to indicate a

Refresh bus cycle.

RD/QSMD OH(Z)

R(WH)

P(1)

ReaD output signals that the accessed memory or I/O device must drive

data information onto the data bus. Upon reset, this pin has an alternate

function. As QSMD, it enablesQueueStatusModewhen grounded. In

Queue Status Mode, the ALE/QS0 and WR/QS1 pinsprovide the

following information about processor/instruction queue interaction:

QS1 QS0 Queue Operation

No Queue Operation

First Opcode Byte Fetched from the Queue

Subsequent Byte Fetched from the Queue

Empty the Queue

WR/QS1 O H(Z)

R(Z)

P(1)

WRite output signals that data available on the data bus are to be written

into the accessed memory or I/O device. In Queue Status Mode, QS1

provides queue status information along with QS0.

ARDY I A(L)

S(L) Asynchronous ReaDY is an input to signal for the end of a bus cycle.

ARDY is asynchronous on rising CLKOUT and synchronous on falling

CLKOUT. ARDY or SRDY must be active to terminate any processor bus

cycle, unless they are ignored due to correct programming of the Chip

Select Unit.

SRDY I S(L) Synchronous ReaDY is an input to signal for the end of a bus cycle.

ARDY or SRDY must be active to terminate any processor bus cycle,

unless they are ignored due to correct programming of the Chip Select

Unit.

DEN OH(Z)

R(Z)

P(1)

Data ENable output to control the enable of bidirectional transceivers

when buffering a system. DEN is active only when data is to be

transferred on the bus.

LOCK OH(Z)

R(WH)

P(1)

LOCK output indicates that the bus cycle in progress is not to be

interrupted. The processor will not service other bus requests (such as

HOLD) while LOCK is active. This pin is configured as a weakly held

high input while RESIN is active and must not be driven low.

Table 5. Pin Descriptions (Sheet 2 of 3)

Pin Name Pin

Type Input

Type Output

States Description

Intel® 80C186XL and Intel® 80C186EA Differences

Product Name Datasheet 21

HOLD I A(L) HOLD request input to signal that an external bus master wishes to gain

control of the local bus. The processor will relinquish control of the local

bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA O H(1)

R(0)

P(0)

HoLD Acknowledge output to indicate that the processor has

relinquished control of the local bus. When HLDA is asserted, the

processor will (or has) floated its data bus and control signals allowing

another bus master to drive the signals directly.

UCS OH(1)

R(1)

P(1)

Upper Chip Select will go active whenever the address of a memory or

I/O bus cycle is within the address limitations programmed by the user.

After reset, UCS is configured to be active for memory accesses

between 0FFC00H and 0FFFFFH. During a processor reset,UCS and

LCS are used to enable ONCE Mode.

LCS OH(1)

R(1)

P(1)

Lower Chip Select will go active whenever the address of a memory

bus cycle is within the address limitations programmed by the user. R(1)

LCSis inactive after a reset. During a processor reset, UCS and LCS are

used to enable ONCE Mode.

MCS0/PEREQ

MCS1/ERROR

MCS2

MCS3/NCS

I/O A(L) H(1)

R(1)

P(1)

These pins provide a multiplexed function. If enabled, these pins

normally comprise a block of Mid-Range Chip Select outputs which will

go active whenever the address of a memory bus cycle is within the

address limitations programmed by the user. In Numerics Mode

(80C186EA only), three of the pins become handshaking pins for the

80C187. TheCoProcessor REQuest input signals that a data transfer is

pending. ERROR is an input which indicates that the previous numerics

coprocessor operation resulted in an exception condition. An interrupt

Type16 isgenerated whenERROR is sampled active at the beginning of

a numerics operation. Numerics Coprocessor Select is an output

signal generated when the processor accesses the 80C187.

PCS4:0 OH(1)

R(1)

P(1)

Peripheral Chip Selects go active whenever the address of a memory

or I/O bus cycle is within the address limitations programmed by the

user.

PCS5/A1

PCS6/A2 OH(1)/

H(X)

R(1)

P(1)

These pins provide a multiplexed function. As additionalPeripheral

Chip Selects, they go active whenever the address of a memory or

I/O bus cycle is within the address limitations by the user. They may also

be programmed to provide latched Address A2:1 signals.

T0OUT

T1OUT OH(Q)

R(1)

P(Q)

Timer OUTput pinscanbeprogrammedtoprovideasingleclockor

continuous waveform generation, depending on the timer mode

selected.

T0IN I A(L)

A(E) Timer INput is used either as clock or control signals, depending on the

timer mode selected. T1IN A(E)

DRQ0

DRQ1 IA(L) DMA ReQuestis asserted by an externalrequest when it is preparedfor

a DMA transfer.

INT0

INT1/SELECT IA(E,L) MaskableINTerrupt input will cause a vector to a specific Type interrupt

routine. To allow interrupt expansion, INT0 and/or INT1 can be used with

INTA0 and INTA1 to interface with an external slave controller. INT1

becomes SELECT when the ICU is configured for Slave Mode.

INT2/INTA0

INT3/INTA1/IRQ I/O A(E,L) H(1)

R(Z)

P(1)

These pins provide multiplexed functions. As inputs, they provide a

maskable INTerrupt that will cause the CPU to vector to a specific Type

interrupt routine. As outputs, each is programmatically controlled to

provide an INTerrupt Acknowledge handshake signal to allow interrupt

expansion. INT3/INTA1 becomes IRQ when the ICU is configured for

Slave Mode.

N.C. No Connect. For compatibility with future products, do not connect to

these pins.

NOTE: Pin names in parentheses apply to the 80C188EA and 80L188EA.

Table 5. Pin Descriptions (Sheet 3 of 3)

Pin Name Pin

Type Input

Type Output

States Description

Intel® 80C186EA Pinout

22 Product Name Datasheet

5.0 Intel®80C186EA Pinout

Table 6 and Table 7 list the 80C186EA pin names with package location for the 68-pin Plastic

Leaded Chip Carrier (PLCC) component. Figure 3 depicts the complete 80C186EA/80L186EA

pinout (PLCC package) as viewed from the top side of the component (i.e., contacts facing down).

Table 6. PLCC Pin Names with Package Location

Address/Data Bus Bus Control Processor Control I/O

Name Location Name Location Name Location Name Location

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8 (A8)

AD9 (A9)

AD10 (A10)

AD11 (A11)

AD12 (A12)

AD13 (A13)

AD14 (A14)

AD15 (A15)

A16

A17

A18

A19/S6

ALE/QS0

BHE (RFSH)

RD/QSMD

WR/QS1

ARDY

SRDY

DEN

LOCK

HOLD

HLDA

RESIN

RESOUT

CLKIN

OSCOUT

CLKOUT

TEST/BUSY

PDTMR

NMI

INT0

INT1/SELECT

INT2/INTA0

INT3/INTA1/

IRQ

UCS

LCS

MCS0/PEREQ

MCS1/ERROR

MCS2

MCS3/NCS

PCS0

PCS1

PCS2

PCS3

PCS4

PCS5/A1

PCS6/A2

T0OUT

T0IN

T1OUT

T1IN

DRQ0

DRQ1

Power

Name Location

VSS

VCC 26, 60

9, 43

NOTE: Pin names in parentheses apply to the 80C188EA/80L188EA.

Table 7. PLCC Package Location with Pin Names

Location Name Location Name Location Name Location Name

AD15 (A15)

AD7

AD14 (A14)

AD6

AD13 (A13)

AD5

AD12 (A12)

AD4

VCC

AD11 (A11)

AD3

AD10 (A10)

AD2

AD9 (A9)

AD1

AD8 (A8)

AD0

DRQ0

DRQ1

T0IN

T1IN

T0OUT

T1OUT

RESIN

PCS0

VSS

PCS1

PCS2

PCS3

PCS4

PCS5/A1

PCS6/A2

LCS

UCS

MCS3/NCS

MCS2

MCS1/ERROR

MCS0/PEREQ

DEN

PDTMR

INT3/INTA1/

IRQ

INT2/INTA0

VCC

INT1/SELECT

INT0

NMI

TEST/BUSY

LOCK

SRDY

HOLD

HLDA

ARDY

CLKOUT

RESOUT

OSCOUT

CLKIN

VSS

ALE/QS0

RD/QSMD

WR/QS1

BHE RFSH

A19/S6

A18

A17

A16

NOTE: Pin names in parentheses apply to the 80C188EA/80L188EA.

Intel® 80C186EA Pinout

Product Name Datasheet 23

Figure 3. 68-Lead PLCC Pinout Diagram

Notes:

1. The nine character alphanumeric code (XXXXXXXXD) underneath the product number is the Intel FPO number.

2. Pin names in parentheses apply to the 80C186EA/80L188EA.

Package Thermal Specifications

24 Product Name Datasheet

6.0 Package Thermal Specifications

The 80C186EA/80L186EA is specified for operation when TC(the case temperature) is within the

range of 0°C to 85°C (PLCC package). TCmay be measured in any environment to determine

whether the processor is within the specified operating range. The case temperature must be

measured at the center of the top surface.

TA(the ambient temperature) can be calculated from θCA (thermal resistance from the case to

ambient) with the following equation:

TA=T

C-P×θCA

Typical values for θCA at various airflows are given in Table 8.

P (the maximum power consumption, specified in watts) is calculated by using the maximum ICC

as tabulated in the DC specifications and VCC of 5.5 V.

Table 8. Thermal Resistance (θCA) at Various Airflows (in °C/Watt)

Airflow Linear ft./min. (m/sec)

(0) 200

(1.01) 400

(2.03) 600

(3.04) 800

(4.06) 1000

(5.07)

θCA (PLCC) 29 25 21 19 17 16.5

Electrical Specification

Product Name Datasheet 25

7.0 Electrical Specification

7.1 Absolute Maximum Ratings*

Note: This data sheet contains preliminary information on new products in production. It is valid for the

devices indicated in the revision history. The specifications are subject to change without notice.

*Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.

These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended

and extended exposure beyond the “Operating Conditions” may affect device reliability.

7.2 Recommended Connections

Power and ground connections must be made to multiple VCC and VSS pins. Every 80C186EA

based circuit board should contain separate power (VCC) and ground (VSS)planes.AllV

CC and

VSS pins must be connected to the appropriate plane. Pins identified as “N.C.” must not be

connected in the system. Decoupling capacitors should be placed near the processor. The value and

type of decoupling capacitors is application and board layout dependent. The processor can cause

transient power surges when its output buffers transition, particularly when connected to large

capacitive loads.

Always connect any unused input pins to an appropriate signal level. In particular, unused interrupt

pins (NMI, INT3:0) should be connected to VSS to avoid unwanted interrupts. Leave any unused

output pin or any “N.C.” pin unconnected.

Storage Temperature: -65 °C to + 150 °C

Case Temperature under Bias: -65 °C to + 150 °C

Supply Voltage with Respect to VSS:-0.5Vto+6.5V

Voltage on Other Pins with Respect to VSS:-0.5VtoV

CC +0.5V

DC Specifications

26 Product Name Datasheet

8.0 DC Specifications

Table 9. DC SPECIFICATIONS (80C186EA/80C188EA)

NOTES:

1.RD/QSMD, UCS,LCS,MCS0/PEREQ, MCS1/ERROR,LOCKand TEST/BUSY have internal pull-ups that

are only activated during RESET. Loading these pins above IOL = -275 µA will cause the processor to

enter alternate modes of operation.

2.Output pins are floated using HOLD or ONCE Mode.

3.Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test

Conditions, and with the device in RESET (RESIN held low). RESET is worst case for ICC.

4.Output capacitance is the capacitive load of a floating output pin.

5.Operating conditions for 25 MHz are 0°Cto+70°C, VCC = 5.0V ±10%.

()

Symbol Parameter Min Max Units Conditions

VCC Supply Voltage 45 55 V

VIL Input Low Voltage for All Pins

05 03 VCC V

VIH Input High Voltage for All Pins 07 VCC VCC

05 V

VOL Output Low Voltage 045 V IOL

3mA(min)

VOH Output High Voltage VCC

05 V IOH

2mA(min)

VHYR Input Hysterisis on RESIN 030 V

IIL1 Input Leakage Current (except g10 mA0V

sVIN sVCC

RDQSMD UCS LCS MCS0PEREQ

MCS1ERROR LOCK and TESTBUSY)

IIL2 Input Leakage Current

275 mAV

07 VCC

(RDQSMD UCS LCS MCS0PEREQ (Note 1)

MCS1 ERROR LOCK and TESTBUSY

IOL Output Leakage Current g10 mA045 sVOUT sVCC

(Note 2)

ICC Supply Current Cold (RESET)

80C186EA2580C188EA25 105 mA (Notes 3 5)

80C186EA2080C188EA20 90 mA

80C186EA1380C188EA13 65 mA

IID Supply Current In Idle Mode

80C186EA2580C188EA25 90 mA (Note 5)

80C186EA2080C188EA20 70 mA

80C186EA1380C188EA13 46 mA

IPD Supply Current In Powerdown Mode

80C186EA2580C188EA25 100 mA (Note 5)

80C186EA2080C188EA20 100 mA

80C186EA1380C188EA13 100 mA

COUT Output Pin Capacitance 0 15 pF TF

1 MHz (Note 4)

CIN Input Pin Capacitance 0 15 pF TF

1 MHz

DC Specifications

Product Name Datasheet 27

Table 10. DC SPECIFICATIONS (80L186EA/80L188EA)

NOTES:

1.RD/QSMD, UCS,LCS,MCS0,MCS1,LOCKand TEST have internal pull-upsthatare only activated during

RESET. Loading these pins above IOL = -275 µA will cause the processor to enter alternate modes of

operation.

2.Output pins are floated using HOLD or ONCE Mode.

3.Measured at worst case temperature and VCC with all outputs loaded as specified in the AC Test

Conditions, and with the device in RESET (RESIN held low).

4.Output capacitance is the capacitive load of a floating output pin.

DC Specifications

28 Product Name Datasheet

8.1 ICC Versus Frequency and Voltage

The current (ICC) consumption of the processor is essentially composed of two components; IPD

and ICCS.

IPD is the quiescent current that represents internal device leakage, and is measured with all inputs

or floating outputs at GND or VCC (no clock applied to the device). IPD is equal to the Powerdown

current and is typically less than 50 µA.

ICCS is the switching current used to charge and discharge parasitic device capacitance when

changing logic levels. Since ICCS is typically much greater than IPD,I

PD can often be ignored when

calculating ICC.

ICCS is related to the voltage and frequency at which the device is operating. It is given by the

formula:

Measuring CDEV on a device like the 80C186EA would be difficult. Instead, CDEV is calculated

using the above formula by measuring ICC at a known VCC and frequency (see Table 11). Using

this CDEV value, ICC can be calculated at any voltage and frequency within the specified operating

range.

EXAMPLE: Calculate the typical ICC when operating at 20 MHz, 4.8V.

ICC =I

CCS =4.8×0.515×20≈ 49 mA

Power=V×I=V

2×C

DEV ×f

∴I=I

CC =I

CCS =V×C

DEV ×f

Where: V = Device operating voltage (VCC)

CDEV = Device capacitance

f = Device operating frequency

ICCS =I

CC = Device current

Table 11. CDEV Values

Parameter Type Max Units Notes

CDEV (Device in Reset) 0.515 0.905 mA/V*MHz 1,2

CDEV (Device in Idle) 0.391 0.635 mA/V*MHz 1,2

1. MaxCDEV is calculated at -40 °C,all floating outputs driven to VCC orGND,andalloutputsloadedto50pF

(including CLKOUT and OSCOUT).

2. Typical CDEV is calculated at 25°C with all outputs loaded to 50 pF except CLKOUT and OSCOUT, which

are not loaded.

DC Specifications

Product Name Datasheet 29

8.2 PDTMR Pin Delay Calculation

The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal

clocks when exiting Powerdown. A delay is required only when using the on-chip oscillator to

allow the crystal or resonator circuit time to stabilize.

Note: The PDTMR pin function does not apply when RESIN is asserted (i.e., a device reset during

Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has

stabilized).

To calculate the value of capacitor required to provide a desired delay, use the equation:

Example 1. To get a delay of 300 µs, a capacitor value of CPD =440×(300 ×10-6)=0.132µFis

required. Round up to standard (available) capacitive values.

Note: The above equation applies to delay times greater than 10 µs and will compute the TYPICAL

capacitance needed to achieve the desired delay. A delay variance of +50% or -25% can occur due

to temperature, voltage, and device process extremes. In general, higher VCC and/or lower

temperature will decrease delay time, while lower VCC and/or higher temperature will increase

delay time.

440×t=C

PD (5V, 25 °C)

Where: t = desired delay in seconds

CPD = capacitive load on PDTMR in microfarads

AC Specifications

30 Product Name Datasheet

9.0 AC Specifications

Table 12. AC Characteristics—80C186EA25/80C186EA20/80C186EA13 (Sheet 1 of 2)

Symbol Parameter Min Max Min Max Min Max Units Notes

INPUT CLOCK 25 MHz

(12)

20 MHz 13 MHz

CLKIN Frequency 0 50 0 40 0 26 MHz 1

CLKIN Period 20 %25 %385 %ns 1

CLKIN High Time 10 %10 %12 %ns 1 2

CLKIN Low Time 10 %10 %12 %ns 1 2

CLKIN Rise Time 1 8 1 8 1 8 ns 1 3

CLKIN Fall Time 1 8 1 8 1 8 ns 1 3

OUTPUT CLOCK

CLKIN to CLKOUT Delay 0 15 0 17 0 23 ns 1 4

T CLKOUT Period 2T

2T

ns 1

CLKOUT High Time (T2)

5 (T2)

5ns1

CLKOUT Low Time (T2)

5 (T2)

5ns1

CLKOUT Rise Time 1 6 1 6 1 6 ns 1 5

CLKOUT Fall Time 1 6 1 6 1 6 ns 1 5

OUTPUT DELAYS

CHOV1

ALE S20 DEN  3 20 3 22 3 25 ns 1 4 6 7

BHE (RFSH) LOCK A1916

CHOV2

MCS30 LCS UCS PCS60 3 25 3 27 3 30 ns 1 4 6 8

NCSRDWR

CLOV1

BHE (RFSH) DEN LOCK 3 20 3 22 3 25 ns 1 4 6

RESOUT HLDA

T0OUT T1OUT A1916

CLOV2

RDWR MCS30 LCS 3 25 3 27 3 30 ns 1 4 6

UCS PCS60 AD150

(A158 AD70)

NCS INTA10 S20

CHOF

RDWR BHE (RFSH)  0 25 0 25 0 25 ns 1

LOCK S20 A1916

CLOF

DEN AD150 (A158 AD70) 0 25 0 25 0 25 ns 1

AC Specifications

Product Name Datasheet 31

NOTES:

1.See AC Timing Waveforms, for waveforms and definition.

2.Measured at VIH for high time, VIL for low time.

3.Onlyrequired to guarantee ICC. Maximum limits are bounded by TC,T

CH and TCL.

4.Specifiedfora50pFload,seeFigure 9 for capacitive derating information.

5.Specifiedfora50pFload,seeFigure 10 for rise and fall times outside 50 pF.

6.See Figure 10 for rise and fall times.

7.TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8.TCHOV2 applies to RD and WR only after a HOLD release.

9.Setup and Hold are required to guarantee recognition.

10.Setup and Hold are required for proper operation.

11.TCHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release.

12.Operating conditions for 25 MHz are 0°Cto+70°C, VCC =5.0V±10%.

13.Pin names in parentheses apply to the 80C188EA/80L188EA.

Table 12. AC Characteristics—80C186EA25/80C186EA20/80C186EA13 (Sheet 2 of 2)

Symbol Parameter Min Max Min Max Min Max Units Notes

SYNCHRONOUS INPUTS 25 MHz(12) 20 MHz 13 MHz

TCHIS TEST NMI INT30 8 10 10 ns 1 9

T10IN ARDY

TCHIH TEST NMI INT30 3 3 3 ns 1 9

T10IN ARDY

TCLIS AD150 (AD70) ARDY 10 10 10 ns 1 10

SRDY DRQ10

TCLIH AD150 (AD70) ARDY 3 3 3 ns 1 10

SRDY DRQ10

TCLIS HOLD PEREQ ERROR 10 10 10 ns 1 9

(80C186EA Only)

TCLIH HOLD PEREQ ERROR 3 3 3 ns 1 9

(80C186EA Only)

TCLIS RESIN (to CLKIN) 10 10 10 ns 1 9

TCLIH RESIN (from CLKIN) 3 3 3 ns 1 9

AC Specifications

32 Product Name Datasheet

Table 13. AC Characteristics—80L186EA13/80C186EA8

Symbol Parameter Min. Max. Units Notes

INPUT CLOCK

TFCLKIN Frequency 0 26 MHz 1

TCCLKIN Period 38.5 ∞ns 1

TCH CLKIN High Time 12 ∞ns 1,2

TCL CLKIN Low Time 12 ∞ns 1,2

TCR CLKIN Rise Time 1 8 ns 1,3

TCF CLKIN Fall Time 1 8 ns 1,3

OUTPUT CLOCK

TCD CLKIN to CLKOUT Delay 0 45 ns 1,4

TCLKOUTPeriod 2*T

Cns 1

TPH CLKOUT High Time (T/2) –5ns1

TPL CLKOUT Low Time (T/2) –5ns1

TPR CLKOUT Rise Time 1 12 ns 1,5

TPF CLKOUT Fall Time 1 12 ns 1,5

OUTPUT DELAYS

TCHOV1 ALE, LOCK 3 27 ns 1,4,6,7

TCHOV2 MCS3:0,LCS, UCS,PCS6:0,RD,WR 3 32 ns 1,4,6,8

TCHOV3 S2:0,(DEN), BHE,(RFSH), A19:16 3 30 ns 1

TCLOV1 LOCK, RESOUT, HLDA, T0OUT, T1OUT 3 27 ns 1, 4, 6

TCLOV2 RD,WR,MCS3:0,LCS, UCS,PCS6:0,INTA1:0 3 32 ns 1,4,6

TCLOV3 BHE,(RFSH), DEN, A19:16 3 30 ns 1, 4, 6

TCLOV4 AD15:0, (A15:8, AD7:0) 3 3 ns 1, 4, 6

TCLOV5 S2:0 3 38 ns 1,4,6

TCHOF RD,WR,BHE,(RFSH), LOCK,S2:0, A19:16 0 27 ns 1

TCLOF DEN, AD15:0, (A15:8, AD7:0) 0 27 ns 1

SYNCHRONOUS INPUTS

TCHIS TEST,NMI,INT3:0,T1:0IN,ARDY 22 ns 1,9

TCHIH TEST,NMI,INT3:0,T1:0IN,ARDY 3 ns 1,9

TCLIS AD15:0, (AD7:0), ARDY, SRDY, DRQ1:0 22 ns 1, 10

TCLIH AD15:0, (AD7:0), ARDY, SRDY, DRQ1:0 3 ns 1, 10

TCLIS HOLD 22 ns 1, 9

TCLIH HOLD 3 ns 1, 9

TCLIS RESIN (to CLKIN) 22 ns 1, 9

TCLIH RESIN (from CLKIN) 3 ns 1, 9

NOTES:

1. See AC Timing Waveforms, for waveforms and definition.

2. Measured at VIH for high time, VIL for low time.

3. Only required to guarantee ICC. Maximum limits are bounded by TC,T

CH and TCL.

4. Specified for a 50 pF load, see Figure 9 for capacitive derating information.

5. Specified for a 50 pF load, see Figure 10 for rise and fall times outside 50 pF.

6. See Figure 10 for rise and fall times.

7. TCHOV1 applies to BHE (RFSH), LOCK and A19:16 only after a HOLD release.

8. TCHOV2 applies to RD and WR only after a HOLD release.

9. Setup and Hold are required to guarantee recognition.

10.Setup and Hold are required for proper operation.

11.TCHOVS applies to BHE (RFSH) and A19:16 only after a HOLD release.

12.Pin names in parentheses apply to the 80C188EA/80L188EA.

AC Specifications

Product Name Datasheet 33

Table 14. Relative Timings (80C186EA25/20/13, 80L186EA13)

NOTES:

1.Assumes equal loading on both pins.

2.Canbeextendedusingwaitstates.

3.Not tested.

4.Not applicable to latched A2:1. These signals change only on falling T1.

5.Forwritecyclefollowedbyreadcycle.

6.Operating conditions for 25 MHz are 0°Cto+70°C, VCC =5.0V±10%.

Symbol Parameter Min Max Unit Notes

RELATIVE TIMINGS

TLHLL ALE Rising to ALE Falling T b15 ns

TAVLL Address Valid to ALE Falling Tb10 ns

TPLLL Chip Selects Valid to ALE Falling Tb10 ns 1

TLLAX Address Hold from ALE Falling Tb10 ns

TLLWL ALE Falling to WR Falling Tb15 ns 1

TLLRL ALE Falling to RD Falling Tb15 ns 1

TRHLH RD Rising to ALE Rising Tb10 ns 1

TWHLH WR Rising to ALE Rising Tb10 ns 1

TAFRL Address Float to RD Falling 0 ns

TRLRH RD Falling to RD Rising (2T) b5ns2

TWLWH WR Falling to WR Rising (2T) b5ns2

TRHAV RD Rising to Address Active T b15 ns

TWHDX Output Data Hold after WR Rising T b15 ns

TWHDEX WR Rising to DEN Rising Tb10 ns 1

TWHPH WR Rising to Chip Select Rising Tb10 ns 1 4

TRHPH RD Rising to Chip Select Rising Tb10 ns 1 4

TPHPL CS Inactive to CS Active Tb10 ns 1

TOVRH ONCE (UCS LCS) Active to RESIN Rising T ns 3

TRHOX ONCE (UCS LCS) to RESIN Rising T ns 3

AC Test Conditions

34 Product Name Datasheet

10.0 AC Test Conditions

The AC specifications are tested with the 50 pF load shown in Figure 4. See the Derating Curves

section to see how timings vary with load capacitance.

Specifications are measured at the VCC/2 crossing point, unless otherwise specified. See AC

Timing Waveforms, for AC specification definitions, test pins, and illustrations.

Figure 4. AC Test Load

Note: CL = 50 pF for all signals.

AC Timing Waveforms

Product Name Datasheet 35

11.0 AC Timing Waveforms

Figure 5. Input and Output Clock Waveform

Figure 6. Output Delay and Float Waveform

Note: 20% VCCk Float k 80% VCC

AC Timing Waveforms

36 Product Name Datasheet

Figure 7. Input Setup and Hold

Note: RESIN measured to CLKIN, not CLKOUT

AC Timing Waveforms

Product Name Datasheet 37

Figure 8. Relative Signal Waveform

Notes: Pin names in parentheses apply to the 80C188EA

TLHLL

TAVLL TLLAX TWHLH

VCC

ALE

RD# or WR#

ADD:15 [AD0:7]

A19:16 [A19:8]

MCS3:0#, LCS#,

UCS#, PCS6:0#

CLKOUT

VCC

DEN#

VCC

RESIN#

UCS#, LCS#

VCC

50% 50%50%

50% 50%

50% 50% TRHLH

TWHDX

TAFRL

TRLRH TWLWH

TLLRL

TLLWL

50%

TPHPL TPLLL TRHPH TWHPH

TRHAV

TWHDEX

50% 50%50%

TOVRH TRHOX

50%

50% 50%

Derating Curves

38 Product Name Datasheet

12.0 Derating Curves

Figure 9. Typical Output Delay Variations Versus Load Capacitance

Figure 10. Typical Rise and Fall Variations Versus Load Capacitance

Reset

Product Name Datasheet 39

13.0 Reset

The processor performs a reset operation any time the RESIN pin is active. The RESIN pin is

actually synchronized before it is presented internally, which means that the clock must be

operating before a reset can take effect. From a power-on state, RESIN must be held active (low) in

order to guarantee correct initialization of the processor. Failure to provide RESIN while the

device is powering up will result in unspecified operation of the device.

Figure 11 shows the correct reset sequence when first applying power to the processor. An external

clock connected to CLKIN must not exceed the VCC threshold being applied to the processor. This

is normally not a problem if the clock driver is supplied with the same VCC that supplies the

processor. When attaching a crystal to the device, RESIN must remain active until both VCC and

CLKOUT are stable (the length of time is application specific and depends on the startup

characteristics of the crystal circuit). The RESIN pin is designed to operate correctly using an RC

reset circuit, but the designer must ensure that the ramp time for VCC is not so long that RESIN is

never really sampled at a logic low level when VCC reaches minimum operating conditions.

Figure 12 shows the timing sequence when RESIN is applied after VCC is stable and the device has

been operating. Note that a reset will terminate all activity and return the processor to a known

operating state. Any bus operation that is in progress at the time RESIN is asserted will terminate

immediately (note that most control signals will be driven to their inactive state first before

floating).

While RESIN is active, signals RD/QSMD,UCS,LCS,MCS0/PEREQ, MCS1/ERROR,LOCK,

and TEST/BUSY are configured as inputs and weakly held high by internal pull-up transistors.

Forcing UCS and LCS low selects ONCE Mode. Forcing QSMD low selects Queue Status Mode.

Forcing TEST/ BUSY high at reset and low four clocks later enables Numerics Mode. Forcing

LOCK low is prohibited and results in unspecified operation.

Reset

40 Product Name Datasheet

Figure 11. Powerup Reset Waveforms

Notes:

1. CLKOUT synchronization occurs approximately 1½ CLKIN periods after RESIN# is sampled low.

2. Pin names in parentheses apply to the 80C188EA.

Reset

Product Name Datasheet 41

Figure 12. Warm Reset Waveforms

Notes:

1. CLKOUT resynchronization occurs approximately 1½ CLKIN periods after RESIN# is sampled low. If RESIN# is

sampled low while transitioning high, then CLKOUT will remain high for two CLKIN periods. If RESIN# is

sampled low while CLKOUT is transitioning high, the CLKOUT will not be affected.

2. Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

42 Product Name Datasheet

14.0 Bus Cycle Waveforms

Figure 13 through Figure 19 present the various bus cycles that are generated by the processor.

What is shown in the figure is the relationship of the various bus signals to CLKOUT. These

figures along with the information present in AC Specifications allow the user to determine all the

critical timing analysis needed for a given application.

Figure 13. Read, Fetch and Refresh Cycle Waveform

Notes:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA or refresh cycle.

2. Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

Product Name Datasheet 43

Figure 14. Write Cycle Waveform

Notes:

1. During the data phase of the bus cycle, A19/S6 is driven high for a DMA cycle.

2. Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

44 Product Name Datasheet

Figure 15. Halt Cycle Waveform

Notes:

1. The processor drives these pins to 0 during Idle and Powerdown Modes.

2. Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

Product Name Datasheet 45

Figure 16. INTA Cycle Waveform

Notes:

1. INTA# occurs one clock later in Slave Mode.

2. Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

46 Product Name Datasheet

Figure 17. HOLD/HLDA Waveform

Note: Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

Product Name Datasheet 47

Figure 18. DRAM Refresh Cycle During Hold Acknowledge

Note: Pin names in parentheses apply to the 80C188EA.

Bus Cycle Waveforms

48 Product Name Datasheet

Figure 19. Ready Waveform

Notes:

1. Generalized diagram for READ or WRITE.

2. ARDY low by either edge causes a wait state. Only rising ARDY is fully synchronized.

3. SRDY low causes a wait state. SRDY must meet setup and hold times to ensure correct device operation.

4. Either ARDY or SRDY active high will terminate a bus cycle.

5. Pin names in parentheses apply to the 80C188EA.

Product Name Execution Timings

Product Name Datasheet 49

15.0 Product Name Execution Timings

A determination of program execution timing must consider the bus cycles necessary to prefetch

instructions as well as the number of execution unit cycles necessary to execute instructions. The

following instruction timings represent the minimum execution time in clock cycle for each

instruction. The timings given are based on the following assumptions:

•The opcode, along with any data or displacement required for execution of a particular

instruction, has been prefetched and resides in the queue at the time it is needed.

•No wait states or bus HOLDs occur.

•All word-data is located on even-address boundaries. (80C186EA only)

All jumps and calls include the time required to fetch the opcode of the next instruction at the

destination address.

All instructions which involve memory accesses can require one or two additional clocks above the

minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU)

and execution unit.

With a 16-bit BIU, the 80C186EA has sufficient bus performance to endure that an adequate

number of prefetched bytes will reside in the queue (6 bytes) most of the time. Therefore, actual

program execution time will not be substantially greater than that derived from adding the

instruction timings shown.

The 80C188EA 8-bit BIU is limited in its performance relative to the execution unit. A sufficient

number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time.

Therefore, actual program execution time will be substantially greater than that derived from

adding the instruction timings shown.

Product Name Execution Timings

50 Product Name Datasheet

Figure 20. Instruction Set Summary

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

DATA TRANSFER

MOV eMove%

Immediatetoregistermemory 1100011w mod000 rm data dataifw

e1 12–13 12–13 816-bit

Immediatetoregister 1011w reg data dataifw

e1 3–4 3–4 816-bit

Memory to accumulator 1010000w addr-low addr-high 8 8

Accumulator to memory 1010001w addr-low addr-high 9 9

Segment register to registermemory 10001100 mod0reg rm 211 215

PUSH ePush%

Memory 11111111 mod110 rm 16 20

Segment register 000reg110 9 13

Immediate 011010s0 data dataifs

e01014

PUSHA ePush All 01100000 36 68

POP ePop%

Memory 10001111 mod000 rm 20 24

Segment register 000reg111 (reg

i01) 8 12

POPA ePopAll 01100001 51 83

XCHG eExchange%

IN eInput from%

Fixedport 1110010w port 10 10

Variableport 1110110w 8 7

OUT eOutput to%

Fixedport 1110011w port 9 9

Variableport 1110111w 7 7

XLAT eTranslate byte to AL 11010111 11 15

LEA eLoad EA to register 10001101 modreg rm 6 6

LDS eLoad pointer to DS 11000101 modreg rm (mod

i11) 18 26

LES eLoad pointer to ES 11000100 modreg rm (mod

i11) 18 26

LAHF eLoad AH with flags 10011111 2 2

SAHF eStoreAHintoflags 10011110 3 3

PUSHF ePush flags 10011100 9 13

POPF ePopflags 10011101 8 12

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

Product Name Execution Timings

Product Name Datasheet 51

Figure 20. Instruction Set Summary (Continued)

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

DATA TRANSFER (Continued)

SEGMENT eSegment Override%

CS 00101110 2 2

SS 00110110 2 2

DS 00111110 2 2

ES 00100110 2 2

ARITHMETIC

ADD eAdd%

Regmemory with register to either 000000dw modreg rm 310 310

Immediatetoregistermemory 100000sw mod000 rm data dataifsw

e01 416 416

Immediate to accumulator 0000010w data dataifw

e1 34 34 816-bit

ADC eAdd with carry%

Regmemory with register to either 000100dw modreg rm 310 310

Immediatetoregistermemory 100000sw mod010 rm data dataifsw

e01 416 416

Immediate to accumulator 0001010w data dataifw

e1 34 34 816-bit

INC eIncrement%

SUB eSubtract%

Regmemory and register to either 001010dw modreg rm 310 310

Immediatefromregistermemory 100000sw mod101 rm data dataifsw

e01 416 416

Immediate from accumulator 0010110w data dataifw

e1 34 34 816-bit

SBB eSubtract with borrow%

Regmemory and register to either 000110dw modreg rm 310 310

Immediatefromregistermemory 100000sw mod011 rm data dataifsw

e01 416 416

Immediate from accumulator 0001110w data dataifw

e1 34 34816-bit

DEC eDecrement

CMP eCompare%

Immediatewithregistermemory 100000sw mod111 rm data dataifsw

e01 310 310

Immediate with accumulator 0011110w data dataifw

e1 34 34 816-bit

NEG eChange sign registermemory 1111011w mod011 rm 310310

AAA eASCII adjust for add 00110111 8 8

DAA eDecimal adjust for add 00100111 4 4

AAS eASCII adjust for subtract 00111111 7 7

DAS eDecimal adjust for subtract 00101111 4 4

MUL eMultiply (unsigned) 1111011w mod100 rm

Memory-Byte 32–34 32– 34

Memory-Word 41–43 41– 48

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

Product Name Execution Timings

52 Product Name Datasheet

Figure 20. Instruction Set Summary (Continued)

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

ARITHMETIC (Continued)

IMUL eInteger multiply (signed) 1111011w mod101 rm

Memory-Byte 31–34 32–34

Memory-Word 40–43 40–43

IMUL eInteger Immediate multiply 011010s1 modreg rm data data if se0 22–25 22-25

(signed) 29–32 29–32

DIV eDivide (unsigned) 1111011w mod110 rm

Memory-Byte 35 35

Memory-Word 44 44

IDIV eInteger divide (signed) 1111011w mod111 rm

Memory-Byte 50–58 50–58

Memory-Word 59–67 59–67

AAM eASCII adjust for multiply 11010100 00001010 19 19

AAD eASCII adjust for divide 11010101 00001010 15 15

CBW eConvert byte to word 10011000 2 2

CWD eConvert word to double word 10011001 4 4

LOGIC

ShiftRotate Instructions%

an17an5

an17an

TTT Instruction

000 ROL

001 ROR

010 RCL

011 RCR

1 0 0 SHLSAL

101 SHR

111 SAR

AND eAnd%

Regmemory and register to either 001000dw modreg rm 310 310

Immediate to registermemory 1000000w mod100 rm data data if we1 416 416

Immediate to accumulator 0010010w data data if we1 34 34816-bit

TESTeAnd function to flags no result%

Immediate data and registermemory 1111011w mod000 rm data data if we1 410 410

Immediate data and accumulator 1010100w data data if we1 34 34 816-bit

OReOr%

Regmemory and register to either 000010dw modreg rm 310 310

Immediate to registermemory 1000000w mod001 rm data data if we1 416 416

Immediate to accumulator 0000110w data data if we1 34 34816-bit

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

Product Name Execution Timings

Product Name Datasheet 53

Figure 20. Instruction Set Summary (Continued)

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

LOGIC (Continued)

XOR

Exclusive or%

Regmemory and register to either 001100dw modreg rm 310 310

Immediate to registermemory 1000000w mod110 rm data data if w

1 416 416

Immediate to accumulator 0011010w data data if w

1 34 34 816-bit

NOT

Invert registermemory 1111011w mod010 rm 310 310

STRING MANIPULATION

MOVS

Move byteword 1010010w 14 14

CMPS

Compare byteword 1010011w 22 22

SCAS

Scan byteword 1010111w 15 15

LODS

Load bytewd to ALAX 1010110w 12 12

STOS

Store bytewd from ALAX 1010101w 10 10

INS

Input bytewd from DX port 0110110w 14 14

OUTS

Output bytewd to DX port 0110111w 14 14

Repeated by count in CX (REPREPEREPZREPNEREPNZ)

MOVS

Move string 11110010 1010010w 8

8n 8

8n

CMPS

Compare string 1111001z 1010011w 5

22n 5

22n

SCAS

Scan string 1111001z 1010111w 5

15n 5

15n

LODS

Load string 11110010 1010110w 6

11n 6

11n

STOS

Store string 11110010 1010101w 6

9n 6

9n

INS

Input string 11110010 0110110w 8

8n 8

8n

OUTS

Output string 11110010 0110111w 8

8n 8

8n

CONTROL TRANSFER

CALL

Call%

Direct within segment 11101000 disp-low disp-high 15 19

indirect within segment

Direct intersegment 10011010 segment offset 23 31

segment selector

Indirect intersegment 11111111 mod011 rm (mod i11) 38 54

JMP

Unconditional jump%

Shortlong 11101011 disp-low 14 14

Direct within segment 11101001 disp-low disp-high 14 14

indirect within segment

Direct intersegment 11101010 segment offset 14 14

segment selector

Indirect intersegment 11111111 mod101 rm (mod i11) 26 34

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

Product Name Execution Timings

54 Product Name Datasheet

Figure 20. Instruction Set Summary (Continued)

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

CONTROL TRANSFER (Continued)

RET eReturn from CALL%

Within segment 11000011 16 20

Within seg adding immed to SP 11000010 data-low data-high 18 22

Intersegment 11001011 22 30

Intersegment adding immediate to SP 11001010 data-low data-high 25 33

JEJZ eJump on equalzero 01110100 disp 413 413 JMP not

JLJNGE eJump on lessnot greater or equal 01111100 disp 413 413 takenJMP

JLEJNG eJump on less or equalnot greater 01111110 disp 413 413

taken

JBJNAE eJump on belownot above or equal 01110010 disp 413 413

JBEJNA eJump on below or equalnot above 01110110 disp 413 413

JPJPE eJump on parityparity even 01111010 disp 413 413

JO eJump on overflow 01110 000 disp 413 413

JS eJumponsign 01111000 disp 413 413

JNEJNZ eJump on not equalnot zero 01110101 disp 413 413

JNLJGE eJump on not lessgreater or equal 01111101 disp 413 413

JNLEJG eJump on not less or equalgreater 01111111 disp 413 413

JNBJAE eJump on not belowabove or equal 01110011 disp 413 413

JNBEJA eJump on not below or equalabove 01110111 disp 413 413

JNPJPO eJump on not parpar odd 01111011 disp 413 413

JNO eJump on not overflow 01110001 disp 413 413

JNS eJumponnotsign 01111001 disp 413 413

JCXZ eJump on CX zero 11100011 disp 515 515

LOOP eLoop CX times 11100010 disp 616 616 LOOP not

LOOPZLOOPE eLoop while zeroequal 11100001 disp 616 616 takenLOOP

LOOPNZLOOPNE eLoop while not zeroequal 11100000 disp 616 616

taken

ENTER eEnter Procedure 11001000 data-low data-high L

Le015 19

Le125 29

Ll1

16(n

1) 26

20(n

LEAVE eLeave Procedure 11001001 8 8

INT eInterrupt%

Type specified 11001101 type 47 47

Type 3 11001100 45 45 ifINTtaken

INTO eInterrupt on overflow 11001110 484 484 if INT not

taken

IRET eInterrupt return 11001111 28 28

BOUND eDetect value out of range 01100010 modreg rm 33–35 33–35

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

Product Name Execution Timings

Product Name Datasheet 55

Figure 20. Instruction Set Summary (Continued)

Function Format

80C186EA 80C188EA

Comments

Clock Clock

Cycles Cycles

PROCESSOR CONTROL

CLC eClear carry 11111000 2 2

CMC eComplement carry 11110101 2 2

STC eSet carry 11111001 2 2

CLD eClear direction 11111100 2 2

STD eSet direction 11111101 2 2

CLI eClear interrupt 11111010 2 2

STI eSet interrupt 11111011 2 2

HLT eHalt 11110100 2 2

WAIT eWait 10011011 6 6 ifTESTe0

LOCK eBus lock prefix 11110000 2 2

NOP eNo Operation 10010000 3 3

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 80868088 microsystems

NOTE%

Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers

The Effective Address (EA) of the memory operand

is computed according to the mod and rm fields

if mod

11 then rm is treated as a REG field

if mod

00 then DISP

0 disp-low and disp-

high are absent

if mod

01 then DISP

disp-low sign-ex-

tended to 16-bits disp-high is absent

if mod

10 then DISP

disp-high disp-low

if rm

000 then EA

(BX)

(SI)

DISP

if rm

001 then EA

(BX)

(DI)

DISP

if rm

010 then EA

(BP)

(SI)

DISP

if rm

011 then EA

(BP)

(DI)

DISP

if rm

100 then EA

(SI)

DISP

if rm

101 then EA

(DI)

DISP

if rm

110 then EA

(BP)

DISP

if rm

111 then EA

(BX)

DISP

DISP follows 2nd byte of instruction (before data if

required)

except if mod

00 and rm

110 then EA

disp-high disp-low

EA calculation time is 4 clock cycles for all modes

and is included in the execution times given whenev-

er appropriate

Segment Override Prefix

0 0 1 reg 1 1 0

reg is assigned according to the following

Segment

reg Register

00 ES

01 CS

10 SS

11 DS

REG is assigned according to the following table

16-Bit (w

1) 8-Bit (w

000 AX 000 AL

001 CX 001 CL

010 DX 010 DL

011 BX 011 BL

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed

by the BP register are computed using the SS seg-

ment register The physical addresses of the desti-

nation operands of the string primitive operations

(those addressed by the DI register) are computed

using the ES segment which may not be overridden

Revision History

56 Product Name Datasheet

16.0 Revision History

Intel 80C186EA/80L186EA devices are marked with a 9-character alphanumeric Intel FPO

number underneath the product number. This data sheet update is valid for devices with an “A”,

“B”, “C”, “D”, or “E” as the ninth character in the FPO number, as illustrated in Figure 3 for the

68-lead PLCC package, and as also illustrated in diagrams of the 84-lead QFP (EIAJ) package in

previous revisions of this datasheet. Such devices may also be identified by reading a value of 01H,

02H, 03H from the STEPID register.

This data sheet replaces the following data sheets:

•272019-002—80C186EA

•272020-002—80C188EA

•272021-002—80L186EA

•272022-002—80L188EA

•272307-001—SB80C186EA/SB80L186EA

•272308-001—SB80C188EA/SB80L188EA

17.0 Errata

An 80C186EA/80L186EA with a STEPID value of 01H or 02H has the following known errata. A

device with a STEPID of 01H or 02H can be visually identified by noting the presence of an “A,”

“B”, or “C” alpha character, next to the FPO number. The FPO number location is shown in

Figure 3.

1. An internal condition with the interrupt controller can cause no acknowledge cycle on the

INTA1 line in response to INT1. This errata only occurs when Interrupt 1 is configured in

cascade mode and a higher priority interrupt exists. This errata will not occur consistently, it is

dependent on interrupt timing.

An 80C186EA/80L186EA with a STEPID value of 03H has no known errata. A device with a

STEPID of 03H can be visually identified by noting the presence of a “D” or “E” alpha character

next to the FPO number. The FPO number location is shown in Figure 3.