Angle Sensor GMR-Based Angle Sensor TLE5012B Data Sheet V 1.1, 2012-01 Final Sensors Edition 2012-01 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2012 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. TLE5012B Revision History Page or Item Subjects (major changes since previous revision) V 1.1, 2012-01 12 Table 1, SPC interface at pin 5 added 31 Table 16, bit[14] and bit[12] updated 33 Sensor with preset PWM added 35 Sensor with preset SPC added 37 Sensor with preset HSM added 41 Sensor with preset IIF added general Correction of typing errors Trademarks of Infineon Technologies AG AURIXTM, BlueMoonTM, COMNEONTM, C166TM, CROSSAVETM, CanPAKTM, CIPOSTM, CoolMOSTM, CoolSETTM, CORECONTROLTM, DAVETM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPACKTM, EconoPIMTM, EiceDRIVERTM, EUPECTM, FCOSTM, HITFETTM, HybridPACKTM, ISOFACETM, IRFTM, IsoPACKTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OmniTuneTM, OptiMOSTM, ORIGATM, PROFETTM, PRO-SILTM, PRIMARIONTM, PrimePACKTM, RASICTM, ReverSaveTM, SatRICTM, SIEGETTM, SINDRIONTM, SMARTiTM, SmartLEWISTM, TEMPFETTM, thinQ!TM, TriCoreTM, TRENCHSTOPTM, X-GOLDTM, XMMTM, X-PMUTM, XPOSYSTM. Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM, ARMTM, MULTI-ICETM, PRIMECELLTM, REALVIEWTM, THUMBTM of ARM Limited, UK. AUTOSARTM is licensed by AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM, FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. FlexRayTM is licensed by FlexRay Consortium. HYPERTERMINALTM of Hilgraeve Incorporated. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM, NUCLEUSTM of Mentor Graphics Corporation. MifareTM of NXP. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM Openwave Systems Inc. RED HATTM Red Hat, Inc. RFMDTM RF Micro Devices, Inc. SIRIUSTM of Sirius Sattelite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM, PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM, WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex Limited. Last Trademarks Update 2010-06-09 Final Data Sheet 3 V 1.1, 2012-01 TLE5012B Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 1.1 1.2 1.3 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 12 12 13 13 13 13 13 14 14 14 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.5 3.5.1 3.5.1.1 3.5.1.2 3.5.1.3 3.5.2 3.5.3 3.5.3.1 3.5.3.2 3.5.3.3 3.5.4 3.5.5 3.6 3.6.1 3.7 3.7.1 3.7.2 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulse Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Short PWM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unit Time Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master Pulse Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Checksum nibble details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 15 18 18 20 20 21 22 23 23 26 27 27 28 30 33 33 35 36 36 37 37 41 42 42 44 44 44 Final Data Sheet 4 8 8 9 9 V 1.1, 2012-01 TLE5012B Table of Contents 3.7.3 3.7.4 4 4.1 4.2 4.3 4.4 4.5 GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Final Data Sheet 5 46 46 46 47 47 48 V 1.1, 2012-01 TLE5012B List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Sensitive bridges of the GMR sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ideal output of the GMR sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TLE5012B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PRO-SILTM Logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit for TLE5012B with SSC and PWM interface (using internal CLK) . . . . . . . . . . Application circuit for TLE5012B with HS Mode (using internal CLK) . . . . . . . . . . . . . . . . . . . . . . Application circuit for TLE5012B with SSC and IIF interface (using external CLK) . . . . . . . . . . . . Application circuit for TLE5012B with only PWM interface (using internal CLK) . . . . . . . . . . . . . . Application circuit for TLE5012B with only SPC interface (S_NR = 00) . . . . . . . . . . . . . . . . . . . . . Magnet performance (ambient temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External CLK timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC configuration in sensor-slave mode with push-pull outputs (high-speed application) . . . . . . SSC configuration in sensor-slave mode and open drain (safe bus systems) . . . . . . . . . . . . . . . . SSC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Update of update registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast CRC polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical example of a PWM signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPC frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPC Master pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HS hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental interface with A/B mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental interface with Step/Direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OV comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PG-DSO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint of PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Final Data Sheet 6 10 11 12 13 14 15 16 16 17 17 19 22 24 25 26 27 28 28 30 30 32 32 33 34 35 36 38 41 41 42 43 44 45 45 46 47 47 47 V 1.1, 2012-01 TLE5012B List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters for 4.5V < VDD < 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical parameters for 3.0V < VDD < 3.6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic GMR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLK timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAD characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bit Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frame configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of status nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predivider setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Master pulse parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Command to enable ADC test vector check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure of Write Data for various test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Final Data Sheet 7 12 18 18 20 21 21 21 22 23 24 26 27 28 29 30 31 31 34 35 36 36 37 38 42 42 43 43 44 46 V 1.1, 2012-01 TLE5012B 1 Product Description 1.1 Overview The TLE5012B is a 360 angle sensor that detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR) elements. Highly precise angle values are adetermined over a wide temperature range and a long lifetime using an internal autocalibration algorithm. Data communications are accomplished with a bi-directional Synchronous Serial Communication (SSC) that is SPI-compatible. The absolute angle value and other values are transmitted via SSC or via a Pulse-Width-Modulation (PWM) Protocol. The sine and cosine raw values can also be read out. These raw signals are digitally processed internally to calculate the angle orientation of the magnetic field (magnet). The TLE5012B is a pre-calibrated sensor. The calibration parameters are stored in laser fuses. At start-up the values of the fuses are written into flip-flops, where these values can be changed by the application-specific parameters. Online diagnostic functions are provided to ensure reliable operation. Product Type Marking Ordering Code Package TLE5012B E1000 012B1000 SP000905682 PG-DSO-8 TLE5012B E3005 012B3005 SP000905686 PG-DSO-8 TLE5012B E5000 012B5000 SP000905690 PG-DSO-8 TLE5012B E9000 012B9000 SP000905694 PG-DSO-8 Final Data Sheet 8 V 1.1, 2012-01 TLE5012B Product Description 1.2 * * * * * * * * * * * * * * Features Giant Magneto Resistance (GMR)-based principle Integrated magnetic field sensing for angle measurement Full calibrated 0 - 360 angle measurement with revolution counter and angle speed measurement Two separate highly accurate single bit SD-ADC 15 bit representation of absolute angle value on the output (resolution of 0.01) 16 bit representation of sine / cosine values on the interface Max. 1.0 angle error over lifetime and temperature-range with activated auto-calibration Bi-directional SSC Interface up to 8Mbit/s Supports Safety Integrity Level (SIL) with diagnostic functions and status information Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM), Short PWM Code (SPC) 0.25 m CMOS technology Automotive qualified: -40C to 150C (junction temperature) ESD > 4kV (HBM) RoHS compliant (Pb-free package) 1.3 Application Example The TLE5012B GMR-based angle sensor is designed for angular position sensing in automotive applications such as: * * * * Electrical commutated motor (e.g. used in Electric Power Steering (EPS)) Rotary switches Steering angle measurements General angular sensing Final Data Sheet 9 V 1.1, 2012-01 TLE5012B Functional Description 2 Functional Description 2.1 General The Giant Magneto Resistance (GMR) sensor is implemented using vertical integration. This means that the GMR-sensitive areas are integrated above the logic portion of the TLE5012B device. These GMR elements change their resistance depending on the direction of the magnetic field. Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense one of two components of the applied magnetic field: * * X component, Vx (cosine) or the Y component, Vy (sine) The advantage of a full-bridge structure is that the maximum GMR signal is available and temperature effects cancel out each other. GMR Resistors S 0 VX VY N ADCX + ADCX - GND ADCY+ ADCY- VDD 90 Figure 1 Sensitive bridges of the GMR sensor Note: In Figure 1, the arrows in the resistors represent the magnetic direction which is fixed in the reference layer. If the external magnetic field is parallel to the direction of the Reference Layer, the resistance is minimal. If they are anti-parallel, resistance is maximal. The output signal of each bridge is only unambiguous over 180 between two maxima. Therefore two bridges are orientated orthogonally to each other to measure 360. With the trigonometric function ARCTAN, the true 360 angle value can be calculated, based on the relationship of X and Y signals. Because only the relative values influence the result, the absolute magnitude of the two signals is of minor importance. Therefore, it is possible to compensate for most external influences on the amplitudes. Final Data Sheet 10 V 1.1, 2012-01 TLE5012B Functional Description Y Component (SIN) VY X Component (COS) VX V VX (COS) 0 90 180 270 360 Angle VY (SIN) Figure 2 Ideal output of the GMR sensor bridges Final Data Sheet 11 V 1.1, 2012-01 TLE5012B Functional Description 2.2 Pin Configuration 8 7 6 5 1 2 3 4 Figure 3 Pin configuration (top view) 2.3 Pin Description Table 1 Pin Description Center of Sensitive Area Pin No. Symbol In/Out Function 1 IFC (CLK / IIF_IDX / HS3) I/O Interface C: External Clock / IIF Index / Hall Switch Signal 3 2 SCK I SSC Clock 3 CSQ I SSC Chip Select 4 DATA I/O SSC Data 5 IFA O (IIF_A / HS1 / PWM / SPC) Interface A: IIF Phase A / Hall Switch Signal 1 / PWM / SPC output 6 VDD - Supply Voltage 7 GND - Ground 8 IFB (IIF_B / HS2) O Interface B: IIF Phase B / Hall Switch Signal 2 Final Data Sheet 12 V 1.1, 2012-01 TLE5012B Functional Description 2.4 Block Diagram TLE5012B VRG VRA VRD X GMR SDADC Digital Signal Processing Unit Y GMR Temp SDADC SDADC VDD GND CSQ SSC Interface DATA IFA CCU Cordic Fuses Incremental IF PWM HSM TLE5012B block diagram 2.5 Functional Block Description 2.5.1 Internal Power Supply IFB IFC Osc Figure 4 SCK PLL The internal stages of the TLE5012B are supplied with several voltage regulators: * * * GMR Voltage Regulator, VRG Analog Voltage Regulator, VRA Digital Voltage Regulator, VRD (derived from VRA) These regulators are directly connected to the supply voltage VDD. 2.5.2 Oscillator and PLL The internal frequency oscillator feeds the Phase-Locked Loop (PLL). Therefore, the external clock (CLK) can also be used. 2.5.3 SD-ADC The SD-ADCs transform the analog GMR voltages and temperature voltage into the digital domain. Final Data Sheet 13 V 1.1, 2012-01 TLE5012B Functional Description 2.5.4 Digital Signal Processing Unit The Digital Signal Processing Unit (DSPU) contains the: * * * Capture Compare Unit (CCU), which is used to generate the PWM signal COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle calculation Fuses, which contain the calibration parameters 2.5.5 Interfaces Various Interfaces can be selected: * * * * * SSC Interface PWM Incremental Interface Hall Switch Mode Short PWM Code 2.5.6 Safety Features The TLE5012B offers a multiplicity of safety features to support the Safety Integrity Level (SIL). Infineon's sensors that are intended for this purpose are identified by the following logo: Figure 5 PRO-SILTM Logo Safety features are: * * * * * * Test vectors switchable to ADC input Inversion or combination of filter input streams Data transmission check via 8-bit Cyclic Redundancy Check (CRC) Self-test routines Two independent active interfaces possible Overvoltage and undervoltage detection Disclaimer PRO-SILTM is a Registered Trademark of Infineon Technologies AG. The PRO-SILTM Trademark designates Infineon products which contain SIL Supporting Features. SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency. SIL respectively A-SIL certification for such a System has to be reached on system level by the System Responsible at an accredited Certification Authority. SIL stands for Safety Integrity Level (according to IEC 61508) A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262) Final Data Sheet 14 V 1.1, 2012-01 TLE5012B Specification 3 Specification 3.1 Application Circuit The application circuits in Figure 6, Figure 7, Figure 8 and Figure 9 show the various communication possibilities of the TLE5012B. TLE5012B VDD (3.0 - 5.5V) 100n 1 k VRG VRA VRD X GMR SDADC Digital Signal Processing Unit Y GMR Temp SDADC SDADC CSQ SSC Interface DATA IFA (PWM) CCU Cordic Fuses SCK Incremental IF PWM HSM Osc PLL SSC *) PWM IFB IFC IFB, IFC can be remain open (internal Pull Down ). GND *) recommended , e.g. 470 Figure 6 Application circuit for TLE5012B with SSC and PWM interface (using internal CLK) Figure 6 shows a basic block diagram of the TLE5012B with PWM interface.In addition to the PWM interface, the SSC interface could be used. Within the SSC interface, the PWM mode is selectable between push-pull and opendrain. Final Data Sheet 15 V 1.1, 2012-01 TLE5012B Specification TLE5012B VDD (3.0 - 5.5V) 100n VRG VRA VRD *) X GMR SDADC Y GMR SDADC Temp SDADC *) *) CSQ Digital Signal Processing Unit SSC Interface DATA Fuses 10 k IFA (HS1) CCU Cordic SCK Incremental IF PWM HSM Osc PLL IFB (HS2) IFC (HS3) GND *) recommended , e.g. 2.2 k Figure 7 Application circuit for TLE5012B with HS Mode (using internal CLK) Figure 7 shows a basic block diagram of the TLE5012B with HS Mode. In addition to the HS Mode, the SSC interface could be used in parallel. Within the SSC- Interface, the HS Mode is selectable between push-pull and open-drain. VDD (3.0 - 5.5V) TLE5012B 100n VRG VRA VRD X GMR SDADC Digital Signal Processing Unit Y GMR SDADC Temp SDADC C PLL CSQ SSC Interface DATA Fuses SSC *) IFA (IIF_A) CCU Cordic SCK Incremental IF PWM HSM Osc PLL IFB (IIF_B) CCU IFC (IIF_IDX) GND *) recommended , e.g. 470 Figure 8 Application circuit for TLE5012B with SSC and IIF interface (using external CLK) Figure 8 shows a basic block diagram of an angle-sensor system using a TLE5012B and a microcontroller for rotor positioning applications. The depicted interface configuration is needed for high-speed applications suchas electrical commutated motor drives. It is possible to connect the TLE5012B to a microcontroller via Incremental Interface and for safety reasons also via the SSC interface. Final Data Sheet 16 V 1.1, 2012-01 TLE5012B Specification The TLE5012B can be configured with PWM only (Figure 9). This is only possible with the TLE5012B-E5000 type.1) TLE5012B VDD (3.0 - 5.5V) 100 n 1 k VRG VRA VRD X GMR SDADC Digital Signal Processing Unit Y GMR Temp SDADC SDADC CSQ DATA Cordic Fuses 10 k DATA and IFB could be remain open or connected via 10 k resistor to GND . IFA (PWM) CCU Incremental IF PWM HSM Osc Figure 9 SCK SSC Interface IFB IFB, IFC can be remain open (internal Pull Down ). IFC GND PLL Application circuit for TLE5012B with only PWM interface (using internal CLK) The TLE5012B can be configured with SPC only (Figure 9). This is only possible with the TLE5012B-E9000 type.1) TLE5012B VDD (3.0 - 5.5V) 100 n 1 k VRG VRA VRD X GMR SDADC Digital Signal Processing Unit Y GMR Temp SDADC SDADC CSQ DATA Cordic Fuses 10 k IFA (SPC) CCU Incremental IF PWM HSM Osc Figure 10 SCK SSC Interface DATA and IFB could be remain open or connected via 10 k resistor to GND . IFB IFC GND PLL Application circuit for TLE5012B with only SPC interface (S_NR = 00) 1) For more information get in contact with Infineon Final Data Sheet 17 V 1.1, 2012-01 TLE5012B Specification 3.2 Absolute Maximum Ratings Table 2 Absolute maximum ratings Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. Voltage on VDD pin with respect to VDD ground (VSS) -0.5 6.5 V Max 40 h/Lifetime Voltage on any pin with respect to VIN ground (VSS) -0.5 6.5 V Additionally VDD + 0.5 V may not be exceeded Junction temperature -40 150 C Magnetic field induction Storage temperature TJ B TST -40 150 C For 1000 h, not additive 200 mT Max. 5 min @ TA = 25C 150 mT Max. 5 h @ TA = 25C 150 C Without magnetic field Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the device. 3.3 Operating Range The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012B. All parameters specified in the following sections refer to these operating conditions, unless otherwise noted. Table 3 is valid for -40C < TJ < 150C unless otherwise noted. Table 3 Operating range Parameter Symbol Values Min. Supply voltage VDD Output current (DATA-Pad) IQ Output current (IFA / IFB / IFC Pad) Input voltage Final Data Sheet Typ. 3.0 5.0 IQ VIN -0.3 Unit Note / Test Condition Max. 5.5 V 1) -25 mA PAD_DRV ='0x', sink current2)3) -5 mA PAD_DRV ='10', sink current2)3) -0.4 mA PAD_DRV ='11', sink current2)3) -15 mA PAD_DRV ='0x', sink current2)3) -5 mA PAD_DRV ='1x', sink current2)3) 5.5 V 18 VDD + 0.3 V may not be exceeded V 1.1, 2012-01 TLE5012B Specification Table 3 Operating range (cont'd) Parameter Symbol Values Min. Magnetic induction at TA = 25C Typ. Unit Note / Test Condition Max. BXY 30 50 mT -40C < TJ < 150C BXY 30 60 mT -40C < TJ < 100C BXY 30 70 mT -40C < TJ < 85C Expanded magnetic induction at TA = 25C 4)5)6) BXY 25 30 mT Additional angle error of 0.1 Angle range Ang 0 4)5) 1) 2) 3) 4) 5) 6) 360 Directly blocked with 100-nF ceramic capacitor Max. current to GND over open-drain output At VDD = 5V Values refer to a homogeneous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT). See Figure 11 0h The field strength of a magnet can be selected within the colored area of Figure 11. By limitation of the junction temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ=100C, a magnet with up to 60mT at TA = 25C is allowed. It is also possible to widen the magnetic field range for higher temperatures. In that case, additional angle errors have to be considered (see Application Note "GMR Angle Error Extension"). Figure 11 Magnet performance (ambient temperature) Note: The thermal resistances listed in Table 29 "Package Parameters" on Page 46 must be used to calculate the corresponding ambient temperature of the sensor. Final Data Sheet 19 V 1.1, 2012-01 TLE5012B Specification Calculation of the Junction Temperature The total power dissipation PTOT of the chip increases its temperature above the ambient temperature. The power multiplied by the total thermal resistance RthJA (junction to ambient) leads to the final junction temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to Ambient. (1) RthJA = RthJC + RthCA TJ = TA + T T = RthJA x PTOT = RthJA x (VDD x I DD + (VDD - VOUT ) x I OUT ) Example (assuming no load on Vout): (2) V DD = 5V I DD = 14 mA K T = 150 W x (5[V ]x 0 . 014 [ A ] + 0 [VA ]) = 10 . 5 K For molded sensors, the calculation with RthJC is more appropriate. 3.4 Characteristics 3.4.1 Electrical Parameters The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values correspond to a supply voltage VDD = 5.0 V and 25 C, unless individually specified. All other values correspond to -40 C < TJ < 150C. Table 4 Electrical parameters Parameter Symbol Values Min. Supply current IDD POR level VPOR POR hysteresis VPORhy Pull-up current IPU Pull-down current Power-on time 1) IPD tPon Typ. Unit Note / Test Condition Max. 14 16 mA 2.0 2.9 V 30 Power-on reset mV -10 -225 A CSQ -10 -150 A DATA 10 225 A SCK 10 150 A IFA, IFB, IFC 5 7 ms 0.5 ms VDD > VDDmin; SBIST = 1 VDD > VDDmin; SBIST = 02) 1) Within "Power-on time," write access is not permitted 2) Not subject to production test - verified by design/characterization Final Data Sheet 20 V 1.1, 2012-01 TLE5012B Specification Table 5 Electrical parameters for 4.5V < VDD < 5.5V Parameter Symbol Values Min. Input signal low level VL5 Input signal high level VH5 Output signal low level VOL5 Table 6 Unit Typ. Note / Test Condition Max. 0.3 VDD V 0.7 VDD V 1 V DATA; IQ = -25 mA (PAD_DRV='0x'), IQ = -5 mA (PAD_DRV='10'), IQ = -0.4 mA (PAD_DRV='11') 1 V IFA,IFB, IFC; IQ = -15 mA (PAD_DRV='0x'), IQ = -5 mA (PAD_DRV='1x') Electrical parameters for 3.0V < VDD < 3.6V Parameter Symbol Values Min. Input signal low level VL3 Input signal high level VH3 Output signal low level VOL3 3.4.2 ESD Protection Table 7 ESD protection Parameter Typ. Note / Test Condition Max. 0.3 VDD V 0.7 VDD Symbol V Values min. ESD voltage Unit 0.9 V DATA; IQ = -15 mA (PAD_DRV='0x'), IQ = -3 mA (PAD_DRV='10'), IQ = -0.24 mA (PAD_DRV='11') 0.9 V IFA,IFB; IQ = - 10 mA (PAD_DRV='0x'), IQ = -3 mA (PAD_DRV='1x') Unit Notes max. VHBM 4.0 kV Human Body Model1) VSDM 0.5 kV Socketed Device Model2) 1) Human Body Model (HBM) according to: AEC-Q100-002 2) Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008 Final Data Sheet 21 V 1.1, 2012-01 TLE5012B Specification 3.4.3 GMR Parameters All parameters apply over BXY = 30mT and TA = 25C, unless otherwise specified. Table 8 Basic GMR parameters Parameter Symbol Values Min. X, Y output range RGADC X, Y amplitude 2) AX, AY Typ. 6000 9500 20620 digits 100 OX, OY -2048 0 +2047 digits X, Y orthogonality error -11.25 0 +11.24 X, Y without field X 0, Y 0 -5000 1) 2) 3) 4) Operating range1) 15781 digits 87.5 X, Y offset k 4) Note / Test Condition Max. 23230 digits 3922 X, Y synchronism 3) Unit Operating range 112.49 % +5000 digits Without magnet1) Not subject to production test - verified by design/characterization See Figure 12 k = 100*(AX/AY) OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2 VY +A 0 Offset 0 90 180 270 360 Angle -A Figure 12 Offset and amplitude definition Final Data Sheet 22 V 1.1, 2012-01 TLE5012B Specification 3.4.4 Angle Performance After internal calculation, the sensor has a remaining error, as shown in Table 9. The error value refers to BZ= 0mT and the operating conditions given in Table 3 "Operating range" on Page 18. The overall angle error represents the relative angle error. This error describes the deviation from the reference line after zero-angle definition. Table 9 Angle performance Parameter Symbol Values Min. Overall angle error (with autocalibration) Typ. Err 1) 2) 3) 4) 5) Note / Test Condition Max. 1) 1.0 Including lifetime and temperature drift2)3)4) 0.61) 1.6 Including temperature drift2)3)5) 0.6 Overall angle error (without auto- Err calibration) Unit At 25C, B = 30mT Including hysteresis error, caused by revolution direction change Only with calibrated GMR-compensation parameters of customer setup; relative error after zero angle definition Not subject to production test - verified by design/characterization 0h Autocalibration The autocalibration enables online parameter calculation and therefore reduces the angle error due to temperature drifts, lifetime drifts, and misalignments. The TLE5012B is a pre-calibrated sensor. After start-up, the parameters in the laser fuses get loaded into flip-flops. The TLE5012B needs 1.5 revolutions to generate new autocalibration parameters. The update mode can be chosen within the Interface Mode 2 register (AUTOCAL). The parameters are updated in a smooth way to avoid an angle jump on the output. Therefore only one Least-Significant Bit (LSB) will be changed within the chosen range or time. The autocalibration is done continuously. AUTOCAL Modes: * * * * 00: No autocalibration 01: Autocalibration Mode 1. One LSB to final values within the update time tupd (depending on FIR_MD setting). 10: Autocalibration Mode 2. Only one LSB update over one full parameter generation (1.5 revolutions). After update of one LSB, the autocalibration will calculate the parameters again. 11: Autocalibration Mode 3. One LSB to final values within an angle range of 11.25 3.4.5 Signal Processing The signal path of the TLE5012B is depicted in Figure 13. It consists of the GMR-bridge, ADC, filter and angle calculation. Depending on the filter configuration, a total delay times is calculated. In addition to this delay time, the delay time of the interface has to be considered. The delay time leads to an additional angle error at higher speeds. By enabling the prediction, the signal delay time can be reduced (Figure 14). The prediction uses the difference between current and last angle value, and calculates the output value by adding this difference to the current value. A linear prediction is achieved with following equation. (t + 1) = 2 (t ) - (t - 1) Final Data Sheet (3) 23 V 1.1, 2012-01 TLE5012B Specification TLE5012B Microcontroller tupd X GMR SDADC Filter Angle Calculation Y GMR SDADC IF Filter tdelIF tadel Figure 13 Signal path At FIR_MD = `00' only raw values can be read out, due to the more time-consuming angle calculation. Table 10 Signal processing Parameter Symbol Values Min. Update rate at interface Angle delay time3) Unit Note / Test Condition 21.3 s FIR_MD = 0 (only raw values)1)2) 42.7 s FIR_MD = 11)2) 85.3 s FIR_MD = 2 (default)1)2) 170.6 s FIR_MD = 31)2) 60 70 s FIR_MD = 11)2) 80 95 s FIR_MD = 21)2) 120 140 s FIR_MD = 31)2) 20 30 s Typ. tupd tadel Angle delay time with prediction3) tadel Max. FIR_MD = 1; PREDICT = 1 1)2) 5 20 s FIR_MD = 2; PREDICT = 1 1)2) -40 -20 s FIR_MD = 3; PREDICT = 1 1)2) Angle noise NAngle 0.11 FIR_MD = 0, (1 Sigma)2) 0.08 FIR_MD = 1, (1 Sigma)2) 0.05 FIR_MD = 2, (1 Sigma)2) (default) 0.04 FIR_MD = 3, (1 Sigma)2) 1) Without internal oscillator frequency variation (Section 3.4.6) 2) Not subject to production test - verified by design/characterization 3) Valid at constant rotation speed Final Data Sheet 24 V 1.1, 2012-01 TLE5012B Specification Sensor output Angle Magnetic field direction tadel Figure 14 t upd With Prediction Without Prediction time Delay of sensor output Final Data Sheet 25 V 1.1, 2012-01 TLE5012B Specification 3.4.6 Clock Supply (CLK Timing Definition) If the external clock supply is selected, the clock signal input IFC must fulfill certain requirements: * * * The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike-filtered. The duty cycle factor should be 0.5 but can vary within the values limited by tCLKh(f_min) and tCLKl(f_min). The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically and the sensor starts with the internal clock. This is indicated by S_RST, CLK_SEL bit, and additionally by the Safety Word. tCLK tCLKh tCLKl VH VL t Figure 15 External CLK timing definition Table 11 CLK timing specification Parameter Symbol Values Min. Input frequency CLK duty cycle 1)2) Typ. Unit Note / Test Condition Max. fCLK 3.8 4.0 4.2 MHz CLKDUTY 30 50 70 % CLK rise time tCLKr 30 ns From VL to VH CLK fall time tCLKf 30 ns From VH to VL Digital clock fDIG 22.8 24 25.2 MHz Internal oscillator frequency fCLK 3.8 4.0 4.2 MHz 1)Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min) 2)Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min) Final Data Sheet 26 V 1.1, 2012-01 TLE5012B Specification 3.5 Interfaces Within the register MOD_3, the driver strength and the slope for push-pull communication can be varied depending on the sensor output. The driver strength is specified in Table 3 and the slope fall and rise time in Table 12. Table 12 PAD characteristic Parameter Symbol Values Min. Output fall time Typ. Unit Note / Test Condition Max. tfall, trise Output rise time 8 ns DATA, 50 pF, PAD_DRV='00'1)2) 28 ns DATA, 50 pF, PAD_DRV='01'1)2) 45 ns DATA, 50 pF, PAD_DRV='10'1)2) 130 ns DATA, 50 pF, PAD_DRV='11'1)2) 15 ns IFA/IFB, 20 pF, PAD_DRV='0x'1)2) 30 ns IFA/IFB, 20 pF, PAD_DRV='1x'1)2) 1) Valid for push-pull output 2) Not subject to production test - verified by design/characterization 3.5.1 Synchronous Serial Communication (SSC) Interface The 3-pin SSC interface has a bi-directional push-pull data line, serial clock signal, and chip select. The SSC Interface is designed to communicate with a microcontroller peer-to-peer for fast applications. (SSC Slave) TLE 5012B C (SSC Master) DATA Shift Reg. **) MRST EN MTSR SCK *) SCK CSQ *) CSQ Shift Reg. EN Clock Gen. *) optional , e.g. 100 **) optional , e.g. 470 Figure 16 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application) Another possibility is a 3-pin SSC interface with bidirectional open-drain data line, serial clock signal, and chip select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLE5012B devices for redundancy reasons). This mode can be activated using bit SSC_OD. Final Data Sheet 27 V 1.1, 2012-01 TLE5012B Specification (SSC Slave) TLE 5012B C (SSC Master) typ. 1k DATA Shift Reg. *) MRST *) Shift Reg. MTSR SCK *) CSQ *) SCK Clock Gen. CSQ *) optional , e.g. 100 Figure 17 SSC configuration in sensor-slave mode and open drain (safe bus systems) 3.5.1.1 SSC Timing Definition tCSs tCSh tSCKp tCSoff CSQ tSCKh tSCKl SCK DATA tDATAs Figure 18 tDATAh SSC timing SSC Inactive Time (CSoff) The SSC inactive time defines the delay time after a transfer before the TLE5012B can be selected again. Table 13 SSC push-pull timing specification Parameter Symbol Values Min. Typ. Unit Note / Test Condition Mbit/s 1) Max. SSC baud rate fSSC CSQ setup time tCSs 105 ns 1) CSQ hold time tCSh 105 ns 1) CSQ off tCSoff 600 ns SSC inactive time1) SCK period tSCKp 120 ns 1) SCK high tSCKh 40 ns 1) Final Data Sheet 8.0 125 28 V 1.1, 2012-01 TLE5012B Specification Table 13 SSC push-pull timing specification (cont'd) Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. SCK low tSCKl 30 ns 1) DATA setup time tDATAs 25 ns 1) DATA hold time tDATAh 40 ns 1) Write read delay twr_delay 130 ns 1) Update time tCSupdate 1 s see Figure 221) SCK off tSCKoff 170 ns 1) Unit Note / Test Condition Mbit/s Pull-up Resistor = 1k1) 1) Not subject to production test - verified by design/characterization Table 14 SSC open-drain timing specification Parameter Symbol Values Min. Typ. Max. SSC baud rate fSSC CSQ setup time tCSs 300 ns 1) CSQ hold time tCSh 400 ns 1) CSQ off tCSoff 600 ns SSC inactive time1) SCK period tSCKp 500 ns 1) SCK high tSCKh 190 ns 1) SCK low tSCKl 190 ns 1) DATA setup time tDATAs 25 ns 1) DATA hold time tDATAh 40 ns 1) Write read delay twr_delay 130 ns 1) Update time tCSupdate 1 s see Figure 221) SCK off tSCKoff 170 ns 1) 2.0 1) Not subject to production test - verified by design/characterization Final Data Sheet 29 V 1.1, 2012-01 TLE5012B Specification 3.5.1.2 SSC Data Transfer The SSC data transfer is word-aligned. The following transfer words are possible: * * * Command Word (to access and change operating modes of the TLE5012B) Data words (any data transferred in any direction) Safety Word (confirms the data transfer and provides status information) twr_delay COMMAND READ Data 1 READ Data 2 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 19 SSC data transfer (data-read example) twr_delay COMMAND WRITE Data 1 SAFETY-WORD SSC-Master is driving DATA SSC-Slave is driving DAT A Figure 20 SSC data transfer (data-write example) Command Word The TLE5012B is controlled by a command word. It is sent first at every data transmission.The structure of the command word is shown in Table 15, where the Update (UPD) bit allows the access to current values or updated values. If an update command is issued and the UPD is set, the immediate values are stored in the update buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Bits with an update buffer are marked by an "u" in the Type column in register descriptions. The initialization of such an update is described on page 32. Table 15 Structure of the Command Word Name Bits Description RW [15] Read - Write 0: Write 1: Read Lock [14..11] 4-bit Lock Value 0000B: Default operating access for addresses 0x00:0x04 1010B: Configuration access for addresses 0x05:0x11 Final Data Sheet 30 V 1.1, 2012-01 TLE5012B Specification Table 15 Structure of the Command Word Name Bits Description UPD [10] Update-Register Access 0: Access to current values 1: Access to updated values ADDR [9..4] 6-bit Address ND [3..0] 4-bit Number of Data Words Safety Word The safety word consists of the following bits: Table 16 Structure of the Safety Word Name Bits Description STAT Chip and Interface Status [15] Indication of chip reset or watchdog overflow (resets after readout) via SSC 0: Reset occurred 1: No reset Reset: 1B [14] System error (e.g. overvoltage; undervoltage; VDD-, GND- off; ROM;...) 0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_FUSE; S_ROM; S_ADCT) 1: No error [13] Interface access error (access to wrong address; wrong lock) 0: Error occurred 1: No error [12] Valid angle value (NO_GMR_A = 0; NO_GMR_XY = 0 ) 0: Angle value invalid 1: Angle value valid RESP [11..8] Sensor number response indicator The sensor number bit is pulled low and the other bits are high CRC [7..0] Cyclic Redundancy Check (CRC) Bit Types The types of bits used in the registers are listed here: Table 17 Bit Types Abbreviation Function Description r Read Read-only registers w Write Read and write registers u Update Update buffer for this bit is present. If an update is issued and the UpdateRegister Access bit (UPD in Command Word) is set, the immediate values are stored in this update buffer simultaneously. This enables a snapshot of all necessary system parameters at the same time. Final Data Sheet 31 V 1.1, 2012-01 TLE5012B Specification Data communication via SSC SSC Transfer twr_delay Command Word Data Word (s) SCK DATA MSB 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LSB MSB 1 LSB CSQ RW LOCK UPD ADDR LENGTH SSC -Master is driving DAT A SSC -Slave is driving DAT A Figure 21 SSC bit ordering (read example) Update -Signal SCK Command Word Data Word (s) Update -Event MSB DATA LSB LSB CSQ tCSupdate SSC -Master is driving DAT A Figure 22 Update of update registers The data communication via SSC interface has the following characteristics: * * * * * * * * * * * * The data transmission order is Most-Significant Bit (MSB) first. Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. The SSC Interface is word-aligned. All functions are activated after each transmitted word. A "high" condition on the negated Chip Select pin (CSQ) of the selected TLE5012B interrupts the transfer immediately. The CRC calculator is automatically reset. After changing the data direction, a delay (twr_delay) has to be implemented before continuing the data transfer. This is necessary for internal register access. Every access to the TLE5012B with the number of data (ND) 1 is performed with address auto-increment. At an overflow at address 3FH , the transfer continues at address 00H. With ND = 0, no auto-increment is done and a continuous readout of the same address can take place. Afterwards no Safety Word is sent, and the transfer ends with high condition on CSQ. After every data transfer with ND 1, the 16-bit Safety Word will be appended by the selected TLE5012B. At a rising edge of CSQ without a preceding data transfer (no SCK pulse), the update registers are updated with according values (Figure 22). After sending the Safety Word, the transfer ends. To start another data transfer, the CSQ has to be deselected once for tCSoff. The SSC is default push-pull. The push-pull driver is active only if the TLE5012B has to send data, otherwise the push-pull is disabled and cannot receive data from the microcontroller. Cyclic Redundancy Check (CRC) * * * This CRC is according to the J1850 Bus Specification. Every new transfer restarts the CRC generation. Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). Final Data Sheet 32 V 1.1, 2012-01 TLE5012B Specification * * * Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used (see Figure 23) The remainder of the fast CRC circuit is initial set to '11111111B'. The remainder is inverted before transmission. Serial CRC output X7 X6 1 X5 1 X4 1 1 xor X3 X2 1 xor X0 X1 1 xor 1 1 & xor Input TX_CRC parallel Remainder Figure 23 Fast CRC polynomial division circuit 3.5.1.3 Registers Chapter The registers of the TLE5012B are described in the application note "TLE5012B Register Setting". 3.5.2 Pulse Width Modulation Interface The Pulse Width Modulation (PWM) interface can be selected via SPI (IF_MD = `001'). The PWM update rate can be programmed within the register 0EH (IFAB_RES) in the following steps: * * * * ~0.25 kHz with 12-bit resolution ~0.5 kHz with 12-bit resolution ~1.0 kHz with 12-bit resolution ~2.0 kHz with 12-bit resolution PWM uses a square wave with constant frequency whose duty cycle is modulated, resulting in an average value of the waveform. Figure 24 shows the principal behavior of a PWM with various duty cycles and the definition of timing values. The duty cycle of a PWM is defined by the following general formulas: Duty Cycle = ton t PWM t PWM = t on + toff f PWM = 1 t PWM (4) The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in Table 18. Sensors with preset PWM are available as TLE5012B E5xxx. The register settings for these sensors can be found in the latest Application Note TLE5012B Register Setting; section 4. Final Data Sheet 33 V 1.1, 2012-01 TLE5012B Specification ON = High level UIFA tON OFF = Low level Duty cycle = 5% Vdd tPWM t OFF 0' UIFA Vdd UIFA 0' Vdd Duty cycle = 50% t Duty cycle = 95% t 0' t Figure 24 Typical example of a PWM signal Table 18 PWM interface Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. PWM output frequency fPWM 244 1953 Hz Selectable by IFAB_RES1)2) Output duty cycle range DYPWM 6.25 93.75 % Absolute angle2) PWM period variation tPWMvar 2 % Electrical Error (S_RST; S_VR)2) 98 % System error (S_FUSE; S_OV; S_XYOL; S_MAGOL; S_ADCT)2) 0 1 % 99 100 % -5 5 % Short to GND2) Short to VDD, power loss2) 2)3) IFAB_RES 1) fPWM = (fDIG * 2 ) / (24 * 4096) 2) Not subject to production test - verified by design/characterization 3) Depends on internal oscillator frequency variation (Section 3.4.6) Final Data Sheet 34 V 1.1, 2012-01 TLE5012B Specification 3.5.3 Short PWM Code The Short PWM Code (SPC) is a synchronized data transmission based on the SENT protocol (Single Edge Nibble Transmission) defined by SAE J2716. SPC enables the use of enhanced protocol functionality due to the ability to select between various sensor slaves (ID selection). The slave number (S_NR) can be given by the external circuit of SCK and IFC pin. In case of VDD on SCK, the S_NR[0] can be set to 1 and in the case of GND on SCK the S_NR[0] is equal to 0. S_NR[1] can be adjusted in the same way by the IFC pin. As in SENT, the time between two consecutive falling edges defines the value of a 4-bit nibble, thus representing numbers between 0 and 15. The transmission time therefore depends on the transmitted data values. The single edge is defined by a 3 Unit Time (UT) low pulse on the output, followed by the high time defined in the protocol (nominal values, may vary depending on the tolerance of the internal oscillator and the influence of external circuitry). All values are multiples of a unit time frame concept. A transfer consists of the following parts (Figure 25): * * * * * * A trigger pulse by the master, which initiates the data transmission A synchronization period of 56 UT (in parallel, a new sample is calculated) A status nibble of 12-27 UT Between 3 and 6 data nibbles of 12-27 UT A CRC nibble of 12-27 UT An end pulse to terminate the SPC transmission Trigger Nibble 11,21,38,65 tck Synchronisation Frame Status -Nibble Data-Nibble 1 Bit 11-8 Data-Nibble 2 Bit 7-4 Data-Nibble 3 Bit 3-0 56 tck 12..27 tck 12..27 tck 12..27 tck 12..27 tck C Activity Sensor Activity Figure 25 CRC 12..27 tck End -Pulse 12 tck Time-Base: 1 tck (3s+/-dtck ) Nibble-Encoding : 12+x*3 tck SPC frame example The CRC checksum includes the status nibble and the data nibbles, and can be used to check the validity of the decoded data. The sensor is available for next sample 90s after the falling edge of the end pulse. In parallel to the SPC, the SPI can be used for individual configuration. The number of transmitted SPC nibbles can be changed to customize the amount of information sent by the sensor. The frame contains a 16-bit angle value and an 8-bit temperature value in the full configuration (Table 19). Sensors with preset SPC are available as TLE5012B E9xxx. The register settings for these sensors can be found in the latest Application Note TLE5012B Register Setting; section 4. Table 19 Frame configuration Frame type IFAB_RES Data nibbles 12-bit angle 00 3 nibbles 16-bit angle 01 4 nibbles 12-bit angle, 8-bit temperature 10 5 nibbles 16-bit angle, 8-bit temperature 11 6 nibbles The status nibble makes it possible to check internal states and conditions of the sensor. Final Data Sheet 35 V 1.1, 2012-01 TLE5012B Specification Table 20 Structure of status nibble Name Bits Description SYS_ERR [3] Indication of system error (S_FUSE, S_OV, S_XYOL, S_MAGOL, S_ADCT) 0: No system error 1: System error occurred ELEC_ERR [2] Indication of electrical error (S_RST, S_VR) 0: No electrical error 1: Electrical error occurred S_NR [1] Slave number bit 1 (level on IFC) [0] Slave number bit 0 (level on SCK) 3.5.3.1 Unit Time Setup The basic SPC protocol unit time granularity is defined as 3 s. Every timing is a multiple of this basic time unit.To achieve more flexibility, trimming of the unit time can be done within IFAB_HYST. This enables a setup of different unit times. Table 21 Predivider setting Parameter Symbol Values Min. Typ. tUnit Unit time Unit Note / Test Condition s IFAB_HYST = 001) Max. 3.0 2.5 IFAB_HYST = 011) 2.0 IFAB_HYST = 101) 1.5 IFAB_HYST = 111) 1) Not subject to production test - verified by design/characterization 3.5.3.2 Master Pulse Requirements An SPC transmission is initiated by a master pulse on the IFA pin. To detect a low level on the IFA pin, the voltage must be below a threshold Vthf. The sensor detects that the IFA line has been released as soon as Vthr is crossed. Figure 26 shows the timing definitions for the master pulse. The master low time tmlow as well as the total trigger time tmtr are given in Table 22. If the master low time exceeds the maximum low time, the sensor does not respond and is available for a next triggering 30 s after the master pulse crosses Vthr. tmd,tot is the delay between internal triggering of the falling edge in the sensor and the triggering of the ECU. tmtr OUT ECU trigger level Vth tmd,tot t mlow Figure 26 SPC Master pulse timing Final Data Sheet 36 V 1.1, 2012-01 TLE5012B Specification Table 22 Master pulse parameters Parameter Symbol Values Unit Note / Test Condition 50 % of VDD 1) 8 % of VDD = 5V1) 3 VDD VDD = 3V1) 90 UT SPC_Trigger = 0;1)2) tmlow +12 UT SP_Trigger = 11) 8 12 14 UT S_NR =001) 16 22 27 S_NR =011) 29 39 48 S_NR =101) 50 66 81 S_NR =111) Min. Threshold Vth Threshold hysteresis Vthhyst Total trigger time Master low time Master delay time Typ. tmtr tmlow tmd,tot 5.8 Max. s 1) 1) Not subject to production test - verified by design/characterization 2) Trigger time in the sensor is fixed to the number of units specified in the "typ." column, but the effective trigger time varies due to the sensor's clock variation 3.5.3.3 Checksum nibble details The checksum nibble is a 4-bit CRC of the data nibbles including the status nibble. The CRC is calculated using a polynomial x4+x3+x2+1 with a seed value of 0101. The remainder after the last data nibble is used are transferred as CRC. 3.5.4 Hall Switch Mode The Hall Switch Mode (HSM) within the TLE5012B makes it possible to emulate the output of 3 Hall switches. Hall switches are often used in electrical commutated motors to determine the rotor position. With these 3 output signals, the motor will be commutated in the right way. Depending on which pole pairs of the rotor are used, various electrical periods have to be controlled. This is selectable within 0EH (HSM_PLP). Figure 27 depicts the three output signals with the relationship between electrical angle and mechanical angle. The mechanical 0 point is always used as reference. The HSM is generally used with push-pull output, but it can be changed to open-drain within IFAB_OD. Sensors with preset HSM are available as TLE5012B E3xxx. The register settings for these sensors can be found in the latest Application Note TLE5012B Register Setting; section 4. Final Data Sheet 37 V 1.1, 2012-01 TLE5012B Specification Hall-Switch-Mode: 3phase Generation Electrical Angle 0 60 120 180 240 300 360 HS1 HS2 HS3 Angle Mech. Angle with 5 Pole Pairs 0 12 24 36 48 60 72 Mech. Angle with 3 Pole Pairs 0 20 40 60 80 100 120 Figure 27 Hall Switch Mode The HSM Interface can be selected via SPI (IF_MD = 010). Table 23 Hall Switch Mode Parameter Symbol Values Min. Rotation speed Final Data Sheet Typ. n Unit Max. 10000 rpm 38 Note / Test Condition Mechanical2) V 1.1, 2012-01 TLE5012B Specification Table 23 Hall Switch Mode Parameter Symbol Values Min. Electrical angle accuracy Mechanical angle switching hysteresis Final Data Sheet Typ. elect HShystm 0 39 Unit Note / Test Condition Max. 0.6 1 1 pole pair with autocalibration1)2) 1.2 2 2 pole pairs with autocal.1)2) 1.8 3 3 pole pairs with autocal.1)2) 2.4 4 4 pole pairs with autocal.1)2) 3.0 5 5 pole pairs with autocal.1)2) 3.6 6 6 pole pairs with autocal.1)2) 4.2 7 7 pole pairs with autocal.1)2) 4.8 8 8 pole pairs with autocal.1)2) 5.4 9 9 pole pairs with autocal.1)2) 6.0 10 10 pole pairs with autocal.1)2) 6.6 11 11 pole pairs with autocal.1)2) 7.2 12 12 pole pairs with autocal.1)2) 7.8 13 13 pole pairs with autocal.1)2) 8.4 14 14 pole pairs with autocal.1)2) 9.0 15 15 pole pairs with autocal.1)2) 9.6 16 16 pole pairs with autocal.1)2) 0.703 Selectable by IFAB_HYST2)3)4) V 1.1, 2012-01 TLE5012B Specification Table 23 Hall Switch Mode Parameter Symbol Values Min. Electrical angle switching hysteresis5) Typ. HShystel Unit Note / Test Condition 1 pole pair; IFAB_HYST=111)2) Max. 0.70 1.41 2 pole pairs; IFAB_HYST=111)2) 2.11 3 pole pairs; IFAB_HYST=111)2) 2.81 4 pole pairs; IFAB_HYST=111)2) 3.52 5 pole pairs; IFAB_HYST=111)2) 4.22 6 pole pairs; IFAB_HYST=111)2) 4.92 7 pole pairs; IFAB_HYST=111)2) 5.62 8 pole pairs; IFAB_HYST=111)2) 6.33 9 pole pairs; IFAB_HYST=111)2) 7.03 10 pole pairs; IFAB_HYST=111)2) 7.73 11 pole pairs; IFAB_HYST=111)2) 8.44 12 pole pairs; IFAB_HYST=111)2) 9.14 13 pole pairs; IFAB_HYST=111)2) 9.84 14 pole pairs; IFAB_HYST=111)2) 10.55 15 pole pairs; IFAB_HYST=111)2) 11.25 16 pole pairs; IFAB_HYST=111)2) Fall time tHSfall 0.02 1 s RL = 2.2k; CL < 50pF2) Rise time tHSrise 0.4 1 s RL = 2.2k; CL < 50pF2) 1) 2) 3) 4) 5) Depends on internal oscillator frequency variation (Section 3.4.6) Not subject to production test - verified by design/characterization GMR hysteresis not considered Minimum hysteresis without switching The hysteresis has to be considered only at change of rotation direction To avoid switching due to mechanical vibrations of the rotor, an artificial hysteresis is recommended (Figure 28). Final Data Sheet 40 V 1.1, 2012-01 TLE5012B Specification Ideal Switching Point HShystel HShystel elect Figure 28 HS hysteresis 3.5.5 Incremental Interface elect 0 The Incremental Interface (IIF) uses an up/down counter of a microcontroller for the angle transmission. The synchronization is done by the parallel active SSC interface. The angle value read out by the SSC interface can be compared to the stored counter value. In case of a non-synchronization, the microcontroller adds the difference to the actual counter value to synchronize the TLE5012B with the microcontroller. The resolution of the IIF can be selected within the interface mode4 register (MOD_4) under IFAB_RES. After startup, the IIF pulses out the actual absolute angle value. Thus, the microcontroller gets the information about the absolute position. The Index Signal that indicates the zero crossing is available on the IFC pin. In register MOD_1, the incremental interface can be chosen between A/B mode and Step/Direction mode (IIF_MOD). Within the TLE5012B, the incremental interface is implemented like a quadrature encoder with a 50% duty cycle. Sensors with preset IIF are available as TLE5012B E1xxx. The register settings for these sensors can be found in the latest Application Note TLE5012B Register Setting; section 4. A/B Mode The phase shift between phases A and B indicates either a clockwise (A follows B) or a counterclockwise (B follows A) rotation of the magnet. Incremental Interface (A/B Mode) 90 el . Phase shift Phase A V H VL Phase B V H VL Counter Figure 29 0 1 2 3 4 5 6 7 6 5 4 3 2 1 Incremental interface with A/B mode Step/Direction Mode Phase A pulses out the increments and phase B indicates the direction (Figure 30). Final Data Sheet 41 V 1.1, 2012-01 TLE5012B Specification Incremental Interface (Step /Direction Mode) VH VL Step Direction VH VL Counter 0 1 2 3 4 5 6 7 Figure 30 Incremental interface with Step/Direction mode Table 24 Incremental Interface Parameter Symbol Values Min. Incremental output frequency fInc Index t0 6 Typ. 5 Unit 4 3 2 1 Note / Test Condition Max. 1.0 MHz 5 s Frequency of phase A and phase B1) 01) 1) Not subject to production test - verified by design/characterization 3.6 Test Structure 3.6.1 ADC Test Vectors It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR effects. This test can be activated within the SIL register (ADCTV_EN). With ADCTV_Y and ADCTV_X, the vector length can be adjusted as shown in Figure 31. The values are generated with resistors on the chip. The following X/Y ADC values can be programmed: * * * * 4 points, circle amplitude = 70% (0,90, 180, 270) 8 points, circle amplitude = 100% (0, 45, 90, 135, 180, 225, 270, 315) 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) 4 points, circle amplitude = 141.4% (45, 135, 225, 315) Note: The 100% values typically correspond to 21700 digits and the 70% values to 15500 digits. Table 25 ADC test vectors Register bits X/Y values (decimal) Min. Typ. 000 0 001 15500 010 21700 011 32767 1) 100 0 101 -15500 110 -21700 111 -32768 Max. 1) Not allowed to use Final Data Sheet 42 V 1.1, 2012-01 TLE5012B Specification ADCTV_Y 122.1% 141.4% 100 .0% 0% 70% Figure 31 ADCTV_X ADC test vectors Examples of ADC test vector check The sensor has to be selected first via CSQ and SCK must be available for the communication. Table 26 shows the structure of the communication to enable the ADC test vector for 54.7. Table 26 SSC Command to enable ADC test vector check SSC Description Word No. Master transmitting 1 Command 0_1010_0_000111_0001 2 Write Data 0_0_000_0_000_1_010_001 3 Safety Word Table 27 TLE5012B transmitting Note Check of 54.7 1_1_1_0_xxxx_xxxxxxxx Structure of Write Data for various test vectors SSC Description Word No. Master transmitting 1 Write Data 0_0_000_0_000_1_001_101 ~135 2 Write Data 0_0_000_0_000_1_010_110 ~135 3 Write Data 0_0_000_0_000_1_101_110 ~215.3 4 Write Data 0_0_000_0_000_1_101_000 ~270 5 Write Data 0_0_000_0_000_1_101_010 ~324.7 Final Data Sheet TLE5012B transmitting 43 Note V 1.1, 2012-01 TLE5012B Specification 3.7 Overvoltage Comparators Various comparators monitor the voltage in order to ensure error-free operation. The overvoltages must be active at least 256 periods of tDIG to set the test comparator bits in the SSC interface registers. This works as digital spike suppression. Table 28 Test comparators Parameter Symbol Values Min. Typ. Unit Note / Test Condition Max. VOVG 2.80 V 1) VOVA 2.80 V 1) VOVD 2.80 V 1) VDD overvoltage VDDOV 6.05 V 1) VDD undervoltage VDDUV 2.70 V 1) GND - off voltage VGNDoff -0.55 V 1) VDD - off voltage VVDDoff 0.55 V 1) Spike filter delay tDEL s 1) Overvoltage detection 10 1) Not subject to production test - verified by design/characterization 3.7.1 Internal Supply Voltage Comparators Every voltage regulator has an overvoltage (OV) comparator to detect malfunctions. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated. VDDA - REF VDD VRG VRA VRD 10s Spike Filter + GND Figure 32 OV comparator 3.7.2 VDD Overvoltage Detection xxx_OV GND The overvoltage detection comparator monitors the external supply voltage at the VDD pin. It activates the S_VR bit.(Figure 32) 3.7.3 GND - Off Comparator The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. It activates the S_VR bit of the SSC - Interface. This circuit can detect a disconnection of the supply GND Pin. Final Data Sheet 44 V 1.1, 2012-01 TLE5012B Specification VDD VDDA Diodereference SCK +dV - 1s Mono Flop + GND 10s Spike Filter GND_OFF GND Figure 33 GND - off comparator 3.7.4 VDD - Off Comparator The VDD - Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012B is supplied by the SCK and CSQ input pins via the ESD structures. It activates the S_VR bit. VDDA - VDD 1s Mono Flop VVDDoff CSQ SCK -dV GND Figure 34 + 10s Spike Filter VDD _OFF GND VDD - off comparator Final Data Sheet 45 V 1.1, 2012-01 TLE5012B Package Information 4 Package Information 4.1 Package Parameters Table 29 Package Parameters Parameter Symbol Limit Values Min. Thermal resistance Unit Notes Typ. Max. 200 K/W Junction to air1) RthJC 75 K/W Junction to case RthJL 85 K/W Junction to lead RthJA Soldering moisture level Lead Frame 150 MSL 3 260C Cu Plating Sn 100% > 7 m 1) according to Jedec JESD51-7 4.2 Package Outline Figure 35 PG-DSO-8 package dimension Final Data Sheet 46 V 1.1, 2012-01 TLE5012B Package Information Position of sensing element 4.3 Footprint 1.31 Figure 36 5.69 0.65 1.27 Figure 37 Footprint of PG-DSO-8 4.4 Packing 0.3 5.2 12 0.3 8 1.75 6.4 2.1 Figure 38 Tape and Reel Final Data Sheet 47 V 1.1, 2012-01 TLE5012B Package Information 4.5 Marking Position Marking Description 1st Line 012Bxxxx See ordering table on Page 8 2nd Line xxx Lot code 3rd Line Gxxxx G..green, 4-digit..date code Processing Note: For processing recommendations, please refer to Infineon's Notes on processing Final Data Sheet 48 V 1.1, 2012-01 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG