Sensors
Data Sheet
V 1.1, 2012-01
Final
TLE5012B
Angle Sensor
GMR-Based Angle Sensor
Edition 2012-01
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2012 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
TLE5012B
Final Data Sheet 3 V 1.1, 2012-01
Trademarks of Infineon Technologies AG
AURIX™, BlueMoon™, COMNEON™, C166™, CROSSAVE™, CanPAK™, CIPOS™, CoolMOS™, CoolSET™,
CORECONTROL™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™,
EiceDRIVER™, EUPEC™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, I²RF™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PROFET™, PRO-SIL™,
PRIMARION™, PrimePACK™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SMARTi™,
SmartLEWIS™, TEMPFET™, thinQ!™, TriCore™, TRENCHSTOP™, X-GOLD™, XMM™, X-PMU™,
XPOSYS™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, PRIMECELL™,
REALVIEW™, THUMB™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership.
Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation
Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation.
FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of
Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of
INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP.
MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Sattelite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2010-06-09
Revision History
Page or Item Subjects (major changes since previous revision)
V 1.1, 2012-01
12 Table 1, SPC interface at pin 5 added
31 Table 16, bit[14] and bit[12] updated
33 Sensor with preset PWM added
35 Sensor with preset SPC added
37 Sensor with preset HSM added
41 Sensor with preset IIF added
general Correction of typing errors
TLE5012B
Table of Contents
Final Data Sheet 4 V 1.1, 2012-01
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.3 SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.4 Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.6 Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4.3 GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4.4 Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.5 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4.6 Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1 Synchronous Serial Communication (SSC) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.1.1 SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.1.2 SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5.1.3 Registers Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.2 Pulse Width Modulation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.3 Short PWM Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.5.3.1 Unit Time Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5.3.2 Master Pulse Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5.3.3 Checksum nibble details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.4 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.5 Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.6 Test Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.6.1 ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.7 Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7.1 Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7.2 VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table of Contents
TLE5012B
Table of Contents
Final Data Sheet 5 V 1.1, 2012-01
3.7.3 GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.7.4 VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.4 Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TLE5012B
List of Figures
Final Data Sheet 6 V 1.1, 2012-01
Figure 1 Sensitive bridges of the GMR sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2 Ideal output of the GMR sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 TLE5012B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 PRO-SILTM Logo. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6 Application circuit for TLE5012B with SSC and PWM interface (using internal CLK) . . . . . . . . . . 15
Figure 7 Application circuit for TLE5012B with HS Mode (using internal CLK) . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8 Application circuit for TLE5012B with SSC and IIF interface (using external CLK) . . . . . . . . . . . . 16
Figure 9 Application circuit for TLE5012B with only PWM interface (using internal CLK) . . . . . . . . . . . . . . 17
Figure 10 Application circuit for TLE5012B with only SPC interface (S_NR = 00) . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 Magnet performance (ambient temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12 Offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 Delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15 External CLK timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 16 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application) . . . . . . 27
Figure 17 SSC configuration in sensor-slave mode and open drain (safe bus systems) . . . . . . . . . . . . . . . . 28
Figure 18 SSC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19 SSC data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20 SSC data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21 SSC bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22 Update of update registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23 Fast CRC polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24 Typical example of a PWM signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 25 SPC frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26 SPC Master pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 28 HS hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 29 Incremental interface with A/B mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 30 Incremental interface with Step/Direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 31 ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32 OV comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 33 GND - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 34 VDD - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 35 PG-DSO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 36 Position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 37 Footprint of PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 38 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
List of Figures
TLE5012B
List of Tables
Final Data Sheet 7 V 1.1, 2012-01
Table 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 5 Electrical parameters for 4.5V < VDD < 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 6 Electrical parameters for 3.0V < VDD < 3.6V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8 Basic GMR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9 Angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11 CLK timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12 PAD characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13 SSC push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 14 SSC open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15 Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 16 Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17 Bit Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18 PWM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19 Frame configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20 Structure of status nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 21 Predivider setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22 Master pulse parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 24 Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 25 ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 26 SSC Command to enable ADC test vector check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 27 Structure of Write Data for various test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 28 Test comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
List of Tables
Product Type Marking Ordering Code Package
TLE5012B E1000 012B1000 SP000905682 PG-DSO-8
TLE5012B E3005 012B3005 SP000905686 PG-DSO-8
TLE5012B E5000 012B5000 SP000905690 PG-DSO-8
TLE5012B E9000 012B9000 SP000905694 PG-DSO-8
TLE5012B
Final Data Sheet 8 V 1.1, 2012-01
1 Product Description
1.1 Overview
The TLE5012B is a 360° angle sensor that detects the orientation of a
magnetic field. This is achieved by measuring sine and cosine angle
components with monolithic integrated Giant Magneto Resistance (iGMR)
elements.
Highly precise angle values are adetermined over a wide temperature
range and a long lifetime using an internal autocalibration algorithm.
Data communications are accomplished with a bi-directional
Synchronous Serial Communication (SSC) that is SPI-compatible.
The absolute angle value and other values are transmitted via SSC or via a Pulse-Width-Modulation (PWM)
Protocol. The sine and cosine raw values can also be read out. These raw signals are digitally processed internally
to calculate the angle orientation of the magnetic field (magnet).
The TLE5012B is a pre-calibrated sensor. The calibration parameters are stored in laser fuses. At start-up the
values of the fuses are written into flip-flops, where these values can be changed by the application-specific
parameters.
Online diagnostic functions are provided to ensure reliable operation.
TLE5012B
Product Description
Final Data Sheet 9 V 1.1, 2012-01
1.2 Features
•Giant Magneto Resistance (GMR)-based principle
• Integrated magnetic field sensing for angle measurement
• Full calibrated 0 - 360° angle measurement with revolution counter and angle speed measurement
• Two separate highly accurate single bit SD-ADC
• 15 bit representation of absolute angle value on the output (resolution of 0.01°)
• 16 bit representation of sine / cosine values on the interface
• Max. 1.0° angle error over lifetime and temperature-range with activated auto-calibration
• Bi-directional SSC Interface up to 8Mbit/s
• Supports Safety Integrity Level (SIL) with diagnostic functions and status information
• Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM), Short PWM Code (SPC)
• 0.25 µm CMOS technology
• Automotive qualified: -40°C to 150°C (junction temperature)
• ESD > 4kV (HBM)
• RoHS compliant (Pb-free package)
1.3 Application Example
The TLE5012B GMR-based angle sensor is designed for angular position sensing in automotive applications such
as:
• Electrical commutated motor (e.g. used in Electric Power Steering (EPS))
• Rotary switches
• Steering angle measurements
• General angular sensing
TLE5012B
Functional Description
Final Data Sheet 10 V 1.1, 2012-01
2 Functional Description
2.1 General
The Giant Magneto Resistance (GMR) sensor is implemented using vertical integration. This means that the
GMR-sensitive areas are integrated above the logic portion of the TLE5012B device. These GMR elements
change their resistance depending on the direction of the magnetic field.
Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense one
of two components of the applied magnetic field:
• X component, Vx (cosine) or the
• Y component, Vy (sine)
The advantage of a full-bridge structure is that the maximum GMR signal is available and temperature effects
cancel out each other.
Figure 1 Sensitive bridges of the GMR sensor
Note: In Figure 1, the arrows in the resistors represent the magnetic direction which is fixed in the reference layer.
If the external magnetic field is parallel to the direction of the Reference Layer, the resistance is minimal. If
they are anti-parallel, resistance is maximal.
The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are
orientated orthogonally to each other to measure 360°.
With the trigonometric function ARCTAN, the true 360° angle value can be calculated, based on the relationship
of X and Y signals.
Because only the relative values influence the result, the absolute magnitude of the two signals is of minor
importance. Therefore, it is possible to compensate for most external influences on the amplitudes.
V
DD
GNDADC
X
+
GMR Resistors
ADC
X
-ADC
Y
+ADC
Y
-
V
X
V
Y
0°
N
S
90°
TLE5012B
Functional Description
Final Data Sheet 11 V 1.1, 2012-01
Figure 2 Ideal output of the GMR sensor bridges
V
Angle α
90° 180° 270° 360°0°
V
X
(COS)
Y Component (SIN)
V
Y
(SIN)
V
Y
V
X
X Component (COS)
TLE5012B
Functional Description
Final Data Sheet 12 V 1.1, 2012-01
2.2 Pin Configuration
Figure 3 Pin configuration (top view)
2.3 Pin Description
Table 1 Pin Description
Pin No. Symbol In/Out Function
1IFC
(CLK / IIF_IDX / HS3)
I/O Interface C:
External Clock / IIF Index / Hall Switch
Signal 3
2 SCK I SSC Clock
3 CSQ I SSC Chip Select
4 DATA I/O SSC Data
5IFA
(IIF_A / HS1 / PWM / SPC)
O Interface A:
IIF Phase A / Hall Switch Signal 1 /
PWM / SPC output
6V
DD - Supply Voltage
7GND-Ground
8IFB
(IIF_B / HS2)
O Interface B:
IIF Phase B / Hall Switch Signal 2
12 34
5678 Center of Sensitive
Area
TLE5012B
Functional Description
Final Data Sheet 13 V 1.1, 2012-01
2.4 Block Diagram
Figure 4 TLE5012B block diagram
2.5 Functional Block Description
2.5.1 Internal Power Supply
The internal stages of the TLE5012B are supplied with several voltage regulators:
• GMR Voltage Regulator, VRG
• Analog Voltage Regulator, VRA
• Digital Voltage Regulator, VRD (derived from VRA)
These regulators are directly connected to the supply voltage VDD.
2.5.2 Oscillator and PLL
The internal frequency oscillator feeds the Phase-Locked Loop (PLL). Therefore, the external clock (CLK) can also
be used.
2.5.3 SD-ADC
The SD-ADCs transform the analog GMR voltages and temperature voltage into the digital domain.
VRG VRA VRD
TLE5012B
VDD
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
CSQ
SCK
DATA
IFA
IFB
GND
IFC
Osc PLL
TLE5012B
Functional Description
Final Data Sheet 14 V 1.1, 2012-01
2.5.4 Digital Signal Processing Unit
The Digital Signal Processing Unit (DSPU) contains the:
•Capture Compare Unit (CCU), which is used to generate the PWM signal
•COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle
calculation
• Fuses, which contain the calibration parameters
2.5.5 Interfaces
Various Interfaces can be selected:
• SSC Interface
•PWM
• Incremental Interface
• Hall Switch Mode
• Short PWM Code
2.5.6 Safety Features
The TLE5012B offers a multiplicity of safety features to support the Safety Integrity Level (SIL). Infineon’s sensors
that are intended for this purpose are identified by the following logo:
Figure 5 PRO-SILTM Logo
Safety features are:
• Test vectors switchable to ADC input
• Inversion or combination of filter input streams
• Data transmission check via 8-bit Cyclic Redundancy Check (CRC)
• Self-test routines
• Two independent active interfaces possible
• Overvoltage and undervoltage detection
Disclaimer
PRO-SIL™ is a Registered Trademark of Infineon Technologies AG.
The PRO-SIL™ Trademark designates Infineon products which contain SIL Supporting Features.
SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according
to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency.
SIL respectively A-SIL certification for such a System has to be reached on system level by the System
Responsible at an accredited Certification Authority.
SIL stands for Safety Integrity Level (according to IEC 61508)
A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262)
TLE5012B
Specification
Final Data Sheet 15 V 1.1, 2012-01
3 Specification
3.1 Application Circuit
The application circuits in Figure 6, Figure 7, Figure 8 and Figure 9 show the various communication
possibilities of the TLE5012B.
Figure 6 Application circuit for TLE5012B with SSC and PWM interface (using internal CLK)
Figure 6 shows a basic block diagram of the TLE5012B with PWM interface.In addition to the PWM interface, the
SSC interface could be used. Within the SSC interface, the PWM mode is selectable between push-pull and open-
drain.
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
Osc
*) r ecom mended , e .g. 470 Ω
100 n
IFA ( PWM)
IFB
DATA
CSQ
SCK
IFC
V
DD
(3.0 – 5.5V)
*)
1 kΩ
SSC
PWM
IFB, IFC can be rem ain open
(inter nal Pul l D ow n ).
GND
PLL
TLE5012B
Specification
Final Data Sheet 16 V 1.1, 2012-01
Figure 7 Application circuit for TLE5012B with HS Mode (using internal CLK)
Figure 7 shows a basic block diagram of the TLE5012B with HS Mode. In addition to the HS Mode, the SSC
interface could be used in parallel. Within the SSC- Interface, the HS Mode is selectable between push-pull and
open-drain.
Figure 8 Application circuit for TLE5012B with SSC and IIF interface (using external CLK)
Figure 8 shows a basic block diagram of an angle-sensor system using a TLE5012B and a microcontroller for
rotor positioning applications. The depicted interface configuration is needed for high-speed applications suchas
electrical commutated motor drives. It is possible to connect the TLE5012B to a microcontroller via Incremental
Interface and for safety reasons also via the SSC interface.
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
Osc
*) recomm ended , e .g. 2.2 kΩ
100 n
IFC (HS3)
V
DD
(3.0 – 5.5V)
*)
GND
PLL
CSQ
SCK
DATA 10 kΩ
IFA (HS1)
IFB (HS2)
*) *)
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
100 n
IFA (IIF_ A)
IFB (IIF_ B)
GND
DATA
CSQ
SCK
IFC (IIF_IDX)
PLL
VDD (3.0 – 5.5V)
µC
*)
*) r ecom m ended , e.g . 470 Ω
SSC
Osc PLL
CCU
TLE5012B
Specification
Final Data Sheet 17 V 1.1, 2012-01
The TLE5012B can be configured with PWM only (Figure 9). This is only possible with the TLE5012B-E5000
type.1)
Figure 9 Application circuit for TLE5012B with only PWM interface (using internal CLK)
The TLE5012B can be configured with SPC only (Figure 9). This is only possible with the TLE5012B-E9000
type.1)
Figure 10 Application circuit for TLE5012B with only SPC interface (S_NR = 00)
1) For more information get in contact with Infineon
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
Osc PLL
100 n
IFA (PWM)
DATA
CSQ
SCK
V
DD
(3.0 – 5.5V)
10 kΩ
1 kΩ
DATA and IFB could be r em ai n
open or connected via 10 kΩ
resistor to GND .
GND
IFB
IFC
IFB, IFC can be rem ain open
(internal Pull D own ).
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CCU
Cordic
Fuses
SSC Interface
Incremental IF
PWM
HSM
Osc PLL
100 n
IFA (SPC)
DATA
CSQ
SCK
V
DD
(3.0 – 5.5V)
10 kΩ
1 kΩ
DATA and IFB could be rem ain
open or connected via 10 kΩ
resistor to GND .
GND
IFB
IFC
TLE5012B
Specification
Final Data Sheet 18 V 1.1, 2012-01
3.2 Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the device.
3.3 Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012B.
All parameters specified in the following sections refer to these operating conditions, unless otherwise noted.
Table 3 is valid for -40°C < TJ < 150°C unless otherwise noted.
Table 2 Absolute maximum ratings
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Voltage on VDD pin with respect to
ground (VSS)
VDD -0.5 6.5 V Max 40 h/Lifetime
Voltage on any pin with respect to
ground (VSS)
VIN -0.5 6.5 V Additionally VDD + 0.5 V may
not be exceeded
Junction temperature TJ-40 150 °C
150 °C For 1000 h, not additive
Magnetic field induction B 200 mT Max. 5 min @ TA = 25°C
150 mT Max. 5 h @ TA = 25°C
Storage temperature TST -40 150 °C Without magnetic field
Table 3 Operating range
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply voltage VDD 3.0 5.0 5.5 V 1)
Output current (DATA-Pad) IQ-25 mA PAD_DRV =’0x’, sink
current2)3)
-5 mA PAD_DRV =’10’, sink
current2)3)
-0.4 mA PAD_DRV =’11’, sink
current2)3)
Output current (IFA / IFB / IFC -
Pad)
IQ-15 mA PAD_DRV =’0x’, sink
current2)3)
-5 mA PAD_DRV =’1x’, sink
current2)3)
Input voltage VIN -0.3 5.5 V VDD + 0.3 V may not be
exceeded
TLE5012B
Specification
Final Data Sheet 19 V 1.1, 2012-01
The field strength of a magnet can be selected within the colored area of Figure 11. By limitation of the junction
temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ=100°C, a magnet with
up to 60mT at TA = 25°C is allowed.
It is also possible to widen the magnetic field range for higher temperatures. In that case, additional angle errors
have to be considered (see Application Note “GMR Angle Error Extension”).
Figure 11 Magnet performance (ambient temperature)
Note: The thermal resistances listed in Table 29 “Package Parameters” on Page 46 must be used to calculate
the corresponding ambient temperature of the sensor.
Magnetic induction at TA = 25°C
4)5)
BXY 30 50 mT -40°C < TJ < 150°C
BXY 30 60 mT -40°C < TJ < 100°C
BXY 30 70 mT -40°C < TJ < 85°C
Expanded magnetic induction at
TA = 25°C 4)5)6)
BXY 25 30 mT Additional angle error of 0.1°
Angle range Ang 0 360 °
1) Directly blocked with 100-nF ceramic capacitor
2) Max. current to GND over open-drain output
3) At VDD = 5V
4) Values refer to a homogeneous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT).
5) See Figure 11
6) 0h
Table 3 Operating range (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Final Data Sheet 20 V 1.1, 2012-01
Calculation of the Junction Temperature
The total power dissipation PTOT of the chip increases its temperature above the ambient temperature.
The power multiplied by the total thermal resistance RthJA (junction to ambient) leads to the final junction
temperature. RthJA is the sum of the addition of the values of the two components Junction to Case and Case to
Ambient.
(1)
Example (assuming no load on Vout):
(2)
For molded sensors, the calculation with RthJC is more appropriate.
3.4 Characteristics
3.4.1 Electrical Parameters
The indicated electrical parameters apply to the full operating range, unless otherwise specified. The typical values
correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond
to -40 °C < TJ < 150°C.
Table 4 Electrical parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply current IDD 14 16 mA
POR level VPOR 2.0 2.9 V Power-on reset
POR hysteresis VPORhy 30 mV
Pull-up current IPU -10 -225 µA CSQ
-10 -150 µA DATA
Pull-down current IPD 10 225 µA SCK
10 150 µA IFA, IFB, IFC
Power-on time 1)
1) Within “Power-on time,” write access is not permitted
tPon 57msV
DD > VDDmin; SBIST = 1
0.5 ms VDD > VDDmin; SBIST = 02)
2) Not subject to production test - verified by design/characterization
))((
OUTOUTDDDDDDthJATOTthJA
AJ
thCAthJCthJA
IVVIVRPRT
TTT
RRR
×−+××=×=Δ
Δ+=
+=
[] [] [ ]
()
KVAAV
W
K
T
mAI
VV
DD
DD
5.100014.05150
14
5
=+××
⎥
⎦
⎤
⎢
⎣
⎡
=Δ
=
=
TLE5012B
Specification
Final Data Sheet 21 V 1.1, 2012-01
3.4.2 ESD Protection
Table 5 Electrical parameters for 4.5V < VDD < 5.5V
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input signal low level VL5 0.3 VDD V
Input signal high level VH5 0.7 VDD V
Output signal low level VOL5 1V DATA; I
Q = -25 mA
(PAD_DRV=’0x’), IQ = -5 mA
(PAD_DRV=’10’), IQ = -0.4 mA
(PAD_DRV=’11’)
1 V IFA,IFB, IFC; IQ = -15 mA
(PAD_DRV=’0x’), IQ = -5 mA
(PAD_DRV=’1x’)
Table 6 Electrical parameters for 3.0V < VDD < 3.6V
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input signal low level VL3 0.3 VDD V
Input signal high level VH3 0.7 VDD V
Output signal low level VOL3 0.9 V DATA; IQ = -15 mA
(PAD_DRV=’0x’), IQ = -3 mA
(PAD_DRV=’10’), IQ = -0.24 mA
(PAD_DRV=’11’)
0.9 V IFA,IFB; IQ = - 10 mA
(PAD_DRV=’0x’), IQ = -3 mA
(PAD_DRV=’1x’)
Table 7 ESD protection
Parameter Symbol Values Unit Notes
min. max.
ESD voltage VHBM ±4.0 kV Human Body Model1)
1) Human Body Model (HBM) according to: AEC-Q100-002
VSDM ±0.5 kV Socketed Device Model2)
2) Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008
TLE5012B
Specification
Final Data Sheet 22 V 1.1, 2012-01
3.4.3 GMR Parameters
All parameters apply over BXY = 30mT and TA = 25°C, unless otherwise specified.
Figure 12 Offset and amplitude definition
Table 8 Basic GMR parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
X, Y output range RGADC ±23230 digits Operating range1)
1) Not subject to production test - verified by design/characterization
X, Y amplitude 2)
2) See Figure 12
AX, AY6000 9500 15781 digits
3922 20620 digits Operating range
X, Y synchronism 3)
3) k = 100*(AX/AY)
k 87.5 100 112.49 %
X, Y offset 4)
4) OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2
OX, OY-2048 0 +2047 digits
X, Y orthogonality error ϕ-11.25 0 +11.24 °
X, Y without field X0, Y0-5000 +5000 digits Without magnet1)
Angle
90° 180° 270° 360°0°
+A
Offset
VY
0
-A
TLE5012B
Specification
Final Data Sheet 23 V 1.1, 2012-01
3.4.4 Angle Performance
After internal calculation, the sensor has a remaining error, as shown in Table 9. The error value refers to BZ= 0mT
and the operating conditions given in Table 3 “Operating range” on Page 18.
The overall angle error represents the relative angle error. This error describes the deviation from the reference
line after zero-angle definition.
Autocalibration
The autocalibration enables online parameter calculation and therefore reduces the angle error due to
temperature drifts, lifetime drifts, and misalignments.
The TLE5012B is a pre-calibrated sensor. After start-up, the parameters in the laser fuses get loaded into flip-flops.
The TLE5012B needs 1.5 revolutions to generate new autocalibration parameters. The update mode can be
chosen within the Interface Mode 2 register (AUTOCAL). The parameters are updated in a smooth way to avoid
an angle jump on the output. Therefore only one Least-Significant Bit (LSB) will be changed within the chosen
range or time. The autocalibration is done continuously.
AUTOCAL Modes:
• 00: No autocalibration
• 01: Autocalibration Mode 1. One LSB to final values within the update time tupd (depending on FIR_MD setting).
• 10: Autocalibration Mode 2. Only one LSB update over one full parameter generation (1.5 revolutions). After
update of one LSB, the autocalibration will calculate the parameters again.
• 11: Autocalibration Mode 3. One LSB to final values within an angle range of 11.25°
3.4.5 Signal Processing
The signal path of the TLE5012B is depicted in Figure 13. It consists of the GMR-bridge, ADC, filter and angle
calculation. Depending on the filter configuration, a total delay times is calculated. In addition to this delay time,
the delay time of the interface has to be considered. The delay time leads to an additional angle error at higher
speeds. By enabling the prediction, the signal delay time can be reduced (Figure 14). The prediction uses the
difference between current and last angle value, and calculates the output value by adding this difference to the
current value. A linear prediction is achieved with following equation.
(3)
Table 9 Angle performance
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Overall angle error (with auto-
calibration)
αErr 0.61)
1) At 25°C, B = 30mT
1.0 ° Including lifetime and
temperature drift2)3)4)
2) Including hysteresis error, caused by revolution direction change
3) Only with calibrated GMR-compensation parameters of customer setup; relative error after zero angle definition
4) Not subject to production test - verified by design/characterization
Overall angle error (without auto-
calibration)
αErr 0.61) 1.6 ° Including temperature
drift2)3)5)
5) 0h
)1()(2)1(
−−⋅=+
ttt
α
α
α
TLE5012B
Specification
Final Data Sheet 24 V 1.1, 2012-01
Figure 13 Signal path
At FIR_MD = ‘00’ only raw values can be read out, due to the more time-consuming angle calculation.
Table 10 Signal processing
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Update rate at interface tupd 21.3 µs FIR_MD = 0 (only raw
values)1)2)
1) Without internal oscillator frequency variation (Section 3.4.6)
2) Not subject to production test - verified by design/characterization
42.7 µs FIR_MD = 11)2)
85.3 µs FIR_MD = 2 (default)1)2)
170.6 µs FIR_MD = 31)2)
Angle delay time3)
3) Valid at constant rotation speed
tadel 60 70 µs FIR_MD = 11)2)
80 95 µs FIR_MD = 21)2)
120 140 µs FIR_MD = 31)2)
Angle delay time with prediction3) tadel 20 30 µs FIR_MD = 1; PREDICT = 1
1)2)
5 20 µs FIR_MD = 2; PREDICT = 1
1)2)
-40 -20 µs FIR_MD = 3; PREDICT = 1
1)2)
Angle noise NAngle 0.11 ° FIR_MD = 0, (1 Sigma)2)
0.08 ° FIR_MD = 1, (1 Sigma)2)
0.05 ° FIR_MD = 2, (1 Sigma)2)
(default)
0.04 ° FIR_MD = 3, (1 Sigma)2)
X
GMR
Y
GMR
SD-
ADC
SD-
ADC
Angle
Calculation
Filter
Filter
TLE5012B Microcontroller
IF
adel
t
delIF
t
upd
t
TLE5012B
Specification
Final Data Sheet 25 V 1.1, 2012-01
Figure 14 Delay of sensor output
time
Angle
With
Prediction
Without
Prediction
t
adel
t
upd
Magnetic field
direction
Sensor output
TLE5012B
Specification
Final Data Sheet 26 V 1.1, 2012-01
3.4.6 Clock Supply (CLK Timing Definition)
If the external clock supply is selected, the clock signal input IFC must fulfill certain requirements:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike-filtered.
• The duty cycle factor should be 0.5 but can vary within the values limited by tCLKh(f_min) and tCLKl(f_min).
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically and the sensor starts with the internal clock. This is indicated by S_RST, CLK_SEL
bit, and additionally by the Safety Word.
Figure 15 External CLK timing definition
Table 11 CLK timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input frequency fCLK 3.8 4.0 4.2 MHz
CLK duty cycle1)2)
1)Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min)= 1 / fCLK(f_min)
2)Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max)= tCLK(f_min) - tCLKl(min)
CLKDUTY 30 50 70 %
CLK rise time tCLKr 30 ns From VL to VH
CLK fall time tCLKf 30 ns From VH to VL
Digital clock fDIG 22.8 24 25.2 MHz
Internal oscillator frequency fCLK 3.8 4.0 4.2 MHz
t
CLKh
t
CLKl
t
CLK
t
V
L
V
H
TLE5012B
Specification
Final Data Sheet 27 V 1.1, 2012-01
3.5 Interfaces
Within the register MOD_3, the driver strength and the slope for push-pull communication can be varied
depending on the sensor output. The driver strength is specified in Table 3 and the slope fall and rise time in
Table 12.
3.5.1 Synchronous Serial Communication (SSC) Interface
The 3-pin SSC interface has a bi-directional push-pull data line, serial clock signal, and chip select. The SSC
Interface is designed to communicate with a microcontroller peer-to-peer for fast applications.
Figure 16 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application)
Another possibility is a 3-pin SSC interface with bidirectional open-drain data line, serial clock signal, and chip
select. This setup is designed to communicate with a microcontroller in a bus system, together with other SSC
slaves (e.g. two TLE5012B devices for redundancy reasons). This mode can be activated using bit SSC_OD.
Table 12 PAD characteristic
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Output fall time tfall, trise 8 ns DATA, 50 pF,
PAD_DRV=’00’1)2)
1) Valid for push-pull output
2) Not subject to production test - verified by design/characterization
Output rise time 28 ns DATA, 50 pF,
PAD_DRV=’01’1)2)
45 ns DATA, 50 pF,
PAD_DRV=’10’1)2)
130 ns DATA, 50 pF,
PAD_DRV=’11’1)2)
15 ns IFA/IFB, 20 pF,
PAD_DRV=’0x’1)2)
30 ns IFA/IFB, 20 pF,
PAD_DRV=’1x’1)2)
Shift Reg. Shift Reg.
Clock Gen.
DATA MRST
MTSR
SCK SCK
(SSC Slave) TLE 5012B µC (SSC Master)
CSQ CSQ
**)
*)
*)
EN EN
*) optional , e.g . 100 Ω
**) opti onal , e.g . 470 Ω
TLE5012B
Specification
Final Data Sheet 28 V 1.1, 2012-01
Figure 17 SSC configuration in sensor-slave mode and open drain (safe bus systems)
3.5.1.1 SSC Timing Definition
Figure 18 SSC timing
SSC Inactive Time (CSoff)
The SSC inactive time defines the delay time after a transfer before the TLE5012B can be selected again.
Table 13 SSC push-pull timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SSC baud rate fSSC 8.0 Mbit/s 1)
CSQ setup time tCSs 105 ns 1)
CSQ hold time tCSh 105 ns 1)
CSQ off tCSoff 600 ns SSC inactive time1)
SCK period tSCKp 120 125 ns 1)
SCK high tSCKh 40 ns 1)
Shift Reg. Shift Reg.
Clock Gen.
DATA MRST
MTSR
SCK SCK
(SSC Slave) TLE 5012B µC (SSC Master)
CSQ CSQ
*)
*)
*)
*)
typ . 1kΩ
*) optional , e.g . 100 Ω
SCK
t
CSs
t
SCKp
t
SCKh
t
CSh
CSQ
t
SCKl
t
CSoff
t
DATAs
DATA
t
DATAh
TLE5012B
Specification
Final Data Sheet 29 V 1.1, 2012-01
SCK low tSCKl 30 ns 1)
DATA setup time tDATAs 25 ns 1)
DATA hold time tDATAh 40 ns 1)
Write read delay twr_delay 130 ns 1)
Update time tCSupdate 1µssee Figure 221)
SCK off tSCKoff 170 ns 1)
1) Not subject to production test - verified by design/characterization
Table 14 SSC open-drain timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SSC baud rate fSSC 2.0 Mbit/s Pull-up Resistor = 1kΩ1)
1) Not subject to production test - verified by design/characterization
CSQ setup time tCSs 300 ns 1)
CSQ hold time tCSh 400 ns 1)
CSQ off tCSoff 600 ns SSC inactive time1)
SCK period tSCKp 500 ns 1)
SCK high tSCKh 190 ns 1)
SCK low tSCKl 190 ns 1)
DATA setup time tDATAs 25 ns 1)
DATA hold time tDATAh 40 ns 1)
Write read delay twr_delay 130 ns 1)
Update time tCSupdate 1µssee Figure 221)
SCK off tSCKoff 170 ns 1)
Table 13 SSC push-pull timing specification (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Final Data Sheet 30 V 1.1, 2012-01
3.5.1.2 SSC Data Transfer
The SSC data transfer is word-aligned. The following transfer words are possible:
• Command Word (to access and change operating modes of the TLE5012B)
• Data words (any data transferred in any direction)
• Safety Word (confirms the data transfer and provides status information)
Figure 19 SSC data transfer (data-read example)
Figure 20 SSC data transfer (data-write example)
Command Word
The TLE5012B is controlled by a command word. It is sent first at every data transmission.The structure of the
command word is shown in Table 15, where the Update (UPD) bit allows the access to current values or updated
values. If an update command is issued and the UPD is set, the immediate values are stored in the update buffer
simultaneously. This enables a snapshot of all necessary system parameters at the same time. Bits with an update
buffer are marked by an “u” in the Type column in register descriptions. The initialization of such an update is
described on page 32.
Table 15 Structure of the Command Word
Name Bits Description
RW [15] Read - Write
0: Write
1: Read
Lock [14..11] 4-bit Lock Value
0000B: Default operating access for addresses 0x00:0x04
1010B: Configuration access for addresses 0x05:0x11
COMMAND READ Data 1 READ Data 2
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DATA
t
wr_delay
COMMAND WRITE Data 1
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DATA
t
wr_delay
TLE5012B
Specification
Final Data Sheet 31 V 1.1, 2012-01
Safety Word
The safety word consists of the following bits:
Bit Types
The types of bits used in the registers are listed here:
UPD [10] Update-Register Access
0: Access to current values
1: Access to updated values
ADDR [9..4] 6-bit Address
ND [3..0] 4-bit Number of Data Words
Table 16 Structure of the Safety Word
Name Bits Description
STAT Chip and Interface Status
[15] Indication of chip reset or watchdog overflow (resets after readout) via SSC
0: Reset occurred
1: No reset
Reset: 1B
[14] System error (e.g. overvoltage; undervoltage; VDD-, GND- off; ROM;...)
0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_FUSE;
S_ROM; S_ADCT)
1: No error
[13] Interface access error (access to wrong address; wrong lock)
0: Error occurred
1: No error
[12] Valid angle value (NO_GMR_A = 0; NO_GMR_XY = 0 )
0: Angle value invalid
1: Angle value valid
RESP [11..8] Sensor number response indicator
The sensor number bit is pulled low and the other bits are high
CRC [7..0] Cyclic Redundancy Check (CRC)
Table 17 Bit Types
Abbreviation Function Description
r Read Read-only registers
w Write Read and write registers
u Update Update buffer for this bit is present. If an update is issued and the Update-
Register Access bit (UPD in Command Word) is set, the immediate values
are stored in this update buffer simultaneously. This enables a snapshot of
all necessary system parameters at the same time.
Table 15 Structure of the Command Word
Name Bits Description
TLE5012B
Specification
Final Data Sheet 32 V 1.1, 2012-01
Data communication via SSC
Figure 21 SSC bit ordering (read example)
Figure 22 Update of update registers
The data communication via SSC interface has the following characteristics:
• The data transmission order is Most-Significant Bit (MSB) first.
• Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
• The SSC Interface is word-aligned. All functions are activated after each transmitted word.
• A “high” condition on the negated Chip Select pin (CSQ) of the selected TLE5012B interrupts the transfer
immediately. The CRC calculator is automatically reset.
• After changing the data direction, a delay (twr_delay) has to be implemented before continuing the data transfer.
This is necessary for internal register access.
• Every access to the TLE5012B with the number of data (ND) ≥ 1 is performed with address auto-increment.
• At an overflow at address 3FH , the transfer continues at address 00H.
• With ND = 0, no auto-increment is done and a continuous readout of the same address can take place.
Afterwards no Safety Word is sent, and the transfer ends with high condition on CSQ.
• After every data transfer with ND ≥ 1, the 16-bit Safety Word will be appended by the selected TLE5012B.
• At a rising edge of CSQ without a preceding data transfer (no SCK pulse), the update registers are updated
with according values (Figure 22).
• After sending the Safety Word, the transfer ends. To start another data transfer, the CSQ has to be deselected
once for tCSoff.
• The SSC is default push-pull. The push-pull driver is active only if the TLE5012B has to send data, otherwise
the push-pull is disabled and cannot receive data from the microcontroller.
Cyclic Redundancy Check (CRC)
• This CRC is according to the J1850 Bus Specification.
• Every new transfer restarts the CRC generation.
• Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
SCK
DATA 811 10 9MSB 14 13 12
CSQ
SSC Transfer
LSB3217 6 5 4
Command Wor d Data Word (s)
SSC -M aster i s dri vi ng DAT A
SSC -Slave is driving DAT A
LSB1
RW ADDR LENGTHLOC K
MSB
t
wr_delay
UPD
SCK
DATA
CSQ
LSB LSBMSB
Command Word Data Word (s)Update -Signal
Update -Event
SSC -Master is dr iving DAT A
tCSupdate
TLE5012B
Specification
Final Data Sheet 33 V 1.1, 2012-01
• Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
(see Figure 23)
• The remainder of the fast CRC circuit is initial set to ’11111111B’.
• The remainder is inverted before transmission.
Figure 23 Fast CRC polynomial division circuit
3.5.1.3 Registers Chapter
The registers of the TLE5012B are described in the application note "TLE5012B Register Setting”.
3.5.2 Pulse Width Modulation Interface
The Pulse Width Modulation (PWM) interface can be selected via SPI (IF_MD = ‘001’).
The PWM update rate can be programmed within the register 0EH (IFAB_RES) in the following steps:
• ~0.25 kHz with 12-bit resolution
• ~0.5 kHz with 12-bit resolution
• ~1.0 kHz with 12-bit resolution
• ~2.0 kHz with 12-bit resolution
PWM uses a square wave with constant frequency whose duty cycle is modulated, resulting in an average value
of the waveform.
Figure 24 shows the principal behavior of a PWM with various duty cycles and the definition of timing values. The
duty cycle of a PWM is defined by the following general formulas:
(4)
The range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. More details are given in
Table 18.
Sensors with preset PWM are available as TLE5012B E5xxx. The register settings for these sensors can be found
in the latest Application Note TLE5012B Register Setting; section 4.
xor
X7 X6 X5 X4 X3 X2
xor
X0
xor xor Input
Serial
CRC
output
&
TX_CRC
1111 1 1 11
X1
parallel
Remainder
PWM
PWM
offonPWM
PWM
on
t
f
ttt
t
t
CycleDuty
1
=
+=
=
TLE5012B
Specification
Final Data Sheet 34 V 1.1, 2012-01
Figure 24 Typical example of a PWM signal
Table 18 PWM interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
PWM output frequency fPWM 244 1953 Hz Selectable by
IFAB_RES1)2)
1) fPWM = (fDIG * 2IFAB_RES) / (24 * 4096)
2) Not subject to production test - verified by design/characterization
Output duty cycle range DYPWM 6.25 93.75 % Absolute angle2)
2 % Electrical Error (S_RST;
S_VR)2)
98 % System error (S_FUSE;
S_OV; S_XYOL;
S_MAGOL; S_ADCT)2)
0 1 % Short to GND2)
99 100 % Short to VDD, power loss2)
PWM period variation tPWMvar -5 5 % 2)3)
3) Depends on internal oscillator frequency variation (Section 3.4.6)
tON
‚0' t
ON = High level OFF = Low level
Duty cycle = 5%
Duty cycle = 50%
Duty cycle = 95%
tPWM tOFF
Vdd
UIFA
Vdd
UIFA
t
‚0' t
Vdd
UIFA
‚0'
TLE5012B
Specification
Final Data Sheet 35 V 1.1, 2012-01
3.5.3 Short PWM Code
The Short PWM Code (SPC) is a synchronized data transmission based on the SENT protocol (Single Edge
Nibble Transmission) defined by SAE J2716. SPC enables the use of enhanced protocol functionality due to the
ability to select between various sensor slaves (ID selection). The slave number (S_NR) can be given by the
external circuit of SCK and IFC pin. In case of VDD on SCK, the S_NR[0] can be set to 1 and in the case of GND
on SCK the S_NR[0] is equal to 0. S_NR[1] can be adjusted in the same way by the IFC pin.
As in SENT, the time between two consecutive falling edges defines the value of a 4-bit nibble, thus representing
numbers between 0 and 15. The transmission time therefore depends on the transmitted data values. The single
edge is defined by a 3 Unit Time (UT) low pulse on the output, followed by the high time defined in the protocol
(nominal values, may vary depending on the tolerance of the internal oscillator and the influence of external
circuitry). All values are multiples of a unit time frame concept. A transfer consists of the following parts
(Figure 25):
• A trigger pulse by the master, which initiates the data transmission
• A synchronization period of 56 UT (in parallel, a new sample is calculated)
• A status nibble of 12-27 UT
• Between 3 and 6 data nibbles of 12-27 UT
• A CRC nibble of 12-27 UT
• An end pulse to terminate the SPC transmission
Figure 25 SPC frame example
The CRC checksum includes the status nibble and the data nibbles, and can be used to check the validity of the
decoded data. The sensor is available for next sample 90µs after the falling edge of the end pulse.
In parallel to the SPC, the SPI can be used for individual configuration. The number of transmitted SPC nibbles
can be changed to customize the amount of information sent by the sensor. The frame contains a 16-bit angle
value and an 8-bit temperature value in the full configuration (Table 19).
Sensors with preset SPC are available as TLE5012B E9xxx. The register settings for these sensors can be found
in the latest Application Note TLE5012B Register Setting; section 4.
The status nibble makes it possible to check internal states and conditions of the sensor.
Table 19 Frame configuration
Frame type IFAB_RES Data nibbles
12-bit angle 00 3 nibbles
16-bit angle 01 4 nibbles
12-bit angle, 8-bit temperature 10 5 nibbles
16-bit angle, 8-bit temperature 11 6 nibbles
Synchronisation Fr ame Status -Nibble Data - Nibble 1
Bit 11 -8
Data-Nibble 2
Bit 7 -4
Data -Ni bble 3
Bit 3-0 CRC
56 tck 12..27 tck 12 .. 27 tck 12 .. 27 tck 12 ..27 tck 12..27 tck
Nibble- Encoding : 12 + x*3 tck
Time-Base: 1 tck (3µs+/-dtck)
Tr i gger Ni bble End -Pulse
11 ,21 ,38 ,65 tck 12 tck
µC Activity
Sensor Activity
TLE5012B
Specification
Final Data Sheet 36 V 1.1, 2012-01
3.5.3.1 Unit Time Setup
The basic SPC protocol unit time granularity is defined as 3 µs. Every timing is a multiple of this basic time unit.To
achieve more flexibility, trimming of the unit time can be done within IFAB_HYST. This enables a setup of different
unit times.
3.5.3.2 Master Pulse Requirements
An SPC transmission is initiated by a master pulse on the IFA pin. To detect a low level on the IFA pin, the voltage
must be below a threshold Vthf. The sensor detects that the IFA line has been released as soon as Vthr is crossed.
Figure 26 shows the timing definitions for the master pulse. The master low time tmlow as well as the total trigger
time tmtr are given in Table 22.
If the master low time exceeds the maximum low time, the sensor does not respond and is available for a next
triggering 30 µs after the master pulse crosses Vthr. tmd,tot is the delay between internal triggering of the falling edge
in the sensor and the triggering of the ECU.
Figure 26 SPC Master pulse timing
Table 20 Structure of status nibble
Name Bits Description
SYS_ERR [3] Indication of system error (S_FUSE, S_OV, S_XYOL, S_MAGOL, S_ADCT)
0: No system error
1: System error occurred
ELEC_ERR [2] Indication of electrical error (S_RST, S_VR)
0: No electrical error
1: Electrical error occurred
S_NR [1] Slave number bit 1 (level on IFC)
[0] Slave number bit 0 (level on SCK)
Table 21 Predivider setting
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Unit time tUnit 3.0 µs IFAB_HYST = 001)
1) Not subject to production test - verified by design/characterization
2.5 IFAB_HYST = 011)
2.0 IFAB_HYST = 101)
1.5 IFAB_HYST = 111)
OUT
ECU trigger
level
V
th
t
mlow
t
md,tot
t
mtr
TLE5012B
Specification
Final Data Sheet 37 V 1.1, 2012-01
3.5.3.3 Checksum nibble details
The checksum nibble is a 4-bit CRC of the data nibbles including the status nibble. The CRC is calculated using
a polynomial x4+x3+x2+1 with a seed value of 0101. The remainder after the last data nibble is used are transferred
as CRC.
3.5.4 Hall Switch Mode
The Hall Switch Mode (HSM) within the TLE5012B makes it possible to emulate the output of 3 Hall switches. Hall
switches are often used in electrical commutated motors to determine the rotor position. With these 3 output
signals, the motor will be commutated in the right way. Depending on which pole pairs of the rotor are used,
various electrical periods have to be controlled. This is selectable within 0EH (HSM_PLP). Figure 27 depicts the
three output signals with the relationship between electrical angle and mechanical angle. The mechanical 0° point
is always used as reference.
The HSM is generally used with push-pull output, but it can be changed to open-drain within IFAB_OD.
Sensors with preset HSM are available as TLE5012B E3xxx. The register settings for these sensors can be found
in the latest Application Note TLE5012B Register Setting; section 4.
Table 22 Master pulse parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Threshold Vth 50 % of
VDD
1)
1) Not subject to production test - verified by design/characterization
Threshold hysteresis Vthhyst 8% of V
DD = 5V1)
3V
DD VDD = 3V1)
Total trigger time tmtr 90 UT SPC_Trigger = 0;1)2)
2) Trigger time in the sensor is fixed to the number of units specified in the “typ.” column, but the effective trigger time varies
due to the sensor’s clock variation
tmlow
+12
UT SP_Trigger = 11)
Master low time tmlow 8 12 14 UT S_NR =001)
16 22 27 S_NR =011)
29 39 48 S_NR =101)
50 66 81 S_NR =111)
Master delay time tmd,tot 5.8 µs 1)
TLE5012B
Specification
Final Data Sheet 38 V 1.1, 2012-01
Figure 27 Hall Switch Mode
The HSM Interface can be selected via SPI (IF_MD = 010).
Table 23 Hall Switch Mode
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Rotation speed n 10000 rpm Mechanical2)
HS1
HS2
HS3
0°Electrical Angle 60° 120° 180° 240° 300° 360°
Hall-Switch-Mode: 3phase Generation
Angle
Mech. Angle with
5 Pole Pairs 0° 12° 24° 36° 48° 60° 72°
0° 20° 40° 60° 80° 100° 120°
Mech. Angle with
3 Pole Pairs
TLE5012B
Specification
Final Data Sheet 39 V 1.1, 2012-01
Electrical angle accuracy αelect 0.6 1 ° 1 pole pair with
autocalibration1)2)
1.2 2 2 pole pairs with autocal.1)2)
1.8 3 3 pole pairs with autocal.1)2)
2.4 4 4 pole pairs with autocal.1)2)
3.0 5 5 pole pairs with autocal.1)2)
3.6 6 6 pole pairs with autocal.1)2)
4.2 7 7 pole pairs with autocal.1)2)
4.8 8 8 pole pairs with autocal.1)2)
5.4 9 9 pole pairs with autocal.1)2)
6.0 10 10 pole pairs with
autocal.1)2)
6.6 11 11 pole pairs with
autocal.1)2)
7.2 12 12 pole pairs with
autocal.1)2)
7.8 13 13 pole pairs with
autocal.1)2)
8.4 14 14 pole pairs with
autocal.1)2)
9.0 15 15 pole pairs with
autocal.1)2)
9.6 16 16 pole pairs with
autocal.1)2)
Mechanical angle switching
hysteresis
αHShystm 0 0.703 ° Selectable by
IFAB_HYST2)3)4)
Table 23 Hall Switch Mode
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Final Data Sheet 40 V 1.1, 2012-01
To avoid switching due to mechanical vibrations of the rotor, an artificial hysteresis is recommended (Figure 28).
Electrical angle switching
hysteresis5)
αHShystel 0.70 ° 1 pole pair;
IFAB_HYST=111)2)
1.41 2 pole pairs;
IFAB_HYST=111)2)
2.11 3 pole pairs;
IFAB_HYST=111)2)
2.81 4 pole pairs;
IFAB_HYST=111)2)
3.52 5 pole pairs;
IFAB_HYST=111)2)
4.22 6 pole pairs;
IFAB_HYST=111)2)
4.92 7 pole pairs;
IFAB_HYST=111)2)
5.62 8 pole pairs;
IFAB_HYST=111)2)
6.33 9 pole pairs;
IFAB_HYST=111)2)
7.03 10 pole pairs;
IFAB_HYST=111)2)
7.73 11 pole pairs;
IFAB_HYST=111)2)
8.44 12 pole pairs;
IFAB_HYST=111)2)
9.14 13 pole pairs;
IFAB_HYST=111)2)
9.84 14 pole pairs;
IFAB_HYST=111)2)
10.55 15 pole pairs;
IFAB_HYST=111)2)
11.25 16 pole pairs;
IFAB_HYST=111)2)
Fall time tHSfall 0.02 1 µs RL = 2.2kΩ; CL < 50pF2)
Rise time tHSrise 0.4 1 µs RL = 2.2kΩ; CL < 50pF2)
1) Depends on internal oscillator frequency variation (Section 3.4.6)
2) Not subject to production test - verified by design/characterization
3) GMR hysteresis not considered
4) Minimum hysteresis without switching
5) The hysteresis has to be considered only at change of rotation direction
Table 23 Hall Switch Mode
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Final Data Sheet 41 V 1.1, 2012-01
Figure 28 HS hysteresis
3.5.5 Incremental Interface
The Incremental Interface (IIF) uses an up/down counter of a microcontroller for the angle transmission. The
synchronization is done by the parallel active SSC interface. The angle value read out by the SSC interface can
be compared to the stored counter value. In case of a non-synchronization, the microcontroller adds the difference
to the actual counter value to synchronize the TLE5012B with the microcontroller. The resolution of the IIF can be
selected within the interface mode4 register (MOD_4) under IFAB_RES.
After startup, the IIF pulses out the actual absolute angle value. Thus, the microcontroller gets the information
about the absolute position. The Index Signal that indicates the zero crossing is available on the IFC pin.
In register MOD_1, the incremental interface can be chosen between A/B mode and Step/Direction mode
(IIF_MOD).
Within the TLE5012B, the incremental interface is implemented like a quadrature encoder with a 50% duty cycle.
Sensors with preset IIF are available as TLE5012B E1xxx. The register settings for these sensors can be found
in the latest Application Note TLE5012B Register Setting; section 4.
A/B Mode
The phase shift between phases A and B indicates either a clockwise (A follows B) or a counterclockwise (B
follows A) rotation of the magnet.
Figure 29 Incremental interface with A/B mode
Step/Direction Mode
Phase A pulses out the increments and phase B indicates the direction (Figure 30).
Ideal Switching Point
α
elect
α
HShystel
α
HShystel
α
elect
0°
90° el . Phase shift
0 1 2 3 4 5 6 7 6 5 4 3 2 1
Phase A
Counter
Phase B
Incremental Int erf ace
(A/B Mode)
V
H
V
L
V
H
V
L
TLE5012B
Specification
Final Data Sheet 42 V 1.1, 2012-01
Figure 30 Incremental interface with Step/Direction mode
3.6 Test Structure
3.6.1 ADC Test Vectors
It is possible to feed the ADCs with appropriate values to simulate a certain magnet position and other GMR
effects. This test can be activated within the SIL register (ADCTV_EN). With ADCTV_Y and ADCTV_X, the vector
length can be adjusted as shown in Figure 31.
The values are generated with resistors on the chip.
The following X/Y ADC values can be programmed:
• 4 points, circle amplitude = 70% (0°,90°, 180°, 270°)
• 8 points, circle amplitude = 100% (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)
• 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°)
• 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°)
Note: The 100% values typically correspond to 21700 digits and the 70% values to 15500 digits.
Table 24 Incremental Interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Incremental output frequency fInc 1.0 MHz Frequency of phase A and
phase B1)
1) Not subject to production test - verified by design/characterization
Index t0° 5µs0°
1)
Table 25 ADC test vectors
Register bits X/Y values (decimal)
Min. Typ. Max.
000 0
001 15500
010 21700
011 32767
1001)
1) Not allowed to use
0
101 -15500
110 -21700
111 -32768
Step
Counter
Direction
Incremental Interface
(Step /Direction Mode)
V
H
V
L
V
H
V
L
0 1 2 3 4 5 6 7 6 5 4 3 2 1
TLE5012B
Specification
Final Data Sheet 43 V 1.1, 2012-01
Figure 31 ADC test vectors
Examples of ADC test vector check
The sensor has to be selected first via CSQ and SCK must be available for the communication. Table 26 shows
the structure of the communication to enable the ADC test vector for 54.7°.
Table 26 SSC Command to enable ADC test vector check
SSC
Word
No.
Description Master transmitting TLE5012B transmitting Note
1 Command 0_1010_0_000111_0001
2 Write Data 0_0_000_0_000_1_010_001 Check of 54.7°
3 Safety Word 1_1_1_0_xxxx_xxxxxxxx
Table 27 Structure of Write Data for various test vectors
SSC
Word
No.
Description Master transmitting TLE5012B transmitting Note
1 Write Data 0_0_000_0_000_1_001_101 ~135°
2 Write Data 0_0_000_0_000_1_010_110 ~135°
3 Write Data 0_0_000_0_000_1_101_110 ~215.3°
4 Write Data 0_0_000_0_000_1_101_000 ~270°
5 Write Data 0_0_000_0_000_1_101_010 ~324.7°
ADCTV_X
ADCTV_Y
0%
122.1%
100.0%
70%
141.4%
TLE5012B
Specification
Final Data Sheet 44 V 1.1, 2012-01
3.7 Overvoltage Comparators
Various comparators monitor the voltage in order to ensure error-free operation. The overvoltages must be active
at least 256 periods of tDIG to set the test comparator bits in the SSC interface registers. This works as digital spike
suppression.
3.7.1 Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage (OV) comparator to detect malfunctions. If the nominal output voltage
of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated.
Figure 32 OV comparator
3.7.2 VDD Overvoltage Detection
The overvoltage detection comparator monitors the external supply voltage at the VDD pin. It activates the S_VR
bit.(Figure 32)
3.7.3 GND - Off Comparator
The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. It activates the
S_VR bit of the SSC - Interface. This circuit can detect a disconnection of the supply GND Pin.
Table 28 Test comparators
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Overvoltage detection VOVG 2.80 V 1)
1) Not subject to production test - verified by design/characterization
VOVA 2.80 V 1)
VOVD 2.80 V 1)
VDD overvoltage VDDOV 6.05 V 1)
VDD undervoltage VDDUV 2.70 V 1)
GND - off voltage VGNDoff -0.55 V 1)
VDD - off voltage VVDDoff 0.55 V 1)
Spike filter delay tDEL 10 µs 1)
REF
-
+
10µs
Spike
Filter
xxx_OV
V
DDA
GNDGND
V
DD
V
RG
V
RA
V
RD
TLE5012B
Specification
Final Data Sheet 45 V 1.1, 2012-01
Figure 33 GND - off comparator
3.7.4 VDD - Off Comparator
The VDD - Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012B is
supplied by the SCK and CSQ input pins via the ESD structures. It activates the S_VR bit.
Figure 34 VDD - off comparator
-
+
10µs
Spike
Filter
GND_OFF
V
DDA
GND
SCK
GND
V
DD
+dV
Diode-
reference
1µs
Mono
Flop
10µs
Spike
Filter
VDD _OFF
V
DDA
GND
V
DD
CSQ
SCK -dV
GND
1µs
Mono
Flop
-
+
V
VDDoff
TLE5012B
Package Information
Final Data Sheet 46 V 1.1, 2012-01
4 Package Information
4.1 Package Parameters
4.2 Package Outline
Figure 35 PG-DSO-8 package dimension
Table 29 Package Parameters
Parameter Symbol Limit Values Unit Notes
Min. Typ. Max.
Thermal resistance RthJA 150 200 K/W Junction to air1)
1) according to Jedec JESD51-7
RthJC 75 K/W Junction to case
RthJL 85 K/W Junction to lead
Soldering moisture level MSL 3 260°C
Lead Frame Cu
Plating Sn 100% > 7 µm
TLE5012B
Package Information
Final Data Sheet 47 V 1.1, 2012-01
Figure 36 Position of sensing element
4.3 Footprint
Figure 37 Footprint of PG-DSO-8
4.4 Packing
Figure 38 Tape and Reel
0.65
1.31
5.69
1.27
8
6.4
5.2
0.3
±0.3
12
2.1
1.75
TLE5012B
Package Information
Final Data Sheet 48 V 1.1, 2012-01
4.5 Marking
Processing
Note: For processing recommendations, please refer to Infineon’s Notes on processing
Position Marking Description
1st Line 012Bxxxx See ordering table on Page 8
2nd Line xxx Lot code
3rd Line Gxxxx G..green, 4-digit..date code
