R8C/20 Group, R8C/21 Group RENESAS MCU 1. REJ03B0120-0200 Rev.2.00 Aug 27, 2008 Overview This MCU is built using the high-performance silicon gate CMOS process using the R8C CPU core and is packaged in a 48-pin plastic molded LQFP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. This Furthermore, the data flash (1 KB x 2 blocks) is embedded in the R8C/21 Group. The difference between R8C/20 and R8C/21 Groups is only the existence of the data flash. Their peripheral functions are the same. 1.1 Applications Automotive, etc. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 1 of 41 R8C/20 Group, R8C/21 Group 1.2 1. Overview Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/20 Group and Table 1.2 outlines the Functions and Specifications for R8C/21 Group. Table 1.1 Functions and Specifications for R8C/20 Group Item Specification Number of fundamental instructions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information for R8C/20 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Function Timers Timer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channel (Circuits of input capture and output compare) Timer RE: With compare match function Serial interface 1 channel (UART0) Clock synchronous I/O, UART 1 channel (UART1) UART Clock synchronous serial interface 1 channel I2C bus interface(2), Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupt Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock generation circuits 2 circuits XIN clock generation circuit (with on-chip feedback resistor) On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has frequency adjustment function. Oscillation stop detection Stop detection of XIN clock oscillation function Voltage detection circuit On-chip Power-on reset circuit include On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version) Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed onchip oscillator stopping) Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 100 times endurance Operating Ambient Temperature -40 to 85C -40 to 125C (option(1)) Package 48-pin mold-plastic LQFP CPU NOTES: 1. When using options, be sure to inquire about the specification. 2. I2C bus is a registered trademark of Koninklijke Philips Electronics N.V. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 2 of 41 R8C/20 Group, R8C/21 Group Table 1.2 1. Overview Functions and Specifications for R8C/21 Group Item Specification Number of fundamental instructions 89 instructions Minimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information for R8C/21 Group Peripheral Ports I/O ports: 41 pins, Input port: 3 pins Function Timers Timer RA: 8 bits x 1 channel, Timer RB: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer RD: 16 bits x 2 channel (Circuits of input capture and output compare) Timer RE: With compare match function Serial interface 1 channel (UART0) Clock synchronous I/O, UART 1 channel (UART1) UART Clock synchronous serial interface 1 channel I2C bus interface(2), Clock synchronous serial I/O with chip select LIN module Hardware LIN: 1 channel (Timer RA, UART0) A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable Interrupts Internal: 11 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels Clock generation circuits 2 circuits XIN clock generation circuit (with on-chip feedback resistor) On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has frequency adjustment function. Oscillation stop detection Stop detection of XIN clock oscillation function Voltage detection circuit On-chip Power-on reset circuit include On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)(J version) Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz)(K version) VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 11.0 mA (VCC = 5 V, f(XIN) = 20 MHz, High-speed onchip oscillator stopping) Typ. 5.3 mA (VCC = 5 V, f(XIN) = 10 MHz, High-speed on-chip oscillator stopping) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 10,000 times (data flash) endurance 1,000 times (program ROM) Operating Ambient Temperature -40 to 85C -40 to 125C (option(1)) Package 48-pin mold-plastic LQFP CPU NOTES: 1. When using options, be sure to inquire about the specification. 2. I2C bus is a registered trademark of Koninklijke Philips Electronics N.V. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 3 of 41 R8C/20 Group, R8C/21 Group 1.3 1. Overview Block Diagram Figure 1.1 shows a Block Diagram. I/O port 8 8 8 6 Port P0 Port P1 Port P2 Port P3 Timer Timer RA (8 bits) Timer RB (8 bits) Timer RD (16 bits x 2 channels) Timer RE (8 bits) 3 3 8 Port P4 Port P6 System clock generation circuit A/D converter (10 bits x 12 channels) XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator UART or clock synchronous serial I/O (8 bits x 1 channel) UART (8 bits x 1 channel) I2C bus interface or clock synchronous serial I/O with chip select (8 bits x 1 channel) LIN module (1 channel) Watchdog timer (15 bits) Memory R8C CPU core R0H R1H R0L R1L R2 R3 SB ISP INTB A0 A1 FB ROM(1) USP RAM(2) PC FLG Multiplier NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.1 Block Diagram Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 4 of 41 R8C/20 Group, R8C/21 Group 1.4 1. Overview Product Information Table 1.3 lists Product Information for R8C/20 Group and Table 1.4 lists Product Information for R8C/21 Group. Table 1.3 Product Information for R8C/20 Group Type No. R5F21206JFP R5F21207JFP R5F21208JFP R5F2120AJFP R5F2120CJFP ROM Capacity 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 128 Kbytes(1) 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes R5F21206KFP R5F21207KFP R5F21208KFP R5F2120AKFP R5F2120CKFP 128 Kbytes(1) Current of Aug. 2008 RAM Capacity 2 Kbytes 2.5 Kbytes 3 Kbytes 5 Kbytes 6 Kbytes Package Type PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A Remarks J version Flash memory version 2 Kbytes 2.5 Kbytes 3 Kbytes 5 Kbytes 6 Kbytes PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A K version NOTE: 1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger of Hardware Manual. Part number R 5 F 21 20 6 J XXX FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) ROM number Classification J: Operating ambient temperature -40C to 85C (J version) K: Operating ambient temperature -40C to 125C (K version) ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/20 Group R8C/2x Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 5 of 41 R8C/20 Group, R8C/21 Group Table 1.4 1. Overview Product Information for R8C/21 Group ROM Capacity Program ROM Data Flash 32 Kbytes 1 Kbyte X 2 48 Kbytes 1 Kbyte X 2 64 Kbytes 1 Kbyte X 2 96 Kbytes 1 Kbyte X 2 128 Kbytes(1) 1 Kbyte X 2 Type No. R5F21216JFP R5F21217JFP R5F21218JFP R5F2121AJFP R5F2121CJFP R5F21216KFP R5F21217KFP R5F21218KFP R5F2121AKFP R5F2121CKFP 32 Kbytes 48 Kbytes 64 Kbytes 96 Kbytes 1 Kbyte X 2 1 Kbyte X 2 1 Kbyte X 2 1 Kbyte X 2 (1) 1 Kbyte X 2 128 Kbytes Current of Aug. 2008 RAM Capacity Package Type Remarks 2 Kbytes 2.5 Kbytes 3 Kbytes 5 Kbytes 6 Kbytes PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A J version Flash memory version 2 Kbytes 2.5 Kbytes 3 Kbytes 5 Kbytes 6 Kbytes PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A PLQP0048KB-A K version NOTE: 1. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger of Hardware Manual. Part number R 5 F 21 21 6 J XXX FP Package type: FP: PLQP0048KB-A (0.5 mm pin-pitch, 7 mm square body) ROM number Classification J: Operating ambient temperature -40C to 85C (J version) K: Operating ambient temperature -40C to 125C (K version) ROM capacity 6: 32 KB 7: 48 KB 8: 64 KB A: 96 KB C: 128 KB R8C/21 Group R8C/2x Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 6 of 41 R8C/20 Group, R8C/21 Group 1.5 1. Overview Pin Assignments P0_7/AN0 P6_3 P6_4 P6_5 P3_0/TRAO P3_1/TRBO P1_0/KI0/AN8 P1_1/KI1/AN9 P1_2/KI2/AN10 P6_7/INT3/RXD1 P6_6/INT2/TXD1 P4_5/INT0 36 35 34 33 32 31 30 29 28 27 26 25 Figure 1.4 shows Pin Assignments (Top View). Pin assignments (top view) P0_6/AN1 37 24 P1_3/KI3/AN11 P0_5/AN2 38 23 P1_4/TXD0 P0_4/AN3 39 22 P1_5/RXD0/(TRAIO)/(INT1)(2) P4_2/VREF 40 21 P1_6/CLK0 P6_0/TREO 41 20 P1_7/TRAIO/INT1 P6_2 42 19 P2_0/TRDIOA0/TRDCLK P6_1 43 18 P2_1/TRDIOB0 P0_3/AN4 44 17 P2_2/TRDIOC0 P0_2/AN5 45 16 P2_3/TRDIOD0 P0_1/AN6 46 15 P2_4/TRDIOA1 P0_0/AN7 47 14 P2_5/TRDIOB1 P3_7/SSO 48 13 P2_6/TRDIOC1 11 12 VCC/AVCC P2_7/TRDIOD1 10 7 P4_6/XIN 6 P4_4 RESET 9 5 P4_3 8 4 MODE VSS/AVSS 3 P4_7/XOUT 2 P3_3/SSI P3_4/SDA/SCS (1) 1 P3_5/SCL/SSCK R8C/20 Group, R8C/21 Group Package: PLQP0048KB-A 0.5 mm pin pitch, 7 mm square body NOTES: 1. P4_7 is an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.4 Pin Assignments (Top View) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 7 of 41 R8C/20 Group, R8C/21 Group 1.6 1. Overview Pin Functions Table 1.5 lists the Pin Functions and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Functions Type Symbol I/O Type Description Power Supply Input VCC VSS I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog Power Supply Input AVCC, AVSS I Applies the power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset Input RESET I Input "L" on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. These pins are provided for the XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. XIN Clock Input XIN I XIN Clock Output XOUT O INT Interrupt Input INT0 to INT3 I INT interrupt input pins. INT0 Timer RD input pins. INT1 Timer RA input pins. I Key input interrupt input pins. Key Input Interrupt KI0 to KI3 Timer RA TRAIO I/O Timer RA I/O pin. TRAO O Timer RA output pin. Timer RB TRBO O Timer RB output pin. Timer RD TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 I/O Timer RD I/O ports. TRDCLK I External clock input pin. Timer RE TREO O Divided clock output pin. Serial Interface CLK0 I/O Transfer clock I/O pin. RXD0, RXD1 I Serial data input pins. TXD0, TXD1 O Serial data output pins. SCL I/O Clock I/O pin. I2C Bus Interface Clock Synchronous Serial I/O with Chip Select SDA I/O Data I/O pin. SSI I/O Data I/O pin. SCS I/O Chip-select signal I/O pin. SSCK I/O Clock I/O pin. SSO I/O Data I/O pin. Reference Voltage Input VREF I Reference voltage input pin to A/D converter. A/D Converter AN0 to AN11 I Analog input pins to A/D converter. I/O Port P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1, P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7 Input Port P4_2, P4_6, P4_7 I: Input O: Output Rev.2.00 Aug 27, 2008 REJ03B0120-0200 I/O I I/O: Input and output Page 8 of 41 CMOS I/O ports. Each port contains an input/output select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull-up resistor or not by a program. Input only ports. R8C/20 Group, R8C/21 Group Table 1.6 Pin Name Information by Pin Number Pin Control Pin Number 1 2 3 4 5 6 7 1. Overview Port Interrupt P3_5 P3_3 P3_4 I/O Pin Functions for of Peripheral Modules Clock Synchronous Serial A/D I2C Bus Timer Serial I/O Interface Interface Converter with Chip Select SSCK SCL SSI SDA SCS MODE P4_3 P4_4 8 9 10 11 12 13 14 15 16 17 18 19 20 RESET XOUT P4_7 VSS/AVSS XIN P4_6 VCC/AVCC P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 INT1 TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOC0 TRDIOB0 TRDIOA0/TRDCLK TRAIO 21 22 P1_6 P1_5 (INT1)(1) (TRAIO)(1) 23 24 P1_4 P1_3 KI3 25 P4_5 INT0 26 P6_6 INT2 TXD1 27 P6_7 INT3 RXD1 28 P1_2 KI2 AN10 29 P1_1 KI1 AN9 30 P1_0 KI0 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 P3_1 P3_0 P6_5 P6_4 P6_3 P0_7 P0_6 P0_5 P0_4 P4_2 P6_0 P6_2 P6_1 P0_3 P0_2 P0_1 P0_0 P3_7 VREF TXD0 AN11 INT0 AN8 TRBO TRAO AN0 AN1 AN2 AN3 TREO NOTE: 1. Can be assigned to the pin in parentheses by a program. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 CLK0 RXD0 Page 9 of 41 AN4 AN5 AN6 AN7 SSO R8C/20 Group, R8C/21 Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB comprise a register bank. Two sets of register banks are provided. b31 b15 R2 R3 b8b7 b0 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 Address registers(1) Frame base registers(1) b0 Interrupt table register INTBL INTBH The 4-high order bits of INTB are INTBH and the 16-low order bits of INTB are INTBL. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL b7 Flag register b0 U I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area NOTE: 1. A register bank comprises these registers. Two sets of register banks are provided. Figure 2.1 CPU Registers Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 10 of 41 R8C/20 Group, R8C/21 Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2 and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies R3R1 as R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A1 can be combined with A0 to be used a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB, a 20-bit register, indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC, 20 bits wide, indicates the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is a 11-bit register indicating the CPU status. 2.8.1 Carry Flag (C) The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debug only. Set to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation resulted in 0; otherwise, 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, 0. 2.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is 0. The register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when the operation resulted in an overflow; otherwise, 0. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 11 of 41 R8C/20 Group, R8C/21 Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 12 of 41 R8C/20 Group, R8C/21 Group 3. 3. Memory Memory 3.1 R8C/20 Group Figure 3.1 shows a Memory Map of R8C/20 Group. The R8C/20 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future user and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXXh 01300h 02000h Reserved area 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step 03000h Internal RAM 0SSSSh Watchdog timer*oscillation stop detection*voltage detection 0YYYYh Address break (Reserved) Reset Internal ROM (program ROM) 0FFFFh ZZZZZh 0FFFFh Internal ROM(2) (program ROM) FFFFFh NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger of Hardware Manual. Internal RAM Internal ROM Part Number Size Address 0YYYYh Address ZZZZZh 2 Kbytes 2.5 Kbytes 00BFFh 00DFFh 04000h 13FFFh 3 Kbytes 00FFFh - 04000h 1BFFFh 5 Kbytes 00FFFh 037FFh 04000h 23FFFh 6 Kbytes 00FFFh 03BFFh 08000h 04000h R5F21208JFP, R5F21208KFP 64 Kbytes R5F2120AJFP, R5F2120AKFP 96 Kbytes R5F2120CJFP, R5F2120CKFP 128 Kbytes Memory Map of R8C/20 Group Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 13 of 41 Address 0XXXXh Address 0SSSSh - R5F21206JFP, R5F21206KFP 32 Kbytes R5F21207JFP, R5F21207KFP 48 Kbytes Figure 3.1 Size - R8C/20 Group, R8C/21 Group 3.2 3. Memory R8C/21 Group Figure 3.2 shows a Memory Map of R8C/21 Group. The R8C/21 Group has 1 Mbyte of address space from address 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM is allocated addresses 04000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal RAM is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXXh 01300h 02000h 02400h Reserved area 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Internal ROM (data flash)(1) 02BFFh 03000h 0SSSSh 0YYYYh Internal RAM Watchdog timer*oscillation stop detection*voltage detection Address break (Reserved) Reset Internal ROM (program ROM) 0FFFFh ZZZZZh 0FFFFh Internal ROM(3) (program ROM) FFFFFh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. 3. Do not use addresses 20000h to 23FFFh because these areas are used for the emulator debugger. Refer to 23. Notes on Emulator Debugger of Hardware Manual. Internal RAM Internal ROM Part Number Size Address 0YYYYh Address ZZZZZh R5F21216JFP, R5F21216KFP 32 Kbytes 08000h - Address 0XXXXh Address 0SSSSh Size 2 Kbytes 00BFFh R5F21217JFP, R5F21217KFP 48 Kbytes 04000h - 2.5 Kbytes 00DFFh R5F21218JFP, R5F21218KFP 64 Kbytes 04000h 13FFFh 3 Kbytes 00FFFh - R5F2121AJFP, R5F2121AKFP 96 Kbytes 04000h 1BFFFh 5 Kbytes 00FFFh 037FFh R5F2121CJFP, R5F2121CKFP 128 Kbytes 04000h 23FFFh 6 Kbytes 00FFFh 03BFFh Figure 3.2 Memory Map of R8C/21 Group Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 14 of 41 - R8C/20 Group, R8C/21 Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Table 4.1 to Table 4.6 list the SFR Information. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01101000b 00100000b Protect Register PRCR 00h Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 OCD WDTR WDTS WDC RMAD0 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Count Source Protect Mode Register CSPR 00h 10000000b(8) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 00h When shipping 00h 0030h 0031h 0032h Voltage Detection Register 1(2) Voltage Detection Register 2(6) VCA1 VCA2 00001000b 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register(7) VW1C Voltage Monitor 2 Circuit Control Register(5) VW2C 0000X000b(3) 0100X001b(4) 00h 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0037h 0038h 0039h 00h(3) 01000000b(4) 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1. 4. Power-on reset, voltage monitor 1 reset or the LVD0ON bit in the OFS register is set to 0. 5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3. 6. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b7. 7. Software reset, the watchdog timer rest, and the voltage monitor 2 reset do not affect other than the b0 and b6. 8. The CSPROINI bit in the OFS register is 0. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 15 of 41 R8C/20 Group, R8C/21 Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4. Special Function Registers (SFRs) SFR Information (2)(1) Register Symbol After reset Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register Timer RE Interrupt Control Register TRD0IC TRD1IC TREIC XXXXX000b XXXXX000b XXXXX000b Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU Interrupt Control Register/IIC Bus Interrupt Control Register(2) KUPIC ADIC SSUIC/IICIC XXXXX000b XXXXX000b XXXXX000b UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register INT2 Interrupt Control Register Timer RA Interrupt Control Register S0TIC S0RIC S1TIC S1RIC INT2IC TRAIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b XXXXX000b Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register TRBIC INT1IC INT3IC XXXXX000b XX00X000b XX00X000b INT0 Interrupt Control Register INT0IC XX00X000b X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 16 of 41 R8C/20 Group, R8C/21 Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4. Special Function Registers (SFRs) SFR Information (3)(1) Register Symbol UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register U0MR U0BRG U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0C0 U0C1 U0RB UART1 Transmit/Receive Mode Register UART1 Bit Rate Register UART1 Transmit Buffer Register U1MR U1BRG U1TB UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1C0 U1C1 U1RB SS Control Register H/IIC Bus Control Register 1(2) SS Control Register L/IIC Bus Control Register 2(2) SS Mode Register/IIC Bus Mode Register 1(2) SS Enable Register/IIC Bus Interrupt Enable Register(2) SS Status Register/IIC Bus Status Register(2) SS Mode Register 2/Slave Address Register(2) SS Transmit Data Register/IIC Bus Transmit Data Register(2) SS Receive Data Register/IIC Bus Receive Data Register(2) SSCRH/ICCR1 SSCRL/ICCR2 SSMR/ICMR SSER/ICIER SSSR/ICSR SSMR2/SAR SSTDR/ICDRT SSRDR/ICDRR X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 17 of 41 After reset 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h 01111101b 00011000b 00h 00h/0000X000b 00h FFh FFh R8C/20 Group, R8C/21 Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4. Special Function Registers (SFRs) SFR Information (4)(1) Register Symbol After reset A/D Register AD XXh XXh A/D Control Register 2 ADCON2 00h A/D Control Register 0 A/D Control Register 1 ADCON0 ADCON1 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 XXh XXh 00h 00h XXh XXh 00h 00h XXh Port P4 Direction Register PD4 00h Port P6 Register P6 XXh Port P6 Direction Register PD6 00h UART1 Function Select Register U1SR XXh Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 PMR INTEN INTF KIEN PUR0 PUR1 00h 00h 00h 00h 00h XX00XX00b X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 18 of 41 R8C/20 Group, R8C/21 Group Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 4. Special Function Registers (SFRs) SFR Information (5)(1) Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA 00h 00h 00h FFh FFh LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR 00h 00h 00h 00h 00h 00h FFh FFh FFh Timer RE Counter Data Register Timer RE Compare Data Register TRESEC TREMIN 00h 00h Timer RE Control Register 1 Timer RE Control Register 2 Timer RE Count Source Select Register TRECR1 TRECR2 TRECSR 00h 00h 00001000b Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1 TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 19 of 41 After reset R8C/20 Group, R8C/21 Group Table 4.6 Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh 4. Special Function Registers (SFRs) SFR Information (6)(1) Register Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 Timer RD General Register A0 TRDGRA0 Timer RD General Register B0 TRDGRB0 Timer RD General Register C0 TRDGRC0 Timer RD General Register D0 TRDGRD0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 Timer RD General Register A1 TRDGRA1 Timer RD General Register B1 TRDGRB1 Timer RD General Register C1 TRDGRC1 Timer RD General Register D1 TRDGRD1 Flash Memory Control Register 4 FMR4 01000000b Flash Memory Control Register 1 FMR1 1000000Xb Flash Memory Control Register 0 FMR0 00000001b Option Function Select Register OFS (Note 2) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 20 of 41 After reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh R8C/20 Group, R8C/21 Group 5. 5. Electrical Characteristics Electrical Characteristics Table 5.1 Absolute Maximum Ratings Symbol Parameter Rated value Unit -0.3 to 6.5 V Input voltage -0.3 to VCC+0.3 V VO Output voltage -0.3 to VCC+0.3 V Pd Power dissipation 300 mW Topr Operating ambient temperature Tstg Storage temperature VCC/AVCC Supply voltage VI Condition -40C Topr 85C 85C < Topr 125C Table 5.2 125 mW -40 to 85 (J version) / -40 to 125 (K version) C -65 to 150 C Recommended Operating Conditions Symbol Parameter Conditions Standard Min. Typ. Max. Unit VCC/AVCC Supply voltage 2.7 - 5.5 VSS/AVCC Supply voltage - 0 - V VIH Input "H" voltage 0.8VCC - VCC V VIL Input "L" voltage IOH(sum) Peak sum output "H" current IOH(peak) IOH(avg) IOL(sum) Peak sum output "L" currents IOL(peak) IOL(avg) f(XIN) XIN clock input oscillation frequency - V 0 - 0.2VCC V - - -60 mA Peak output "H" current - - -10 mA Average output "H" current - - -5 mA - - 60 mA Peak output "L" currents - - 10 mA Average output "L" current - - 5 mA 3.0 V VCC 5.5 V -40C Topr 85C 0 - 20 MHz 3.0 V VCC 5.5 V -40C Topr 125C 0 - 16 MHz System clock Sum of all Pins IOH (peak) Sum of all Pins IOL (peak) 2.7 V VCC < 3.0 V 0 - 10 MHz OCD2 = 0 When XIN clock is selected. 3.0 V VCC 5.5 V -40C Topr 85C 0 - 20 MHz 3.0 V VCC 5.5 V -40C Topr 125C 0 - 16 MHz 2.7 V VCC < 3.0 V 0 - 10 MHz OCD2 = 1 When on-chip oscillator clock is selected. FRA01 = 0 When low-speed onchip oscillator clock is selected. - 125 - kHz FRA01 = 1 When high-speed onchip oscillator clock is selected. 3.0 V VCC 5.5 V -40C Topr 85C - - 20 MHz FRA01 = 1 When high-speed onchip oscillator clock is selected. - - 10 MHz NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 21 of 41 R8C/20 Group, R8C/21 Group Table 5.3 5. Electrical Characteristics A/D Converter Characteristics Symbol Parameter - Resolution - Absolute Accuracy Rladder Resistor ladder tconv Conversion time Conditions Standard Min. Typ. Max. Unit Vref = AVCC - - 10 Bits 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 3 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 2 LSB 10-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 5 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 2 LSB Vref = AVCC 10 - 40 k 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V 3.3 - - s 8-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V 2.8 - - s 2.7 - AVCC V 0 - AVCC V 0.25 - 10 MHz 1 - 10 MHz Vref Reference voltage VIA Analog input voltage(2) - A/D operating clock frequency Without sample & hold With sample & hold NOTES: 1. VCC = AVCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. When analog input voltage exceeds reference voltage, A/D conversion result is 3FFh in 10-bit mode, FFh in 8-bit mode. P0 P1 P2 P3 P4 P6 Figure 5.1 30pF Ports P0 to P4, P6 Timing Measurement Circuit Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 22 of 41 R8C/20 Group, R8C/21 Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics Symbol - 5. Electrical Characteristics Parameter Program/erase endurance(2) Conditions Standard Unit Min. Typ. Max. R8C/20 Group 100(3) - - times R8C/21 Group 1,000(3) - - times s - Byte program time - 50 400 - Block erase time - 0.4 9 s - - 97 + CPU clock x 6 cycle s 650 - - s td(SR-SUS) Time delay from suspend request until erase suspend - Interval from erase start/restart until following suspend request - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3 + CPU clock x 4 cycle s V - Program, erase voltage 2.7 - 5.5 - Read voltage 2.7 - 5.5 V - Program, erase temperature 0 - 60 C - Data hold time(7) 20 - - year Ambient temperature = 55C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 23 of 41 R8C/20 Group, R8C/21 Group Table 5.5 5. Electrical Characteristics Flash Memory (Data Flash Block A, Block B) Electrical Characteristics(4) Symbol Parameter Conditions Standard Min. Typ. Max. Unit - Program/erase endurance(2) 10,000(3) - - times - Byte program time (Program/erase endurance 1,000 times) - 50 400 s - Byte program time (Program/erase endurance > 1,000 times) - 65 - s - Block erase time (Program/erase endurance 1,000 times) - 0.2 9 s - Block erase time (Program/erase endurance > 1,000 times) - 0.3 - s - - 97 + CPU clock x 6 cycle s 650 - - s td(SR-SUS) Time delay from suspend request until erase suspend - Interval from erase start/restart until following suspend request - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3 + CPU clock x 4 cycle s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.7 - 5.5 V - Program, erase temperature -40 - 85(8) C - Data hold time(9) 20 - - year Ambient temperature = 55C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. MInimum endurance to guarantee all electrical characteristics after program and erase (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times are the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure endurance can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number. 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. 125C for K version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 24 of 41 R8C/20 Group, R8C/21 Group 5. Electrical Characteristics Suspend request (Maskable interrupt request) FMR46 Fixed time Clock-dependent time Access restart td(SR-SUS) Figure 5.2 Table 5.6 Time delay until Suspend Voltage Detection 1 Circuit Electrical Characteristics Symbol Vdet1 td(Vdet1-A) Parameter Condition Voltage detection level(3, 4) Voltage monitor 1 reset generation time(5) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(2) Vccmin MCU operating voltage minimum value VCA26 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 2.70 2.85 3.00 V - 40 200 s - 0.6 - A - - 100 s 2.70 - - V NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85C (J version) / -40C to 125C (K version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 3. Hold Vdet2 > Vdet1. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. 5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter, its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet1 when the power supply falls. Table 5.7 Voltage Detection 2 Circuit Electrical Characteristics Symbol Parameter Vdet2 Voltage detection level(4) td(Vdet2-A) Voltage monitor 2 reset/interrupt request generation time(2, 5) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) Condition VCA27 = 1, VCC = 5.0V Standard Max. Unit Min. Typ. 3.3 3.6 3.9 V - 40 200 s - 0.6 - A - - 100 s NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85C (J version) / -40C to 125C (K version). 2. Time until the voltage monitor 2 reset/interrupt request is generated since the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. 4. Hold Vdet2 > Vdet1. 5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this time until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 25 of 41 R8C/20 Group, R8C/21 Group Table 5.8 5. Electrical Characteristics Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics(3) Symbol Parameter Condition Standard Min. Typ. Unit Max. Vpor1 Power-on reset valid voltage(4) - - 0.1 V Vpor2 Power-on reset or voltage monitor 1 valid voltage 0 - Vdet1 V trth External power VCC rise gradient VCC 3.6 V 20(2) - - mV/msec VCC > 3.6 V 20(2) - 2,000 mV/msec NOTES: 1. Topr = -40C to 85C (J version) / -40C to 125C (K version), unless otherwise specified. 2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 1.0 V. 3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30s or more if -20C Topr 125C, maintain tw(por1) for 3,000s or more if -40C Topr < -20C. Vdet1(3) Vdet1(3) 2.0 V trth External power Vcc trth td(Vdet1-A) Vpor2 Vpor1 tw(por1) Sampling time(1, 2) Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S NOTES: 1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. Figure 5.3 Power-on Reset Circuit Electrical Characteristics Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 26 of 41 R8C/20 Group, R8C/21 Group Table 5.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol fOCO40M 5. Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence - The value of the FRA1 register when the reset is deasserted - High-speed on-chip oscillator adjustment range - Oscillation stability time - Self power consumption when high-speed on-chip oscillator oscillating Condition Standard Unit Min. Typ. Max. VCC = 4.75 V to 5.25 V, 0C Topr 60C(2) 39.2 40 40.8 MHz VCC = 3.0 V to 5.25 V, -20C Topr 85C(2) 38.8 40 41.2 MHz VCC = 3.0 V to 5.5 V, -40C Topr 85C(2) 38.4 40 41.6 MHz VCC = 3.0 V to 5.5 V, -40C Topr 125C(2) 38.0 40 42.0 MHz VCC = 2.7 V to 5.5 V, -40C Topr 125C(2) 37.6 40 42.4 MHz 08h 40 F7h - Adjust the FRA1 register to -1 bit (the value when the reset is deasserted) - + 0.3 - MHz - 10 100 s VCC = 5.0 V, Topr = 25C - 600 - A NOTES: 1. VCC = 2.7 V to 5.5 V, Topr = -40C to 85C (J version) / -40C to 125C (K version), unless otherwise specified. 2. The standard value shows when the reset is deasserted for the FRA1 register. Table 5.10 Low-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit fOCO-S Low-speed on-chip oscillator frequency 40 125 250 - Oscillation stability time - 10 100 s - Self power consumption when low-speed on-chip oscillator oscillating - 15 - A VCC = 5.0 V, Topr = 25C kHz NOTE: 1. VCC = 2.7 V to 5.5 V, Topr = -40C to 85C (J version) / -40C to 125C (K version), unless otherwise specified. Table 5.11 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit td(P-R) Time for internal power supply stabilization during power-on(2) 1 - 2000 s td(R-S) STOP exit time(3) - - 150 s NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40C to 85C (J version) / -40C to 125C (K version), unless otherwise specified. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 27 of 41 R8C/20 Group, R8C/21 Group Table 5.12 5. Electrical Characteristics Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Symbol Parameter Conditions Standard Min. Typ. Unit Max. tSUCYC SSCK clock cycle time 4 - - tCYC(2) tHI SSCK clock "H" width 0.4 - 0.6 tSUCYC tLO SSCK clock "L" width tRISE SSCK clock rising time 0.4 - 0.6 tSUCYC Master - - 1 tCYC(2) Slave - - 1 s Master - - 1 tCYC(2) s tFALL SSCK clock falling time - - 1 tSU SSO, SSI data input setup time 100 - - ns tH SSO, SSI data input hold time 1 - - tCYC(2) tLEAD Slave SCS setup time Slave 1tCYC + 50 - - ns tLAG SCS hold time Slave 1tCYC + 50 - - ns tOD SSO, SSI data output delay time - - 1 tCYC(2) tSA SSI slave access time - - 1tCYC + 100 ns tOR SSI slave out open time - - 1tCYC + 100 ns NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 28 of 41 R8C/20 Group, R8C/21 Group 5. Electrical Characteristics 4-wire bus communication mode, Master, CPHS = 1 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-wire bus communication mode, Master, CPHS = 0 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SSMR register Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 29 of 41 R8C/20 Group, R8C/21 Group 5. Electrical Characteristics 4-wire bus communication mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-wire bus communication mode, Slave, CPHS = 0 VIH or VOH SCS (input) VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SSMR register Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 30 of 41 R8C/20 Group, R8C/21 Group 5. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 5.6 tH I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 31 of 41 R8C/20 Group, R8C/21 Group Table 5.13 5. Electrical Characteristics Timing Requirements of I2C Bus Interface(1) Symbol Parameter Conditions Standard Typ. - Max. - - - ns - - ns - 300 - ns ns Unit tSCL SCL input cycle time tSCLH SCL input "H" width tSCLL SCL input "L" width tsf tSP SCL, SDA input falling time SCL, SDA input spike pulse rejection time Min. 12tCYC + 600(2) 3tCYC + 300(2) 5tCYC + 300(2) - - tBUF SDA input bus-free time 5tCYC(2) - 1tCYC(2) - tSTAH Start condition input hole time 3tCYC(2) - - ns tSTAS Retransmit start condition input setup time 3tCYC(2) - - ns - - ns tSOAS Stop condition input setup time Data input setup time 3tCYC(2) - - ns tSDAH Data input hold time 1tCYC + 20(2) 0 - - ns tSTOP ns NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0V at Topr = -40 to 85C (J version) / -40 to 125C (K version), unless otherwise specified. 2. 1tCYC = 1/f1(s) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOP SCL P(2) S(1) tSf Sr(3) tSCLL tSr tSCL tSDAS tSDAH NOTES: 1. Start condition 2. Stop condition 3. Retransmit "Start" condition Figure 5.7 I/O Timing of I2C Bus Interface Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 32 of 41 P(2) ns R8C/20 Group, R8C/21 Group Table 5.14 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH 5. Electrical Characteristics IOH = -1 mA Standard Min. Typ. VCC - 2.0 - VCC - 0.3 - VCC - 2.0 - Max. VCC VCC VCC IOH = -500 A VCC - 2.0 - VCC V - - - - IOL = 1 mA - - 2.0 0.45 2.0 V V V IOL = 500 A - - 2.0 V INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSO 0.1 0.5 - V RESET 0.1 1.0 - V - - - 30 - 50 1.0 5.0 -5.0 167 - A - A k M 2.0 - - V Parameter Output "H" Voltage Except XOUT XOUT VOL Output "L" Voltage Except XOUT XOUT VT+-VT- IIH IIL RPULLUP RfXIN VRAM Hysteresis Input "H" current Input "L" current Pull-Up Resistance Feedback Resistance RAM Hold Voltage Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW VI = 5 V, VCC = 5 V VI = 0 V, VCC = 5 V VI = 0 V, VCC = 5 V XIN During stop mode Unit V V V NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 20 MHz, unless otherwise specified. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 33 of 41 R8C/20 Group, R8C/21 Group Table 5.15 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [VCC = 5 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), Unless Otherwise Specified.) Parameter Condition Power supply current High-clock (VCC = 3.3 to 5.5 V) mode In single-chip mode, the output pins are open and other pins are VSS Rev.2.00 Aug 27, 2008 REJ03B0120-0200 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed XIN clock off on-chip High-speed on-chip oscillator on fOCO = 10 MHz oscillator Low-speed on-chip oscillator on = 125 kHz mode No division XIN clock off High-speed on-chip oscillator on fOCO= 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Low-speed XIN clock off on-chip High-speed on-chip oscillator off oscillator Low-speed on-chip oscillator on = 125 kHz mode Divide-by-8 FMR47 = 1 Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA20 = 0 VCA26 = VCA27 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA20 = 0 VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Page 34 of 41 Min. - Standard Typ. Max. 11.0 22.0 Unit mA - 8.8 17.6 mA - 5.8 - mA - 5.0 - mA - 3.8 - mA - 2.8 - mA - 5.8 11.6 mA - 2.5 - mA - 143 286 A - 53 106 A - 38 76 A - 0.8 3.0 A - 1.2 - A - 4.0 - A R8C/20 Group, R8C/21 Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] XIN Input Table 5.16 Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 50 - 25 - 25 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width Unit ns ns ns Vcc = 5V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.8 Table 5.17 XIN Input Timing Diagram when VCC = 5 V TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 100 - 40 - 40 - Parameter TRAIO input cycle time TRAIO input "H" width TRAIO input "L" width Vcc = 5V tc(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.9 TRAIO Input Timing Diagram when VCC = 5 V Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 35 of 41 Unit ns ns ns R8C/20 Group, R8C/21 Group Table 5.18 5. Electrical Characteristics Serial Interface Symbol Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Parameter tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLK0 input cycle time CLK0 input "H" width CLK0 input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 Vcc = 5V tc(CK) tW(CKH) CLK0 tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.10 Table 5.19 Serial Interface Timing Diagram when VCC = 5 V External Interrupt INTi (i = 0 to 3) Input tW(INH) INTi input "H" width Standard Min. Max. (1) - 250 tW(INL) INTi input "L" width 250(2) Symbol Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. Vcc = 5V tW(INL) INTi input tW(INH) i = 0 to 3 Figure 5.11 External Interrupt INTi Input Timing Diagram when VCC = 5 V (i = 0 to 3) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 36 of 41 R8C/20 Group, R8C/21 Group Table 5.20 Electrical Characteristics (3) [VCC = 3 V] Symbol VOH VOL VT+-VT- IIH IIL RPULLUP RfXIN VRAM 5. Electrical Characteristics Parameter Output "H" voltage Output "L" voltage Hysteresis Input "H" current Input "L" current Pull-up resistance Feedback resistance RAM hold voltage Except XOUT XOUT IOH = -0.1 mA Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - Max. VCC VCC IOH = -50 A VCC - 0.5 - VCC V Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Unit V V - - IOL = 0.1 mA - - 0.5 0.5 V V IOL = 50 A - - 0.5 V INT0, INT1, INT2, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD1, CLK0, SSI, SCL, SDA, SSO 0.1 0.3 - V RESET 0.1 0.4 - V - - - 66 - 2.0 160 3.0 - 4.0 -4.0 500 - - A - Except XOUT XOUT VI = 3 V, VCC = 3 V VI = 0 V, VCC = 3 V VI = 0 V, VCC = 3 V XIN During stop mode A k M V NOTE: 1. VCC = 2.7 to 3.3 V at Topr = -40 to 85C (J version) / -40 to 125C (K version), f(XIN) = 10 MHz, unless otherwise specified. Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 37 of 41 R8C/20 Group, R8C/21 Group Table 5.21 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (4) [VCC = 3 V] (Topr = -40 to 85C (J version) / -40 to 125C (K version), Unless Otherwise Specified.) Parameter Condition Power supply current High-clock (VCC = 2.7 to 3.3 V) mode In single-chip mode, the output pins are open and other pins are VSS Rev.2.00 Aug 27, 2008 REJ03B0120-0200 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 High-speed XIN clock off on-chip High-speed on-chip oscillator on fOCO = 10 MHz oscillator Low-speed on-chip oscillator on = 125 kHz mode No division XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Low-speed XIN clock off on-chip High-speed on-chip oscillator off oscillator Low-speed on-chip oscillator on = 125 kHz mode Divide-by-8 FMR47 = 1 Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA20 = 0 VCA26 = VCA27 = 0 XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA20 = 0 VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Stop mode XIN clock off Topr = 125C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Page 38 of 41 Min. - Standard Typ. Max. 10.5 21.0 Unit mA - 8.3 16.6 mA - 5.3 10.6 mA - 4.5 - mA - 3.3 - mA - 2.3 - mA - 5.6 11.2 mA - 2.4 - mA - 138 276 A - 48 96 A - 35 70 A - 0.7 3.0 A - 1.1 - A - 3.8 - A R8C/20 Group, R8C/21 Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0V at Topr = 25C) [VCC = 3 V] Table 5.22 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 100 - 40 - 40 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width Unit ns ns ns Vcc = 3V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.12 Table 5.23 XIN Input Timing Diagram when VCC = 3 V TRAIO Input Symbol tc(TRAIO) tWH(TRAIO) tWL(TRAIO) Standard Min. Max. 300 - 120 - 120 - Parameter TRAIO input Cycle time TRAIO input "H" width TRAIO input "L" width Vcc = 3V tc(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.13 TRAIO Input Timing Diagram when VCC = 3 V Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 39 of 41 Unit ns ns ns R8C/20 Group, R8C/21 Group Table 5.24 5. Electrical Characteristics Serial Interface Symbol Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Parameter tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLK0 input cycle time CLK0 input "H" width CLK0 input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 Vcc = 3V tc(CK) tW(CKH) CLK0 tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.14 Table 5.25 Serial Interface Timing Diagram when VCC = 3 V External Interrupt INTi (i = 0 to 3) Input tW(INH) INTi input "H" width Standard Min. Max. (1) - 380 tW(INL) INTi input "L" width 380(2) Symbol Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use the INTi input HIGH width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INTi input filter select bit, use the INTi input LOW width to the greater value, either (1/digital filter clock frequency x 3) or the minimum value of standard. Vcc = 3V tW(INL) INTi input tW(INH) i = 0 to 3 Figure 5.15 External Interrupt INTi Input Timing Diagram when VCC = 3 V (i = 0 to 3) Rev.2.00 Aug 27, 2008 REJ03B0120-0200 Page 40 of 41 R8C/20 Group, R8C/21 Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code P-LQFP48-7x7-0.50 RENESAS Code PLQP0048KB-A Previous Code 48P6Q-A MASS[Typ.] 0.2g HD *1 D 36 25 37 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 24 bp c c1 *2 E HE b1 Reference Symbol 48 13 1 ZE Terminal cross section 12 c A F A2 Index mark ZD A1 L D E A2 HD HE A A1 bp b1 c c1 e Rev.2.00 Aug 27, 2008 REJ03B0120-0200 *3 bp Detail F x Page 41 of 41 Min 6.9 6.9 8.8 8.8 0 0.17 0.09 0 L1 y Dimension in Millimeters e x y ZD ZE L L1 0.35 Nom Max 7.0 7.1 7.0 7.1 1.4 9.0 9.2 9.0 9.2 1.7 0.1 0.2 0.22 0.27 0.20 0.145 0.20 0.125 8 0.5 0.08 0.10 0.75 0.75 0.5 0.65 1.0 REVISION HISTORY R8C/20 Group, R8C/21 Group Datasheet Description Rev. Date 0.10 Mar 08, 2005 - First Edition issued 0.20 Sep 29, 2005 - Words standardized - Clock synchronous serial interface Clock synchronous serial I/O - Chip-select clock synchronous interface(SSU) Clock synchronous serial I/O with chip select - I2C bus interface(IIC) I2C bus interface Page Summary 2, 3 Table1.1 R8C/20 Group Performance, Table1.2 R8C/21 Group Performance Serial Interface revised: - Clock Synchronous Serial Interface: 1 channel I2C bus Interface (3), Clock synchronous serial I/O with chip select - Power-On Reset Circuit added - Power Consumption value determined 5, 6 Table 1.3 Product Information of R8C/20 Group, Table 1.4 Product Information of R8C/21 Group Date revised. 7 Figure 1.4 Pin Assignment Pin name revised: - P3_5/SSCK(/SCL) P3_5/ SCL/SSCK - P3_4/SCS(/SDA) P3_4/ SDA /SCS - VSS VSS/AVSS - VCC VCC/AVCC - P1_5/RXD0/(TRAIO/INT1) P1_5/RXD0/(TRAIO)/(INT1) - P6_6/INT2/(TXD1) P6_6/INT2/TXD1 - P6_7/INT3/(RXD1) P6_7/INT3/RXD1 - NOTE2 added 8 Table 1.5 Pin Description - Analog Power Supply Input: line added - I2C Bus Interface (IIC) I2C Bus Interface - SSU Clock Synchronous Serial I/O with Chip Select 9 Table 1.6 Pin Name Information by Pin Number revised - Pin Number 1: (SCL) SCL - Pin Number 2: (SDA) SDA - Pin Number 9: VSS VSS/AVSS - Pin Number 11: VCC VCC/AVCC - Pin Number 26: (TXD1) TXD1 - Pin Number 27: (RXD1) RXD1 15 Table 4.1 SFR Information (1) revised - 0013h: XXXXXX00b 00h 17 Table 4.3 SFR Information (3) revised - 00BCh: 0000X000b 00h/0000X000b 18 Table 4.4 SFR Information (4) revised - 00D6h: 00000XXXb 00h - 00F5h: UART1 Function Select Register added 19 Table 4.5 SFR Information (5) revised - 0104h: TRATR TRA A-1 REVISION HISTORY Rev. Date 0.20 Sep 29, 2005 1.00 Nov 15, 2006 R8C/20 Group, R8C/21 Group Datasheet Description Page Summary 20 Table 4.6 SFR Information (6) revised - 0145h: POCR0 TRDPOCR0 - 0146h, 0147h: TRDCNT0 TRD0 - 0148h, 0149h: GRA0 TRDGRA0 - 014Ah, 014Bh: GRB0 TRDGRB0 - 014Ch, 014Dh: GRC0 TRDGRC0 - 014Eh, 014Fh: GRD0 TRDGRD0 - 0155h: POCR1 -> TRDPOCR1 - 0156h, 0157h: TRDCNT1 TRD1 - 0158h, 0159h: GRA1 TRDGRA1 - 015Ah, 015Bh: GRB1 TRDGRB1 - 015Ch, 015Dh: GRC1 TRDGRC1 - 015Eh, 015Fh: GRD1 TRDGRD1 22 5. Electrical Characteristics added All pages "Preliminary" and "Under development" deleted 2 Table 1.1 Functions and Specifications for R8C/20 Group revised. NOTE1 deleted. 3 Table 1.2 Functions and Specifications for R8C/21 Group revised. NOTE1 deleted. 5 Table 1.3 Product Information for R8C/20 Group; "R5F2120AJFP (D)", "R5F2120CJFP (D)", "R5F2120AKFP (D)", "R5F2120CKFP (D)", and NOTE added. Figure 1.2 Type Number, Memory Size, and Package of R8C/20 Group; "A: 96 KB" and "C: 128 KB" added. 6 Table 1.4 Product Information for R8C/21 Group; "R5F2121AJFP (D)", "R5F2121CJFP (D)", "R5F2121AKFP (D)", "R5F2121CKFP (D)", and NOTE added. Figure 1.3 Type Number, Memory Size, and Package of R8C/21 Group; "A: 96 KB" and "C: 128 KB" added. 13 Figure 3.1 Memory Map of R8C/20 Group revised. 14 Figure 3.2 Memory Map of R8C/21 Group revised. 15 Table 4.1 SFR Information (1)(1); NOTE8; "The CSPROINI bit in the OFS register is set to 0." "The CSPROINI bit in the OFS register is 0." revised. 21 Table 5.1 Absolute Maximum Ratings; Power dissipation revised. Table 5.2 Recommended Operating Conditions; System clock revised. 26 Table 5.8 Voltage Monitor 1 Reset Circuit Electrical Characteristics Table 5.8 Power-on Reset Circuit, Voltage Monitor 1 Reset Circuit Electrical Characteristics(1) replaced. Table 5.8 revised. NOTE3 added. Table 5.9 Power-on Reset Circuit Electrical Characteristics deleted. Figure 5.3 Power-on Reset Circuit Electrical Characteristics revised. 27 Table 5.10 High-Speed On-Chip Oscillator Circuit Electrical Characteristics Table 5.9 High-Speed On-Chip Oscillator Circuit Electrical Characteristics revised. A-2 REVISION HISTORY Rev. Date 1.00 Nov 15, 2006 2.00 Aug 27, 2008 R8C/20 Group, R8C/21 Group Datasheet Description Page Summary 33 Table 5.15 Electrical Characteristics (1) [VCC = 5 V] Table 5.14 Electrical Characteristics (1) [VCC = 5 V] revised. RAM Hold Voltage, Min.; "1.8" "2.0" corrected. 34 Table 5.16 Electrical Characteristics (2) [Vcc = 5 V] Table 5.15 Electrical Characteristics (2) [Vcc = 5 V] revised. Wait mode revised. 37 Table 5.21 Electrical Characteristics (3) [VCC = 3 V Table 5.20 Electrical Characteristics (3) [VCC = 3 V] revised. RAM hold voltage, Min.;"1.8" "2.0" corrected. 38 Table 5.22 Electrical Characteristics (4) [Vcc = 3 V] Table 5.21 Electrical Characteristics (4) [Vcc = 3 V] revised. Wait mode revised. - "RENESAS TECHNICAL UPDATE" reflected: TN-16C-A172A/E 5, 6 13, 14 Table 1.3, Table 1.4 revised Figure 1.2, Figure 1.3; ROM number "XXX" added Figure 3.1, Figure 3.2; "Expanding area" deleted 21 Table 5.2; NOTE2 revised 23 Table 5.4; NOTE2 and NOTE4 revised 24 Table 5.5; NOTE2 and NOTE5 revised 25 Table 5.6; "td(Vdet1-A)" added, NOTE5 added Table 5.7; "td(Vdet2-A)" and NOTE2 revised, NOTE5 added 26 Table 5.8; "trth" and NOTE2 revised Figure 5.3 revised All trademarks and registered trademarks are the property of their respective owners. A-3 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 (c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.2