OBSOLETE 54ACT573 www.ti.com SNOS141B - AUGUST 1998 - REVISED APRIL 2013 54ACT573 Octal Latch with Tri-State Outputs Check for Samples: 54ACT573 FEATURES DESCRIPTION * * The 'ACT573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. 1 23 * * * * * * ICC and IOZ Reduced by 50% Inputs and Outputs on Opposite Sides of Package Allowing Easy Interface with Microprocessors Useful as Input or Output Port for Microprocessors Functionally Identical to 'ACT373 Tri-State Outputs for Bus Interfacing Outputs Source/Sink 24 mA 'ACT573 has TTL-Compatible Inputs Standard Military Drawing (SMD) - 'ACT573: 5962-87664 The 'ACT573 is functionally identical to the 'ACT373 but has inputs and outputs on opposite sides. Logic Symbols Figure 1. Figure 2. IEEE/IEC Pin Names Description D0-D7 Data Inputs LE Latch Enable Input OE Tri-State Output Enable Input O0-O7 Tri-State Latch Outputs 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FACT is a registered trademark of Fairchild Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1998-2013, Texas Instruments Incorporated OBSOLETE 54ACT573 SNOS141B - AUGUST 1998 - REVISED APRIL 2013 www.ti.com Connection Diagrams Figure 3. Pin Assignment for CDIP and CLGA Figure 4. Pin Assignment for LCCC Functional Description The 'ACT573 contains eight D-type latches with Tri-State output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The Tri-State buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. TRUTH TABLE (1) Inputs (1) Outputs OE LE D On L H H H L H L L L L X O0 H X X Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 2 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 54ACT573 OBSOLETE 54ACT573 www.ti.com SNOS141B - AUGUST 1998 - REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) -0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V -20 mA VI = VCC + 0.5V +20 mA -0.5V to VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V -20 mA VO = VCC + 0.5V +20 mA -0.5V to VCC + 0.5V DC Output Voltage (VO) DC Output Sourceor Sink Current (IO) 50 mA DC VCC or Ground Current per Output Pin (ICC or IGND) 50 mA -65C to +150C Storage Temperature (TSTG) Junction Temperature (TJ) (1) CDIP 175C Absolute Maximum Ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Texas Instruments does not recommend operation of FACT(R) circuits outside databook specifications. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. (2) RECOMMENDED OPERATING CONDITIONS Supply Voltage (VCC) 'ACT 4.5V to 5.5V Input Voltage (VI) 0V to VCC Output Voltage (VO) 0V to VCC Operating Temperature (TA) -55C to +125C 54ACT Minimum Input Edge Rate (V/t) VIN from 0.8V to 2.0V 'ACT Devices 125 mV/ns VCC @ 4.5V, 5.5V DC CHARACTERISTICS FOR 'ACT FAMILY DEVICES 54ACT Symbol Parameter VCC TA = (V) -55C to +125C Units Conditions Specified Limits VIH VIL VOH VOL IIN (1) Minimum High Level Input Voltage 4.5 2.0 5.5 2.0 Maximum Low Level Input Voltage 4.5 0.8 5.5 0.8 Minimum High Level Output Voltage 4.5 4.4 5.5 5.4 Maximum Low Level Output Voltage Maximum Input Leakage Current VOUT = 0.1V V V or VCC - 0.1V V or VCC - 0.1V VOUT = 0.1V IOUT = -50 A VIN = VIL or VIH (1) 4.5 3.70 5.5 4.70 4.5 0.1 5.5 0.1 V -24 mA IOH -24 mA V IOUT = 50 A VIN = VIL or VIH (1) 4.5 0.50 5.5 0.50 5.5 1.0 V IOL 24 mA 24 mA A VI = VCC, GND All outputs loaded; thresholds on input associated with output under test. Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 54ACT573 3 OBSOLETE 54ACT573 SNOS141B - AUGUST 1998 - REVISED APRIL 2013 www.ti.com DC CHARACTERISTICS FOR 'ACT FAMILY DEVICES (continued) 54ACT Symbol Parameter VCC TA = (V) -55C to +125C Units Conditions Specified Limits IOZ Maximum Tri-State Leakage Current ICCT IOLD IOHD ICC 5.5 5.0 A VI = VIL, VIH VO = VCC, GND MaximumICC/Input 5.5 1.6 mA VI = VCC - 2.1V Minimum Dynamic Output Current (2) 5.5 50 mA VOLD = 1.65V Max 5.5 -50 mA VOHD = 3.85V Min 5.5 80.0 A VIN = VCC or GND Maximum Quiescent Supply Current (2) Maximum test duration 2.0 ms, one output loaded at a time. AC ELECTRICAL CHARACTERISTICS 54ACT TA = -55C VCC Symbol Parameter to +125C (V) (1) Fig. Units CL = 50 pF Min Max tPLH Propagation Delay Dm to On 5.0 1.5 13.5 ns tPHL Propagation Delay Dn to On 5.0 1.5 13.5 ns tPLH Propagation Delay LE to On 5.0 1.5 13.0 ns tPHL Propagation Delay LE to On 5.0 1.5 12.0 ns tPZH Output Enable Time 5.0 1.5 11.5 ns tPZL Output Enable Time 5.0 1.5 11.0 ns tPHZ Output Disable Time 5.0 1.5 13.5 ns tPLZ Output Disable Time 5.0 1.5 10.5 ns (1) No. Voltage Range 5.0 is 5.0V 0.5V AC OPERATING REQUIREMENTS 54ACT VCC Symbol Parameter (V) (1) TA = -55C to +125C Fig. Units No. CL = 50 pF Specified Minimum ts Setup Time, HIGH or LOW Dn to LE 5.0 4.5 ns th Hold Time, HIGH or LOW Dn to LE 5.0 1.0 ns tw LE Pulse Width, HIGH 5.0 5.0 ns (1) Voltage Range 5.0 is 5.0V 0.5V CAPACITANCE Symbol Parameter Typ Units Conditions CIN Input Capacitance 5.0 pF VCC = OPEN CPD Power Dissipation Capacitance 25.0 pF VCC = 5.0V 4 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 54ACT573 OBSOLETE 54ACT573 www.ti.com SNOS141B - AUGUST 1998 - REVISED APRIL 2013 REVISION HISTORY Changes from Revision A (April 2013) to Revision B * Page Changed layout of National Data Sheet to TI format ............................................................................................................ 4 Submit Documentation Feedback Copyright (c) 1998-2013, Texas Instruments Incorporated Product Folder Links: 54ACT573 5 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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