LTC1604ACG - ANALOG DEVICES

LTC1604

1604fa

TYPICAL APPLICATION

FEATURES DESCRIPTION

High Speed, 16-Bit, 333ksps

Sampling A/D Converter

with Shutdown

The LTC

1604 is a 333ksps, 16-bit sampling A/D con-

verter that draws only 220mW from ±5V supplies. This

high performance device includes a high dynamic range

sample-and-hold, a precision reference and a high speed

parallel output. Two digitally selectable power shutdown

modes provide power savings for low power systems.

The LTC1604’s full-scale input range is ±2.5V. Outstand-

ing AC performance includes 90dB S/(N+D) and –100dB

THD at a sample rate of 333ksps.

The unique differential input sample-and-hold can acquire

single-ended or differential input signals up to its 15MHz

bandwidth. The 68dB common mode rejection allows

users to eliminate ground loops and common mode noise

by measuring signals differentially from the source.

The ADC has μP compatible,16-bit parallel output port.

There is no pipeline delay in conversion results. A separate

convert start input and a data ready signal (BUSY) ease

connections to FlFOs, DSPs and microprocessors.

LTC1604 4096 Point FFT

APPLICATIONS

n A Complete, 333ksps 16-Bit ADC

n 90dB S/(N+D) and –100dB THD (Typ)

n Power Dissipation: 220mW (Typ)

n No Pipeline Delay

n No Missing Codes over Temperature

n Nap (7mW) and Sleep (10μW) Shutdown Modes

n Operates with Internal 15ppm/°C Reference

or External Reference

n True Differential Inputs Reject Common Mode Noise

n 5MHz Full Power Bandwidth

n ±2.5V Bipolar Input Range

n 36-Pin SSOP Package

n Telecommunications

n Digital Signal Processing

n Multiplexed Data Acquisition Systems

n High Speed Data Acquisition

n Spectrum Analysis

n Imaging Systems L, LTC and LT are registered trademarks of Linear Technology Corporation.

2.2μF 10μF 10μF

10Ω

47μF

DIFFERENTIAL

ANALOG INPUT

±2.5V

REFCOMP

4.375V

CONTROL

LOGIC

AND

TIMING

B15 TO B0

16-BIT

SAMPLING

ADC

–

10μF

5V OR

μP

CONTROL

LINES

D15 TO D0

OUTPUT

BUFFERS 16-BIT

PARALLEL

BUS

11 TO 26

1604 TA01

OGND

OVDD

AIN+

AIN–

SHDN

CONVST

BUSY

7.5k

336 35 10

5V 5V

AVDD AVDD DVDD DGND

VREF

AGND

–5V

VSS

10μF

2.5V

REF

10μF

1.75X

+ +

FREQUENCY (kHz)

AMPLITUDE (dB)

120

1604 TA02

40 80 160

–20

–40

–60

–80

–100

–120

–140 20 60 100 140

fSAMPLE = 333kHz

fIN = 100kHz

SINAD = 89dB

THD = –96dB

LTC1604

1604fa

PACKAGE/ORDER INFORMATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ..................................................6V

Negative Supply Voltage (VSS) ..................................–6V

Total Supply Voltage (VDD to VSS) ............................12V

Analog Input Voltage

(Note 3) ..........................(VSS – 0.3V) to (VDD + 0.3V)

VREF Voltage (Note 4) ................... –0.3V to (VDD + 0.3V)

REFCOMP Voltage (Note 4) .......... –0.3V to (VDD + 0.3V)

Digital Input Voltage (Note 4) ..................... –0.3V to 10V

Digital Output Voltage .................. –0.3V to (VDD + 0.3V)

Power Dissipation .............................................. 500mW

Operating Temperature Range

LTC1604C ................................................ 0°C to 70°C

LTC1604I ..............................................–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec) ................... 300°C

TOP VIEW

G PACKAGE

36-LEAD PLASTIC SSOP

AVDD

VSS

SHDN

CONV

OVDD

OGND

BUSY

AIN+

AIN–

VREF

REFCOMP

AGND

DVDD

DGND

D15 (MSB)

D14

D13

D12

D11

D10

TJMAX = 125°C, θJA = 95°C/W

ORDER

PART NUMBER

LTC1604CG

LTC1604IG

LTC1604ACG

LTC1604AIG

Consult factory for Military grade parts.

CONVERTER CHARACTERISTICS

ANALOG INPUT

With Internal Reference (Notes 5, 6)

PARAMETER CONDITIONS

LTC1604 LTC1604A

UNITSMIN TYP MAX MIN TYP MAX

Resolution (No Missing Codes) l15 16 16 16 Bits

Integral Linearity Error (Note 7) l±1 ±4 ±0.5 ±2 LSB

Transition Noise (Note 8) 0.7 0.7 LSB

Offset Error (Note 9) l±0.05 ±0.125 ±0.05 ±0.125 %

Offset Tempco (Note 9) 0.5 0.5 ppm/°C

Full-Scale Error Internal Reference

External Reference

±0.125 ±0.25

±0.25

±0.125 ±0.25

±0.25

Full-Scale Tempco IOUT(Reference) = 0, Internal Reference ±15 ±15 ppm/°C

AVDD = DVDD = OVDD = VDD (Notes 1, 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Analog Input Range (Note 2) 4.75 ≤ VDD ≤ 5.25V, –5.25 ≤ VSS ≤ –4.75V,

VSS ≤ (AIN–, AIN+) ≤ AVDD

±2.5 V

IIN Analog Input Leakage Current CS = High l±1 μA

CIN Analog Input Capacitance Between Conversions

During Conversions

tACQ Sample-and-Hold Acquisition Time 380 ns

tAP Sample-and-Hold Acquisition Delay Time –1.5 ns

tjitter Sample-and-Hold Acquisition Delay Time Jitter 5 psRMS

CMRR Analog Input Common Mode Rejection Ratio –2.5V < (AIN– = AIN+) < 2.5V 68 dB

LTC1604

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DYNAMIC ACCURACY

(Note 5)

SYMBOL PARAMETER CONDITIONS

LTC1604 LTC1604A

UNITSMIN TYP MAX MIN TYP MAX

S/N Signal-to-Noise Ratio 5kHz Input Signal

100kHz Input Signal

l90

87 90

S/(N + D) Signal-to-(Noise + Distortion) Ratio 5kHz Input Signal

100kHz Input Signal (Note 10) l

89 84

THD Total Harmonic Distortion

Up to 5th Harmonic

5kHz Input Signal

100kHz Input Signal l

–100

–94

–100

–94 –88

SFDR Spurious Free Dynamic Range 100kHz Input Signal 96 96 dB

IMD Intermodulation Distortion fIN1 = 29.37kHz, fIN2 = 32.446kHz –88 –88 dB

Full Power Bandwidth 5 5 MHz

Full Linear Bandwidth (S/(N + D) ≥ 84dB 350 350 kHz

INTERNAL REFERENCE CHARACTERISTICS

DIGITAL INPUTS AND DIGITAL OUTPUTS

PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 2.475 2.500 2.515 V

VREF Output Tempco IOUT = 0 ±15 ppm/°C

VREF Line Regulation 4.75 ≤ VDD ≤ 5.25V

–5.25V ≤ VSS ≤ –4.75V

0.01

LSB/V

VREF Output Resistance 0 ≤ |IOUT| ≤ 1mA 7.5 kΩ

REFCOMP Output Voltage IOUT = 0 4.375 V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VDD = 5.25V l2.4 V

VIL Low Level Input Voltage VDD = 4.75V l0.8 V

IIN Digital Input Current VIN = 0V to VDD l±10 μA

CIN Digital Input Capacitance 5pF

VOH High Level Output Voltage VDD = 4.75V, IOUT = –10μA

VDD = 4.75V, IOUT = –400μA l4.0

4.5 V

VOL Low Level Output Voltage VDD = 4.75V, IOUT = 160μA

VDD = 4.75V, IOUT = 1.6mA l

0.05

0.10 0.4

IOZ Hi-Z Output Leakage D15 to D0 VOUT = 0V to VDD, CS High l±10 μA

COZ Hi-Z Output Capacitance D15 to D0 CS High (Note 11) l15 pF

ISOURCE Output Source Current VOUT = 0V –10 mA

ISINK Output Sink Current VOUT = VDD 10 mA

LTC1604

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POWER REQUIREMENTS

TIMING CHARACTERISTICS

(Note 5)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Positive Supply Voltage (Notes 12, 13) 4.75 5.25 V

VSS Negative Supply Voltage (Note 12) –4.75 –5.25 V

IDD Positive Supply Current

Nap Mode

Sleep Mode

CS = RD = 0V

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

l18

1.5

2.4

100

μA

ISS Negative Supply Current

Nap Mode

Sleep Mode

CS = RD = 0V

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

l26

100

μA

PDPower Dissipation

Nap Mode

Sleep Mode

CS = RD = 0V

CS = 0V, SHDN = 0V

CS = 5V, SHDN = 0V

l220

7.5

0.01

350

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL(MAX) Maximum Sampling Frequency l333 kHz

tCONV Conversion Time l1.5 2.45 2.8 μs

tACQ Acquisition Time (Note 11) l480 ns

tACQ+CONV Throughput Time (Acquisition + Conversion) l3μs

t1CS to RD Setup Time (Notes 11, 12) l0ns

t2CS↓ to CONVST↓ Setup Time (Notes 11, 12) l10 ns

t3SHDN↓ to CS↑ Setup Time (Notes 11, 12) l10 ns

t4SHDN↑ to CONVST↓ Wake-Up Time CS = Low (Note 12) 400 ns

t5CONVST Low Time (Note 12) l40 ns

t6CONVST to BUSY Delay CL = 25pF

t7Data Ready Before BUSY↑

l32

60 ns

t8Delay Between Conversions (Note 12) l200 ns

t9Wait Time RD↓ After BUSY↑ (Note 12) l–5 ns

t10 Data Access Time After RD↓CL = 25pF

40 50

CL = 100pF

45 60

t11 Bus Relinquish Time

LTC1604C

LTC1604I

50 60

t12 RD Low Time (Note 12) lt10 ns

t13 CONVST High Time (Note 12) l40 ns

t14 Aperture Delay of Sample-and-Hold 2 ns

LTC1604

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TIMING CHARACTERISTICS

(Note 5)

The l denotes specifications that apply over the full operating temperature

range.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND, OGND

and AGND wired together unless otherwise noted.

Note 3: When these pin voltages are taken below VSS or above VDD, they

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below VSS, they will be clamped

by internal diodes. This product can handle input currents greater than

100mA below VSS without latchup. These pins are not clamped to VDD.

Note 5: VDD = 5V, VSS = –5V, fSMPL = 333kHz, and tr = tf = 5ns unless

otherwise specified.

Note 6: Linearity, offset and full-scale specification apply for a single-

ended AIN+ input with AIN– grounded.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Typical RMS noise at the code transitions. See Figure 17 for

histogram.

Note 9: Bipolar offset is the offset voltage measured from –0.5LSB when

the output code flickers between 0000 0000 0000 0000 and 1111 1111

1111 1111.

Note 10: Signal-to-Noise Ratio (SNR) is measured at 5kHz and distortion

is measured at 100kHz. These results are used to calculate Signal-to-Nosie

Plus Distortion (SINAD).

Note 11: Guaranteed by design, not subject to test.

Note 12: Recommended operating conditions.

Note 13: The falling CONVST edge starts a conversion. If CONVST returns

high at a critical point during the conversion it can create small errors. For

best performance ensure that CONVST returns high either within 250ns

after conversion start or after BUSY rises.

TYPICAL PERFORMANCE CHARACTERISTICS

Integral Nonlinearity vs

Output Code

Signal-to-Noise Ratio vs

Input Frequency

Differential Nonlinearity vs

Output Code

Distortion vs Input Frequency

S/(N + D) vs Input Frequency

and Amplitude

Spurious-Free Dynamic Range

vs Input Frequency

CODE

INL (LSB)

–32768 –16384 0 16384 32767

1604 G11

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

CODE

–32768 –16384 16384 32767

DNL (LSB)

1604 G10

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0FREQUENCY (Hz)

SINAD (dB)

100

010k 100k 1M

1604 G01

VIN = 0dB

VIN = –20dB

VIN = –40dB

FREQUENCY (Hz)

100

SIGNAL-TO-NOISE RATIO (dB)

1604 G03

1k 10k 100k 1M

INPUT FREQUENCY (Hz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

1604 G04

1k 10k 100k 1M

THD

3RD

2ND

INPUT FREQUENCY (Hz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

SPURIOUS-FREE DYNAMIC RANGE (dB)

1604 G05

1k 10k 100k 1M

LTC1604

1604fa

TYPICAL PERFORMANCE CHARACTERISTICS

Intermodulaton Distortion

Power Supply Feedthrough vs

Ripple Frequency

Input Common Mode Rejection

vs Input Frequency

FREQUENCY (kHz)

020

AMPLITUDE (dB)

80 100

–20

–40

–60

–80

–100

–120

–140

1604 G06

40 60 160120 140

fSAMPLE = 333kHz

fIN1 = 29.3kHz

fIN2 = 32.4kHz

INPUT FREQUENCY (Hz)

AMPLITUDE OF POWER SUPPLY

FEEDTHROUGH (dB)

–20

–40

–60

–80

–100

–120 10k 100k 1M

1604 G07

fSAMPLE = 333kHz

VRIPPLE = 10mV

VSS

AVDD

INPUT FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

10k 100k

1604G09

PIN FUNCTIONS

AIN+ (Pin 1): Positive Analog Input. The ADC converts the

difference voltage between AIN+ and AIN– with a differ-

ential range of ±2.5V. AIN+ has a ±2.5V input range when

AIN– is grounded.

AIN– (Pin 2): Negative Analog Input. Can be grounded, tied

to a DC voltage or driven differentially with AIN+.

VREF (Pin 3): 2.5V Reference Output. Bypass to AGND with

2.2μF tantalum in parallel with 0.1μF ceramic.

REFCOMP (Pin 4): 4.375 Reference Compensation Pin.

Bypass to AGND with 47μF tantalum in parallel with 0.1μF

ceramic.

AGND (Pins 5 to 8): Analog Grounds. Tie to analog ground

plane.

DVDD (Pin 9): 5V Digital Power Supply. Bypass to DGND

with 10μF tantalum in parallel with 0.1μF ceramic.

DGND (Pin 10): Digital Ground for Internal Logic. Tie to

analog ground plane.

D15 to D0 (Pins 11 to 26): Three-State Data Outputs. D15

is the Most Significant Bit.

BUSY (Pin 27): The BUSY output shows the converter

status. It is low when a conversion is in progress. Data is

valid on the rising edge of BUSY.

OGND (Pin 28): Digital Ground for Output Drivers.

OVDD (Pin 29): Digital Power Supply for Output Drivers.

Bypass to OGND with 10μF tantalum in parallel with 0.1μF

ceramic.

RD (Pin 30): Read Input. A logic low enables the output

drivers when CS is low.

CONVST (Pin 31): Conversion Start Signal. This active

low signal starts a conversion on its falling edge when

CS is low.

CS (Pin 32): The Chip Select Input. Must be low for the

ADC to recognize CONVST and RD inputs.

SHDN (Pin 33): Power Shutdown. Drive this pin low with

CS low for nap mode. Drive this pin low with CS high for

sleep mode.

VSS (Pin 34): –5V Negative Supply. Bypass to AGND with

10μF tantalum in parallel with 0.1μF ceramic.

AVDD (Pin 35): 5V Analog Power Supply. Bypass to AGND

with 10μF tantalum in parallel with 0.1μF ceramic.

AVDD (Pin 36): 5V Analog Power Supply. Bypass to AGND

with 10μF tantalum in parallel with 0.1μF ceramic and

connect this pin to Pin 35 with a 10Ω resistor.

LTC1604

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FUNCTIONAL BLOCK DIAGRAM

TEST CIRCUIT

2.2μF 10μF 10μF

10Ω

47μF

DIFFERENTIAL

ANALOG INPUT

±2.5V

REFCOMP

4.375V

CONTROL

LOGIC

AND

TIMING

B15 TO B0

16-BIT

SAMPLING

ADC

–

10μF

5V OR

μP

CONTROL

LINES

D15 TO D0

OUTPUT

BUFFERS 16-BIT

PARALLEL

BUS

11 TO 26

1604 TA01

OGND

OVDD

AIN+

AIN–

SHDN

CONVST

BUSY

7.5k

336 35 10

5V 5V

AVDD AVDD DVDD DGND

VREF

AGND

–5V

VSS

10μF

2.5V

REF

10μF

1.75X

+ +

Load Circuits for Access Timing Load Circuits for Output Float Delay

(A) Hi-Z TO VOH AND VOL TO VOH

DNDN

(B) Hi-Z TO VOL AND VOH TO VOL

1604 TC01

(A) VOH TO Hi-Z

DNDN

(B) VOL TO Hi-Z

1604 TC02

LTC1604

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CONVERSION DETAILS

The LTC1604 uses a successive approximation algorithm

and internal sample-and-hold circuit to convert an analog

signal to a 16-bit parallel output. The ADC is complete with

a sample-and-hold, a precision reference and an internal

clock. The control logic provides easy interface to micro-

processors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) resets. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 16-bit

capacitive DAC output is sequenced by the SAR from the

Most Significant Bit (MSB) to the Least Significant Bit

(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are

acquired during the acquire phase and the comparator

offset is nulled by the zeroing switches. In this acquire

phase, a duration of 480ns will provide enough time for the

sample-and-hold capacitors to acquire the analog signal.

During the convert phase the comparator zeroing switches

open, putting the comparator into compare mode. The

input switches connect the CSMPL capacitors to ground,

transferring the differential analog input charge onto the

APPLICATIONS INFORMATION

summing junctions. This input charge is successively

compared with the binary-weighted charges supplied by

the differential capacitive DAC. Bit decisions are made by

the high speed comparator. At the end of a conversion, the

differential DAC output balances the AIN+ and AIN– input

charges. The SAR contents (a 16-bit data word) which

represent the difference of AIN+ and AIN– are loaded into

the 16-bit output latches.

DIGITAL INTERFACE

The A/D converter is designed to interface with micropro-

cessors as a memory mapped device. The CS and RD

control inputs are common to all peripheral memory

interfacing. A separate CONVST is used to initiate a con-

version.

Internal Clock

The A/D converter has an internal clock that runs the A/D

conversion. The internal clock is factory trimmed to achieve

a typical conversion time of 2.45μs and a maximum

conversion time of 2.8μs over the full temperature range.

No external adjustments are required. The guaranteed

maximum acquisition time is 480ns. In addition, a through-

put time (acquisition + conversion) of 3μs and a minimum

sampling rate of 333ksps are guaranteed.

3V Input/Output Compatible

The LTC1604 operates on ±5V supplies, which makes the

device easy to interface to 5V digital systems. This device

can also talk to 3V digital systems: the digital input pins

(SHDN, CS, CONVST and RD) of the LTC1604 recognize

3V or 5V inputs. The LTC1604 has a dedicated output

supply pin (OVDD) that controls the output swings of the

digital output pins (D0 to D15, BUSY) and allows the part

to talk to either 3V or 5V digital systems. The output is

two’s complement binary.

Power Shutdown

The LTC1604 provides two power shutdown modes, Nap

and Sleep, to save power during inactive periods. The

Nap mode reduces the power by 95% and leaves only the

digital logic and reference powered up. The wake-up

time from Nap to active is 200ns. In Sleep mode all bias

Figure 1. Simplified Block Diagram

–

COMP

AIN+

CSMPL

HOLD

SAMPLE

AIN–

CSMPL

+CDAC

+VDAC

–CDAC

–VDAC

HOLD

SAMPLE

HOLD

SAR OUTPUT

LATCHES

16 D15

1604 F01

ZEROING SWITCHES

LTC1604

1604fa

APPLICATIONS INFORMATION

currents are shut down and only leakage current remains

(about 1μA). Wake-up time from Sleep mode is much

slower since the reference circuit must power up and

settle. Sleep mode wake-up time is dependent on the value

of the capacitor connected to the REFCOMP (Pin 4). The

wake-up time is 160ms with the recommended 47μF

capacitor.

Shutdown is controlled by Pin 33 (SHDN). The ADC is in

shutdown when SHDN is low. The shutdown mode is

selected with Pin 32 (CS). When SHDN is low, CS low

selects nap and CS high selects sleep.

Timing and Control

Conversion start and data read operations are controlled

by three digital inputs: CONVST, CS and RD. A falling edge

applied to the CONVST pin will start a conversion after the

ADC has been selected (i.e., CS is low). Once initiated,

it cannot be restarted until the conversion is complete.

Converter status is indicated by the BUSY output. BUSY

is low during a conversion.

We recommend using a narrow logic low or narrow logic

high CONVST pulse to start a conversion as shown in

Figures 5 and 6. A narrow low or high CONVST pulse

prevents the rising edge of the CONVST pulse from upset-

ting the critical bit decisions during the conversion time.

Figure 4 shows the change of the differential nonlinearity

error versus the low time of the CONVST pulse. As shown,

if CONVST returns high early in the conversion (e.g.,

CONVST low time <500ns), accuracy is unaffected.

Similarly, if CONVST returns high after the conversion is

over(e.g., CONVST low time >tCONV), accuracy is unaf-

fected. For best results, keep t5 less than 500ns or greater

than tCONV.

Figures 5 through 9 show several different modes of op-

eration. In modes 1a and 1b (Figures 5 and 6), CS and RD

are both tied low. The falling edge of CONVST starts the

conversion. The data outputs are always enabled and data

can be latched with the BUSY rising edge. Mode 1a shows

operation with a narrow logic low CONVST pulse. Mode 1b

shows a narrow logic high CONVST pulse.

In mode 2 (Figure 7) CS is tied low. The falling edge of

CONVST signal starts the conversion. Data outputs are

SHDN

1604 F02a

SHDN

CONVST

1604 F02b

CONVST

1604 F03

CHANGE IN DNL (LSB)

2800

1604 F04

400 800 16001200 2000 2400

CONVST LOW TIME, t5 (ns)

tCONV tACQ

Figure 2a. Nap Mode to Sleep Mode Timing

Figure 2b. SHDN to CONVST Wake-Up Timing

Figure 3. CS top CONVST Setup Timing

Figure 4. Change in DNL vs CONVST Low Time. Be Sure the

CONVST Pulse Returns High Early in the Conversion or After

the End of Conversion

LTC1604

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Figure 5. Mode 1a. CONVST Starts a Conversion. Data Outputs Always Enabled

Figure 6. Mode 1b. CONVST Starts a Conversion. Data Outputs Always Enabled

Figure 7. Mode 2. CONVST Starts a Conversion. Data is Read by RD

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

DATA (N – 1)

D15 TO D0

CONVST

CS = RD = 0

BUSY

1604 F05

tCONV

t6t8

DATA

(CONVST = )

DATA (N – 1)

D15 TO D0

CONVST

BUSY

1604 F06

tCONV

t13

CS = RD = 0

DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

DATA

CONVST

CS = 0

BUSY

1604 F07

tCONV t8

t13

t9t12

DATA N

D15 TO D0

t11

t10

DATA

(CONVST = )

APPLICATIONS INFORMATION

LTC1604

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Figure 8. Mode 2. Slow Memory Mode Timing

Figure 9. ROM Mode Timing

APPLICATIONS INFORMATION

RD = CONVST

CS = 0

BUSY

1604 F08

tCONV

DATA (N – 1)

D5 TO D0

DATA DATA N

D15 TO D0

DATA (N + 1)

D15 TO D0

DATA N

D15 TO D0

t11

t10 t7

RD = CONVST

BUSY

CS = 0

1604 F09

tCONV

DATA (N – 1)

D15 TO D0

DATA DATA N

D15 TO D0

t10

t11

in three-state until read by the MPU with the RD signal.

Mode 2 can be used for operation with a shared data bus.

In slow memory and ROM modes (Figures 8 and 9) CS

is tied low and CONVST and RD are tied together. The

MPU starts the conversion and reads the output with the

combined CONVST-RD signal. Conversions are started

by the MPU or DSP (no external sample clock is needed).

In slow memory mode the processor applies a logic low

to RD (= CONVST), starting the conversion. BUSY goes

low, forcing the processor into a wait state. The previous

conversion result appears on the data outputs. When the

conversion is complete, the new conversion results ap-

pear on the data outputs; BUSY goes high, releasing the

processor and the processor takes RD (=CONVST) back

high and reads the new conversion data.

In ROM mode, the processor takes RD (=CONVST) low,

starting a conversion and reading the previous conversion

result. After the conversion is complete, the processor

can read the new result and initiate another conversion.

DIFFERENTIAL ANALOG INPUTS

Driving the Analog Inputs

The differential analog inputs of the LTC1604 are easy

to drive. The inputs may be driven differentially or as a

single-ended input (i.e., the AIN– input is grounded). The

AIN+ and AIN– inputs are sampled at the same instant.

Any unwanted signal that is common mode to both in-

puts will be reduced by the common mode rejection of

the sample-and-hold circuit. The inputs draw only one

small current spike while charging the sample-and-hold

capacitors at the end of conversion. During conversion

the analog inputs draw only a small leakage current. If the

source impedance of the driving circuit is low, then the

LTC1604 inputs can be driven directly. As source imped-

ance increases so will acquisition time (see Figure 10). For

minimum acquisition time with high source impedance, a

buffer amplifier should be used. The only requirement is

that the amplifier driving the analog input(s) must settle

after the small current spike before the next conversion

LTC1604

1604fa

starts (settling time must be 200ns for full throughput

rate).

Choosing an Input Amplifier

Choosing an input amplifier is easy if a few requirements

are taken into consideration. First, to limit the magnitude

of the voltage spike seen by the amplifier from charging

the sampling capacitor, choose an amplifier that has a low

output impedance (<100Ω) at the closed-loop band-width

frequency. For example, if an amplifier is used in a gain

of +1 and has a unity-gain bandwidth of 50MHz, then the

output impedance at 50MHz should be less than 100Ω.

The second requirement is that the closed-loop bandwidth

must be greater than 15MHz to ensure adequate small-

signal settling for full throughput rate. If slower op amps

are used, more settling time can be provided by increasing

the time between conversions.

The best choice for an op amp to drive the LTC1604 will

depend on the application. Generally applications fall into

two categories: AC applications where dynamic specifica-

tions are most critical and time domain applications where

DC accuracy and settling time are most critical. The follow-

ing list is a summary of the op amps that are suitable for

driving the LTC1604. More detailed information is available

in the Linear Technology databooks, the LinearView™

CD-ROM and on our web site at: www.linear-tech. com.

LT ®1007: Low Noise Precision Amplifier. 2.7mA supply

current, ±5V to ±15V supplies, gain bandwidth product

8MHz, DC applications.

LT1097: Low Cost, Low Power Precision Amplifier. 300μA

supply current, ±5V to ±15V supplies, gain bandwidth

product 0.7MHz, DC applications.

LT1227: 140MHz Video Current Feedback Amplifier. 10mA

supply current, ±5V to ±15V supplies, low noise and low

distortion.

LT1360: 37MHz Voltage Feedback Amplifier. 3.8mA supply

current, ±5V to ±15V supplies, good AC/DC specs.

LT1363: 50MHz Voltage Feedback Amplifier. 6.3mA sup-

ply current, good AC/DC specs.

LT1364/LT1365: Dual and Quad 50MHz Voltage Feedback

Amplifiers. 6.3mA supply current per amplifier, good AC/

DC specs.

Input Filtering

The noise and the distortion of the input amplifier and

other circuitry must be considered since they will add to

the LTC1604 noise and distortion. The small-signal band-

width of the sample-and-hold circuit is 15MHz. Any noise

or distortion products that are present at the analog inputs

will be summed over this entire bandwidth. Noisy input

circuitry should be filtered prior to the analog inputs to

minimize noise. A simple 1-pole RC filter is sufficient for

many applications. For example, Figure 11 shows a 3000pF

capacitor from AIN+ to ground and a 100Ω source resistor to

limit the input bandwidth to 530kHz. The 3000pF capacitor

also acts as a charge reservoir for the input sample-and-hold

and isolates the ADC input from sampling glitch sensitive

circuitry. High quality capacitors and resistors should be

used since these components can add distortion. NPO and

silver mica type dielectric capacitors have excellent linearity.

Carbon surface mount resistors can also generate distor-

tion from self heating and from damage that may occur

during soldering. Metal film surface mount resistors are

much less susceptible to both problems.

APPLICATIONS INFORMATION

SOURCE RESISTANCE (Ω)

1 10 100 1k 10k

ACQUISITION TIME (μs)

0.1

0.01

1604 F10

Figure 10. tACQ vs Source Resistance

LinearView is a trademark of Linear Technology Corporation.

LTC1604

1604fa

APPLICATIONS INFORMATION

Input Range

The ±2.5V input range of the LTC1604 is optimized for

low noise and low distortion. Most op amps also perform

well over this same range, allowing direct coupling to

the analog inputs and eliminating the need for special

translation circuitry.

Some applications may require other input ranges. The

LTC1604 differential inputs and reference circuitry can

accommodate other input ranges often with little or no

additional circuitry. The following sections describe the

reference and input circuitry and how they affect the input

range.

Internal Reference

The LTC1604 has an on-chip, temperature compensated,

curvature corrected, bandgap reference that is factory

trimmed to 2.500V. It is connected internally to a reference

amplifier and is available at VREF (Pin 3) (see Figure 12a).

A 7.5k resistor is in series with the output so that it can be

easily overdriven by an external reference or other circuitry

(see Figure 12b). The reference amplifier gains the volt-

age at the VREF pin by 1.75 to create the required internal

reference voltage. This provides buffering between the

VREF pin and the high speed capacitive DAC. The refer-

ence amplifier compensation pin (REFCOMP, Pin 4) must

be bypassed with a capacitor to ground. The reference

amplifier is stable with capacitors of 22μF or greater.

For the best noise performance a 47μF ceramic or 47μF

tantalum in parallel with a 0.1μF ceramic is recommended.

The VREF pin can be driven with a DAC or other means

shown in Figure 13. This is useful in applications where

the peak input signal amplitude may vary. The input span

of the ADC can then be adjusted to match the peak input

signal, maximizing the signal-to-noise ratio. The filtering

of the internal LTC1604 reference amplifier will limit the

bandwidth and settling time of this circuit. A settling time

of 20ms should be allowed for after a reference adjustment.

Differential Inputs

The LTC1604 has a unique differential sample-and-hold

circuit that allows rail-to-rail inputs. The ADC will always

convert the difference of AIN+ – AIN– independent of the

common mode voltage (see Figure 15a). The common

mode rejection holds up to extremely high frequencies

(see Figure 14a). The only requirement is that both inputs

LTC1604

AIN+

AIN–

VREF

REFCOMP

AGND

1604 F11

47μF

3000pF

100Ω

ANALOG INPUT

12k

16k

REFERENCE

AMP

47μF

REFCOMP

AGND

VREF

7.5k

2.500V

4.375V

LTC1604

1604 F12a

BANDGAP

REFERENCE

0.1μF10μF

ANALOG

INPUT

1604 F12b

LT1019A-2.5

VOUT

VIN

5V AIN+

AIN–

VREF

LTC1604

AGND

REFCOMP

Figure 11. RC Input Filter

Figure 12a. LTC1604 Reference Circuit

Figure 12b. Using the LT1019-2.5 as an External Reference

LTC1604

1604fa

can not exceed the AVDD or VSS power supply voltages.

Integral nonlinearity errors (INL) and differential nonlin-

earity errors (DNL) are independent of the common

mode voltage, however, the bipolar zero error (BZE) will

vary. The change in BZE is typically less than 0.1% of the

common mode voltage. Dynamic performance is also

affected by the common mode voltage. THD will degrade

as the inputs approach either power supply rail, from 96dB

with a common mode of 0V to 86dB with a common mode

of 2.5V or –2.5V.

Differential inputs allow greater flexibility for accepting

different input ranges. Figure 14b shows a circuit that

converts a 0V to 5V analog input signal with only an

additional buffer that is not in the signal path.

APPLICATIONS INFORMATION

LTC1604

AIN+

ANALOG INPUT

2V TO 2.7V

DIFFERENTIAL AIN–

VREF

REFCOMP

AGND

1604 F13

47μF

LTC1450 2V TO 2.7V

INPUT FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

10k 100k

1604 G14a

LTC1604

AIN+

AIN–

VREF

0V TO

±2.5V

REFCOMP

AGND

1604 F14b

10μF

ANALOG INPUT

–

1604 F15a

011...111

011...110

000...001

000...000

111...111

111...110

100...001

100...000

FS – 1LSB

–(FS – 1LSB)

INPUT VOLTAGE (AIN+ – AIN–)

OUTPUT CODE

Figure 13. Driving VREF with a DAC Figure 14b. Selectable 0V to 5V or ±2.5V Input Range

Figure 15a. LTC1604 Transfer Characteristics

Figure 14a. CMRR vs Input Frequency

Full-Scale and Offset Adjustment

Figure 15a shows the ideal input/output characteristics

for the LTC1604. The code transitions occur midway

between successive integer LSB values (i.e., –FS +

0.5LSB, –FS + 1.5LSB, –FS + 2.5LSB,... FS – 1.5LSB,

FS – 0.5LSB). The output is two’s complement binary with

1LSB = FS – (–FS)/65536 = 5V/65536 = 76.3μV.

In applications where absolute accuracy is important,

offset and full-scale errors can be adjusted to zero. Offset

error must be adjusted before full-scale error. Figure 15b

shows the extra components required for full-scale er-

ror adjustment. Zero offset is achieved by adjusting the

offset applied to the AIN– input. For zero offset error apply

LTC1604

1604fa

APPLICATIONS INFORMATION

Figure 15b. Offset and Full-Scale Adjust Circuit

–38μV (i.e., –0.5LSB) at AIN+ and adjust the offset at the

AIN– input until the output code flickers between 0000

0000 0000 0000 and 1111 1111 1111 1111. For full-scale

adjustment, an input voltage of 2.499886V (FS/2 – 1.5LSBs)

is applied to AIN+ and R2 is adjusted until the output code

flickers between 0111 1111 1111 1110 and 0111 1111

1111 1111.

BOARD LAYOUT AND GROUNDING

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1604, a printed circuit board

with ground plane is required. Layout should ensure that

digital and analog signal lines are separated as much as

possible. Particular care should be taken not to run any

digital track alongside an analog signal track or underneath

the ADC. The analog input should be screened by AGND.

An analog ground plane separate from the logic system

ground should be established under and around the ADC.

Pin 5 to Pin 8 (AGNDs), Pin 10 (ADC’s DGND) and all other

analog grounds should be connected to this single analog

ground point. The REFCOMP bypass capacitor and the

DVDD bypass capacitor should also be connected to this

ANALOG

INPUT

1604 F15b

100Ω

50k

24k

–5V

24k

50k

47k

0.1μF

47μF

AIN+

AIN–

VREF

REFCOMP

AGND

LTC1604

analog ground plane. No other digital grounds should be

connected to this analog ground plane. Low impedance

analog and digital power supply common returns are

essential to low noise operation of the ADC and the foil

width for these tracks should be as wide as possible. In

applications where the ADC data outputs and control

signals are connected to a continuously active micropro-

cessor bus, it is possible to get errors in the conversion

results. These errors are due to feedthrough from the

microprocessor to the successive approximation com-

parator. The problem can be eliminated by forcing the

microprocessor into a WAIT state during conversion or by

using three-state buffers to isolate the ADC data bus. The

traces connecting the pins and bypass capacitors must

be kept short and should be made as wide as possible.

The LTC1604 has differential inputs to minimize noise

coupling. Common mode noise on the AIN+ and AIN– leads

will be rejected by the input CMRR. The AIN– input can be

used as a ground sense for the AIN+ input; the LTC1604

will hold and convert the difference voltage between AIN+

and AIN–. The leads to AIN+ (Pin 1) and AIN– (Pin 2) should

be kept as short as possible. In applications where this is

not possible, the AIN+ and AIN– traces should be run side

by side to equalize coupling.

SUPPLY BYPASSING

High quality, low series resistance ceramic, 10μF or 47μF

bypass capacitors should be used at the VDD and REFCOMP

pins as shown in Figure 16 and in the Typical Application

on the first page of this data sheet. Surface mount ceramic

capacitors such as Murata GRM235Y5V106Z016 provide

excellent bypassing in a small board space. Alternatively,

10μF tantalum capacitors in parallel with 0.1μF ceramic

capacitors can be used. Bypass capacitors must be located

as close to the pins as possible. The traces connecting the

pins and the bypass capacitors must be kept short and

should be made as wide as possible.

LTC1604

1604fa

APPLICATIONS INFORMATION

1604 F16

AIN+

VSS OVDD

DGNDAVDD

LTC1604 DIGITAL

SYSTEM

ANALOG

INPUT

CIRCUITRY

AGND

5 TO 8

234 29

DVDD OGND

2810

REFCOMP

47μF

VREF

2.2μF

AIN–

10μF

AVDD

10μF 10μF

–9

10μF

CODE

–5 –4 –3 –2 –1 0 1 2 3 4 5

COUNT

2500

2000

1500

1000

500

1604 F17

FREQUENCY (kHz)

AMPLITUDE (dB)

–60

–40

–20

1604 F18a

–80

–100

20 40 80 100 120 140 160

–120

–140

0fSAMPLE = 333kHz

fIN = 4.959kHz

SINAD = 90.2dB

THD = –103.2dB

Figure 16. Power Supply Grounding Practice

Figure 17. Histogram for 4096 Conversions

Figure 18a. This FFT of the LTC1604’s Conversion of a

Full-Scale 5kHz Sine Wave Shows Outstanding Response

with a Very Low Noise Floor When Sampling at 333ksps

DC PERFORMANCE

The noise of an ADC can be evaluated in two ways: signal-

to-noise raio (SNR) in frequency domain and histogram

in time domain. The LTC1604 excels in both. Figure 18a

demonstrates that the LTC1604 has an SNR of over 90dB

in frequency domain. The noise in the time domain

histogram is the transition noise associated with a high

resolution ADC which can be measured with a fixed DC

signal applied to the input of the ADC. The resulting output

codes are collected over a large number of conversions.

The shape of the distribution of codes will give an indica-

tion of the magnitude of the transition noise. In Figure 17

the distribution of output codes is shown for a DC input

that has been digitized 4096 times. The distribution is

Gaussian and the RMS code transition noise is about

0.66LSB. This corresponds to a noise level of 90.9dB

relative to full scale. Adding to that the theoretical 98dB

of quantization error for 16-bit ADC, the resultant corre-

sponds to an SNR level of 90.1dB which correlates very

well to the frequency domain measurements in DYNAMIC

PERFORMANCE section.

DYNAMIC PERFORMANCE

The LTC1604 has excellent high speed sampling capability.

Fast fourier transform (FFT) test techniques are used to test

the ADC’s frequency response, distortions and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. Figures 18a and 18b show

typical LTC1604 FFT plots.

LTC1604

1604fa

APPLICATIONS INFORMATION

Figure 18b. Even with Inputs at 100kHz, the LTC1604’s

Dynamic Linearity Remains Robust

Figure 19. Effective Bits and Signal/(Noise + Distortion)

vs Input Frequency

Figure 20. Distortion vs Input Frequency

Signal-to-Noise Ratio

The signal-to-noise plus distortion ratio [S/(N + D)] is the

ratio between the RMS amplitude of the fundamental input

frequency to the RMS amplitude of all other frequency

components at the A/D output. The output is band limited

to frequencies from above DC and below half the sampling

frequency. Figure 18a shows a typical spectral content with

a 333kHz sampling rate and a 5kHz input. The dynamic

performance is excellent for input frequencies up to and

beyond the Nyquist limit of 167kHz.

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement

of the resolution of an ADC and is directly related to the

S/(N + D) by the equation:

N = [S/(N + D) – 1.76]/6.02

where N is the effective number of bits of resolution and

S/(N + D) is expressed in dB. At the maximum sampling

rate of 333kHz the LTC1604 maintains above 14 bits up to

the Nyquist input frequency of 167kHz (refer to Figure 19).

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of all harmonics of the input signal to the fundamental

itself. The out-of-band harmonics alias into the frequency

band between DC and half the sampling frequency. THD

is expressed as:

THD=20Log V22+V32+V42+...Vn2

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through Vn are the amplitudes of the

second through nth harmonics. THD vs Input Frequency

is shown in Figure 20. The LTC1604 has good distortion

performance up to the Nyquist frequency and beyond.

FREQUENCY (kHz)

AMPLITUDE (dB)

–60

–40

–20

1604 F18b

–80

–100

–120

–140

06020 40 80 100 120 140 160

fSAMPLE = 333kHz

fIN = 97.152kHz

SINAD = 89dB

THD = –96dB

FREQUENCY (Hz)

EFFECTIVE BITS

SINAD (dB)

10k 100k 1M

1604 F19

INPUT FREQUENCY (Hz)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

AMPLITUDE (dB BELOW THE FUNDAMENTAL)

1604 G04

1k 10k 100k 1M

THD

3RD

2ND

LTC1604

1604fa

APPLICATIONS INFORMATION

Intermodulation Distortion

If the ADC input signal consists of more than one spectral

component, the ADC transfer function nonlinearity can

produce intermodulation distortion (IMD) in addition to

THD. IMD is the change in one sinusoidal input caused

by the presence of another sinusoidal input at a different

frequency.

If two pure sine waves of frequencies fa and fb are applied

to the ADC input, nonlinearities in the ADC transfer function

can create distortion products at the sum and difference

frequencies of mfa ±nfb, where m and n = 0, 1, 2, 3,

etc. For example, the 2nd order IMD terms include

(fa – fb). If the two input sine waves are equal in magnitude,

the value (in decibels) of the 2nd order IMD products can

be expressed by the following formula:

IMD fa±fb

()

=20Log Amplitude at (fa ± fb)

Amplitude at fa

Peak Harmonic or Spurious Noise

The peak harmonic or spurious noise is the largest spectral

component excluding the input signal and DC. This value

is expressed in decibels relative to the RMS value of a

full-scale input signal.

Full-Power and Full-Linear Bandwidth

The full-power bandwidth is that input frequency at which

the amplitude of the reconstructed fundamental is reduced

by 3dB for a full-scale input signal.

The full-linear bandwidth is the input frequency at which

the S/(N + D) has dropped to 84dB (13.66 effective bits).

The LTC1604 has been designed to optimize input band-

width, allowing the ADC to undersample input signals with

frequencies above the converter’s Nyquist Frequency. The

noise floor stays very low at high frequencies; S/(N + D)

becomes dominated by distortion at frequencies far

beyond Nyquist.

FREQUENCY (kHz)

020

AMPLITUDE (dB)

80 100

–20

–40

–60

–80

–100

–120

–140

1604 G06

40 60 160120 140

fSAMPLE = 333kHz

fIN1 = 29.3kHz

fIN2 = 32.4kHz

Figure 21. Intermodulation Distortion Plot

LTC1604

1604fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

Dimensions in inches (millimeters) unless otherwise noted.

G36 SSOP 1196

0.005 – 0.009

(0.13 – 0.22)

0° – 8°

0.022 – 0.037

(0.55 – 0.95)

0.205 – 0.212**

(5.20 – 5.38)

0.301 – 0.311

(7.65 – 7.90)

12345678 9 10 11 12 14 15 16 17 1813

0.499 – 0.509*

(12.67 – 12.93)

2526 22 21 20 19232427282930313233343536

0.068 – 0.078

(1.73 – 1.99)

0.002 – 0.008

(0.05 – 0.21)

0.0256

(0.65)

BSC 0.010 – 0.015

(0.25 – 0.38)

DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

G Package

36-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

LTC1604

1604fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

1604a LT/TP 1098 REV A 2K • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

SAMPLING ADCs

PART NUMBER DESCRIPTION COMMENTS

LTC1410 12-Bit, 1.25Msps, ±5V ADC 71.5dB SINAD at Nyquist, 150mW Dissipation

LTC1415 12-Bit, 1.25Msps, Single 5V ADC 55mW Power Dissipation, 72dB SINAD

LTC1418 14-Bit, 200ksps, Single 5V ADC 15mW, Serial/Parallel ±10V

LTC1419 Low Power 14-Bit, 800ksps ADC True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation

LTC1605 16-Bit, 100ksps, Single 5V ADC ±10V Inputs, 55mW, Byte or Parallel I/O

DACs

PART NUMBER DESCRIPTION COMMENTS

LTC1595 16-Bit Serial Multiplying IOUT DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade

LTC1596 16-Bit Serial Multiplying IOUT DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade

LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors

LTC1650 16-Bit Serial VOUT DAC Low Power, Low Gritch, 4-Quadrant Multiplication

Using the LTC1604 and Two LTC1391s as an 8-Channel Differential 16-Bit ADC System

D15 TO D0

VSS

AGNDAGNDAGNDAGND

REFCOMP

4.375V

11 TO 26

1604 TA03

CH7+

CH0+16

LTC1391

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

V+

V–

DOUT

DIN

CLK

GND

CH7–

CH0–1μF

DIN

CLK

–5V

10Ω

2.2μF 10μF 5V 10μF 5V

3536

10μF

–5V

1μF

10μF

3000pF

47μF

AIN+

VREF AVDD AVDD DVDD DGND

OVDD

OGND 28

μP

CONTROL

LINES

5V OR

10μF

SHDN

CONVST

BUSY

AIN–

678

1μF

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

V+

V–

DOUT

DIN

CLK

GND

16-BIT

SAMPLING

ADC

+ +

1.75X 2.5V

REF

CONTROL

LOGIC

AND

TIMING

OUTPUT

BUFFERS 16-BIT

PARALLEL

BUS

7.5k

LTC1604

B15 TO B0

μP

CONTROL

LINES

–