The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
MOS INTEGRATED CIRCUIT
MC-458CB641ES
,
458CB641PS
,
458CB641XS
8M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Document No. E0069N10 (1st edition)
(Previous No. M14015EJ5V0DS00)
Date Published January 2001 CP (K)
Printed in Japan
DATA SHEET
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The MC-458CB641ES, MC-458CB641PS and MC-458CB641XS are 8,388,608 words by 64 bits synchronous
dynamic RAM module (Small Outline DIMM) on which 4 pieces of 128M SDRAM:
µ
PD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 8,388,608 words by 64 bits organization
• Clock frequency and access time from CLK
Part number /CAS latency Clock frequency (MAX.) Access time from CLK (MAX.)
MC-458CB641ES-A80 CL = 3 125 MHz 6 ns
CL = 2 100 MHz 6 ns
MC-458CB641ES-A10 CL = 3 100 MHz 6 ns
CL = 2 77 MHz 7 ns
MC-458CB641PS-A80 CL = 3 125 MHz 6 ns
CL = 2 100 MHz 6 ns
MC-458CB641PS-A10 CL = 3 100 MHz 6 ns
CL = 2 77 MHz 7 ns
MC-458CB641XS-A80 CL = 3 125 MHz 6 ns
CL = 2 100 MHz 6 ns
MC-458CB641XS-A10 CL = 3 100 MHz 6 ns
CL = 2 77 MHz 7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length: 1, 2, 4, 8 and Full Page
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ±0.3 V power supply
Data Sheet E0069N10
2
MC-458CB641ES, 458CB641PS, 458CB641XS
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
Ordering Information
Part number Clock frequency
MHz (MAX.)
Package Mounted devices
MC-458CB641ES-A80 125 MHz 144-pin Small Outline DIMM 4 pieces of
µ
PD45128163G5 (Rev. E)
MC-458CB641ES-A10 100 MHz (Socket Type) (10.16mm (400) TSOP (II))
MC-458CB641PS-A80 125 MHz Edge connector: Gold plated 4 pieces of
µ
PD45128163G5 (Rev. P)
MC-458CB641PS-A10 100 MHz 25.4 mm height (10.16mm (400) TSOP (II))
MC-458CB641XS-A80 125 MHz 4 pieces of
µ
PD45128163G5 (Rev. X)
MC-458CB641XS-A10 100 MHz (10.16mm (400) TSOP (II))
Data Sheet E0069N10 3
MC-458CB641ES, 458CB641PS, 458CB641XS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
Vss
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB0
DQMB1
A0
A1
A2
Vss
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
CLK0
Vcc
/RAS
/WE
/CS0
NC
NC
Vss
NC
NC
DQ 16
DQ 17
DQ 18
DQ 19
Vss
DQ 20
DQ 21
DQ 22
DQ 23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQMB2
DQMB3
Vss
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
Vss
SDA
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
Vss
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
CKE0
Vcc
/CAS
NC
NC
NC
CLK1
Vss
NC
NC
Vcc
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
A7
BA0 (A13)
Vss
BA1 (A12)
A11
Vcc
DQMB6
DQMB7
Vss
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
/xxx indicates active low signal.
A0 - A11 : Address Inputs
[Row: A0 - A11, Column: A0 - A8]
BA0(A13),BA1(A12) : SDRAM Bank Select
DQ0 - DQ63 : Data Inputs/Outputs
CLK0, CLK1 : Clock Input
CKE0 : Clock Enable Input
/CS0 : Chip Select Input
/RAS : Row Address Strobe
/CAS : Column Address Strobe
/WE : Write Enable
DQMB0 - DQMB7 : DQ Mask Enable
SDA : Serial Data I/O for PD
SCL : Clock Input for PD
VCC : Power Supply
VSS : Ground
NC : No Connection
Data Sheet E0069N10
4
MC-458CB641ES, 458CB641PS, 458CB641XS
Block Diagram
/WE
/CS0
A0 - A11 A0 - A11 : D0 - D3
V
CC
D0 - D3
D0 - D3
SERIAL PD
SCL SDA
A0 A1 A2
DQMB0
DQMB1
/CS /WE
D0
LDQM
UDQM
DQ 0
DQ 1
DQ 4
DQ 3
DQ 2
DQ 5
DQ 6
DQ 7
DQMB2
DQMB3
/CS /WE
D1
LDQM
UDQM
DQMB6
DQMB7
/CS /WE
D3
LDQM
UDQM
DQMB4
DQMB5
/CS /WE
D2
LDQM
UDQM
DQ 0
DQ 1
DQ 2
DQ 5
DQ 4
DQ 3
DQ 6
DQ 7
DQ 8
DQ 9
DQ 10
DQ 13
DQ 12
DQ 11
DQ 14
DQ 15
DQ 15
DQ 14
DQ 11
DQ 12
DQ 13
DQ 10
DQ 9
DQ 8
DQ 16
DQ 17
DQ 18
DQ 21
DQ 20
DQ 19
DQ 22
DQ 23
DQ 24
DQ 25
DQ 26
DQ 29
DQ 28
DQ 27
DQ 30
DQ 31
DQ 8
DQ 9
DQ 12
DQ 11
DQ 10
DQ 13
DQ 14
DQ 15
DQ 7
DQ 6
DQ 3
DQ 4
DQ 5
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 3
DQ 4
DQ 5
DQ 2
DQ 1
DQ 0
DQ 8
DQ 9
DQ 12
DQ 11
DQ 10
DQ 13
DQ 14
DQ 15
DQ 48
DQ 49
DQ 50
DQ 53
DQ 52
DQ 51
DQ 54
DQ 55
DQ 56
DQ 57
DQ 58
DQ 61
DQ 60
DQ 59
DQ 62
DQ 63
DQ 32
DQ 33
DQ 34
DQ 37
DQ 36
DQ 35
DQ 38
DQ 39
DQ 40
DQ 41
DQ 42
DQ 45
DQ 44
DQ 43
DQ 46
DQ 47
DQ 0
DQ 1
DQ 4
DQ 3
DQ 2
DQ 5
DQ 6
DQ 7
DQ 15
DQ 14
DQ 11
DQ 12
DQ 13
DQ 10
DQ 9
DQ 8
/RAS /RAS : D0 - D3
/CAS /CAS : D0 - D3
CKE0 CKE : D0 - D3
V
SS
BA0 A13 : D0 - D3
CLK0 CLK1
CLK : D0 - D3
10 Ω
10 pF
C
BA1 A12 : D0 - D3
Remarks 1. D0 - D3:
µ
PD45128163 (2M words x 16 bits x 4 banks)
2.
The value of all resistors is 10 Ω.
Data Sheet E0069N10 5
MC-458CB641ES, 458CB641PS, 458CB641XS
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100
µ
s and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND VCC –0.5 to +4.6 V
Voltage on input pin relative to GND VT –0.5 to +4.6 V
Short circuit output current IO 50 mA
Power dissipation PD 4 W
Operating ambient temperature TA 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC + 0.3 V
Low level input voltage VIL –0.3 + 0.8 V
Operating ambient temperature TA 0 70
°C
Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Symbol Test condition MIN. TYP. MAX. Unit
Input capacitance CI1 A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE
15 30 pF
C
I2 CLK0 23 37
C
I3 CKE0 15 26
C
I4 /CS0 15 26
C
I5 DQMB0 - DQMB7 5 10
Data input/output capacitance CI/O DQ0 - DQ63 5 12 pF
Data Sheet E0069N10
6
MC-458CB641ES, 458CB641PS, 458CB641XS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition MIN. MAX. Unit Notes
Operating current ICC1 Burst length = 1, tRC ≥ tRC(MIN.) /CAS latency = 2 -A80 440 mA 1
-A10 440
/CAS latency = 3 -A80 440
-A10 440
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns 4 mA
power down mode ICC2PS CKE ≤ VIL(MAX.), tCK = ∞ 4
Precharge standby current in
non power down mode
ICC2N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
80 mA
I
CC2NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. 32
Active standby current in ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns 20 mA
power down mode ICC3PS CKE ≤ VIL(MAX.), tCK = ∞ 16
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
120 mA
I
CC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable. 80
Operating current ICC4 t
CK ≥ tCK(MIN.), IO = 0 mA /CAS latency = 2 -A80 580 mA 2
(Burst mode) -A10 440
/CAS latency = 3 -A80 700
-A10 560
CBR (Auto) refresh current ICC5 t
RC ≥ tRC(MIN.) /CAS latency = 2 -A80 920 mA 3
-A10 920
/CAS latency = 3 -A80 920
-A10 920
Self refresh current ICC6 CKE ≤ 0.2 V 8 mA
Input leakage current II(L) V
I = 0 to 3.6 V, All other pins not under test = 0 V – 4 +4
µ
A
Output leakage current IO(L) D
OUT is disabled, VO = 0 to 3.6 V –1.5 +1.5
µ
A
High level output voltage VOH I
O = – 4.0 mA 2.4 V
Low level output voltage VOL I
O = + 4.0 mA 0.4 V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. I
CC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
Data Sheet E0069N10 7
MC-458CB641ES, 458CB641PS, 458CB641XS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Value Unit
AC high level input voltage / low level input voltage 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing measurement reference level 1.4 V
tCK
tCH tCL
2.4 V
1.4 V
0.4 V
CLK
2.4 V
1.4 V
0.4 V
Input
tSETUP tHOLD
Output
tAC
tOH
Data Sheet E0069N10
8
MC-458CB641ES, 458CB641PS, 458CB641XS
Synchronous Characteristics
Parameter Symbol -A80 -A10 Unit Note
MIN. MAX. MIN. MAX.
Clock cycle time /CAS latency = 3 tCK3 8 (125 MHz) 10 (100 MHz) ns
/CAS latency = 2 t
CK2 10 (100 MHz) 13 (77 MHz) ns
Access time from CLK /CAS latency = 3 tAC3 6 6 ns 1
/CAS latency = 2 t
AC2 6 7 ns 1
CLK high level width tCH 3 3 ns
CLK low level width tCL 3 3 ns
Data-out hold time /CAS latency = 3 tOH3 3 3 ns 1
/CAS latency = 2 t
OH2 3 3 ns 1
Data-out low-impedance time tLZ 0 0 ns
Data-out high-impedance time /CAS latency = 3 tHZ3 3 6 3 6 ns
/CAS latency = 2 t
HZ2 3 6 3 7 ns
Data-in setup time tDS 2 2 ns
Data-in hold time tDH 1 1 ns
Address setup time tAS 2 2 ns
Address hold time tAH 1 1 ns
CKE setup time tCKS 2 2 ns
CKE hold time tCKH 1 1 ns
CKE setup time (Power down exit) tCKSP 2 2 ns
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
t
CMS 2 2 ns
Command (/CS0, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
t
CMH 1 1 ns
Note 1. Output load
Output Z = 50 Ω
50 pF
Remark These specifications are applied to the monolithic device.
Data Sheet E0069N10 9
MC-458CB641ES, 458CB641PS, 458CB641XS
Asynchronous Characteristics
Parameter Symbol -A80 -A 10 Unit Note
MIN. MAX. MIN. MAX.
ACT to REF/ACT command period (Operation) tRC 70 70 ns
REF to REF/ACT command period (Refresh) tRC1 70 78 ns
ACT to PRE command period tRAS 48 120,000 50 120,000 ns
PRE to ACT command period tRP 20 20 ns
Delay time ACT to READ/WRITE command tRCD 20 20 ns
ACT(one) to ACT(another) command period tRRD 16 20 ns
Data-in to PRE command /CAS latency = 3 tDPL3 8 10 ns
period /CAS latency = 2 tDPL2 8 10 ns
Data-in to ACT(REF) command /CAS latency = 3 tDAL3 1CLK+20
1CLK+20
ns
period (Auto precharge) /CAS latency = 2 tDAL2 1CLK+20
1CLK+20
ns
Mode register set cycle time tRSC 2 2 CLK
Transition time tT 0.5 30 1 30 ns
Refresh time (4,096 refresh cycles) tREF 64 64 ms
Data Sheet E0069N10
10
MC-458CB641ES, 458CB641PS, 458CB641XS
Serial PD (1/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
0 Defines the number of bytes written into
serial PD memory
80H 1 0 0 0 0 0 0 0 128 bytes
1 Total number of bytes of serial PD memory 08H 0 0 0 0 1 0 0 0 256 bytes
2 Fundamental memory type 04H 0 0 0 0 0 1 0 0 SDRAM
3 Number of rows 0CH 0 0 0 0 1 1 0 0 12 rows
4 Number of columns 09H 0 0 0 0 1 0 0 1 9 columns
5 Number of banks 01H 0 0 0 0 0 0 0 1 1 bank
6 Data width 40H 0 1 0 0 0 0 0 0 64 bits
7 Data width (continued) 00H 0 0 0 0 0 0 0 0 0
8 Voltage interface 01H 0 0 0 0 0 0 0 1 LVTTL
9 CL = 3 Cycle time -A80 80H 1 0 0 0 0 0 0 0 8 ns
-A10 A0H 1 0 1 0 0 0 0 0 10 ns
10 CL =3 Access time -A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 60H 0 1 1 0 0 0 0 0 6 ns
11 DIMM configuration type 00H 0 0 0 0 0 0 0 0 None
12 Refresh rate/type 80H 1 0 0 0 0 0 0 0 Normal
13 SDRAM width 10H 0 0 0 1 0 0 0 0 ×16
14 Error checking SDRAM width 00H 0 0 0 0 0 0 0 0 None
15 Minimum clock delay 01H 0 0 0 0 0 0 0 1 1 clock
16 Burst length supported 8FH 1 0 0 0 1 1 1 1 1, 2, 4, 8, F
17 Number of banks on each SDRAM 04H 0 0 0 0 0 1 0 0 4 banks
18 /CAS latency supported 06H 0 0 0 0 0 1 1 0 2, 3
19 /CS latency supported 01H 0 0 0 0 0 0 0 1 0
20 /WE latency supported 01H 0 0 0 0 0 0 0 1 0
21 SDRAM module attributes 00H 0 0 0 0 0 0 0 0
22 SDRAM device attributes : General 0EH 0 0 0 0 1 1 1 0
23 CL = 2 Cycle time -A80 A0H 1 0 1 0 0 0 0 0 10 ns
-A10 D0H 1 1 0 1 0 0 0 0 13 ns
24 CL = 2 Access time -A80 60H 0 1 1 0 0 0 0 0 6 ns
-A10 70H 0 1 1 1 0 0 0 0 7 ns
25-26 00H 0 0 0 0 0 0 0 0
27 tRP(MIN.) -A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
28 tRRD(MIN.) -A80 10H 0 0 0 1 0 0 0 0 16 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
29 tRCD(MIN.) -A80 14H 0 0 0 1 0 1 0 0 20 ns
-A10 14H 0 0 0 1 0 1 0 0 20 ns
30 tRAS(MIN.) -A80 30H 0 0 1 1 0 0 0 0 48 ns
-A10 32H 0 0 1 1 0 0 1 0 50 ns
31 Module bank density 10H 0 0 0 1 0 0 0 0 64M bytes
Data Sheet E0069N10 11
MC-458CB641ES, 458CB641PS, 458CB641XS
(2/2)
Byte No. Function Described Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
32 Command and address -A80 20H 0 0 1 0 0 0 0 0 2 ns
signal setup time -A10 20H 0 0 1 0 0 0 0 0 2 ns
33 Command and address -A80 10H 0 0 0 1 0 0 0 0 1 ns
signal hold time -A10 10H 0 0 0 1 0 0 0 0 1 ns
34 Data signal input setup time -A80 20H 0 0 1 0 0 0 0 0 2 ns
-A10 20H 0 0 1 0 0 0 0 0 2 ns
35 Data signal input hold time -A80 10H 0 0 0 1 0 0 0 0 1 ns
-A10 10H 0 0 0 1 0 0 0 0 1 ns
36-61 00H 0 0 0 0 0 0 0 0
62 SPD revision -A80 12H 0 0 0 1 0 0 1 0 1.2 A
-A10 12H 0 0 0 1 0 0 1 0 1.2 A
63 Checksum for bytes 0 - 62 -A80 E7H 1 1 1 0 0 1 1 1
-A10 4DH 0 1 0 0 1 1 0 1
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency -A80 64H 0 1 1 0 0 1 0 0 100 MHz
-A10 64H 0 1 1 0 0 1 0 0 100 MHz
127 Intel specification /CAS -A80 87H 1 0 0 0 0 1 1 1
latency support -A10 85H 1 0 0 0 0 1 0 1
Timing Chart
Refer to the µ
µµ
µPD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0069N10
12
MC-458CB641ES, 458CB641PS, 458CB641XS
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
M1 (AREA B)
R
M2 (AREA A) H
D
U1
T
Q
U2
detail of A part
D2
D1 X
V
A
(OPTIONAL HOLES)
F
I
S
W
N
A (AREA B)
C
B
A1 (AREA A)
E
M
L
ITEM MILLIMETERS
D
D1
H
4.6
1.5±0.10
0.8 (T.P.)
B 23.2
A 67.6
F 3.7
M 25.4±0.15
M1 3.4
A1 67.6±0.15
I 3.3
C 29.0
D2
E4.0
32.8
L 20.0
R
S
V
4.0±0.10
1.8
0.25 MAX.
N 3.8 MAX.
U2 4.0 MIN.
M2 22.0
W 0.6±0.05
Q R2.0
T
U1 1.0±0.1
3.2 MIN.
X 2.55 MIN.
M144S-80A15
Y 2.0 MIN.
φ
Y
Data Sheet E0069N10 13
MC-458CB641ES, 458CB641PS, 458CB641XS
[MEMO]
Data Sheet E0069N10
14
MC-458CB641ES, 458CB641PS, 458CB641XS
[MEMO]
Data Sheet E0069N10 15
MC-458CB641ES, 458CB641PS, 458CB641XS
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
MC-458CB641ES, 458CB641PS, 458CB641XS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
M8E 00. 4
The information in this document is current as of September, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or
data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all
products and/or types are available in every country. Please check with an Elpida Memory, Inc. for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document.
Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of Elpida semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of Elpida or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
Elpida semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in
Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in
applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine
Elpida's willingness to support a given application.
(Note)
(1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned
subsidiaries.
(2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or
for Elpida (as defined above).
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